NCV7357 CAN FD Transceiver, High Speed Description The NCV7357 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus. The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. The NCV7357 is an addition to the CAN high-speed transceiver family complementing NCV7344 CAN stand-alone transceivers and previous generations such as AMIS42665, AMIS3066x, etc. The NCV7357 guarantees additional timing parameters to ensure robust communication at data rates beyond 1 Mbps to cope with CAN flexible data rate requirements (CAN FD). These features make the NCV7357 an excellent choice for all types of HS-CAN networks, in nodes that require only a basic CAN capability. Features * Compatible with ISO 11898-2:2016 * CAN FD Timing Specified up to 5 Mbps * VIO Pin on NCV7357-3 Version Allowing Direct Interfacing with * * * * * * * * * * * 3 V to 5 V Microcontrollers Low Current, Listen Only Silent Mode Low Electromagnetic Emission (EME) and High Electromagnetic Immunity Very Low EME without Common-mode (CM) Choke No Disturbance of the Bus Lines with an Unpowered Node Transmit Data (TxD) Dominant Timeout Function Under All Supply Conditions the Chip Behaves Predictably Very High ESD Robustness of Bus Pins, >8 kV System ESD Pulses Thermal Protection Bus Pins Short Circuit Proof to Supply Voltage and Ground Bus Pins Protected Against Transients in an Automotive Environment These are Pb-free Devices www.onsemi.com SOIC-8 D SUFFIX CASE 751AZ MARKING DIAGRAM 8 1 NV7357-X ALYWG G PIN ASSIGNMENT 1 GND VCC S EP RxD CANH CANL NC (-0) VIO (-3) NCV7357D1x (Top View) TxD 1 GND 2 V CC 3 RxD 4 NCV7357-X * Automotive * Industrial Networks 8 TxD * Wettable Flank Package for Enhanced Optical Inspection * NCV Prefix for Automotive and Other Applications Requiring Typical Applications 1 NV7357-X ALYWG G NV7357-X = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package Quality Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable DFNW8 MW SUFFIX CASE 507AB 8 S 7 CANH 6 CANL 5 NC (-0) V IO (-3) NCV7357MWx (Top View) ORDERING INFORMATION See detailed ordering, marking and shipping information on page 11 of this data sheet. (c) Semiconductor Components Industries, LLC, 2015 March, 2019 - Rev. 0 1 Publication Order Number: NCV7357/D NCV7357 VCC NC 5 3 NCV7357-0 VCC 7 1 Timer TxD CANH Thermal Shutdown VCC 6 CANL S RxD Mode control 8 4 Driver control 2 COMP GND Figure 1. NCV7357-0 Block Diagram VIO VCC 5 3 NCV7357-3 VIO 7 TxD 1 Timer Thermal Shutdown CANH VIO 6 S RxD 8 4 Mode control CANL Driver control 2 COMP Figure 2. NCV7357-3 Block Diagram www.onsemi.com 2 GND NCV7357 VBAT IN 5V -reg OUT VCC NC VCC 3 S Micro- controller 8 TxD 1 RxD 4 RLT = 60 W 7 NCV 7357-0 5 CANH CAN BUS CANL 6 . RLT = 60 W 2 GND GND Figure 3. Application Diagram NCV7357-0 VBAT IN 5V -reg OUT IN 3V -reg OUT VIO VCC 3 S Micro- controller TxD RxD 8 1 4 NCV7357-3 5 . 7 RLT = 60 W CANH CAN BUS 6 CANL RLT = 60 W 2 GND GND Figure 4. Application Diagram NCV7357-3 Table 1. PIN FUNCTION DESCRIPTION Pin Name 1 TxD Transmit data input; low input U dominant driver; internal pull-up current 2 GND Ground 3 VCC Supply voltage 4 RxD Receive data output; dominant transmitter U low output 5 5 NC VIO Not connected. On NCV7357-0 only Digital Input / Output pins supply voltage. On NCV7357-3 only 6 CANL Low-level CAN bus line (low in dominant mode) 7 CANH High-level CAN bus line (high in dominant mode) 8 S Silent mode control input; internal pull-up current EP Description Exposed Pad. Recommended to connect to GND or left floating in application (DFNW8 package only). www.onsemi.com 3 NCV7357 FUNCTIONAL DESCRIPTION High speed CAN FD transceiver * Transmit dominant timeout, long * Support of bit rates up to 5 Mbps * Normal Bus biasing NCV7357 implements high-speed physical layer CAN FD transceiver compatible with ISO11898-2, implementing following optional features or alternatives: * Extended bus load range Operating Modes NCV7357 provides two modes of operation as illustrated in Table 2. These modes are selectable through pin S. Table 2. OPERATING MODES Pin S Mode Low Normal High Pin TxD BUS Pin RxD 0 Dominant 0 1 Recessive 1 X Dominant (1) 0 Silent X Recessive 1. CAN BUS driven by another transceiver on the BUS 2. 'X' = don't care 1 Power-off Overtemperature Detection This virtual mode is entered as soon as the VCC or VIO undervoltage condition is detected. The internal logic is reset and the transceiver is disabled. CAN bus pins are kept floating. As soon as both VCC and VIO voltages rise above corresponding undervoltage recovery thresholds, the device proceeds to Normal or Silent mode, depending on S pin state. A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds TJ(sd) value. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off-state resets when the temperature decreases below the shutdown threshold and pin TxD goes high. The thermal protection circuit is particularly needed when a bus line short circuits. Normal Mode In the normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give low EME. TxD Dominant Timeout Function A TxD dominant timeout timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication) if pin TxD is forced permanently low by a hardware and/or software application failure. The timer is triggered by a negative edge on pin TxD. If the duration of the low-level on pin TxD exceeds the internal timer value tdom(TxD), the transmitter is disabled, driving the bus into a recessive state. The timer is reset by a positive edge on pin TxD. This TxD dominant timeout time tdom(TxD) defines the minimum possible bit rate to 17 kbps. Silent Mode In the silent mode, the transmitter is disabled. The bus pins are in recessive state independent of TxD input. Transceiver listens to the bus and provides data to controller, but controller is prevented from sending any data to the bus. Any mode UV detected Power-off CAN: off (no bias) RxD: High-Z TxD, S: High-Z No UV and S = Low Normal mode Fail Safe Features No UV and S = High S = High Silent mode S = Low S = High CAN: Tx/Rx CAN bias: VCC/2 S = Low CAN: Rx only CAN bias: VCC/2 Notes: NCV7357-0 UV detected: VCC < VUVDVCC No UV: V CC > VUVDVCC A current-limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. Detection of undervoltage on supply pin (VCC or VIO) causes switching off device. After supply voltage is recovered TxD pin must be first released to high to allow sending dominant bits again. The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see NCV7357-3 UV detected: VCC < VUVDVCC and/or VIO < VUVDVIO No UV: V CC > VUVDVCC and VIO > VUVDVIO www.onsemi.com 4 NCV7357 Figure 7). Pins TxD and S are biased internally should the input become disconnected. Pins TxD, S and RxD will be floating, preventing reverse supply should the VCC supply be removed. between microcontroller and transceiver are properly adjusted. See Figure 4. Definitions All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. VIO Supply Pin The VIO pin (available only on NCV7357-3 version) should be connected to microcontroller supply pin. By using VIO supply pin shared with microcontroller the I/O levels ABSOLUTE MAXIMUM RATINGS Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min. Max. Unit -0.3 +6.0 V 0 < VCC < 5.5 V; no time limit -42 +42 V 0 < VCC < 5.5 V; no time limit -42 +42 V DC voltage between CANH and CANL -42 +42 V DC voltage at pin TxD, RxD, S -0.3 +6.0 V -6 +6 kV -750 +750 V -8 +8 kV VSUP Supply voltage VCC, VIO VCANH DC voltage at pin CANH VCANL DC voltage at pin CANL VCANH - CANL VI/O Conditions VesdHBM Electrostatic discharge voltage at all pins, Component HBM (Note 3) VesdCDM Electrostatic discharge voltage at all pins, Component CDM (Note 4) VesdIEC Electrostatic discharge voltage at pins CANH and CANL, System HBM (Note 6) (Note 5) Vschaff Voltage transients, pins CANH, CANL. According to ISO7637-3, Class C (Note 6) test pulses 1 V test pulses 2a test pulses 3a Latch-up -100 Static latch-up at all pins +75 -150 V V test pulses 3b +100 V (Note 7) 150 mA +150 C +170 C Tstg Storage temperature -55 TJ Maximum junction temperature -40 MSLSOIC Moisture sensitivity level for SOIC-8 2 - MSLDFN Moisture sensitivity level for DFNW8 1 - Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA-JESD22. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor 4. Standardized charged device model ESD pulses when tested according to AEC-Q100-011 5. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000-4-2. Equivalent to discharging a 150 pF capacitor through a 330 W resistor referenced to GND 6. Results were verified by external test house 7. Static latch-up immunity: Static latch-up protection level when tested according to EIA/JESD78 www.onsemi.com 5 NCV7357 Table 4. THERMAL CHARACTERISTICS Symbol Value Unit Thermal characteristics SOIC-8 (Note 8) Thermal Resistance Junction-to-Air, Free air, 1S0P PCB (Note 9) Thermal Resistance Junction-to-Air, Free air, 2S2P PCB (Note 10) Parameter RqJA RqJA 131 81 C/W C/W Thermal characteristics DFNW8 (Note 8) Thermal Resistance Junction-to-Air, Free air, 1S0P PCB (Note 9) Thermal Resistance Junction-to-Air, Free air, 2S2P PCB (Note 10) RqJA RqJA 125 58 C/W C/W 8. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters 9. Values based on test board according to EIA/JEDEC Standard JESD51-3, signal layer with 10% trace coverage 10. Values based on test board according to EIA/JEDEC Standard JESD51-7, signal layers with 10% trace coverage Table 5. ELECTRICAL CHARACTERISTICS (VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.25 V; for typical values TA = 25C, for min/max values TJ = -40 to +150C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2). Positive currents flow into the respective pin; (Notes 11)) Symbol Parameter Conditions Min Typ Max Unit (Note 12) 4.75 5.0 5.25 V Dominant; VTxD = Low 30 45 55 mA Recessive; VTxD = High 2.0 5.0 10 mA Normal mode, Dominant; VTxD = 0 V; one of bus wires shorted -3 V (VCANH, VCANL) +18 V 2.0 - SUPPLY (Pin VCC) VCC Power supply voltage ICC Supply current in Normal mode ICCS VUVDVCC 105 mA Supply current in silent mode NCV7357-3 version 0.1 - 1.3 mA Supply current in silent mode NCV7357-0 version 0.1 - 1.5 mA Undervoltage detection on VCC pin 3.5 4.0 4.3 V 2.8 - 5.5 V mA VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7357-3 version VIO Supply voltage on pin VIO IIOS Supply current on pin VIO in silent mode VTxD = VIO - 120 200 IIONM Supply current on pin VIO during normal mode Dominant; VTxD = Low - 700 900 Recessive; VTxD = High - 460 600 2.0 2.3 2.6 V VUVDVIO Undervoltage detection voltage on VIO pin mA TRANSMITTER DATA INPUT (Pin TxD) VIH High-level input voltage Output recessive 2.0 - - V VIL Low-level input voltage Output dominant -0.3 - 0.8 V IIH High-level input current VTxD = VCC / VIO -5.0 0 5.0 mA IIL Low-level input current VTxD = 0 V -300 -150 -75 mA Ci Input capacitance (Note 13) - 5 10 pF TRANSMITTER DATA INPUT (Pin S) VIH High-level input voltage Silent mode 2.0 - - V VIL Low-level input voltage Normal mode -0.3 - 0.8 V IIH High-level input current VS = VCC / VIO -1.0 0 1.0 mA IIL Low-level input current VS = 0 V -15 - -1.0 mA Ci Input capacitance (Note 13) - 5 10 pF www.onsemi.com 6 NCV7357 Table 5. ELECTRICAL CHARACTERISTICS (VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.25 V; for typical values TA = 25C, for min/max values TJ = -40 to +150C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2). Positive currents flow into the respective pin; (Notes 11)) RECEIVER DATA OUTPUT (Pin RxD) IOH High-level output current Normal mode VRxD = VCC / VIO - 0.4 V -8.0 -3.0 -1.0 mA IOL Low-level output current VRxD = 0.4 V 1.0 6.0 12 mA CAN TRANSMITTER (PINS CANH AND CANL) Vo(dom)(CANH) Dominant output voltage at pin CANH Normal mode; VTxD = Low; t < tdom(TxD); 50 W < RLT < 65 W 2.75 3.5 4.5 V Vo(dom)(CANL) Dominant output voltage at pin CANL Normal mode; VTxD = Low; t < tdom(TxD); 50 W < RLT < 65 W 0.5 1.5 2.25 V Recessive output voltage at pins CANH and CANL Normal or Silent mode; VTxD = High or VTxD = Low and t > tdom(TxD); no load 2.0 2.5 3.0 V Differential dominant output voltage (VCANH - VCANL) Normal mode; VTxD = Low; t < tdom(TxD); 45 W < RLT < 65 W 1.5 2.25 3.0 V Normal mode; VTxD = Low; t < tdom(TxD); RLT = 2 240 W (Note 13) 1.5 - 5.0 V Differential recessive output voltage (VCANH - VCANL) Normal or Silent mode; VTxD = High or VTxD = Low and t > tdom(TxD); no load -50 0 +50 mV Vo(dom)(sym) Dominant output voltage driver symmetry Vo(dom)(sym) = Vo(CANH)(dom) + Vo(CANL)(dom) TxD = square wave up to 1 MHz; CST = 4.7 nF 0.9 1.0 1.1 VCC Io(sc)(CANH) Short circuit output current at pin CANH in dominant Normal mode; TxD = Low, t < tdom(TxD); -3 V VCANH +18 V -100 -70 +1.0 mA Io(sc)(CANL) Short circuit output current at pin CANL in dominant Normal mode; TxD = Low, t < tdom(TxD); -3 V VCANL +36 V -1.0 +70 +100 mA Io(sc)(rec) Short circuit output current at pins CANH and CANL in recessive Normal or Silent mode; TxD = High, -27 V < VCANH, VCANL < + 32 V -5.0 - +5.0 mA 0 W < R(VCC to GND) < 1 MW VCANH = VCANL = 5 V -5.0 0 +5.0 mA VCC = VIO = 0 V VCANH = VCANL = 5 V -5.0 0 +5.0 mA Vo(rec) Vo(dom)(diff) Vo(dom)(diff)_ARB Vo(rec)(diff) CAN RECEIVER (Pins CANH and CANL) ILEAK(off) Input leakage current Vi(rec)(diff)_NM Differential input voltage range recessive state Normal or Silent mode; -12 V VCANH, VCANL +12 V; no load -3.0 - 0.5 V Vi(dom)(diff)_NM Differential input voltage range dominant state Normal or Silent mode; -12 V VCANH, VCANL +12 V; no load 0.9 - 8.0 V Differential receiver threshold voltage voltage Normal or Silent mode; -12 V VCANH, VCANL +12 V; no load 0.5 - 0.9 V Normal or Silent mode; extended, -30 V VCANH, VCANL +35 V; no load 0.4 - 1.0 V 15 25 37 kW Vi(th)(diff)_NM Vi(th)(diff)_NM_E Ri(cm) Common-mode input resistance at pins CANH and CANL -2 V VCANH, VCANL +7 V www.onsemi.com 7 NCV7357 Table 5. ELECTRICAL CHARACTERISTICS (VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.25 V; for typical values TA = 25C, for min/max values TJ = -40 to +150C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2). Positive currents flow into the respective pin; (Notes 11)) Ri(cm)(m) Ri(diff) Ci Ci(diff) Matching between pin CANH and pin CANL common mode input resistance Differential input resistance VCANH = VCANL = + 5 V Ri(diff) = Ri(cm)(CANH) + Ri(cm)(CANL) -2 V VCANH, VCANL + 7 V -1 0 +1 % 25 50 75 kW Input capacitance at pins CANH and CANL VTxD = High; (Note 13) - 7.5 20 pF Differential input capacitance VTxD = High; (Note 13) - 3.75 10 pF TIMING CHARACTERISTICS (see Figure 5, Figure 6 and Figure 8) td(TxD-BUSon) Propagation delay TxD to bus active Normal mode (Note 14) - 75 - ns td(TxD-BUSoff) Propagation delay TxD to bus inactive Normal mode (Note 14) - 85 - ns td(BUSon-RxD) Propagation delay bus active to RxD Normal or Silent mode (Note 14) - 24 - ns td(BUSoff-RxD) Propagation delay bus inactive to RxD Normal or Silent mode (Note 14) - 32 - ns 50 100 210 ns 50 120 210 ns Silent mode to Normal mode 5.0 11 50 ms TxD dominant timeout Normal mode; VTxD = Low 1.0 - 10 ms Bit time on RxD pin tbit(TxD) = 500 ns (Note 14) 400 - 550 ns tbit(TxD) = 200 ns (Note 14) 120 - 220 ns tbit(TxD) = 500 ns (Note 14) 435 - 530 ns tbit(TxD) = 200 ns (Note 14) 155 - 210 ns tbit(TxD) = 500 ns (Note 14) -65 - 40 ns tbit(TxD) = 200 ns (Note 14) -45 - 15 ns Junction temperature rising 160 180 200 C tpd_dr Propagation delay TxD to RxD dominant to recessive transition Normal mode (Note 14) tpd_rd Propagation delay TxD to RxD recessive to dominant transition Normal mode (Note 14) td(s-nm) tdom(TxD) tbit(RxD) tbit(Vi(diff)) Operating mode change delay Bit time on bus (CANH - CANL pin) Receiver timing symmetry Dtrec trec = tbit(RxD) - tbit(Vi(diff)) THERMAL SHUTDOWN TJ(sd) Shutdown junction temperature Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 12. In the range between VUVDVCC and 4.75 V and from 5.25 V to 6 V the chip is fully functional; some parameters may be outside of the specification 13. Values based on design and characterization, not tested in production 14. CLT = 100 pF, CST not present, CRxD = 15 pF www.onsemi.com 8 NCV7357 MEASUREMENTS SETUPS AND DEFINITIONS recessive TxD dominant recessive 0.7 x VIO* 0.3 x VIO* CANH CANL Vi(diff) = VCANH - VCANL RxD 900 mV 500 mV 0.7 x VIO* 0.3 x VIO* td(TxD-BUSon) td(BUSon-RXD) td(TxD-BUSoff) td(BUSoff-RXD) Edge length below 10 ns *On NCV7357-0 version VIO is replaced by VCC Figure 5. Transceiver Timing Diagram - Propagation Delays TxD 0.7 x VIO* 0.3 x VIO* 0.3 x VIO* 5 x tbit(TxD) tbit(TxD) Vi(diff) = VCANH - VCANL tpd_rd 900 mV 500 mV tbit(Vi(diff)) 0.7 x VIO* RxD tpd_dr Edge length below 10 ns *On NCV7357-0 version VIO is replaced by VCC 0.3 x VIO* tbit(RxD) Figure 6. Transceiver Timing Diagram - Loop Delay and Recessive Bit Time www.onsemi.com 9 NCV7357 +5 V +5 V VIO 3 TxD RxD NCV 7357-3 5 1 4 8 15 pF 100 nF VCC 7 CANH TxD 1 nF 1 Transient Generator 1 nF 6 RxD CANL 2 S VIO 4 8 GND 15 pF Figure 7. Test Circuit for Automotive Transients VCC 3 5 7 NCV7357-3 100 nF CANH RLT /2 CLT 6 CST RLT /2 CANL 100 pF 2x 30 W 2 S GND Figure 8. Test Circuit for Timing Characteristics www.onsemi.com 10 NCV7357 Table 6. ISO 11898-2:2016 Parameter Cross-Reference Table ISO 11898-2:2016 Specification Parameter NCV7357 Datasheet Notation Symbol Single ended voltage on CAN_H VCAN_H Vo(dom)(CANH) Single ended voltage on CAN_L DOMINANT OUTPUT CHARACTERISTICS VCAN_L Vo(dom)(CANL) Differential voltage on normal bus load VDiff Vo(dom)(diff) Differential voltage on effective resistance during arbitration VDiff Vo(dom)(diff)_ARB Differential voltage on extended bus load range (optional) VDiff Vo(dom)(diff) VSYM Vo(dom)(sym) Absolute current on CAN_H ICAN_H Io(SC)(CANH) Absolute current on CAN_L ICAN_L Io(SC)(CANL) Single ended output voltage on CAN_H VCAN_H NA Single ended output voltage on CAN_L VCAN_L NA VDiff NA Single ended output voltage on CAN_H VCAN_H Vo(off) (CANH) Single ended output voltage on CAN_L VCAN_L Vo(off) (CANL) VDiff Vo(off) (diff) Transmit dominant timeout, long tdom tdom(TxD) Transmit dominant timeout, short tdom NA Recessive state differential input voltage range VDiff Vi(rec)(diff)_NM Dominant state differential input voltage range VDiff Vi(dom)(diff)_NM RDiff Ri(diff) RCAN_H RCAN_L Ri(cm) Ri(cm) mR Ri(cm)(m) tLoop tpd_rd tpd_dr DRIVER SYMMETRY Driver symmetry DRIVER OUTPUT CURRENT RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING ACTIVE Differential output voltage RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING INACTIVE Differential output voltage OPTIONAL TRANSMIT DOMINANT TIMEOUT STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING ACTIVE/ INACTIVE RECEIVER INPUT RESISTANCE Differential internal resistance Single ended internal resistance RECEIVER INPUT RESISTANCE MATCHING Matching a of internal resistance IMPLEMENTATION LOOP DELAY REQUIREMENT Loop delay OPTIONAL IMPLEMENTATION DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 1 MBIT/S AND UP TO 2 MBIT/S Transmitted recessive bit width @ 2 Mbit/s tBit(Bus) tbit(Vi(diff)) Received recessive bit width @ 2 Mbit/s tBit(RXD) tbit(RxD) DtRec Dtrec Receiver timing symmetry @ 2 Mbit/s OPTIONAL IMPLEMENTATION DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 2 MBIT/S AND UP TO 5 MBIT/S Transmitted recessive bit width @ 5 Mbit/s tBit(Bus) tbit(Vi(diff)) Transmitted recessive bit width @ 5 Mbit / s tBit(RXD) tbit(RxD) www.onsemi.com 11 NCV7357 Received recessive bit width @ 5 Mbit / s DtRec Dtrec VDiff VCANH - CANL General maximum rating VCAN_H and VCAN_L VCAN_H VCAN_L VCANH VCANL Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_H VCAN_L NA ICAN_H, ICAN_L ILEAK(off) CAN activity filter time, long tFilter NA CAN activity filter time, short tFilter NA Wake-up timeout, short tWake NA MAXIMUM RATINGS OF VCAN_H, VCAN_L AND VDIFF Maximum rating VDiff MAXIMUM LEAKAGE CURRENTS ON CAN_H AND CAN_L, UNPOWERED Leakage current on CAN_H, CAN_L BUS BIASING CONTROL TIMINGS Wake-up timeout, long Timeout for bus inactivity (Required for selective wake-up implementation only) Bus Bias reaction time (Required for selective wake-up implementation only) tWake NA tSilence NA tBias NA Table 7. ORDERING INFORMATION Part Number Description NCV7357D10R2G High Speed CAN FD Transceiver NCV7357D13R2G High Speed CAN FD Transceiver with VIO pin NCV7357MW0R2G High Speed CAN FD Transceiver NCV7357MW3R2G High Speed CAN FD Transceiver with VIO pin Temperature Range Package Shipping SOIC 150 8 GREEN (Matte Sn, JEDEC MS-012) (Pb-Free) 3000 / Tape & Reel -40C to +150C DFNW8 Wettable Flank (Pb-Free) 3000 / Tape & Reel -40C to +150C www.onsemi.com 12 3000 / Tape & Reel 3000 / Tape & Reel NCV7357 PACKAGE DIMENSIONS SOIC-8 CASE 751AZ ISSUE B NOTES 4&5 0.10 C D 45 5 CHAMFER D h NOTE 6 D A 8 H 2X 5 0.10 C D E E1 NOTES 4&5 L2 1 0.20 C D 4 8X B NOTE 6 TOP VIEW b 0.25 M L C DETAIL A C A-B D NOTES 3&7 DETAIL A A2 NOTE 7 c 0.10 C A e A1 SIDE VIEW NOTE 8 SEATING PLANE C END VIEW SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF MAXIMUM MATERIAL CONDITION. 4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE. 5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER MOST EXTREMES OF THE PLASTIC BODY AT DATUM H. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H. 7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP. 8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. DIM A A1 A2 b c D E E1 e h L L2 MILLIMETERS MIN MAX --1.75 0.10 0.25 1.25 --0.31 0.51 0.10 0.25 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.25 0.41 0.40 1.27 0.25 BSC GENERIC MARKING DIAGRAM* 8X 0.76 8X 1.52 7.00 1 1.27 PITCH DIMENSIONS: MILLIMETERS *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G", may or not be present. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 13 NCV7357 DFNW8 3x3, 0.65P CASE 507AB ISSUE D A B D L3 L PIN ONE REFERENCE EEE EEE EEE L E EXPOSED COPPER A1 A4 A DETAIL B PLATING C C NOTE 4 A4 C SIDE VIEW SEATING PLANE D2 DETAIL A 1 L3 PLATED SURFACES NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.10 AND 0.20mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. THIS DEVICE CONTAINS WETTABLE FLANK DESIGN FEATURES TO AID IN FILLET FORMATION ON THE LEADS DURING MOUNTING. DIM A A1 A3 A4 b D D2 E E2 e K L L3 DETAIL B A3 0.05 C 8X ALTERNATE CONSTRUCTION DETAIL A TOP VIEW 0.05 C L3 MILLIMETERS MIN NOM MAX 0.90 0.80 0.85 --- --- 0.05 0.20 REF 0.10 --- --- 0.25 0.30 0.35 2.95 3.00 3.05 2.30 2.40 2.50 2.95 3.00 3.05 1.50 1.60 1.70 0.65 BSC 0.30 REF 0.35 0.40 0.45 0.00 0.05 0.10 GENERIC MARKING DIAGRAM* SECTION C-C 4 L E2 K e/2 8 5 e BOTTOM VIEW 8X b 0.10 C A B 0.05 C NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 2.55 2.28 (Note: Microdot may be in either location) 8X 0.75 8 5 1 4 *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. Some products may not follow the Generic Marking. 3.30 1.76 0.65 PITCH PACKAGE OUTLINE 8X 0.33 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 14 NCV7357 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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