September 1983
Revised February 1999
MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register
© 1999 Fairchild Semicond uctor Corpor ation DS005316.prf www.fairchildsemi.com
MM74HC165
Parallel-in/Serial-out 8-Bit Shift Register
General Descript ion
The MM 74HC165 h igh speed PARALLE L-I N /SE RIA L-O U T
SHIFT REGISTER utilizes advanced silicon-gate CMOS
technology. It has the low power consumption and high
noise immunity of standard CMOS integrated circuits,
along with the ability to drive 10 LS-TTL loads.
This 8-bit serial shift register shifts data from QA to QH
when clocked. Parallel inputs to each stage are enabled by
a low level at the SHIFT/LOAD input. Also included is a
gated CLOCK in put and a compl ementa ry output from t he
eighth bit.
Clocking is accomplishe d throu gh a 2-inp ut NOR ga te per-
mitting one input to be used as a CLOCK INHIBIT function.
Holding either of the CLOCK in puts high inhibits clocking,
and holding either CLOCK input low with the SHIFT/LOAD
input high enables the other CLOCK input. Data transfer
occurs on the positive going edge of the clock. Parallel
loading is inhibited as long as the SHIFT/LOAD input is
HIGH. When taken LOW, data at the parallel inputs is
loaded directly into the re gister ind epend ent of the stat e of
the clock.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to VCC and ground.
Features
■Typical propagation delay: 20 ns (clock to Q)
■Wide operating supply voltage range: 2–6V
■Low input curre nt: 1 µA maximum
■Low quiescent supply current: 80 µA maximum (74HC
Series)
■Fanout of 10 LS-TTL loads
Ordering Code:
Devices also ava ilable in Ta pe and Reel. Spe ci fy by append ing the suffix let t er “X” to the o rdering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Function Table
H = HIGH Level (steady state), L = LOW Level (steady sta t e)
X = Irrelevant (an y input, including trans it ions)
↑ = Transition from LOW-to-HIGH level
QA0, QB0, QH0 = The level of QA, QB, or Q H, respectively, before the indi-
cated s te ady-stat e input con dit ions were establ is hed.
QAN, QGN = The level of QA or QG before the most recent ↑ transition of the
clock; indicates a one-bit s hif t .
Order Number Package Number Package Description
MM74HC165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC165SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC165MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC165 N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs Internal Output
Shift/ Clock Clock Serial Parallel Outputs QH
Load Inhibit A. . .H QAQB
LXXXa...habh
HL LX XQ
A0 QB0 QH0
HL ↑HXHQ
AN QGN
HL ↑LXLQ
AN QGN
HHXX XQ
A0 QB0 QH0
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MM74HC165
Logic Diagrams
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MM74HC165
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute M aximum Ra tings are those valu es beyond w hich dam-
age to the device may occur.
Note 2: Unles s ot herwise specified all v olt ages are referenc ed to ground.
Note 3: Power Dis sipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: F or a pow er sup ply of 5V ±1 0% the worst case output voltages (VOH, and V OL) occu r for HC a t 4.5V. Thus the 4.5V values shou ld be use d when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V a nd 4.5V respectiv ely. (The VIH v alue at 5. 5V is 3.8 5V.) The worst c as e leakage cur-
rent (IIN, ICC, and IOZ) occur fo r C M OS at the h igher volta ge and so th e 6. 0V values s hould be used.
Supply Voltage (VCC)−0.5 to +7.0V
DC Input Voltage (VIN)−1.5 to VCC +1.5V
DC Output Voltage (VOUT)−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)±20 mA
DC Output Current, per pin (IOUT)±25 mA
DC VCC or GND Current, per pin (ICC)±50 mA
Stora ge Temper atu re R ang e (TSTG)−65°C to +150°C
Power Di ssipa tion (P D)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Tem perature (TL)
(Soldering 10 seconds) 260 °C
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage
(VIN, VOUT)0V
CC V
Operati ng Temperature Range (TA)−40 +85 °C
Input Rise or Fall Times
(tr, tf) VCC
= 2.0V 1000 ns
VCC = 4.5V 500 ns
VCC = 6.0V 400 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current VCC = 2−6V
ICC Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA
Supply Curre nt IOUT = 0 µA
VCC = 2−6V
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MM74HC165
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol Parameter Conditions Typ Guaranteed
Limit Units
fMAX Maximum Operating Frequency 50 30 MHz
tPHL, tPLH Maximum Propagation Delay H to QH or Q H15 25 ns
tPHL, tPLH Maximum Propagation Delay 13 25 ns
Serial Shift/Parallel Load to QH
tPHL, tPLH Maximum Propagation Delay 15 25 ns
Clock to Output
tSMinimum Setup Time Serial Input 10 20 ns
to Clock, Parallel or Data to Shift/Load
tSMinimum Setup Time Shift/Load to Clock 11 20 ns
tSMinimum Setup Time Clock Inhibit to Clock 10 20 ns
tHMinimum Hold Time Serial 0ns
Input to Clock or
Paralle l Data to Shift/Load
tWMinimum Pulse Width Clock 16 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guarant eed Lim its
fMAX Maximum Operating 2.0V 10 5 4 4 MHz
Frequency 4.5V 45 27 21 18 MHz
6.0V 50 32 25 21 MHz
tPHL, tPLH Maximum Propagation 2.0V 70 150 189 225 ns
Delay H to QH or Q H4.5V 21 30 38 45 ns
6.0V 18 26 33 39 ns
tPHL, tPLH Maximum Propagation 2.0V 70 175 220 260 ns
Delay Serial Shift/ 4.5V 21 35 44 52 ns
Parallel Load to QH6.0V 18 30 37 44 ns
tPHL, tPLH Maximum Propagation 2.0V 70 150 189 225 ns
Delay Clock to Output 4.5V 21 30 38 45 ns
6.0V 18 26 33 39 ns
tSMinimum Setup Time 2.0V 35 100 125 150 ns
Serial Input to Clock, 4.5V 11 20 25 30 ns
or Parallel Data to Shift/Load 6.0V 9 17 21 25 ns
tSMinimum Setup Time 2.0V 38 100 125 150 ns
Shift/Load to Clock 4.5V 12 20 25 30 ns
6.0V 9 17 21 25 ns
tSMinimum Setup Time 2.0V 35 100 125 150 ns
Clock Inhibit to Clock 4.5V 11 20 25 30 ns
6.0V 9 17 21 25 ns
tHMinimum Hold Time Serial 2.0V 0 0 0 ns
Input to Clock or 4.5V 0 0 0 ns
Parallel Data to Shift/Load 6.0V 0 0 0 ns
tWMinimum Pulse Width, 2.0V 30 80 100 120 ns
Clock 4.5V 9 16 20 24 ns
6.0V 8 14 18 20 ns
tTHL, tTLH Maximum Output 2.0V 30 75 95 110 ns
Rise and Fall Time 4.5V 9 15 19 22 ns
6.0V 8 13 16 19 ns
tr, tfMaximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time 4.5V 500 500 500 ns
6.0V 400 400 400 ns
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MM74HC165
AC Electrical Characteristics (Continued)
Note 5: CPD determ ines the no load dynamic po w er c onsump ti on, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumptio n,
IS = CPD VCC f + ICC.
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
CPD Power Dissipation (per package) 100 pF
Capacitance (Note 5)
CIN Maximum Input Capacitance 5 10 10 10 pF
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MM74HC165
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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MM74HC165
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Packag e Num be r MTC 16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC165 Parallel-in/Serial-out 8-Bit Shift Regis ter
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent i n any compon ent of a life su pport
device or system whose failure to perform can be rea-
sonabl y ex pect ed to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), MS-001, 0.300” Wide
Package N16E