ATMEGA329PA-MU - Atmel - searchdatasheet.com

Features

•High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16MIPS Throughput at16MHz (ATmega169A/169PA/649A/649P)

– Up to 20 MIPS Throughput at 20MHz (ATmega329A/329PA/3290A/3290PA/6490A/6490P)

– On-Chip 2-cycle Multiplier

•High Endurance Non-volatile Memory segments

– In-System Self-programmable Flash Program Memory

• 16Kbytes (ATmega169A/ATmega169PA)

• 32Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA)

• 64Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P)

–EEPROM

• 512bytes (ATmega169A/ATmega169PA)

• 1Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA)

• 2Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P)

–Internal SRAM

• 1Kbytes (ATmega169A/ATmega169PA)

• 2Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA)

• 4Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P)

– Write/Erase cyles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C(1)

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

•QTouch® library support

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix acquisition

– Up to 64 sense channels

•JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•Peripheral Features

– 4 x 25 Segment LCD Driver

(ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P)

– 4 x 40 Segment LCD Driver (ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P)

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Universal Serial Interface with Start Condition Detector

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby

•I/O and Packages

– 54/69 Programmable I/O Lines

–64/100-lead TQFP, 64-pad QFN/MLF, and 64-pad DRQFN

•Speed Grade:

– ATmega169A/169PA/649A/649P:

• 0 - 16MHz @ 1.8 - 5.5V,

– ATmega3290A/3290PA/6490A/6490P:

• 0 - 20MHz @ 1.8 - 5.5V,

•Temperature range:

– -40°C to 85°C Industrial

•Ultra-Low Power Consumption (picoPower devices)

– Active mode:

• 1MHz, 1.8V: 215µA

• 32kHz, 1.8V: 8µA (including Oscillator)

• 32kHz, 1.8V: 25µA (including Oscillator and LCD)

– Power-down Mode:

• 0.1µA at 1.8V

– Power-save Mode:

• 0.6µA at 1.8V (Including 32kHz RTC)

• 750nA at 1.8V

8-bit Atmel

Microcontroller

with 16/32/64K

Bytes In-System

Programmable

Flash

ATmega169A

ATmega169PA

ATmega329A

ATmega329PA

ATmega649A

ATmega649P

ATmega3290A

ATmega3290PA

ATmega6490A

ATmega6490P

Summary

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

1. Pin Configurations

1.1 Pinout - 64A (TQFP) and 64M1 (QFN/MLF)

Figure 1-1. Pinout ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P

PC0 (SEG12)

VCC

GND

PF0 (ADC0)

PF7 (ADC7/TDI)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

AREF

GND

AVCC

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

LCDCAP

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC2A/PCINT15) PB7

(T1/SEG24) PG3

(OC1B/PCINT14) PB6

(T0/SEG23) PG4

(OC1A/PCINT13) PB5

PC1 (SEG11)

PG0 (SEG14)

(SEG15) PD7

PC2 (SEG10)

PC3 (SEG9)

PC4 (SEG8)

PC5 (SEG7)

PC6 (SEG6)

PC7 (SEG5)

PA7 (SEG3)

PG2 (SEG4)

PA6 (SEG2)

PA5 (SEG1)

PA4 (SEG0)

PA3 (COM3)

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

PG1 (SEG13)

(SEG16) PD6

(SEG17) PD5

(SEG18) PD4

(SEG19) PD3

(SEG20) PD2

(INT0/SEG21) PD1

(ICP1/SEG22) PD0

(TOSC1) XTAL1

(TOSC2) XTAL2

RESET/PG5

GND

VCC

INDEX CORNER

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

1.2 Pinout - 100A (TQFP)

Figure 1-2. Pinout ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P

Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be sol-

dered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen

from the board.

(OC2A/PCINT15) PB7

DNC

(T1/SEG33) PG3

(T0/SEG32) PG4

RESET/PG5

VCC

GND

(TOSC2) XTAL2

(TOSC1) XTAL1

DNC

(PCINT26/SEG31) PJ2

(PCINT27/SEG30) PJ3

(PCINT28/SEG29) PJ4

(PCINT29/SEG28) PJ5

(PCINT30/SEG27) PJ6

DNC

(ICP1/SEG26) PD0

(INT0/SEG25) PD1

(SEG24) PD2

(SEG23) PD3

(SEG22) PD4

(SEG21) PD5

(SEG20) PD6

(SEG19) PD7

AVCC

AGND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

DNC

PH7 (PCINT23/SEG36)

PH6 (PCINT22/SEG37)

PH5 (PCINT21/SEG38)

PH4 (PCINT20/SEG39)

DNC

GND

VCC

DNC

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

DNC

PH3 (PCINT19/SEG7)

PH2 (PCINT18/SEG8)

PH1 (PCINT17/SEG9)

PH0 (PCINT16/SEG10)

DNC

PC5 (SEG11)

PC4 (SEG12)

PC3 (SEG13)

PC2 (SEG14)

PC1 (SEG15)

PC0 (SEG16)

PG1 (SEG17)

PG0 (SEG18)

INDEX CORNER

100

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

GND

DNC

(PCINT24/SEG35) PJ0

(PCINT25/SEG34) PJ1

DNC

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

TQFP

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

1.3 Pinout - 64MC (DRQFN)

Figure 1-3. Pinout ATmega169A/ATmega169PA

Table 1-1. DRQFN-64 Pinout ATmega169A/ATmega169PA

Top view Bottom view

A10

A11

B10

A12

B11

A13

B12

A14

B13

A15

B14

A16

B15

A17

A25

B22

A24

B21

A23

B20

A22

B19

A21

B18

A20

B17

A19

B16

A18

A34

B30

A33

B29

A32

B28

A31

B27

A30

B26

A29

B25

A28

B24

A27

B23

A26

A25

B22

A24

B21

A23

B20

A22

B19

A21

B18

A20

B17

A19

B16

A18

A17

B15

A16

B14

A15

B13

A14

B12

A13

B11

A12

B10

A11

A10

A26

B23

A27

B24

A28

B25

A29

B26

A30

B27

A31

B28

A32

B29

A33

B30

A34

A1 PE0 A9 PB7 A18 PG1 (SEG13) A26 PA2 ( C O M2 )

B1 VLCDCAP B8 PB6 B16 PG0 (SEG14) B23 PA3 ( C O M3 )

A2 PE1 A10 PG3 A19 PC0 (SEG12) A27 PA 1 ( C O M 1 )

B2 PE2 B9 PG4 B17 PC1 (SEG11) B24 PA 0 ( C O M 0 )

A3 PE3 A11 RESET A20 PC2 (SEG10) A28 VCC

B3 PE4 B10 VCC B18 PC3 (SEG9) B25 GND

A4 PE5 A12 GND A21 PC4 (SEG8) A29 PF7

B4 PE6 B11 XTAL2 (TOSC2) B19 PC5 (SEG7) B26 PF6

A5 PE7 A13 XTAL1 (TOSC1) A22 PC6 (SEG6) A30 PF5

B5 PB0 B12 PD0 (SEG22) B20 PC7 (SEG5) B27 PF4

A6 PB1 A14 PD1 (SEG21) A23 PG2 (SEG4) A31 PF3

B6 PB2 B13 PD2 (SEG20) B21 PA7 (SEG3) B28 PF2

A7 PB3 A15 PD3 (SEG19) A24 PA6 (SEG2) A32 PF1

B7 PB5 B14 PD4 (SEG18) B22 PA4 (SEG0) B29 PF0

A8 PB4 A16 PD5 (SEG17) A25 PA5 (SEG1) A33 AREF

B15 PD7 (SEG15) B30 AVCC

A17 PD6 (SEG16) A34 GND

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

2. Overview

The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a low-power CMOS 8-bit microcon-

troller based on the Atmel®AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle,

the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P achieves throughputs approaching 1

MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTE

DATA DIR.

REG. PORTA

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTE

DATA REGISTER

PORTA

DATA REGISTER

PORTD

TIMING AND

CONTROL

OSCILLATOR

INTERRUPT

UNIT

EEPROM

SPI

USART

STATUS

ALU

PORTB DRIVERS

PORTE DRIVERS

PORTA DRIVERS

PORTF DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB0 - PB7PE0 - PE7

PA0 - PA7PF0 - PF7

VCCGND

XTAL1

XTAL2

CONTROL

LINES

ANALOG

COMPARATOR

PC0 - PC7

8-BIT DATA BUS

RESET

CALIB. OSC

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

ON-CHIP DEBUG

JTAG TAP

PROGRAMMING

LOGIC

BOUNDARY-

SCAN

DATA DIR.

REG. PORTF

DATA REGISTER

PORTF

ADC

PD0 - PD7

DATA DIR.

REG. PORTG

DATA REG.

PORTG

PORTG DRIVERS

PG0 - PG4

AGND

AREF

AVCC

UNIVERSAL

SERIAL INTERFACE

AVR CPU

LCD

CONTROLLER/

DRIVER

PORTH DRIVERS

PH0 - PH7

DATA DIR.

REG. PORTH

DATA REGISTER

PORTH

PORTJ DRIVERS

PJ0 - PJ6

DATA DIR.

REG. PORTJ

DATA REGISTER

PORTJ

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P provides the

following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write

capabilities, 512/1K/2K bytes EEPROM, 1K/2K/4K byte SRAM, 54/69 general purpose I/O lines,

32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging

support and programming, a complete On-chip LCD controller with internal contrast control,

three flexible Timer/Counters with compare modes, internal and external interrupts, a serial pro-

grammable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-

bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five

software selectable power saving modes. The Idle mode stops the CPU while allowing the

SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down

mode saves the register contents but freezes the Oscillator, disabling all other chip functions

until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the

LCD controller continues to run, allowing the user to maintain a timer base and operate the LCD

display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU

and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching

noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running

while the rest of the device is sleeping. This allows very fast start-up combined with low-power

consumption.

Atmel® offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels

functionality into AVR® microcontrollers. The patented charge-transfer signal acquisition offers

robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key

Suppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use

QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip In-System re-Programmable (ISP) Flash allows the program memory to be repro-

grammed In-System through an SPI serial interface, by a conventional non-volatile memory

programmer, or by an On-chip Boot program running on the AVR core. The Boot program can

use any interface to download the application program in the Application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is updated,

providing true Read-While-Write operation.

By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a powerful

microcontroller that provides a highly flexible and cost effective solution to many embedded con-

trol applications.

The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P AVR is sup-

ported with a full suite of program and system development tools including: C Compilers, Macro

Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

2.2 Comparison Between

ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P

Table 2-1. Differences between: ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P

Device Flash EEPROM RAM LCD Segments

ATmega169A 16Kbyte 512Bytes 1Kbyte 4 x 25

ATmega169PA 16Kbyte 512Bytes 1Kbyte 4 x 25

ATmega329A 32Kbyte 1Kbyte 2Kbyte 4 x 25

ATmega329PA 32Kbyte 1Kbyte 2Kbyte 4 x 25

ATmega3290A 32Kbytes 1Kbyte 2Kbyte 4 x 40

ATmega3290PA 32Kbyte 1Kbyte 2Kbyte 4 x 40

ATmega649A 64Kbyte 2Kbyte 4Kbyte 4 x 25

ATmega649P 64Kbyte 2Kbyte 4Kbyte 4 x 25

ATmega6490A 64Kbyte 2Kbyte 4Kbyte 4 x 40

ATmega6490P 64Kbyte 2Kbyte 4Kbyte 4 x 40

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

2.3 Pin Descriptions

The following section describes the I/O-pin special functions.

2.3.1 VCC

Digital supply voltage.

2.3.2 GND

Ground.

2.3.3 Port A (PA7...PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page

74.

2.3.4 Port B (PB7...PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page

75.

2.3.5 Port C (PC7...PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of special features of the

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page

78.

2.3.6 Port D (PD7...PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

Port D also serves the functions of various special features of the

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page

79.

2.3.7 Port E (PE7...PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page

81.

2.3.8 Port F (PF7...PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the

JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will

be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

2.3.9 Port G (PG5...PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port G output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port G also serves the functions of various special features of the

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page

85.

2.3.10 Port H (PH7...PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port H output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3290PA/6490P as

listed on page 87.

2.3.11 Port J (PJ6...PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port J output buffers have symmetrical drive characteristics with both high sink and source capa-

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

bility. As inputs, Port J pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3290PA/6490P as

listed on page 90.

2.3.12 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characteristics” on page 353. Shorter pulses are not guaranteed to generate a reset.

2.3.13 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.3.14 XTAL2

Output from the inverting Oscillator amplifier.

2.3.15 AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-

nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC

through a low-pass filter.

2.3.16 AREF

This is the analog reference pin for the A/D Converter.

2.3.17 LCDCAP

An external capacitor (typical > 470nF) must be connected to the LCDCAP pin as shown in Fig-

ure 23-2, if the LCD module is enabled and configured to use internal power. This capacitor acts

as a reservoir for LCD power (VLCD). A large capacitance reduces ripple on VLCD but increases

the time until VLCD reaches its target value.

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

6. Capacitive touch sensing

The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive inter-

faces on most Atmel AVR® microcontrollers. The QTouch Library includes support for the

QTouch and QMatrix® acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library

for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch chan-

nels and sensors, and then calling the touch sensing API’s to retrieve the channel information

and determine the touch sensor states.

The QTouch Library is FREE and downloadable from the Atmel website at the following location:

www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the

Atmel QTouch Library User Guide - also available for download from the Atmel website.

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

7. Register Summary

Note: Registers with bold type only available in ATmega3290A/3290PA/6490A/6490P.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) LCDDR19 SEG339 SEG338 SEG337 SEG336 SEG335 SEG334 SEG333 SEG332 254

(0xFE) LCDDR18 SEG331 SEG330 SEG329 SEG328 SEG327 SEG326 SEG325 SEG324 254

(0xFD) LCDDR17 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 254

(0xFC) LCDDR16 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 254

(0xFB) LCDDR15 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 254

(0xFA) LCDDR14 SEG239 SEG238 SEG237 SEG236 SEG235 SEG234 SEG233 SEG232 254

(0xF9) LCDDR13 SEG231 SEG230 SEG229 SEG228 SEG227 SEG226 SEG225 SEG224 254

(0xF8) LCDDR12 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 254

(0xF7) LCDDR11 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 254

(0xF6) LCDDR10 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 254

(0xF5) LCDDR09 SEG139 SEG138 SEG137 SEG136 SEG135 SEG134 SEG133 SEG132 254

(0xF4) LCDDR08 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 254

(0xF3) LCDDR07 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 254

(0xF2) LCDDR06 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 254

(0xF1) LCDDR05 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 254

(0xF0) LCDDR04 SEG039 SEG038 SEG037 SEG036 SEG035 SEG034 SEG033 SEG032 254

(0xEF) LCDDR03 SEG031 SEG030 SEG029 SEG028 SEG027 SEG026 SEG025 SEG024 254

(0xEE) LCDDR02 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 254

(0xED) LCDDR01 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG009 SEG008 254

(0xEC) LCDDR00 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 254

(0xEB) Reserved --------

(0xEA) Reserved --------

(0xE9) Reserved --------

(0xE8) Reserved --------

(0xE7) LCDCCR LCDDC2 LCDDC1 LCDDC0 LCDMDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 252

(0xE6) LCDFRR - LCDPS2 LCDPS1 LCDPS0 - LCDCD2 LCDCD1 LCDCD0 250

(0xE5) LCDCRB LCDCS LCD2B LCDMUX1 LCDMUX0 LCDPM3 LCDPM2 LCDPM1 LCDPM0 249

(0xE4) LCDCRA LCDEN LCDAB - LCDIF LCDIE LCDBD LCDCCD LCDBL 248

(0xE3) Reserved --------

(0xE2) Reserved --------

(0xE1) Reserved --------

(0xE0) Reserved --------

(0xDF) Reserved --------

(0xDE) Reserved --------

(0xDD) PORTJ - PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 96

(0xDC) DDRJ - DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 96

(0xDB) PINJ - PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 96

(0xDA) PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 95

(0xD9) DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 96

(0xD8) PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 96

(0xD7) Reserved --------

(0xD6) Reserved --------

(0xD5) Reserved --------

(0xD4) Reserved --------

(0xD3) Reserved --------

(0xD2) Reserved --------

(0xD1) Reserved --------

(0xD0) Reserved --------

(0xCF) Reserved --------

(0xCE) Reserved --------

(0xCD) Reserved --------

(0xCC) Reserved --------

(0xCB) Reserved --------

(0xCA) Reserved --------

(0xC9) Reserved --------

(0xC8) Reserved --------

(0xC7) Reserved --------

(0xC6) UDR0 USART0 Data Register 199

(0xC5) UBRR0H USART0 Baud Rate Register High 203

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

(0xC4) UBRR0L USART0 Baud Rate Register Low 203

(0xC3) Reserved --------

(0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 201

(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 200

(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 199

(0xBF) Reserved --------

(0xBE) Reserved --------

(0xBD) Reserved --------

(0xBC) Reserved --------

(0xBB) Reserved --------

(0xBA) USIDR USI Data Register 212

(0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 212

(0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 213

(0xB7) Reserved --------

(0xB6) ASSR --- EXCLK AS2 TCN2UB OCR2UB TCR2UB 163

(0xB5) Reserved --------

(0xB4) Reserved --------

(0xB3) OCR2A Timer/Counter 2 Output Compare Register A 163

(0xB2) TCNT2 Timer/Counter2 163

(0xB1) Reserved --------

(0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 161

(0xAF) Reserved --------

(0xAE) Reserved --------

(0xAD) Reserved --------

(0xAC) Reserved --------

(0xAB) Reserved --------

(0xAA) Reserved --------

(0xA9) Reserved --------

(0xA8) Reserved --------

(0xA7) Reserved --------

(0xA6) Reserved --------

(0xA5) Reserved --------

(0xA4) Reserved --------

(0xA3) Reserved --------

(0xA2) Reserved --------

(0xA1) Reserved --------

(0xA0) Reserved --------

(0x9F) Reserved --------

(0x9E) Reserved --------

(0x9D) Reserved --------

(0x9C) Reserved --------

(0x9B) Reserved --------

(0x9A) Reserved --------

(0x99) Reserved --------

(0x98) Reserved --------

(0x97) Reserved --------

(0x96) Reserved --------

(0x95) Reserved --------

(0x94) Reserved --------

(0x93) Reserved --------

(0x92) Reserved --------

(0x91) Reserved --------

(0x90) Reserved --------

(0x8F) Reserved --------

(0x8E) Reserved --------

(0x8D) Reserved --------

(0x8C) Reserved --------

(0x8B) OCR1BH Timer/Counter1 Output Compare Register B High 137

(0x8A) OCR1BL Timer/Counter1 Output Compare Register B Low 137

(0x89) OCR1AH Timer/Counter1 Output Compare Register A High 137

(0x88) OCR1AL Timer/Counter1 Output Compare Register A Low 137

(0x87) ICR1H Timer/Counter1 Input Capture Register High 138

(0x86) ICR1L Timer/Counter1 Input Capture Register Low 138

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

(0x85) TCNT1H Timer/Counter1 High 137

(0x84) TCNT1L Timer/Counter1 Low 137

(0x83) Reserved --------

(0x82) TCCR1C FOC1A FOC1B ------136

(0x81) TCCR1B ICNC1 ICES1 - WGM13WGM12CS12CS11CS10 135

(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 --WGM11WGM10133

(0x7F) DIDR1 ------ AIN1D AIN0D 218

(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 236

(0x7D) Reserved --------

(0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 232

(0x7B) ADCSRB -ACME- - - ADTS2 ADTS1 ADTS0 217/235

(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 234

(0x79) ADCH ADC Data Register High 235

(0x78) ADCL ADC Data Register Low 235

(0x77) Reserved --------

(0x76) Reserved --------

(0x75) Reserved --------

(0x74) Reserved --------

(0x73) PCMSK3 - PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 65

(0x72) Reserved --------

(0x71) Reserved --------

(0x70) TIMSK2 ------ OCIE2A TOIE2 164

(0x6F) TIMSK1 --ICIE1-- OCIE1B OCIE1A TOIE1 138

(0x6E) TIMSK0 ------ OCIE0A TOIE0 145

(0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 65

(0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 65

(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 65

(0x6A) Reserved --------

(0x69) EICRA ------ISC01ISC0062

(0x68) Reserved --------

(0x67) Reserved --------

(0x66) OSCCAL Oscillator Calibration Register [CAL7...0] 38

(0x65) Reserved --------

(0x64) PRR --- PRLCD PRTIM1 PRSPI PSUSART0 PRADC 46

(0x63) Reserved --------

(0x62) Reserved --------

(0x61) CLKPR CLKPCE --- CLKPS3 CLKPS2 CLKPS1 CLKPS0 38

(0x60) WDTCR --- WDCE WDE WDP2 WDP1 WDP0 53

0x3F (0x5F) SREG I T H S V N Z C 14

0x3E (0x5E) SPH Stack Pointer High 16

0x3D (0x5D) SPL Stack Pointer Low 16

0x3C (0x5C) Reserved --------

0x3B (0x5B) Reserved --------

0x3A (0x5A) Reserved --------

0x39 (0x59) Reserved --------

0x38 (0x58) Reserved --------

0x37 (0x57) SPMCSR SPMIE RWWSB - RWWSRE BLBSET PGWRT PGERS SPMEN 307

0x36 (0x56) Reserved

0x35 (0x55) MCUCR JTD BODS BODSE PUD -- IVSEL IVCE 60/93/293

0x34 (0x54) MCUSR --- JTRF WDRF BORF EXTRF PORF 53

0x33 (0x53) SMCR ---- SM2 SM1 SM0 SE 45

0x32 (0x52) Reserved --------

0x31 (0x51) OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 260

0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 217

0x2F (0x4F) Reserved --------

0x2E (0x4E) SPDR SPI Data Register 175

0x2D (0x4D) SPSR SPIF WCOL ----- SPI2X 174

0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 173

0x2B (0x4B) GPIOR2 General Purpose I/O Register 28

0x2A (0x4A) GPIOR1 General Purpose I/O Register 29

0x29 (0x49) Reserved --------

0x28 (0x48) Reserved --------

0x27 (0x47) OCR0A Timer/Counter0 Output Compare A 145

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a complex microcontroller with more periph-

eral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the

Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

0x26 (0x46) TCNT0 Timer/Counter0 144

0x25 (0x45) Reserved --------

0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 142

0x23 (0x43) GTCCR TSM ----- PSR2 PSR10 146/165

0x22 (0x42) EEARH ----- EEPROM Address Register High 27

0x21 (0x41) EEARL EEPROM Address Register Low 27

0x20 (0x40) EEDR EEPROM Data Register 28

0x1F (0x3F) EECR ---- EERIE EEMWE EEWE EERE 28

0x1E (0x3E) GPIOR0 General Purpose I/O Register 29

0x1D (0x3D) EIMSK PCIE PCIE2 PCIE1 PCIE0 ---INT063

0x1C (0x3C) EIFR PCIF3 PCIF2 PCIF1 PCIF0 --- INTF0 64

0x1B (0x3B) Reserved --------

0x1A (0x3A) Reserved --------

0x19 (0x39) Reserved --------

0x18 (0x38) Reserved --------

0x17 (0x37) TIFR2 ------OCF2ATOV2165

0x16 (0x36) TIFR1 --ICF1--OCF1BOCF1ATOV1139

0x15 (0x35) TIFR0 ------OCF0ATOV0146

0x14 (0x34) PORTG --- PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 95

0x13 (0x33) DDRG --- DDG4 DDG3 DDG2 DDG1 DDG0 95

0x12 (0x32) PING -- PING5 PING4 PING3 PING2 PING1 PING0 95

0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 95

0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 95

0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 95

0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 94

0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 94

0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 95

0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 94

0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 94

0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 94

0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 94

0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 94

0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 94

0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 93

0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 93

0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 93

0x02 (0x22) P O RTA P O R TA7 P O RTA 6 P O RTA 5 P O RTA 4 P O R TA 3 P O R TA 2 P O R TA 1 P O R TA 0 9 3

0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 93

0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 93

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

8. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2

FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← kNone3

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← ZNone3

CALL k Direct Subroutine Call PC ← kNone4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

Mnemonics Operands Description Operation Flags #Clocks

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

9. Ordering Information

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC, see Figure 28-1 on page 351.

4. Tape & Reel

9.1 ATmega169A

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

16 1.8 - 5.5V

ATmega169A-AU

ATmega169A-AUR(4)

ATmega169A-MU

ATmega169A-MUR(4)

ATmega169A-MCH

ATmega169A-MCHR(4)

64A

64M1

64MC

Industrial

(-40°C to 85°C)

Package Type

64A 64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Fr ame Package (QFN/MLF)

64MC 64-lead (2-row Staggered), 7 x 7 x 1.0mm body, 4.0 x 4.0 mm Exposed Pad, Quad Flat No-Lead Package (QFN)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

9.2 ATmega169PA

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC, see Figure 28-1 on page 351.

4. Tape & Reel

5. See Appendix A - ATmega169PA specification at 105°C.

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

16 1.8 - 5.5V

ATmega169PA-AU

ATmega169PA-AUR(4)

ATmega169PA-MU

ATmega169PA-MUR(4)

ATmega169PA-MCH

ATmega169PA-MCHR(4)

64A

64M1

64MC

Industrial

(-40°C to 85°C)

ATmega169PA-AN

ATmega169PA-ANR(4)

ATmega169PA-MN

ATmega169PA-MNR(4)

64A

64M1

Extended

(-40°C to 105°C)(5)

Package Type

64A 64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Fr ame Package (QFN/MLF)

64MC 64-lead (2-row Staggered), 7 x 7 x 1.0mm body, 4.0 x 4.0mm Exposed Pad, Quad Flat No-Lead Package (QFN)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

9.3 ATmega329A

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC see Figure 28-2 on page 351.

4. Tape & Reel

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

20 1.8 - 5.5V

ATmega329A-AU

ATmega329A-AUR(4)

ATmega329A-MU

ATmega329A-MUR(4)

64A

64M1

Industrial

(-40°C to 85°C)

Package Type

64A 64-lead, 14 x 14 x 1.0mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC see Figure 28-2 on page 351.

4. Tape &Reel

9.4 ATmega329PA

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

20 1.8 - 5.5V

ATmega329PA-AU

ATmega329PA-AUR(4)

ATmega329PA-MU

ATmega329PA-MUR(4)

64A

64M1

Industrial

(-40°C to 85°C)

Package Type

64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC see Figure 28-2 on page 351.

4. Tape & Reel

9.5 ATmega3290A

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

20 1.8 - 5.5V ATmega3290A-AU

ATmega3290A-AUR(4)

100A

Industrial

(-40°C to 85°C)

Package Type

100A 100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC see Figure 28-2 on page 351.

4. Tape & Reel.

9.6 ATmega3290PA

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

20 1.8 - 5.5V ATmega3290PA-AU

ATmega3290PA-AUR(4)

100A

Industrial

(-40°C to 85°C)

Package Type

100A 100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

9.7 ATmega649A

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC see Figure 28-1 on page 351.

4. Tape & Reel

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

16 1.8 - 5.5V

ATmega649A-AU

ATmega649A-AUR(4)

ATmega649A-MU

ATmega649A-MUR(4)

64A

64M1

Industrial

(-40°C to 85°C)

Package Type

64A 64-lead, 14 x 14 x 1.0mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

9.8 ATmega649P

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC see Figure 28-1 on page 351.

4. Tape & Reel

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

16 1.8 - 5.5 V

ATmega649P-AU

ATmega649P-AUR(4)

ATmega649P-MU

ATmega649P-MUR(4)

64A

64M1

Industrial

(-40°C to 85°C)

Package Type

64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

9.9 ATmega6490A

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC see Figure 28-2 on page 351.

4. Tape & Reel

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

20 1.8 - 5.5V ATmega6490A-AU

ATmega6490A-AUR(4)

100A

Industrial

(-40°C to 85°C)

Package Type

100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

9.10 ATmega6490P

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. VCC see Figure 28-2 on page 351.

4. Tape & Reel

Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range

20 1.8 - 5.5V ATmega6490P-AU

ATmega6490P-AUR(4)

100A

Industrial

(-40°C to 85°C)

Package Type

100A 100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

10. Packaging Information

10.1 64A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) C

64A

2010-10-20

PIN 1 IDENTIFIER

0°~7°

PIN 1

A1 A2 A

E1 E

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes:

1.This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) C

64A

2010-10-20

PIN 1 IDENTIFIER

0°~7°

PIN 1

A1 A2 A

E1 E

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes:

1.This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

10.2 64M1

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

64M1

2010-10-19

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.80 0.90 1.00

A1 – 0.02 0.05

b 0.18 0.25 0.30

D2 5.20 5.40 5.60

8.90 9.00 9.10

E2 5.20 5.40 5.60

e 0.50 BSC

L 0.35 0.40 0.45

Notes:

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

2. Dimension and tolerance conform to ASMEY14.5M-1994.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Marked Pin# 1 ID

SEATING PLANE

0.08

K 1.25 1.40 1.55

Pin #1 Corner

Pin #1

Triangle

Pin #1

Chamfer

(C 0.30)

Option A

Option B

Pin #1

Notch

(0.20 R)

Option C

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

64M1

2010-10-19

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.80 0.90 1.00

A1 – 0.02 0.05

b 0.18 0.25 0.30

D2 5.20 5.40 5.60

8.90 9.00 9.10

E2 5.20 5.40 5.60

e 0.50 BSC

L 0.35 0.40 0.45

Notes:

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

2. Dimension and tolerance conform to ASMEY14.5M-1994.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Marked Pin# 1 ID

SEATING PLANE

0.08

K 1.25 1.40 1.55

Pin #1 Corner

Pin #1

Triangle

Pin #1

Chamfer

(C 0.30)

Option A

Option B

Pin #1

Notch

(0.20 R)

Option C

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

10.3 64MC

TITLE DRAWING NO.GPC REV.

Package Drawing Contact:

packagedrawings@atmel.com 64MCZXC A

64MC, 64QFN (2-Row Staggered),

7 x 7 x 1.00 mm Body, 4.0 x 4.0 mm Exposed Pad,

Quad Flat No Lead Package

10/3/07

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.80 0.90 1.00

A1 0.00 0.02 0.05

b 0.18 0.23 0.28

C 0.20 REF

D 6.90 7.00 7.10

D2 3.95 4.00 4.05

E 6.90 7.00 7.10

E2 3.95 4.00 4.05

eT – 0.65 –

eR – 0.65 –

K 0.20 – – (REF)

L 0.35 0.40 0.45

y 0.00 – 0.075

SIDE VIEW

TOP VIEW

BOTTOM VIEW

Note: 1. The terminal #1 ID is a Laser-marked Feature.

Pin 1 ID

EA1

eT/2

R0.20 0.40

B30

A34

B16

A18

B22

A25

K(0.1) REF

(0.18) REF

B15

A17

A26

B23

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

10.4 100A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) D

100A

2010-10-20

PIN 1 IDENTIFIER

0°~7°

PIN 1

A1 A2 A

eE1 E

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.17 – 0.27

C 0.09 – 0.20

L 0.45 – 0.75

e 0.50 TYP

Notes:

1. This package conforms to JEDEC reference MS-026, Variation AED.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.08 mm maximum.

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

11. Errata

11.1 ATmega169A

No known errata

11.2 ATmega169A/169PA Rev. A to F

Not sampled.

11.3 ATmega169PA Rev. G

No known errata.

11.4 ATmega329A/329PA rev. A

•Interrupts may be lost when writing the timer registers in the asynchronous timer

•Using BOD disable will make the chip reset

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the

asynchronous Timer/Counter register (TCNTx) is 0x00.

Problem Fix/ Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor

0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous

Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

2. Using BOD disable will make the chip reset

If the part enters sleep with the BOD turned off with the BOD disable option

enabled, a BOD reset will be generated at wakeup and the chip will reset.

Problem Fix/Workaround

Do not use BOD disable

11.5 ATmega329A/329PA rev. B

•Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the

asynchronous Timer/Counter register (TCNTx) is 0x00.

Problem Fix/ Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor

0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous

Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

11.6 ATmega329A/329PA rev. C

•Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the

asynchronous Timer/Counter register (TCNTx) is 0x00.

Problem Fix/ Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor

0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous

Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

11.7 ATmega3290A/3290PA rev. A

•Interrupts may be lost when writing the timer registers in the asynchronous timer

•Using BOD disable will make the chip reset

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the

asynchronous Timer/Counter register (TCNTx) is 0x00.

Problem Fix/ Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor

0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous

Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

2. Using BOD disable will make the chip reset

If the part enters sleep with the BOD turned off with the BOD disable option

enabled, a BOD reset will be generated at wakeup and the chip will reset.

Problem Fix/Workaround

Do not use BOD disable

11.8 ATmega3290A/3290PA rev. B

•Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the

asynchronous Timer/Counter register (TCNTx) is 0x00.

Problem Fix/ Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor

0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous

Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

11.9 ATmega3290A/3290PA rev. C

•Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the

asynchronous Timer/Counter register (TCNTx) is 0x00.

Problem Fix/ Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor

0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous

Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

11.10 ATmega649A/649P/ATmega6490A/6490P

No known errata.

8284DS–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

12. Datasheet Revision History

Please note that the referring page numbers in this section are referring to this document.The

referring revision in this section are referring to the document revision.

12.1 Rev. 8284D - 06/11

12.2 Rev. 8284C - 06/11

12.3 Rev. 8284B - 03/11

12.4 Rev. 8284A - 10/10

1. Removed “Preliminary” from the front page

2. Updated the Table 29-16 on page 354. VPOT falling / Min. is 0.05V, not 0.5V

1. Updated ”Signature Bytes” on page 313. A, P, and PA devices have different signature (0x002)

bytes.

2. Updated all ”DC Characteristics” on page 344.

1. Updated the datasheet according to the Atmel new Brand Style Guide.

2. Updated all ”Ordering Information” on page 19.

3. Updated ”Packaging Information” on page 29.

1. Initial revision

8284DS–AVR–6/11

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