Spartan-II: Detailed Functional Description - Xilinx, Inc.

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Preliminary Product Specification 1-800-255-7778 1

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Architectural Description

Spartan-II Array

The Spartan-II user-programmable gate array, shown in

Figure 1, is composed of five major configurab le elements:

• IOBs provide the interface between the package pins

and the internal logic

• CLBs provide the functional elements for constructing

most logic

• Dedicated block RAM mem orie s of 4096 bits each

• Clock DLLs for clock-distribution delay compensation

and clock doma in control

• Versatile multi-level interconnect structure

As can be seen in Figure 1, the CLBs for m the cen tral logic

structure with easy acce ss to all suppor t an d ro uting stru c-

tures. The IOBs are located around all the logic and mem-

ory elements for easy and quick routing of signals on and off

the chip.

Values stored in static memory cells control all the config-

urable logic elements and interconnect resources. These

values load into the memory cells on power-up, and can

reload if necessary to change the function of the device.

Each of these elements will be discussed in detail in the fol -

lowing sections.

Input/Output Block

The Spartan-II IOB, as seen in Figure 1, features inputs and

outputs that support a wide variety of I/O signaling stan-

dard s. These high-speed inputs and outputs are cap able of

supporting various state of the art memory and bus inter-

faces. Table 1 lists s eve ral of the stand ards which are sup-

ported along with the required reference, output and

ter m inat ion voltages needed to meet the standard.

The three IOB registers function either as edge-triggered

D-type flip-flops or as level- sensitive latches. Each IOB has

a clock signal (CLK) shared by the three registers and inde-

pendent Clock Enable (CE) signals for each regist er.

0Spartan-II 2.5V FPGA Family:

Functional Description

DS001-2 (v2.1) March 5, 2001 00Preliminary Product Speci fication

Figure 1: Sparta n-I I I npu t /O ut p ut Block (IOB)

Package Pin

Package

Package Pin

SR Q

Programmable

Bias &

ESD Network

CCO

I/O

I/O, V

REF

Internal

Reference

To Next I/O

To Other

External V

REF

Inputs

of Bank

Programmable

Input Buffer

Programmable

Output Buffer

Programmable

Delay

VCC

OCE

ICE

CLK

TCE

DS001_02_090600

TFF

OFF

IFF

Spartan - II 2.5V FP GA Family: Functional Description

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2 1-800-255-7778 Preliminary Product Specification

In addition to the CLK and CE control signals, the three reg-

isters share a Set/Reset (SR). Fo r each register, th is signal

can be independently configured as a synchronous Set, a

synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

A fe ature not shown in the block diagram, but controlled by

the software, i s polarity control. The input and output b uff ers

and all of the IOB control signals have independent polarity

controls.

Optional pull-up and pull-down resistors and an optional

weak-ke eper circuit are at tached t o each pad. Prior to c on-

figuration all outputs not in volved in configuration are forced

into their high-impedance state. The pull-down resistors and

the weak-k eeper circuits are inactiv e, b ut inputs may option-

ally be pulled up.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins will float.

Consequently, external pull-up or pull-down resistors must

be provided on pins required to be at a well-defined logic

le vel prior to confi guration.

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. Two

form s of over-voltage prote ction are provided, o ne that pe r-

mits 5V compliance, and one tha t does not. For 5V compli-

ance, a zener-like structure connected to ground turns on

when the output rises to approximately 6.5V. When 5V com-

pliance is not required, a conventional clamp d iode may be

connected to the output supply voltage, VCCO. The type of

over-voltage protection can be selected independently for

each pad.

All Spartan-II IOBs support IEEE 1149.1-compatible bound-

ary scan testing.

Input Path

A buff er In the Spartan-II IOB input path routes the input sig-

nal either directly to internal logic or through an optional

input flip-flop.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used , assures that the pad-to-pad hold time is zero.

Each input buff er can be configured to conform to any of the

low-voltage signaling standards supported. In some of

these standards the input buffer utilizes a user-supplied

threshold vol tag e, VREF

. The need to suppl y VREF imposes

constraints on whi c h sta ndards c an us ed i n close proxi mity

to each other. See I/O Banking, page 3.

There are optional pull-up and pull-down resistors at each

input for use after configuration.

Output Pa th

The out put p ath includes a 3-state output buffer that drives

the output signal onto the pad. The output signal can be

routed to the buff er directly from the internal logic or through

an option al IOB output flip-flop.

The 3-state control of the output can also be rou ted directly

from the internal logic or through a flip-flip t hat pro vides syn-

chrono us enable and disable.

Each output driver can be individually programmed for a

wide range of low-voltage s ig naling standa rd s. Each output

buffer can so urce up to 24 mA and si nk up to 48 mA. Drive

strength and slew rate controls minimize bus transients .

In most signaling standards, the output high voltage

depends on an externally supplied VCCO voltage. The need

to supply VCCO imposes constraints on which standards

can be used in close pro ximity to each other . See I/O Bank-

ing.

An optional weak-keeper circuit is connected to each out-

put. W hen sel ected, the c ircuit monitors the voltage on the

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way helps eliminate bus chatter.

Because the weak-keeper circuit uses the IOB input buffer

to monitor the input level, an appropriate VREF voltage must

be provided if the signaling standard requires one. The pro-

vision of this voltage must comply with the I/O banking

rules.

Table 1: Standar ds Supported by I/O (Typical Values)

I/O Standard

Input

Reference

Voltage

(VREF)

Output

Source

Voltage

(VCCO)

Board

Termination

Voltage

(VTT)

LVT TL (2-24 m A) N /A 3.3 N /A

LVCMOS2 N/A 2.5 N/A

PCI (3V/ 5 V,

33 MHz/66 MHz) N/A 3.3 N/A

GTL 0.8 N/A 1.2

GTL+ 1.0 N/A 1.5

HSTL Class I 0.75 1.5 0.75

HSTL Class III 0.9 1.5 1.5

HSTL Class IV 0.9 1.5 1.5

SSTL3 Class I

and II 1.5 3.3 1.5

SSTL2 Class I

and II 1.25 2.5 1.25

CTT 1.5 3.3 1.5

AGP-2X 1.32 3.3 N/A

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Preliminary Product Specification 1-800-255-7778 3

I/O Bank ing

Some of the I/O standards described above require VCCO

and/or VREF voltages. These voltages are externally con-

nected to device pins that serve groups of IOBs, called

banks. Consequently, restrictions exist about which I/O

standards can be comb ined within a given bank.

Eight I/O banks result from separating each edge of the

FPGA i nto two bank s (see Figure 2). Each ban k has multi-

ple VCCO pins which must be connected to the same volt-

age. Vol tage is determ ined by the output standards in use.

Within a bank, output standards may be mixed only if they

use the same VCCO. Compatible standards are shown in

Table 2. GTL and GTL+ appear under all vo ltages because

their open-drain outputs do not depend on VCCO.

Some input standards require a user-supplied threshold

voltage, VREF. In this case, certain user-I/O pins are auto-

matically configured as inputs for the VREF voltage. About

one in six of the I/O pins in the bank assume this role.

VREF pins within a bank are interconnected internally and

consequently only one VREF voltage can be used within

each bank. All VREF pins in the bank, however , must be con-

nected to the exter nal voltage sourc e for correc t operation.

In a bank, inputs requiring VREF can be mixed with those

that do not but only one VREF voltage may be used within a

bank. Input buffers that use VREF are not 5V tolerant.

LV TTL, LVCMO S2 , and PCI are 5V tolerant. The V CCO and

VREF pins fo r each bank appear in the device pinout tables.

Within a giv en package, the n umber of VREF and VCCO pi n s

can vary depending on the size of devi ce . In larger devices,

m o r e I/O p ins convert to VREF pins. Since these are always

a superset of the VREF pins used for smaller devices, it is

possi ble to design a PCB that per mits migration to a larger

device. Al l VREF pins for the largest device anticipated must

be connected to the VREF vo ltage, a nd not used for I/O.

Conf igurable Logic Block

The basic building block of the Spartan-II CLB is the logic

cell (LC). An LC includes a 4-input function generator , carry

logic, and storage element. Output from the function gener-

ator in each LC drives t he CLB output and the D input of the

flip-flop. Each Spar ta n-II CLB con tains four LCs, organized

in two similar slices; a single slice is shown in Figure 3.

In addition to the four basic LCs, the Spartan-II CLB con-

tains logic that combines function generators to provide

funct ions of five or six input s.

Look-Up Tables

Spartan-II function generators are implemented as 4-input

look-up tabl es (LUTs). In addition to operating as a function

generator, each LUT can provide a 16 x 1-bit synchronous

RAM. Furthermore, the two LUTs within a slice can be com-

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16 x 1-bit dual-port synchronous RA M.

The Spartan-II LUT can also provide a 16-bit shift register

that is ideal for capturing high-speed or burst-mode data.

This mode can also be used to store data in applications

such as Digital Signal Processing.

Storage Elements

Storage el ements in t he Spa rt an-II slice can be con figured

either as edge-triggered D-type flip-flops or as level-sensi-

tive latches. The D inputs can be driven either by function

generators within the slice or directly from slice inputs,

bypassing the function generators.

Figure 2: Spartan-II I/O Banks

Table 2: Com patible Output Standards

VCCO Compatible Standar ds

3.3V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AG P,

GTL, GTL+

2.5V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+

1.5 V HSTL I, H STL III, HS TL IV, G TL , G TL +

DS001_03_060100

Bank 0

GCLK3 GCLK2

GCLK1 GCLK0

Bank 1

Bank 5 Bank 4

Spartan-II

Device

Bank 7Bank 6

Bank 2Bank 3

Table 3: In de pendent Ba nks Available

Package VQ100

PQ208 CS144

TQ144 FG256

FG456

Independent Banks 1 4 8

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In addition to Clock and Clock Enable signals, each slice

has synchronous set and reset signals (SR and BY). SR

forces a storage element into the initialization state speci-

fied for it in the co nfiguration . BY forces it into the opposite

state. Alternatively, these signals may be configured to

operate asynchronously.

All control signals are independently invertible, and are

shared by t he two flip-flops within the slice.

Addition al Logic

The F5 multiplexer in each slice combines the function gen-

erator outputs. This combination provides either a function

generator that can implement any 5-input function, a 4:1

multiplexer, or selec ted functions of up to nine inputs.

Similarly, the F6 multiplexer combines the outputs of all four

function generators in the CLB by selecting one of the

F5-multiplexer outputs. This permits the implementation of

any 6-input function, an 8:1 multiplexer, or selected func-

tions of up to 19 inputs.

Figure 3: Spartan-II CLB Slice (two identical slices in each CLB)

Look-Up

Table D

Look-Up

Table D

SXQ

CLK

CIN

F5IN

COUT

Carry

and

Control

Logic

Carry

and

Control

Logic

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Preliminary Product Specification 1-800-255-7778 5

Each CLB has four direct feedthrough paths, one per LC.

These paths provide e xtr a data input lines or additional local

routing that does not consume logic resources.

Arithmetic Logic

Dedicated carry logic pro vides f ast arithmetic carry capabil-

ity for high-speed arithmetic functions. The Spar tan-II CLB

supports two separate carry chains, one per slice. The

height of the carr y chains is two b its per CLB.

The arithmetic logic includes an XOR gate that allows a

1-bit full adder to be implement ed wi thin an LC. In addition,

a dedicated AND gate improves the efficiency of multiplier

implementation.

The dedicated carry path can also be used to cascade func-

tion generators for implem enting wide logic functions.

BUFTs

Each Spar tan-II CLB contains two 3-state drive rs (BUFTs)

that can drive on-chip busses. See Dedicated Routing,

page 6. Each Spa rt an-II BU FT has an indep endent 3-state

control pin and an independent input pin.

Block RAM

Spartan-II FPGAs incorporate several large block RAM

memories. These complement the distributed RAM

Look-Up Tables (LUTs) that provid e shallow memo ry stru c-

tures implemented in CLBs.

Block RAM memory blocks are organized in columns. All

Spartan-II devices contain two such columns, one along

each vert ical e dge. These colum ns extend t he f ull height of

the chip. Each memory block is four CLBs high, and conse-

quently, a Spartan-II device eight CLBs high will contain two

memory blocks per colum n, and a total of four blocks.

Each block RAM cell, as illustrated in Figure 4, is a ful ly s yn -

chronous dual -p ort ed 4096-bit RAM with independ ent con-

trol signals for each por t. The data widths of the two ports

can be configured independently, providing built-in

bus-width conversion.

Table 5 shows the depth and width aspect ratios for the

bloc k RAM.

The Spartan-II block RAM also includes dedicated routing

to provide an efficient interface with both CLBs and other

bloc k RAMs.

Programmable Routing Matrix

It is the longest delay path that limits the speed of any

worst-case design. Consequently, the Spartan-II routing

architecture and its place-and-route software were defined

in a single optimization process. This joint optimization min-

imizes long-path delays, and consequently, yields the best

system perform ance.

The joint optimization also reduces design compilation

times because the architecture is software-friendly. Design

cycles are correspondingly reduced due to shorter design

iteration times.

Local Routing

The local routing resources, as shown in Figure 5, provide

the following three types of connections :

•Interconnections among the LUTs, flip-flops, and

General Routing Matr ix (GRM)

•Internal CLB feedback paths that provide high-speed

connections to LUTs within the same CLB, chaining

Table 4: Spar tan-II Block RAM Amounts

Spartan-II

Device # of Bl ocks Total Block RAM

Bits

XC2S15 4 16K

XC2S30 6 24K

XC2S50 8 32K

XC2S100 10 40K

XC2S150 12 48K

XC2S200 14 56K

Figure 4: Dual-Port Block RAM

Table 5: Block RAM Port Aspect Ratios

Width Depth ADDR Bus Data Bus

1 4096 ADDR<11:0> DATA<0>

2 2048 ADDR<10:0> DATA<1:0>

4 1024 ADDR<9:0> DATA<3:0>

8 512 ADDR<8:0> DATA<7:0>

16 256 ADDR<7:0> DATA<15:0>

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

WEA

ENA

RSTA

CLKA

ADD[#:0]

DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

DS001_05_060100

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them together with minimal routing delay

•Direct paths that provide high-speed connections

between horizontally adjacent CLBs, eliminating the

delay of the GRM

General Purpose Routing

Most Spar tan-II signals are routed on the general purpose

routing, and consequently, the majority of interconnect

resources are a ssociated with t his level of the routing hie r-

archy. The general routing resources are located in horizon-

tal and vertical routing channels associated with the rows

and columns CLBs. The general-purpose routing resources

are listed below.

•Adjacent to each CLB is a General Routing Matrix

(GRM). The GRM is the sw itch matrix through which

hor izontal and ver t ical routing resources connec t, and

is also the means by which the CLB gains access to

the general purpose routing.

•24 single-length lines route GRM signal s to adjacent

GR Ms in each of the four directions.

•96 buffered He x lines route GRM signals to other

GRMs six bloc ks away in each one of the four

directions. Organized in a staggered pattern, Hex li nes

may be driven only at their endpoints. Hex-line signal s

can be acces sed either at the endpoints or at the

midp oint (three blocks from the source). One third of

the Hex lines are bidirectional, while the remaining

ones are unidirectional.

•12 Longline s are buffered, bidirectiona l wires that

distr ibute signals across the device quickly an d

efficiently. Ver t ical Longlines spa n the full height of th e

device, and hor izontal ones span the full wid th of the

device.

I/O Routing

Spartan-II devices ha ve addi tional routing resources around

their periphery that form an interf ace between the CLB arra y

and the IOBs. This additional routing , called the VersaRing,

facilitates pin-swapping and pin-locking, such that logic

redesigns can adapt to existing PCB layouts. T ime-to-mar-

ket is reduced, since PCBs and other system components

can be manufactured while the logic design is still in

progress.

De dicated R o u ti n g

Some classes of signal require dedicated routing resources

to maximize performance. In the Spartan-II architecture,

dedicat ed routing resources are provided for two classes of

signal.

•Horizontal routing resources are provided f or on-chip

3-state busses. Four partition able bus lines are

provided per CLB row, permitting multiple busses

within a row, as shown in Figure 6.

•Two dedicated nets per CLB propagate carry signals

vertically to the adjacent CLB.

Figure 5: Spartan-II Local Routing

DS001_06_032300

CLB

GRM

Adjacent

GRM To Adjacent

GRM

Direct

Connection

To Adjacent

CLB

To Adjacent

GRM

To Adjacent

GRM

Direct Connection

To Adjacent

CLB

Figure 6: BUF T Connection s to Dedicated Horizontal Bus Lines

CLB CLB CLB CLB

3-State

Lines

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Preliminary Product Specification 1-800-255-7778 7

Global Routing

Global Routing resources distribute clocks and other sig-

nals with very hig h fanout throu ghout the device. Spart an-II

devices include two tiers of global routing resources

referred to as primary and secondary global routing

resources.

•The primary global routing resources are four

dedicated global nets with dedicated input pins that are

designed to distribute high-fanout clock signals with

minimal skew. Each glob al clock net can drive all CLB,

IOB, and block RAM clock pins. The primary global

nets may only be driven by global buffers. There are

four global buffers, one for each global net.

•The secondary global routing resources consist of 24

backbone lines, 12 across the top of the chip and 12

across bottom. From these lines, up to 12 unique

signals per column can be distributed via the 12

longlines in the column. These secondary resources

are more flexible than the prim ary resources since they

are not restricted to routing only to clock pins.

Clock Distribution

The Spar tan-II family provides high-speed, low-skew clock

distribution through the primary global routing resources

described above. A typical cloc k distrib ution net is shown in

Figure 7.

F our global buff ers are provided, two at the top center of the

device and two at the bottom center. These drive the four

primary global nets that in tur n drive any clock pin.

Four dedicated clock pads are provided, one adjacent to

each of the global buffers. The input to the global buffer is

selected either from t hese pads or from sig nals in the gen-

eral purpose routing.

Delay-Locked Loop (DLL)

Associated with each global clock input buff er is a fully digi-

tal Delay-Locked Loop (DLL) that can eliminate skew

between the clock input pad and internal clock-input pins

throughout the device. Each DLL can drive two global clock

networks . The DLL m onitors the input clo ck an d the di str ib-

uted clock, and automatically adjusts a clock dela y element.

Additional delay is introduced such that clock edges reach

internal flip-flops exactly one clock period after they arriv e at

the input. This closed-loop system effectively eliminates

clock-distribution delay by ensuring that clock edges arrive

at internal flip-flops in synchronism with clock edges arriving

at the input.

In addition to eliminating clock-distribution delay, the DLL

provides advanced control of multiple clock domains. The

DLL provides four quadrature phases of the source clock,

can double the clock, or d ivide the clock by 1.5, 2, 2.5, 3, 4,

5, 8, or 16. It has six outputs.

The DLL also operates as a clock mirror. By driving the out-

put from a DLL off-chip and then back on again, the DLL can

be used to desk ew a board le v el clock among multiple Spar-

tan-II devices.

In order to guarantee that the system clock is operating cor-

rectly prior to the FPGA star ting up after configuration, the

DLL c an de lay the completion of the configu ration process

until after it has achieved lock .

Boundary Scan

Spartan-II devices support all the mandatory bound-

ary-scan instructions specified in the IEEE standard 1149.1.

A Test Access Port (TAP) and registers are provided that

implement the EXTEST, SAMPLE/PRELOAD , and BYPASS

instructions. The TAP also supports two USERCODE

instructions and internal scan chains.

The TAP uses dedicated package pins that always ope rate

using L VTTL. For TDO to operate using L VTTL, the VCCO for

Bank 2 must be 3.3V. Otherwise, TDO switches rail-to-rail

between ground and V CCO.

Boundary-scan operation is independent of individual IOB

configurations, and unaffected by package type. All IOBs,

including unbonded ones, are treated as independent

3-state bidirectional pins in a single scan chain. Retention of

the b idirectional test capabi lity af ter configu ration facili tates

the testing of ex t er nal interconnec t ions.

Table 6 lists the boundary-scan instructions supported in

Spar tan-II FPGAs. Internal signals can be captured during

EXTEST by connecting them to unbonded or unused IOBs.

They may also be connected to the unused outputs of IOBs

defin ed as unidirectional input pins. This technique partia lly

compens ates for the abs ence of INTEST support.

Figure 7: Global Clock Distribution Network

Global Clock

Spine

Global Clock

Column

GCLKPAD2

GCLKBUF2

GCLKPAD3

GCLKBUF3

GCLKBUF1

GCLKPAD1 GCLKBUF0

GCLKPAD0

Global

Clock Rows

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The public boundary-scan instructions are availab le prior to

configuration. After configuration, the public instructions

remain av ailable t ogether with an y USERCODE instructions

installed during the configuration. While the SAMPLE and

BYPASS instructions are avai lab l e during configuration, it is

recommended that boundary-scan operations not be per-

formed during this transitional period.

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the

FP GA, and also to read back th e configu ration data.

To f acilitate internal scan chains, the User Register prov ides

three outputs (Reset, Upda te, and Shift) that represent the

corresponding states in the boundary-scan internal state

machine.

Figure 8 is a diagram of the Spartan-II f amily boundary scan

logic. It includes three bits of Data Register per IOB, the

IEEE 1149.1 Test Access Port controller , and the Instruction

Table 6: Boun dar y-Scan Instru ctions

Boundary-Scan

Command Binary

Code[4:0] Description

EXTEST 00000 Enables boundary-scan

EXTES T operation

SAMPLE 00001 Enables boundary-scan

SAMPLE operation

U SR1 0 0010 Ac ces s user-defined

U SR2 0 0011 Ac ces s user-defined

CFG_OUT 00100 Access the

configu ration bus for

Readback

CFG_IN 00101 Access the

configu ration bus for

Configuration

INTEST 00111 Enables boundary-scan

INTES T operation

USRCODE 01000 Ena bles shifting out

USER cod e

IDCODE 01001 Enables shifting out of

ID Code

HIZ 01010 Disables output pins

while enabling the

Bypass Register

JSTART 01100 Clock the start-up

sequen ce when

StartupClk is TCK

BYPASS 11111 Enables BYPASS

RESERVED All oth er

codes Xilinx reserved

instructions

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Preliminary Product Specification 1-800-255-7778 9

Bit Seque nce

The bit sequence within each IOB is: In, Out, 3-State. The

input-only pins contribute only the In bit to the boundary

scan I/O data register , while the output-only pins contributes

all three b its.

From a cavity-up view of the chip (as shown in the FPGA

Editor), start i ng in the upper right chip corner , the boundary

scan data-register bits are ordered as sho wn in Figure 9.

BSDL (Boundary Scan Description Language) files for

Spartan-II family devices are available on the Xilinx website,

in the File Download area.

Figure 8: Spartan-II Family Boundary Scan Logic

D Q

IOB

Bypass

IOB IOB

TDO

TDI

IOB IOB IOB

D Q

IOB

D Q

0DQ

IOB.T

DATA IN

IOB.I

IOB.Q

IOB.T

IOB.I

SHIFT/

CAPTURE CLOCK DATA

DATAOUT UPDATE EXTEST

DS001_09_032300

Instruction Register

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Development System

Spartan-II FPGAs are supported by the Xilinx Foundation

and Alliance CAE tools. The basic methodology for Spar-

tan-II design consists of three interrelated steps: design

entry, implementation, and verification. Industry-standard

tools are used f or design entry and simulation (f or example,

Synopsys FPGA Express), while Xilinx provides proprietary

architecture-specific tools fo r implemen tation.

The Xilinx development system is integrated under the

Xilinx Design M anager software, providing des igners with a

common user interface regardless of their choice of entry

and verification tools. The software simplifies the selection

of implementation options with pull-down m enus and on-line

help.

Application programs ranging from schematic capture to

Placement and Routi ng (PAR) can be accessed through the

software. The program command sequence is generated

prior to e xecution, and stored for documentation.

Several advanced software features facilitate Spartan-II

design. Relationally-Placed Macros (RPMs), for example,

are schematic-based macros with relative location con-

straints to g uide their placement . They help en sure optim al

implement ation of commo n functions.

F or HDL des ign entry, the Xilinx F PGA de v elopment system

provides interfaces to several synthesis design environ-

ments.

A standard interface-file specification, Electronic Design

Interchange Format (EDIF), simplifies file transf ers into and

out of the developmen t system .

Spartan-II FPGAs supported b y a unified library of standard

functions. This l ibrary contains over 400 primitives and m ac-

ros, r anging from 2-input AND gates to 16-bit accumulators,

and includes arithmetic functions, comparators, counters,

data registers, decoders, encoders, I/O functions, latches,

Boolean functions, multiplexers, shift registers, and barrel

shifters.

The "soft macro" portion of the library contains detailed

descriptions of common logic functions, but does not con-

tain any partitioning or placement information. The perfor-

mance of these macros depends, therefore, on the

partitioning and placement obtained during implementation.

RPMs, on the other hand, do contain predeter mined par ti-

tioning and placement information that permits optimal

implementation of these functions. Users can create their

own library of soft macros or RPMs based on the macros

and primitives in the standard library.

The design environment supports hierarchical design entry,

with high-level schematics that comprise major functional

blocks, while lower-level schematics define the logic in

these blocks. Thes e hie rarchical design ele men ts are auto-

matically combined by the implementation tools. Different

design entry tools can be combined within a hierarchical

design, thus allowing the most convenient entry method to

be used fo r each portion of the design.

Design Implementation

The place-and-route tools (PAR) automatically provide the

implementation flow described in this section. The parti-

tioner takes the EDIF netlist for the design and maps the

logic into the architectural resources of the FPGA (CLBs

and IOBs, for example). The placer then determines the

best locations for these blocks based on their interconnec-

tions and the desired perfor mance. Final ly, the router inter-

conn ects the blocks.

The PAR algorithms support fully automatic implementation

of most designs. For demanding applications, however, the

user can exercise various degrees of control over the pro-

cess. User p art itioning, placement , and rou ting inform ation

is optionally spec i fied duri ng t he design -e ntry pro cess. The

implementation of highly structured designs can benefit

greatly from basic floorplanning.

The implementation software incorpo rates Timing Wizard®

timing-driven placement and routing. Designers specify tim-

ing requirements along entire paths during design entry.

The timing path analysis routines in PAR then recognize

these user-specified requirements and accommodate them.

Timing requirements are entered on a schematic in a form

directly relating to the system requirements, such as the tar-

geted clock frequency, or the maximum allowable delay

between two regist ers. I n this way, the overall perform ance

of the syst em along entire signal path s is autom atically tai-

lored to user-generated specifications. Specific timing infor-

mation for individual nets is unnecessar y.

Design Verification

In addition to conv entional software sim ulation, FPGA users

can use in-circuit debugging techniques. Because Xilinx

devices are infinitely reprogrammable, designs ca n be veri-

Figure 9: Bo un da ry S c an B i t Se qu e nce

Bit 0 ( TDO end)

Bit 1

Bit 2

TDO.T

TDO.O

Top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom)

MODE.I

Bottom-edge IOBs (Left to Right)

Right-edge IOBs (Bottom to Top)

BSCANT.UPD

(TDI end)

DS001_10_032300

Spartan -II 2.5V FPGA Family: Functional Description

DS001-2 (v2.1) Marc h 5, 2001 www.xilinx.com Module 2 of 4

Preliminary Product Specification 1-800-255-7778 11

fied in real tim e without the need for extensive sets o f soft-

ware simulation vectors.

The de v elo pment syst em supports both so ftware simul ation

and in-circuit debugging techniques. For simulation, the

system extracts the post-layout timing informat ion from t he

design database, and back-annotates this information into

the netlist for use by the simulator. Alternatively, the user

can verify timing-critical portions of the design using the

static timing analyzer.

For in-circuit debugging, the development system includes

a download and readback cable, which connects the FPG A

in the target system to a PC or workstation. After download-

ing the design into the FPG A, the designer can single-step

the logic, readback the contents of the flip-flops, and so

observe the internal logic state. Simple modifications can

be down loaded into th e system in a matter of minutes.

Configuration

Configuration is the process by which the bitstream of a

design, as generated by the Xilinx development softw are, i s

loaded into the inter nal configura tion memory of the FPGA .

Spartan-II devices support both serial configuration, using

the master/slave serial and JTAG modes, as well as

byte -wide configuration employing the Slave Parallel mode.

Configuration File

Spartan-II devices are configured by sequentially loading

frames of data that have been conca ten ated into a configu-

ration file. Table 7 shows how much nonvolatile storage

space is needed for Spartan-II devices.

It is important to note that, while a PROM is commonly used

to store configuration data before loading them into the

FPGA, it is by no means required. Any of a number of diff er-

ent kinds of under populated nonvolatile storage already

availab l e either on or off the board (i.e. , hard driv es, FLASH

cards, etc.) can be used. For more information on configu-

ration without a PROM , refer to XAPP098, The L ow -Cost,

Efficient Serial Configuration of Spartan FPGAs.

Modes

Spartan-II devices support the following four configuration

modes:

•Slave Serial mode

•Master Serial mode

•Slave Paral lel mode

•Boundary-scan mode

The Configuration mode pins (M2, M1, M0) select among

these configuration modes with the option in each case of

having the IOB pins either pulled up or left floating prior to

configuration. The selection codes are listed in Table 8.

Configuration through the boundary-scan port is always

available, inde pendent of the mod e select ion. Se lecting t he

boundary-scan mode simply turns off the other modes. The

three mo de pi ns have internal pul l-up resi stors, and default

to a logic High if left unconnec ted.

Table 7: Sparta n-II Conf i gurat io n Fi le S ize

Device C onfiguration File Size (Bits)

XC2S15 197,696

XC2S30 336,768

XC2S50 559,200

XC2S100 781,216

XC2S150 1,040,096

XC2S200 1,335,840

Table 8: Co nf i gura tio n Mode s

Co nf ig urat io n Mode Preconfiguration

Pull-ups M0 M1 M2 CCLK

Direction Data Width S er ial DOUT

Master Serial mode No 0 0 0 Out 1 Yes

Yes 0 0 1

Slave Parallel mode Yes 0 1 0 In 8 No

No 0 1 1

Boundary-Scan mode Yes 1 0 0 N/A 1 No

No 1 0 1

Slave Serial mode Yes 1 1 0 In 1 Yes

No 1 1 1

Spartan - II 2.5V FP GA Family: Functional Description

Modu le 2 of 4 www.xilinx.com DS001-2 (v2 .1) March 5, 2001

12 1-800-255-7778 Preliminary Product Specification

Signals

There are two kinds of pins that are used to configure

Spartan-II devices: Dedicated pins perform only specific

configuration-related f unct ions; t he other pi ns can serve as

general purpose I/Os once user operation has begun.

The dedicated pins c omprise the mode pins (M2, M 1, M0),

the configuration clock pin (CCLK), the PROGRAM pin, th e

DONE pin and the boundary-scan pins (TDI, TDO, TMS,

TCK). Depending on the selected configuration mode,

CCLK ma y be an output generated by the FPGA, or may be

generated ex ternally, and provided to the FPGA as an input.

Note that some configuration pins can act as outputs. For

correct operation, these pins require a VCCO of 3.3V to driv e

an LV TT L signal. All the relevant pins fall in banks 2 or 3.

For a more d etailed description than that give n below, see

DS001-4, Spartan-II 2.5V FPGA Family: Pinout Tables

and XAPP176, Spartan-II FPGA Series Configuration

and Readback.

The Process

The sequence of steps necessary to configure Spartan-II

devices are shown in Figure 10. The overall flow can be

divided into three different phases.

•Initiating Configuration

•Configuration memor y clear

•Loading data frames

•Start-up

The memory clearing and start-up phases are the same for

all configuration modes; however, the steps for the loading

of data frames are different. Thus, the details f or data frame

loading are d escr ibed se parately in th e sec tions devoted to

each mode.

Init iating Conf igura ti on

There are two diff erent w ays to i nitiate the configuration pro-

cess: applying power to the device or asserting the PRO-

GRAM input.

Configuration on power-up occurs aut om atically unless i t is

delayed by the user, as described in a separate section

below. The waveform for configuration on power-up is

shown in Figure 11, page 13. Before configuration can

begin, VCCO Bank 2 must be greater than 1.0V. Further-

more, all VCCINT power pins must be connected to a 2.5V

supply. For more infor m ation on delaying configuration, see

Clearing Configuration Memory, page 13.

Once in user operation, the device can be re-configured

simply by pulling the PROGRAM pin Low. The device

ackno wledges the beginning of the configuration process by

driving DONE Low , then enters the memory-clearing phase. Figure 10: Configuration Flow Diagram

FPGA Drives

INIT Low

Abort Start-up

INIT

Low?

User Holding

PROGRAM

Low?

FPGA

Drives INIT

and DONE Low

Load

Configuration

Data Frames

User Operation

Configuration

at Power-up

DS001_11_090600

CRC

Correct?

Yes

FPGA

Samples

Mode Pins

Delay

Configuration

Delay

Configuration

Clear

Configuration

Memory

User Pulls

PROGRAM

Low

Start-up Sequence

FPGA Drives DONE High,

Activates I/Os,

Releases GSR net

Yes

Configuration During

User Operation

CCO

AND

CCINT

High?

Spartan -II 2.5V FPGA Family: Functional Description

DS001-2 (v2.1) Marc h 5, 2001 www.xilinx.com Module 2 of 4

Preliminary Product Specification 1-800-255-7778 13

Clearing Configuration Memory

The de vice indicates that clearing the configuration memory

is in progress by driving INIT Low. At this time, the user can

delay configuration by holding either PROGRAM or INIT

Low, which causes the device to remain in the memory

clearing phase. Note that the bidirectional INIT line is driv-

ing a Low logic le vel during memory clearing. Thus, to av oid

contention, use an open-drain dr iver to ke ep INIT Low.

With no delay in f orce, the de vice indicates that the memory

is completely clear by driving INIT High. The FPGA samples

its mode pins on this Low-to-High tra nsition.

Loading Configuration Data

Once INIT is High , the user can begin loading configuration

data frames into t he device. The de tails of lo ading t he con-

figuration data are discussed in the sections treating the

configuration modes individually. The sequence of opera-

tions necessary to load configuration data using the serial

modes is shown in Figure 13. Loading data using the Slave

Parallel mode is shown in Fig ure 18, page 18 .

CRC Error Checking

During the loading of configuration data, a CRC value

embedded in the configuration file is checked against a

CRC value calculated within the FPGA. If the CRC values

do n o t m atc h, the F PG A d r ives IN IT Low to indicate that a

frame error has occurred and configuration is abor t ed.

To reconfigure the device, the PROGRAM pin should be

asserted to reset the configuration logic. Recycling power

also resets the FPGA for configuration. See Clearing Con-

figuration Memory.

Start-up

The start-up sequence oversees the transition of the FP GA

from the configuration state to full user operation. A match

of CRC v alues, i ndicating a success ful l oading of the confi g-

uration data, initiates the sequence.

During star t -up, the device perfo rm s four operatio ns :

1. The assertion of DONE. The failure of DONE to go High

may indicate the unsuccessful loading of configuration

data.

2. The release of the Global Three State. This activ ates all

the I/Os.

3. Negate s Global Set Reset (GSR). This allows all

flip-flops to change state.

4. The assertion of Global Write Enabl e (GWE). This

allows all RAMs and flip-flops to change state.

Notes: referring to w aveform above:

1. Before configuration can begin, VCCINT must be gr eater than 1.6V and VCCO Bank 2 must be greater than 1.0V.

Figure 11: Con fig uration Ti min g on Power-Up

DS001_12_032300

POR

ICCK

Valid

CCLK Output or Input

M0, M1, M2

(Required)

PROGRAM

INIT

(1)

. Symbol Description Units

TPOR Power-on reset 2 ms, max

TPL Program latency 100 µs, max

TICCK CCLK output delay (Master Serial

mode only) 0.5 µs, min

4µs, max

TPROGRAM Program pulse width 300 ns, min

Spartan - II 2.5V FP GA Family: Functional Description

Modu le 2 of 4 www.xilinx.com DS001-2 (v2 .1) March 5, 2001

14 1-800-255-7778 Preliminary Product Specification

By default, these operations are synchronized to CCLK.

The entire start-up sequence lasts eight cycles, called

C0-C7, after whi ch the loaded design is fully functional. The

default timing for start-up is shown in the top half of

Figure 12. The f our operations can be selected to s witch on

any CCLK cycle C1-C6 through settings in the Xilinx

Development Software. Heavy lines show default settings.

The bottom half of Figure 12 shows another commonly

used version of the start-up timing known as

Sync-to-DONE. This version makes the GTS, GSR, and

GWE events conditional upon the DONE pin going High.

This timing is import ant fo r a da isy chain of multipl e FPGAs

in serial mode, since it ensures that all FPGAs go through

start-up together, after all their DONE pins hav e gone High.

Sync-to-DONE timing is selected by setting the GTS, GS R,

and GWE cycles to a value of DONE in the configuration

options. This causes these signals to transition one clock

cycle after DONE exter n ally transitions High.

Serial Modes

There are two ser ial configuration modes: In Master Serial

mode, the FPGA controls the configuration process by driv-

ing CCLK as an output. In Slave Serial mode, the FPGA

passiv ely receiv es CCLK as an input from an e xternal agent

(e.g., a microprocessor, CPLD, or second FPGA in master

mode) that is controlling the con figuration process. In both

modes, the FPGA is configured by loading one bit per CCLK

cycle. The MSB of each configuration data byte is always

writte n to the DIN pin first.

See Figure 13 for the sequence for loading data into the

Spartan-II FPGA serially. Th is is an expansio n of the "Lo ad

Configuration Data Fram es" blo ck in Figure 10, page 12.

Slave Serial Mode

In Slave Serial mode, the FPGAs CCLK pin is d riven by an

external source, allowing FPGAs to be configured from

other logic devices such as microprocessors or in a

daisy -cha in configuration. Figure 14 shows connections for

a Master Serial FPGA configuring a Slave Serial FPGA

from a PROM. A Spartan-II device in slave serial mode

shou ld be connecte d as shown for the thi rd device from the

left. S lave Serial mod e is selecte d by a <11x> on th e mo de

pins (M0, M1, M2).

Figure 15 shows the timing for Slave Serial configuration.

The serial bitstream must be setup at the DIN input pin a

short time before each rising edge of an externally gener-

ated CCLK. Multiple FPGAs in Slave Serial mode can be

daisy-chained for configuration from a single source. After

an FPGA is configured, data for the next device is routed to

the DOUT pin. Data on the DOUT pin changes on the rising

edge of CCLK. Configuration must be delayed until INIT

pins of all daisy-chained FPGAs are High. For more infor-

mation, see Start-up, page 13.

Figure 12: Start-Up Waveforms

Start-up CLK

Default Cycles

Sync to DONE

01234567

DONE High

234567

Phase

Start-up CLK

Phase

DONE

GTS

GSR

GWE

DS001_13_090600

DONE

GTS

GSR

GWE Figure 13: Loa d in g S e ri al M ode Co nfi gura tio n D at a

Yes

End of

Configuration

Data File?

After INIT

Goes High

User Load One

Configuration

Bit on Next

CCLK Rising Edge

To CRC Check

DS001_14_032300

Spartan -II 2.5V FPGA Family: Functional Description

DS001-2 (v2.1) Marc h 5, 2001 www.xilinx.com Module 2 of 4

Preliminary Product Specification 1-800-255-7778 15

Notes:

1. If t he DriveDone configuration option is not act ive for any of the FPGAs , pull up DONE with a 3.3K Ω resistor.

Figure 14: Master/Slave Serial Configuration Circuit Diagram

Figure 15: S l ave Serial Mod e Timing

Spartan-II

(Master Serial)

17S00A

PROM

PROGRAM

M0 M1

DOUT

CCLK CLK

3.3V

DATA

CE CEO

RESET/OE

DIN

INIT

DONE

PROGRAM

3.3 K

DS001_15_022601

GND GND

Vcc

3.3V

Vcco

Vccint

2.5V3.3V 3.3V 2.5V

Spartan-II

(Slave)

DONE INIT

PROGRAM

CCLK

DIN DOUT

M0 M1

GND

Vcco

Vccint

TCCH

TCCO

TCCL

TCCD

TDCC

DIN

CCLK

DOUT

(Output)

DS001_16_032300

.Symbol Description Units

TDCC

CCLK

DIN setup 5 ns, min

TCCD D IN hold 0 ns, min

TCCO D OUT 12 ns, max

TCCH High time 5 ns, min

TCCL L ow tim e 5 n s, mi n

FCC Maximum frequenc y 66 M Hz, max

Spartan - II 2.5V FP GA Family: Functional Description

Modu le 2 of 4 www.xilinx.com DS001-2 (v2 .1) March 5, 2001

16 1-800-255-7778 Preliminary Product Specification

Mas t er Seri al M o de

In Master Serial mode, the CCLK output of the FPGA drives

a Xilinx P ROM wh ich feeds a serial s tream of c onf igu ration

data to the FPGA’s DIN input. Figure 14 shows a Master

Serial FPGA configuring a Slave Serial FPGA from a

PROM. A Spartan-II device in Master Serial mode should

be connected as shown f or the de vice on the left side . Mas-

ter Serial mode is selected by a <00x> on the mode pins

(M 0 , M1, M2). T he PROM R ESET pin is d r iven by INIT, and

CE input is driven by DONE. The interface is identi cal to the

slave serial mode except that an oscillator internal to the

FPGA is used to generate the configuration clock (CCLK).

Any of a number of different frequencies ranging from 4 to

60 MHz can be set using the ConfigRate option in the Xilinx

de velopment software. On power-up, while the first 60 byt es

of the configuration data are being loaded, the CCLK fre-

quenc y i s always 2.5 M Hz. This frequency is used until the

ConfigRate bits, part of the configuration file, have been

loaded into the FPGA, at which point, the frequency

chan ges to the selected ConfigRa te. Unless a different fre-

quenc y i s specified in the design, the de fault ConfigRate is

4 MHz . The period o f the CCLK signal created by the inter-

na l o s c illator ha s a var ian c e o f +45%, –30% fr om the spec -

ified value.

Figure 16 sh ows the timing for Master Serial configu ration.

The FPGA accepts one bit of configuration data on each ris-

ing CCLK e dge. Af ter the FPGA h as been loaded, the data

for the next device in a daisy-chain is presented on the

DOUT pin after the rising CCLK edge.

Sla ve Parallel Mode

The Slave Parallel mode is the fast est configura tio n optio n.

Byte-wide data is written into the FPGA. A BUSY flag is pro-

vided for controlling the flow of data at a clock frequency

FCCNH above 50 MHz.

Figure 17, page 17 shows the connections for two

Spartan-II devices using the Slave Parallel mode. Slave

P arallel mode is selected by a <011> on the mode pins (M0,

M1 , M2).

The agent controlling configuration is not sho wn. Typically, a

processor, a microcontroller, or CPLD controls the Slave

Parallel interface. The controllin g a gent provides byte-wide

configuration data, CCLK, a Chip Select (CS) signal and a

Write signal (WRITE). If BUSY is asserted (High) by the

FP GA , the data must be held until BUS Y goe s Low.

After configuration, the pins of the Slave Parallel port

(D0-D7) can be used as additional user I/O. Alternatively,

the port may be retained to permit high-speed 8-bit read-

back. Then data can b e read by de-ass er ting WRIT E. See

Readback, page 18.

Figure 16: M aster S eri al Mod e Timing

Serial Data In

CCLK

(Output)

Serial DOUT

(Output)

TDSCK

TCKDS

DS001_17_032300

Symbol Description Units

TDSCK

CCLK

DIN setup 5.0 ns, m in

TCKDS DIN hold 0.0 ns, min

Frequ ency tolerance with respect to

nominal + 45%, –30% -

Spartan -II 2.5V FPGA Family: Functional Description

DS001-2 (v2.1) Marc h 5, 2001 www.xilinx.com Module 2 of 4

Preliminary Product Specification 1-800-255-7778 17

Multiple Spartan-II FPGAs can be configured using the

Slave Parallel mode, and be made to start-up simulta-

neously. To configure multiple devices in this way, wire the

individual CCLK, Data, WRITE, and BUSY pins of all the

devices in parallel. The indi vidual devices are loaded sepa-

rately by asserting the CS pin of each device in turn and

writing the appropr iate data. Syn c-to-DONE star t-up timing

is used to ensure that the start-up sequence does not begin

until all the FPGAs have been loaded. See Start-up,

page 13.

Write

When using the Slave Parallel Mode, write operations send

packets of byte-wide configuration data into the FPGA.

F i gur e 18 , pag e 18 shows a flo wchart of the write sequence

used to load data into the Spartan-II FPGA. This is an

ex pansion of the "Load Configuration Data Fr ames" block in

Figure 10, page 12. The timing f or wri te operations is shown

in Fig ure 19 , page 19 .

For the present example, the user holds WRITE and CS

Low throughout the sequence of write operations. Note that

when CS is asserted on successive CCLKs, WRITE must

remain either asse rt ed or de-ass er ted. Ot herwise an ab ort

will be initiated, as in the next section.

1. Dr ive data on to D0-D7. Note th at to avoid contention ,

the data source should not be enabled while CS is Low

and WRITE is High. Similarly, while WRITE is High, no

mo re than on e device’s CS should be asse rted.

2. On the rising edge of CCLK: If BUSY is Low , the data is

accepted on this clock. If BUSY is High (from a previous

write), the data is not accepted. Acceptance will instead

occur on the first clock after BUSY goes Low, and the

data must be held until this happens.

3. Re peat steps 2 and 3 until all the data has been sent.

4. De-assert CS and WRITE.

Figure 17: S lave Pa ral lel Configuration Circu it Diagram

M1 M2

D0:D7

CCLK

WRITE

BUSY

PROGRAM

DONE INIT

CCLK

DATA[7:0]

WRITE

BUSY

CS(0)

Spartan-II

DONE

INIT

PROGRAM

M1 M2

D0:D7

CCLK

WRITE

BUSY

PROGRAM

DONE INIT

CS(1)

Spartan-II

DS001_18_032300

2.5V 2.5V

GND GND

Spartan - II 2.5V FP GA Family: Functional Description

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18 1-800-255-7778 Preliminary Product Specification

If CCLK is slower than F CCNH, the FPGA will never asser t

BUSY. In this case, the above handshake is unnecessary,

and data can simply be entered into the FPGA every CCLK

cycle.

A configuration packet does not have to be written in one

continuous stretch, rather it can be split into many write

sequences. Each seque nce would involve asser t ion of CS.

In applications where multip le cloc k cycles may be required

to access the configuration data before each byte can be

loaded i nto the Slave Para llel interface, a new byte of data

ma y not be ready for each consecutiv e CCLK edge . In such

a case the CS signal ma y be de-assert ed until the ne xt byte

is valid on D0-D7. While CS is High, the Slav e P arallel inter-

face does not expect any data an d ignores all CCLK transi-

tions. However, to avoid aborting configuration, WRITE

must continue to be asserted while CS is asserted.

Abort

To abort configuration during a write sequence, de-assert

WRITE while holding CS Low. The abort operation is initi-

ated at the rising edge of CCLK, as shown in Figure 20,

page 19. The device will remain BUSY until the aborted

operation is complete. After aborting configuration, data is

assumed to be unaligned to w ord boundaries and the FPGA

requires a new synchroni zation word pr io r to accepting any

new packet s.

Boundary-Scan Mode

In the boundary-scan mode, no nondedicated pins are

required, configuration being done entirely through the

IEEE 1149. 1 Test Acces s Port .

Configuration through the TAP uses the special CFG_IN

instruction. This instruction allows data input on TDI to be

converted into data packets for the internal configuration

bus.

The following steps are required to configure the FPGA

through the boundary-scan port.

1. Load the CFG_I N instr uc tion into the b oundary- scan

instruction register (IR)

2. Enter the Shift-DR (SD R) state

3. Shift a standard configuration bitstream into TDI

4. Retur n to Run-Test-Idle (RTI)

5. Lo ad the JSTART instr uc tion into IR

6. Enter the SDR state

7. Clock TCK through the sequence (the length is

programmable)

8. Retu rn to RTI

Configuration and readback via the TAP is alwa ys availab le.

The boundary-scan mode simply loc ks out the other modes.

The boundary-scan mode is selected by a <10x> on the

mode pin s (M0, M1, M2).

Readback

The configurati on data stored in the Spartan-II configuration

memory can be readback for verification. Along with the

configu ration data it is possible to readback the contents of

all flip-flops/latches, LUT RAMs, and block RAMs. This

capability is used for real-time debugging.

For more detailed information see XAPP176, Spartan-II

FP GA Family Configuration and Readback.

F igure 18: Load ing Conf igura tion Data for the Slave

Parallel Mode

Yes

FPGA

Driving BUSY

High?

After INIT

Goes High

Load One

Configuration

Byte on Next

CCLK Rising Edge

To CRC Check

DS001_19_032300

End of

Configuration

Data File?

Yes

User Drives

WRITE and CS

Low

User Drives

WRITE and CS

High

Spartan -II 2.5V FPGA Family: Functional Description

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Preliminary Product Specification 1-800-255-7778 19

Figure 19: Slave Parallel Write Timing

Figure 20: Slave Parallel Write Abort Waveforms

DS001_20_061200

CCLK

No Write Write No Write Write

DATA[7:0]

WRITE

TSMDCC TSMCCD

TSMCKBY

TSMCCCS

TSMWCC

TSMCCW

TSMCSCC

BUSY

Symbol Description Units

TSMDCC

CCLK

D0-D7 setup/hold 5 ns, min

TSMCCD D0-D7 hold 0 ns, min

TSMCSCC CS se tup 7 ns, min

TSMCCCS CS hold 0 ns, min

TSMCCW WRITE setup 7 ns, min

TSMWCC WRITE hold 0 ns, min

TSMCKBY BUSY propagation dela y 12 ns, max

FCC Maximum frequenc y 66 MHz, max

FCCNH Maximum frequenc y with no handshake 50 M Hz, max

DS001_21_032300

CCLK

WRITE

Abort

DATA[7:0]

BUSY

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20 1-800-255-7778 Preliminary Product Specification

Design Considerations

This section contains more detailed design information on

the foll owi ng features:

•Delay-Locked Loop . . . see page 20

•Block RAM . . . see page 24

•Versatile I/O . . . see page 29

Using Delay-Locked Loops

The S part an-II FPGA family provides up t o four fully digital

dedicated on-chip Delay-Locked Loop (DLL) circuits which

provide zero propagation delay, low clock skew between

output clock signals distributed throughou t the device, and

advanced clock domain control. These dedicated DLLs can

be used to implement several circuits which improve and

simplify system level design.

Introduction

As FPGAs grow in size, quality on-chip clock distribution

becomes increasingly important. Clock skew and clock

delay impac t device perfor m anc e and the task of managing

clock skew and clock delay with conventional clock trees

becomes more difficult in large devices. The Spartan-II f am-

ily of devices resolve this potential problem by providing up

to four fully digital dedicated on-chip Delay-Locked Loop

(DLL) circuits which provide zero propagation dela y and lo w

clock skew between output clock signals distributed

throughout the device.

Each DLL can drive up to two globa l clock routing networ ks

within the device. The global clock distribution network min-

imizes clock skews due t o loading d ifferences. By monitor-

ing a sample of the DLL output clock, the DLL can

compensate for the delay on the routing network, eff ectively

eliminating the dela y from the external input port to the indi-

vidual clock loads within the dev ice.

In addition to providing zero delay with respect to a user

source clock, the DLL can provide multiple phases of the

source cl ock. The DLL can al so ac t as a c lock doubler or i t

can divide the user source clock by up to 16.

Clock multiplication gives the designer a number of design

alternatives. For instance, a 50 MHz source clock doubled

by the DLL can drive an FPGA design operating at

100 MHz. This technique can simplify board design

because the clock path on the board no longer distributes

such a high-speed signal. A multiplied clock also provides

designers the option of time-domain-multiplex ing, using one

circuit twice per cl ock cycle, consuming less area than two

copies of the same circuit. Two DLLs in can be connected in

series to increase the effective clock multiplication fa ctor to

four.

The DLL can also act a s a clock mirror. By dr iving the DLL

output off-chip and then back in again, the DLL can be used

to de-skew a board level clock between multiple devices.

In order to guarantee the system clock establishes prior to

the de vice "waking up ," the DLL can dela y the completion of

the device configuration process until after the DLL

achieves lock.

By taking advantage of the DLL to remove on-chip clock

delay, the designer can greatly simplify and improve sys tem

le vel design inv olving high-f anout, high-perf ormance clocks .

Library DLL Symbols

Figure 21 shows the simplified Xilinx library DLL macro

symbol, BUFGDLL. This macro delivers a quick and effi-

cient way to provide a system clock with zero propagation

delay throughout th e device. Figure 22 and Figure 23 show

the two library DLL primitives. These symbols provide

access to the complete set of DLL features when imple-

menting m ore compl ex appl ications.

Figure 21: Simplified DLL Macro Symbol BUFGDLL

Figure 22: Standard DLL Symbol CLKDLL

Figure 23: High-Frequen cy DLL Symbol CLKDLLHF

0 ns

DS001_22_032300

CLK0

CLK90

CLK180

CLK270

CLKIN

DS001_23_032300

CLKDLL

RST

CLKFB

CLK2X

CLKDV

LOCKED

CLK0

CLK180

CLKDV

LOCKED

CLKIN

DS001_24_032300

CLKDLLHF

RST

CLKFB

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Preliminary Product Specification 1-800-255-7778 21

BUFGDLL Pin Descriptions

Use the BUFGDLL macro as the simplest way to provide

zero propagation d elay for a high-fanout on-chip c lock from

an ex ternal input. This macro uses the IBUF G, CLKDLL and

BUFG primi ti ves to im plement the most basic DL L applica-

tion as shown in Figure 24.

This symbol does not provide access to the advanced cloc k

domain controls or to the clock multiplication or clock divi-

sion features of the DLL. This symbol also does not provide

access to the RST, or LOCKED pins of the DLL. F or acc ess

to these features, a designer must use the library DLL prim-

itives des cribed in the following sections.

Source Clock Input — I

The I pin provides the user source clock, the clock signal on

which the DLL operates, to the BUFGDLL. For the BUF-

GDLL macro the source clock frequency must f al l in the low

frequency range as specified in the data sheet. The BUF-

GDLL requires an external signal source clock. Therefore,

only an ext ernal input por t can source the signal tha t drives

the BUFGDLL I pin.

Clock Output — O

The clock output pin O represents a delay-compensated

vers ion of the source clock (I) signal. This signal, sourced by

a global clock buffer BU F G sym bol, t akes advantage of t he

dedicated global clock routing resources of the device.

The output clock has a 50/50 duty cycle unless yo u deac ti-

vate the duty cycle correction property.

CL KDLL Primi tive Pin Descrip tion s

The library CLKDLL primitives provide access to the com-

plete set of DLL features needed whe n impl ementing more

complex applications with the DLL.

Source Clock Input — CLKIN

The CLKIN pin provides the user source clock (the clock

signal on which the DLL operates) to the DLL. The CLKIN

frequency must f al l in the ranges specified in t he data sheet.

A global clock buffer (BUFG) driven from another CLKDLL

or one of the global cloc k input buff ers (IBUFG) must source

this clock signal.

Feedbac k Clock Input — CLKFB

The DLL requires a referen ce or feedback si gnal to provide

the delay-compensated output. Connect only the CLK0 or

CLK2X DLL outputs to the feedback clock input (CLKFB)

pin to provide the necessary feedback to the DLL. The feed-

back cloc k input can also be prov ided through one of the fol-

lowing pin.

IBUFG - Global Clock Input Pad

If an IBUFG sources the CLKFB pin, the following special

r ules apply.

1. An external input port must source the signal that drives

the IBUFG I pin.

2. The CLK2X output must feed back to the device if both

the CLK0 and CLK 2X outputs are dr iving off chip

devices.

3. That signal must directly drive only OBUFs and nothing

else.

These rules enable the software determine which DLL clock

outpu t sources the CLKFB pin.

Reset Input — RST

When the reset pin RST activat es the LOCKED signal deac-

tivates w ith in four source clock cycles. The RST pin, active

High, must either connect to a dynamic signal or tied to

ground. As the DLL delay taps reset to zero, glitches can

occur on the DLL clock output pins. Activation of the RST

pin can a lso seve rely affect the duty cycle of the clock out-

put pins. Furthermore, the DLL output clocks no longer

deskew with respect to one another. For these reasons,

rarely use the reset p in unless re-conf iguring th e device or

changing the input frequency.

2x Clock Output — CLK2X

The output pin CLK2X provides a frequency-doubled clock

with an automatic 50/50 duty-cycle correction. Until the

CLKDLL has achiev ed lock, the CLK2X output appears as a

1x version of the input clock with a 25/75 duty cycle. This

behavior allows the DLL to lock on the correct edge with

respect to source clock. This pin is not available on the

CLKDL LHF primitive.

Clock Divide Output — CLKDV

The clock divide output pin CLKDV provides a lower fre-

quency version of the source clock. The CLKDV_DIVIDE

property controls CLKDV such that the source clock is

divided by N whe re N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 1 6.

This feature provides automatic duty cycle correction such

that the CLKDV output pin always has a 50/50 duty cycle.

1x Clock Outputs — CLK[0|90|180|270]

The 1x clock output pin CLK0 represents a delay-compen-

sated version of the source clock (CLKIN) signal. The

Figure 24: BUFGDLL Schematic

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

DS001_25_032300

CLKDLL BUFG

IBUFG O

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22 1-800-255-7778 Preliminary Product Specification

CLKDLL pr imitive provides three phase-shifted versions of

the CLK0 signal while CLKDLLHF provides only the 180

phase-shifted version. The relationship between phase shift

and the corresponding period shift appears in Table 9.

The timing diagrams in Figure 25 illustrate the DLL clock

output characteristics.

The DLL provides duty cycle correction on all 1x clock out-

puts such that all 1x clock outputs by default have a 50/50

duty cycle. The DUTY_CYCLE_CORRECTION property

(TRU E by default), controls this feature. In order to deacti-

vate the DLL duty cycle correction, attach the

DUTY_CYCLE_CORRECTION=FALSE property to the

DLL symbol. When duty cycle correction deactivates, the

output clock has the sam e duty cycle as the source clock.

The DLL clock outputs can drive an OBUF, a BUFG, or the y

can route directly to destination clock pins. The DLL clock

outputs can only dr ive the BUFGs that resi de on t he same

edge (top or bottom).

Lock ed Output — LOCKED

In order to achieve lock, the DLL may need to sample sev-

eral thousand clock cycles. A fter the DLL a ch ieves lock the

LOCKED signal activates. The DLL timing parameter sec-

tion of the data sheet provides estimates for locking times.

In order to guarantee that the system clock is established

prior to the dev ice "waking up," the DLL can delay the com-

pletion of the device configuration process until after the

DLL loc ks. The STARTUP_W AIT property activ ates this f ea-

ture.

Until the LOCKED signal activates, the DLL output clocks

are not valid and can exhi bit glitches, spikes, or other spuri-

ous movement. In pa rticular the CLK2X output will appear

as a 1x clock with a 25/7 5 duty cycle.

DLL Propertie s

Proper ties provide access to some of the Spartan-II family

DLL features, (for example, clock division and duty cycle

correction).

Duty Cycle Correction P roperty

The 1x cloc k outputs, CLK0, CLK90, CLK180, and CLK270,

use the duty-cycle corrected default, exhibiting a 50/50 duty

cycle. The DUTY_CYCLE_CORRECTION property (by

default TRUE) controls this feature. To deactivate the DLL

duty-cycle correction for the 1x clock outputs, attach the

DUTY_CYCLE_CORRECTION=FALSE property to the

DLL symbol. When duty-cycle correction deactivates, the

output clock has the same duty cycle as the source clock.

Clock Di vi d e Prop er ty

The CLKDV_DIVIDE property specifies how the signal on

the CLKDV pin is frequency divided with respect to the

CLK0 pin. The values allowed for this property are 1.5, 2,

2.5, 3, 4, 5, 8, or 16; the default v alue is 2.

Startup Delay Property

This property, STARTUP_WAIT, takes on a value of TRUE

or FALSE (the default value). When TRUE the device con-

figuration DONE signal waits until the DLL locks before

going to High.

DLL Location Cons traints

The DLLs are distributed such that t here is one DLL i n each

cor ner of the device. The locat ion constraint LOC, attached

to the DLL symbol with the numeric identifier 0, 1, 2, or 3,

controls DLL location. The ori entation of th e four DLLs a nd

their corresponding clock resources appears in Figure 26.

Table 9: Relationship of Phase-Shifted Output Clock to

Pe ri od Shift

Phase (degrees) Period Shift (per cent)

00%

90 25%

180 50%

270 75%

F igure 25: D LL Outpu t Characteristi cs

DS001_26_032300

CLKIN

CLK2X

CLK0

CLK90

CLK180

CLK270

CLKDV

CLKDV_DIVIDE = 2

DUTY_CYCLE_CORRECTION = FALSE

CLK0

CLK90

CLK180

CLK270

DUTY_CYCLE_CORRECTION = TRUE

0 90 180 270 0 90 180 270

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Preliminary Product Specification 1-800-255-7778 23

The LOC property uses the fol l owi ng f orm.

LOC = DLL2

Desi gn Factors

Use the fol l owi ng design considerations to a void pitf al l s and

improve success designing with Xilinx devices.

Input Clock

The outpu t clock signal of a DLL, essen tially a delayed ver-

sion of the input clock signal, reflects any instability on the

input clock in the output waveform. For this reason the qual-

ity of the DLL input clock relates directly to the quality of the

output clock waveforms generated by the DLL. The DLL

input clock requ irements are spec ified in the data sheet.

In most systems a crystal oscillator generates the system

clock. The DLL can be used with any commercially available

quartz crystal oscillator. For example, most crystal oscilla-

tors produce an output wa veform with a frequency tolerance

of 100 PPM, meaning 0.01 percent change in the clock

period. The DLL operates reliably on an input wavef orm with

a frequency drift of up to 1 ns — orders of magnitude in

ex cess of that needed to support any crystal oscillator in the

industry. However, the cycle-to-cycle jitter must be kept to

less than 300 ps in the low frequencies and 150 ps for the

high frequencies.

Input Clock Changes

Changing the period of t he input clock be yond t he maximum

drift amount requires a manual reset of the CLKDLL. Failure

to reset the DLL will produce an unreliable lock signal and

output cloc k.

It is po ssible to sto p t he inpu t clock with little impact to the

DLL. Stopping the clock should be limited to less than

100 µs to keep device cooling to a minimum. The clock

should be s topped during a Low phas e, and when restored

the full High period should be seen. During this time

LOCK ED will stay High and remain Hig h when the clo ck is

restored.

W hen the clock is sto pped, one to four more clocks will still

be obs erved as the delay line is f lushed. When the c lock is

restar ted, the output clocks will not be observed for one to

four clocks as the delay line is filled. The most common

case will be two or three clocks.

In a similar m anner, a phase shift of t he input c lock is also

possibl e. The phase shift will propagate to the output one to

four clocks after the original shift, with no di sr uption to the

CLKDLL control.

Output Clock s

As mentioned earlier in the DLL pin descriptions, some

restrictions apply regarding the connectivity of the output

pins. The DLL clock outputs can drive an OBUF, a global

clock buffer BUFG, or they can route directly to destinati on

clock pins. The only BUFGs that the DLL clock outputs can

driv e are the two on t he same edge of the dev ice (top or bot-

tom).

Do not use the DLL output clock signals until after activat ion

of the LOCKED signal. Prior to the activation of the

LOCKED signal, the DLL output clocks are not valid and

can exhibit glitches, spikes, or other spurious movement.

Useful Application Examples

The Spartan-II DLL can be used in a variety of creative and

useful applications. The following examples show some of

the more common applications.

Stan da rd U sag e

The circuit shown in Figure 27 resembles the BUFGDLL

macro implemented to provide access to the RST and

LOCKED pins of the CLKDLL.

Deske w of Cloc k and Its 2x Multiple

The circuit shown in Figure 28 implements a 2x clock multi-

plier and also uses the CLK0 cloc k output with zero ns skew

between registers on the same chip. A clock divider circuit

Figure 26: Orie nt at i on of DLLs

DS001_27_032300

GCLKPAD1

DLL1

GCLKBUF1

GCLKPAD0

DLL0

GCLKBUF0

GCLKPAD2

DLL2

GCLKBUF2

GCLKPAD3

DLL3

GCLKBUF3

F igure 27: Stan dard DLL Implementation

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

DS001_28_061200

CLKDLL BUFG

IBUFG

OBUF

IBUF

Spartan - II 2.5V FP GA Family: Functional Description

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24 1-800-255-7778 Preliminary Product Specification

could alternatively be implemented using similar connec-

tions.

Because any single DLL can only access at most two

BUFGs, any addi tio nal output clock sign als must be routed

from the DLL in this example on the high speed backbone

routing.

Generating a 4x Clock

By connecting two DLL circuits each implementing a 2x

clock multiplier in series as shown in Figure 29, a 4x clock

multiply can be implemented with zero ns skew between

registers in the same device.

If other clock output is needed, the clock could access a

BUFG on ly if th e DLLs are cons trained to exist on opposi te

edges (Top or Bo ttom) of the device.

When using this circuit it is vital to use the SRL16 cell to

reset the second DLL after the initial chip reset. If this is not

done, the second DLL may not recognize the change of fre-

quencies from when the input changes from a 1x (25/75)

waveform to a 2x (50/50) wav eform.

Using Block RAM Features

The Spartan-II FPGA family provides dedicated blocks of

on-chip, true dual-read/write port synchronous RAM, with

4096 memory cells. Each port of the block RAM memory

can be independently configured as a read/write port, a

read port, a write por t, and can be configured to a specific

dat a widt h. Th e block RAM m em or y o ffe rs new ca pa bilities

allowing the FPGA designer to simplify designs.

Operating Mo des

Block RAM memory su pports two operating modes.

•Read Through

•Writ e Back

Read Through (One Clock Edge)

The read address is registered on t he read port clock edge

and data appears on the output after the RAM access time.

Some memories may place the latch/register at the outputs

depending on the desire to hav e a fast er clock-to-out versus

setup time. This is generally considered to be an inferior

solution since it changes the read operation to an asynchro-

nous function with the possibility of missing an address/con-

trol line transition during the generation of the read pulse

clock.

W ri te Back (On e C lock Edg e)

The write address is registered on the write port clock edge

and the data input is written to the memory and mirrored on

the write port input.

Block RAM Characteristics

1. All inputs are registered with the por t clock and have a

setup to clock timin g speci fication.

2. All outputs have a read through or write back function

depending on the state of the port WE pin. The outputs

relative to the port clock are available after the

clock-to-out timing specification.

3. The block RAM are true SRAM mem ories and do not

have a c om binatorial path from the address to the

output. The LUT cells in the CLBs are still available with

this function.

4. The ports are completely independent from each other

(i.e., clocking, control, address, read/write function, and

data width) without arbitration.

F igure 28: DLL Deskew of Clock and 2x Multiple

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

DS001_29_061200

CLKDLL BUFG

IBUFG

OBUF

BUFG

IBUF

Figure 29: DLL Generation of 4x Clock

DS001_30_061200

RST

CLKFB

CLKIN

CLKDLL

LOCKED

CLKDV INV

BUFG

OBUF

SRL16

WCLK

BUFG

IBUFG

CLK2X

CLK0

CLK90

CLK180

CLK270

RST

CLKFB

CLKIN

CLKDLL

LOCKED

CLKDV

CLK2X

CLK0

CLK90

CLK180

CLK270

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Preliminary Product Specification 1-800-255-7778 25

5. A write operation requires only one clock edge.

6. A read operat ion requires only one clock e dge.

The output port s are latched with a self timed circuit to guar-

antee a glitch free read. The state of the output port will not

change u ntil the port executes anot her read or wri te opera-

tion.

Library Primitives

Figure 30 an d Figure 31 show th e two generi c library block

RAM primitives. Table 10 describes all of the a vailabl e prim-

itives for synthesis and simulation.

Figure 30: Du al-Po r t Block RAM Memory

Figure 31: Single-Port Block RAM Memory

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

WEA

ENA

RSTA

CLKA

ADDRA[#:0]

DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

DS001_31_061200

DS001_32_061200

DO[#:0]

RST

CLK

ADDR[#:0]

DI[#:0]

RAMB4_S#

Table 10: Available Library Primitives

Primitive Po rt A Width Port B Width

RAMB4_S1

RAMB4_S1_S1

RAMB4_S1_S2

RAMB4_S1_S4

RAMB4_S1_S8

RAMB4_S1_S16

1N/A

RAMB4_S2

RAMB4_S2_S2

RAMB4_S2_S4

RAMB4_S2_S8

RAMB4_S2_S16

2N/A

RAMB4_S4

RAMB4_S4_S4

RAMB4_S4_S8

RAMB4_S4_S16

4N/A

RAMB4_S8

RAMB4_S8_S8

RAMB4_S8_S16

8N/A

RAMB4_S16

RAMB4_S16_S16 16 N/A

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26 1-800-255-7778 Preliminary Product Specification

Port Signals

Each block RAM por t ope rates indepen dently of the others

while accessing the same set of 4096 memory cells.

Table 11 describes the depth and width aspect ratios for the

block RAM memory.

Clock—CLK[A|B]

Each port is fully synchrono us with independent clock pins.

All port input pins have setup time referenced to the port

CLK pin . The data out put bus has a c lo ck-to-out time refer-

enced to the CLK pin.

Enable—EN[A|B]

The enable pin affects the read, write and reset functionality

of the port. P ort s with an inactiv e enable pin keep the output

pins in the previous state and do not write data to the mem-

ory cells.

Write Enable—WE[A|B]

Activ ating the write enable pin all ows t he port to write to the

memory cells. When active, the contents of the data input

bu s are written to the RAM at the address pointed to by the

address bus, and the new data also reflects on the data out

bus. When inactive, a read operation occurs and the con-

tents of the memory cells referenced by the address bus

reflect on the data out bus.

Reset—RST[A|B]

The reset pin forc es the data output bus latches to zero syn-

chronously. This does not affect the memory cells of the

RAM and does not disturb a write operation on the other

port.

Address Bus—ADDR[A|B]<#:0>

The address b us selects the memory cells for read or write.

The width of the port deter mines the required width of this

bu s as shown in Table 11.

Data In Bus —DI[A|B]<#:0>

The data in bus provides the new data value to be written

into the RAM. This bus and the port have the same width, as

shown in Table 11.

Data Output Bus—DO[A|B]<#:0>

The d ata out bus refl ects the con ten ts of the memory cells

referenced by the address bus at the last activ e clock edge.

During a wr ite operation, the dat a out bus reflects the data

in bus. The width of this bus equals the width of the port.

The allowed widths appear in Table 11.

Inverting Control Pins

The four control pins (CLK, EN, WE and RST) for each port

have independent inversion control as a configuration

option.

Address Mapping

Each port accesses the same set of 4096 memory cells

using an addressing scheme dependent on the width of the

por t. The physical RAM location addressed for a par ticular

width are described in the following formula (of interest only

when the two port s use different aspect ratios).

Star t = ([ADDRpor t + 1] * Width port) – 1

End = ADDRport * W idth port

Table 12 shows low order address mapping for each port

width.

Creating Larger RAM Structures

The block RAM columns have specialized routing to allow

cascading bl ock s together with minimal routing delays. This

achieves wider or deeper RAM structures with a smaller

timing pena lty than when using nor m al routing cha nnels.

Location Cons tr aint s

Block RAM instanc es can have LOC properties a ttached to

them to constrain the placement. The b lock RAM placement

locations are separate from the CLB location naming con-

vention, a llowing the LOC proper ties to transfer easily from

arra y to array.

Table 11: Block RA M Por t Asp ect Ratios

Width Dep th ADDR Bus Data Bus

1 4096 ADDR<11:0> DATA<0>

2 2048 ADDR<10:0> DATA<1:0>

4 1024 ADDR<9:0> DATA<3:0>

8 512 ADDR<8:0> DATA<7:0>

16 256 ADDR<7:0> DATA<15:0>

Table 12: Port Address Map ping

Port

Widt

hPort

Addresses

1 4095... 1

2 2047... 07 06 05 04 03 02 01 00

4 1023... 03 02 01 00

8 511... 01 00

16 255... 00

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Preliminary Product Specification 1-800-255-7778 27

The LOC properties use the f ollo wing form:

LOC = RAMB 4_R#C#

RAMB4_R0C0 is the upper left RAMB4 location on the

device.

Conflict Resolution

The block RAM me mory is a true dual-read/write po rt RA M

that allows simultaneous access of the same memory cell

from both por ts. When one port writes to a given memory

cell, the other port must not address that memory cell (for a

write or a read) within th e clock-to-clock setu p window. The

f ollowing lists specifics of port and memory cell write conflict

resolution.

•If both ports write to the same memory cell

simultaneously, violating the clock-to-clock setup

requirement, consider the data stored as invalid.

•If o ne port attem pts a read of the same memory c ell

the other simultaneously writes, violating the

clock-to-clock setup requirement, the fo llowing occurs.

- The write succeeds

- The data out on the wr iting por t ac curately reflects

the data written.

- The data out on the reading port is invalid.

Conflicts do not cause any phys ical damage.

Single Port Timing

Figure 32 shows a timing diagram for a single port of a bloc k

RAM mem or y. The block RAM AC switching characteristics

are specified in the data sheet. The block RAM memory is

initially disabled.

At the first rising edge of the CLK pin, the ADDR, DI, EN,

WE, and RST pins are sampled. The EN pin is High and the

WE pin is Low indicating a read operation. The DO bus con-

tains the contents of the memory location, 0x00, as indi-

cated by the ADDR bu s.

At the second rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN and WE pins

are High indicating a write operation. The DO bus mirrors

the DI bus. The DI bus is written to the memory location

0x0F.

At the third rising edge of the CLK pin, the ADDR, DI, EN,

W R, and RST pins are samp led again. The E N pin is Hi gh

and the WE pin is Low indicating a read ope ration. The DO

bus contains the contents of the memor y location 0x7E as

indicated by the A DDR bus.

At the f ourth rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN pin is Low

indicating that the block RAM memory is now disabled. The

DO bus retains the last value.

Dual P ort Timing

Figure 33 shows a timing diagram for a true dual-port

read/write block RAM memory. The clock on port A has a

longer peri od than the c lock on Por t B. The timing parame-

ter TBCCS, (clock-to-clock setup) is shown on this diagram.

The parameter, TBCCS is violated once in the diagram. All

other timi ng p arameters are iden tical t o the single po rt ver-

sion shown in Figure 32.

TBCCS is only of importance when the address of both ports

are the same and at least one port is performing a write

operation . When the clock-to-clock set-up parameter is vio-

lated for a WRITE-WRITE condition, the contents of the

memory at that location will be invalid. When the

clock-to-clock set-up parameter is violated for a

WRITE-READ condition, the contents of the memory will be

correct, but the read por t will have invalid data. At the first

rising edge of the CLKA, memory location 0x00 is to be writ-

ten with the v alue 0xAAAA and is mirrored on the DOA b us.

The last operation of P ort B was a read to the same memory

location 0x00. The DOB bus of Port B does not change with

the new value on Por t A, and re tains the last read value. A

short time later, Port B executes another read to memory

location 0x00, and the DOB bus no w reflects the new mem-

ory value written by Port A.

At th e second r ising edge of CLK A, memor y l ocatio n 0x7E

is written with the v al ue 0x9999 and is mirrored on the DO A

bus. Port B then executes a read operation to the same

memory location without violating the TBCCS parameter and

the DOB reflects the new mem ory valu es written by Port A.

Spartan - II 2.5V FP GA Family: Functional Description

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28 1-800-255-7778 Preliminary Product Specification

Figure 32: Timin g Diagr am for Singl e-Port Block RAM Memory

Figure 33: Timing Diagram for a Tr ue Dual-Por t Read /Write Block RAM Memory

DS001_33_061200

CLK

TBPWH

TBACK

ADDR 00

DDDD

MEM (00) CCCC MEM (7E)

CCCC

7E 8F

BBBB 2222

DIN

DOUT

RST

DISABLED READ WRITE READ DISABLED

TBDCK

TBECK

TBWCK

TBCKO

TBPWL

DS001_34_061200

CLK_A

PORT APORT B

ADDR_A

00 7E 0F

00 00 7E 7E 1A0F 0F

0F 7E

AAAA 9999 AAAA 0000 1111

2222

AAAA 9999 AAAA UNKNOWN

EN_A

WE_A

DI_A

DO_A

1111 1111 1111 2222 FFFFBBBB 1111

AAAAMEM (00) 9999 2222 FFFFBBBB UNKNOWN

CLK_B

ADDR_B

EN_B

WE_B

DI_B

DO_B

TBCCS

VIOLATION

TBCCS TBCCS

Spartan -II 2.5V FPGA Family: Functional Description

DS001-2 (v2.1) Marc h 5, 2001 www.xilinx.com Module 2 of 4

Preliminary Product Specification 1-800-255-7778 29

At the third rising edge of CLKA, the TBCCS parameter is

violated with two writes to mem or y location 0 x0 F. The DOA

and DOB busses reflect the contents of the DIA and DIB

busses, but the s t ored value at 0x7E is invalid.

At the four th rising edge of CLKA, a read operation is per-

formed at memory location 0x0F and inv alid data is present

on the DOA bus. Port B also executes a read operation to

memory location 0x0F and also reads inval id data.

At the fifth rising edge of CLKA a read operation is per-

formed that does not violate the TBCCS parameter to the

previous write of 0x7 E by Port B. THe DOA bus reflects the

recently written value by Po rt B.

Initialization

The bloc k RAM memory can initializ e during the dev ice con-

figuration sequence. The 16 initialization properties of 64

hex values each (a total of 4096 bits) set the initialization of

each RAM. These properties appear in Table 13. Any initial-

ization pro pert ies not explicitly set conf igure as zeros. Pa r-

tial initialization strings pad with zeros. Initialization strings

greater than 64 hex values generate an error. The RAMs

can be simulated with the initialization values using gener-

ics in VHDL simulators and parameters in Verilog simula-

tors.

Initialization in VHDL and Synopsys

The block RAM structures may be initialized in VHDL for

both simulation and synth es is for inc lusion in the E DI F out-

put file. The simulation of the V HDL code us es a generic to

pass the initialization. Synopsys FPGA compiler does not

presently support generics. The initialization values instead

attach as attributes to the RAM by a built-in Synopsys

dc_script. The translate_off statement stops synthesis

translation of the generic statements. The following code

illu strates a module tha t employs these techni ques.

Initialization in Verilog and Synopsys

The block RAM structures may be initialized in Verilog for

both simulation and synth es is for inc lusion in the E DI F out-

put file. The simulation of the Verilog code uses a defparam

to pass the initialization. The Synopsys FPGA compiler

does not presentl y supp ort defparam. The initialization val-

ues instead attach as attributes to the RAM by a built-in

Synopsys dc_script. The translate_off statement stops syn-

thesis translation of the defparam statements. The following

code illu strates a modu le that employs these techniq ues.

Block Memory Generation

The CoreGen program ge nerates mem ory st ruct ures us ing

the bl ock RAM feat ures. This program outputs VHDL or Ver-

ilog simulation code templates and an EDIF file for inclusion

in a d esign.

Using Versatile I/O

The S part an-II FPGA family includes a highl y configurable,

high-performance I/O resource called Versatile I/O to pro-

vide support for a wide variety of I/O standa rds. The Versa-

tile I/O resource is a robust set of features including

programmable control of output drive strength, slew rate,

and input dela y and hold time. Taking advantage of the flex-

ibility and Versatile I/O features and the design consider-

ation s descr ibed in this docume nt can improve and simplify

system level design.

Introduction

As F P GA s c ontinue to grow in s ize and capacity, the l arger

and more complex systems designed for them demand an

incre ased variety of I/O standards. Furthermo re, as system

clock speeds continue to increase, the need f or hi gh-perf or-

mance I/O becomes more important. While chip-to-chip

delays have an increasingly substantial impact on overall

system speed, the task of achie ving the desi red syst em per-

formance becomes more difficult with the proliferation of

low-voltage I/O standards. Versatile I/O, the revolutionary

input/output resources of Spartan-II devices, has resolved

this potential problem by providing a highly configurable,

high-performance alternative to the I/O resources of more

conventional programm able devices. T he Spar tan-II Versa-

tile I/O features combine the flexibility and time-to-market

advantages of programmable logic with the high perfor-

Table 13: RAM Initi a lizat io n Pr o perties

Property Memory Cells

INIT_00 255 to 0

INIT_01 511 to 256

INIT_02 767 to 512

INIT_03 1023 to 768

INIT_04 1279 to 1024

INIT_05 1535 to 1280

INIT_06 1791 to 1536

INIT_07 2047 to 1792

INIT_08 2303 to 2048

INIT_09 2559 to 2304

INIT_0a 2815 to 2560

INIT_0b 3071 to 2816

INIT_0c 3327 to 3072

INIT_0d 3583 to 3328

INIT_0e 3839 to 3584

INIT_0f 4095 to 3840

Spartan - II 2.5V FP GA Family: Functional Description

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30 1-800-255-7778 Preliminary Product Specification

mance previously available only with ASICs and custom

ICs.

Each Versatile I/O bloc k can support up to 16 I/O standards.

Suppor ting such a variety of I/O standards allows the sup-

port of a wide variety of application s, from gene ral purpose

standard applications to high-speed low-voltage memory

busses.

Versatile I/O blocks also provide selectable output drive

strengths and programmable slew rates for the LVTTL out-

put buffers, as well as an optional, programmable weak

pull-up, weak pull-down, or weak "keeper" circuit ideal for

use in external bussing applications.

Each Input/Output Block (IOB) includes three registers, one

each for the input, output, and 3-state signals within the

IOB. These registers are optionally configurable as either a

D-type flip-flop or as a level sensitive latch.

The input buffer has an optional delay element used to guar-

antee a zero hold time req uirement for input signals regis-

tered within the IOB.

The Versatile I/O features also provide dedicated resources

f or input r ef erence v oltage (VREF) and output source voltage

(VCCO), along with a conv enient banking system that simpli-

fies board design.

By taking adva ntage of the built-in f eatures and wide variety

of I/O standards supported by the Versatile I/O features,

system-lev el design and board design can be greatly simpli-

fied and improved.

Fundamentals

Modern bus applications, pi oneered by t he largest and most

influential companies in the digital electronics industr y, are

commonl y introduc ed with a new I/O standard tailored spe-

cifically to the needs of that application. The bus I/O stan-

dards provide specifications to other vendors who create

products designed to interface with these applications.

Each standard often h as its own specifications for current,

voltage, I/O buffering, and ter mination techniques.

The ability to provide the flexibility and time-to-market

advantages of programmable logic is increasingly depen-

dent on the capability of the programmable log ic device to

support an eve r increasing variety of I/O standards

The V ersatile I/O resources feature highly configurable input

and output buffers which provide suppor t for a wide variety

of I/O standards. As shown in Table 14, each b uff er type can

support a variety of voltage requirem ents.

Overview of Supported I/O Standards

This section provides a brief overview of the I/O standards

supp orted by all Spar tan-I I devices.

While most I/O standards specify a range of allowed volt-

ages, this document records typical voltage values only.

Detailed inf o rmation on each specification ma y be found on

the Electronic Industry Alliance Jedec website at

http://www.jedec.org

LV TTL — Low-Voltage TTL

The Low-Voltage TTL (LVTTL) standard is a general pur-

pose EIA/JES DS A standard for 3.3V a pplication s that uses

an LVTTL input buffer and a Push-Pull output buffer. This

standard requi res a 3.3V out put source voltage (VCCO), bu t

does not require the use of a referen ce voltage (V REF) or a

ter m ination voltage (VTT).

LVCMOS2 — L ow -Vo l tage C M OS for 2. 5V

The Low-Voltage CMOS f or 2.5V or lo wer (LVCMOS2) stan-

dard is an extension of the LVCMOS standard (JESD 8.5)

used for general purpose 2.5V applications. This standard

requires a 2.5V outp ut source voltage (VCCO), but does not

require the use of a reference voltage (VREF) or a board ter-

mination vol tage (VTT).

Table 14: Versatile I/O Suppo r ted Standards (Typical

Values)

I/O Standard

Input

Reference

Voltag e

(VREF)

Out put

Source

Voltage

(VCCO)

Board

Termination

Voltage

(VTT)

LVTTL (2-24 mA) N/A 3.3 N/A

LVCMOS2 N/A 2.5 N/A

PCI (3V/5 V,

33 MHz/66 M Hz) N/A 3.3 N/A

GTL 0.8 N/A 1.2

GTL+ 1.0 N/A 1.5

HSTL Class I 0.75 1.5 0.75

HSTL Class III 0.9 1.5 1.5

HSTL Class IV 0.9 1.5 1. 5

SSTL3 Class I

and II 1.5 3.3 1.5

SSTL2 Class I

and II 1.25 2.5 1.25

CTT 1.5 3.3 1.5

AGP-2X 1.32 3.3 N/A

Spartan -II 2.5V FPGA Family: Functional Description

DS001-2 (v2.1) Marc h 5, 2001 www.xilinx.com Module 2 of 4

Preliminary Product Specification 1-800-255-7778 31

PCI — Peripheral Component Int erface

The Peripheral Component Interface (PCI) standard speci-

fies suppo rt for b oth 33 M Hz an d 66 M Hz PC I bus applica-

tions. It uses a LVTTL input buffer and a push-pull output

buff er. This standard does not require the use of a ref erence

voltage (VREF) or a board termination voltage (VTT), how-

ever, it does require a 3.3V output source voltage (VCCO).

I/Os configured for the PCI, 33 MHz, 5V standard are also

5V-tolerant.

GTL — Gunning Transceiver Logic Terminated

The Gunning Transceiver Logic (GTL) standard is a

high-speed bus standard (JESD8. 3) invented by Xerox. Xil-

inx has implemented the terminated variation of this stan-

dard. This standard requires a differential amplifier input

buffer and an open-drain output buffer.

GTL+ — Gunning Tr ansceiv er Logic Plus

The Gunning Transceiver Logic Plus (GTL+) standard is a

high-speed bus standard (JESD8.3) first used by the Pen-

tium Pro processor.

HSTL — High-Speed Transceiver Logic

The High-Speed Transceiver Logic (HSTL) standard is a

general purpose high-speed, 1.5V bus standard spons ored

by IBM (EIA/JESD 8-6). This standard has four v ariations or

classes. Versatile I/O devices support Class I, III, and IV.

This standard requires a Differential Amplifier input buffer

and a Push-Pull output buffer.

SSTL3 — S tub Series Terminated Logic for 3 .3V

The Stub Series Terminated Logic for 3.3V (SSTL3) stan-

dard is a gene ral pur pose 3.3V m emor y bus stand ard also

sponsored by Hitachi and IBM (JESD8-8). This standard

has two classes, I and II. Versatile I/O devices support both

classes for the SSTL3 standard. This standard requires a

Differential Amplifier input buffer and an Push-Pull output

buffer.

SSTL2 — S tub Series Terminated Logic for 2 .5V

The Stub Series Terminated Logic for 2.5V (SSTL2) stan-

dard is a general purpose 2.5V memory bus standard spon-

sored by Hitachi and IBM (JESD8-9). This standard has two

classes, I and II. Versatile I/O devices support both classes

for the SS TL2 standard. This standard requires a Differen-

tial Amplifier inp ut buffer and an Push-Pu ll output buffe r.

CTT — Cent er Tap Ter mi n ated

The Center Tap Terminated (CTT) standard is a 3.3V mem-

ory bus standard sponsored by Fujitsu (JESD8-4). This

standard require s a Differential Amplifier input bu ffer and a

Push-Pull output buffer.

AGP-2X — A dvanced Gra p h i cs Port

The Intel AGP standard is a 3.3V Advanced Graphics

Port-2X bus standard used with the P entium II processor f or

graphics applications. This standard requires a Push-Pull

outpu t buffer and a Di fferential Amplifier input bu ffer.

Library Symbols

The Xilinx library includes an extensive list of symbols

designed to provide suppor t for the variety of Versatile I/O

features. M ost of these symbols represe nt variations of the

five generic Versatile I/O symbol s:

•IBUF (input buffer)

•IBUFG (global clock inpu t buffer)

•OBUF (output buffer)

•OBUFT (3 -state output buffer)

•IOBUF (input/output buffer)

IBUF

Signals used as inputs to the Spartan-II device must source

an input buff er (IBUF) via an ex ternal input port. The generic

IBUF symbol appears in Figure 34. The extension to the

base nam e defines whi c h I/O st andard the IBUF uses. T he

assum ed stand ard is LVT TL when the generi c IBUF has no

specified extension.

The following list details the variations of the IBUF symbol:

•IBUF

•IBUF_LVCMOS2

•IBUF_PCI33_3

•IBUF_PCI33_5

•IBUF_PCI66_3

•IBUF_GTL

•IBUF_GTLP

•IBUF_HSTL_I

•IBUF_HSTL_III

•IBUF_HSTL_IV

•IBUF_SSTL3_I

•IBUF_SSTL3_II

•IBUF_SSTL2_I

•IBUF_SSTL2_II

•IBUF_CTT

•IBUF_AGP

When the IBUF symbol supports an I/O standard such as

LV TTL, LVCM OS, or P CI33_5, t he IBUF a uto matically c on-

figures as a 5V tolerant input buffer unless the VCCO for the

bank is less than 2V. If the single-ended IBUF is placed in a

Figure 34: Input Buffer (IBUF) Symbols

IBUF

DS001_35_061200

Spartan - II 2.5V FP GA Family: Functional Description

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32 1-800-255-7778 Preliminary Product Specification

bank with an HSTL standard (VCCO < 2V), the input buff er is

not 5V tolerant.

The voltage reference signal is "banked" within the

Spartan-II device on a half-edge basis such that f or all pack-

ages there are eight independent VREF banks internally.

See Figure 35 for a rep resentation of th e I/ O bank s. Within

each bank approximately one of ever y six I/O pins is auto-

matically configured as a VREF input.

IBUF placement restrictions require that any differential

amplifier input signals within a bank be of the same stan-

dard. How to specify a specific location for the IBUF via the

LOC property is descr ibed below. Table 15 summariz es th e

input standards compat ibility requirements.

An optional delay element is associated with each IBUF.

When the IBUF drives a flip-flop within the IOB, the delay

element by default activates to ensure a zero hold-time

requirement. The NODE LAY =T RUE prop erty overr ides this

default.

When the IBUF does not drive a flip-flop within the IOB, the

dela y element de-activat es by defaul t to provide higher per-

for mance. To delay the input signal, activate the delay ele-

ment with the DELAY=TRUE property.

IBUFG

Signals used as high fanout clock inputs to the

Spartan-II device should drive a global clock input buffer

(IBUFG) via an external input por t in order to take advan-

tage of one of the four dedicated global clock distribution

networks . The output of the IBUFG symbol can only d rive a

CLKDLL, CLKDLLHF, or a BUFG symbol. The generic

IBUFG symbol appears in Figure 36.

The extension to the base name determines which I/O stan-

dard is used by the IBUFG. With no exten si on sp ecifi ed for

the generic IBUFG symbol, the assumed standard is

LVTTL.

The following list details variations of the IBUFG symbol.

•IBUFG

•IBUFG_LVCMOS2

•IBUFG_PCI33_3

•IBUFG_PCI33_5

•IBUFG_PCI66_3

•IBUFG_GTL

•IBUFG_GTLP

•IBUFG_HSTL_I

•IBUFG_HSTL_III

•IBUFG_HSTL_IV

•IBUFG_SSTL3_I

•IBUFG_SSTL3_II

•IBUFG_SSTL2_I

•IBUFG_SSTL2_II

•IBUFG_CTT

•IBUFG_AGP

The voltage reference signal is "banked" within the

Spartan-II de vice on a half-edge basis such that for all pack-

ages there are eight independent VREF banks internally.

See Figure 35 for a represent ation of the I/O banks. Within

each bank app roximately one of ever y six I/O pins is auto-

matically conf igured as a VREF input.

IBUFG placement restrictions require any differential ampli-

fier input signals within a bank be of the same standard. The

LOC property can specify a location for the IBUFG.

As an added convenience, the BUFGP can be used to

instantiate a high fanout clock input. The BUFGP symbol

represents a combination of the LVTTL IBUFG and BUFG

symbols, such that the output of the BUFGP can connect

directly to the clock pins throughout the design.

The S partan-II BUFGP sym bol can onl y be placed in a glo-

bal clock pad location. The LOC property can specify a

location for the BUFGP.

Figure 35: I/O B a n ks

Table 15: X i lin x I n put Sta ndards Compa t ibilit y

Requirements

Rule 1 All differential amplifier input signals within a

bank are required to be of the same standard.

Rule 2 The re are no placement restrictions for inputs

with standards that require a single-ended input

buffer.

DS001_03_060100

Bank 0

GCLK3 GCLK2

GCLK1 GCLK0

Bank 1

Bank 5 Bank 4

Spartan-II

Device

Bank 7Bank 6

Bank 2Bank 3

Figure 36: Global Clock Input Buffer (IBUFG) Symbol

IBUFG

DS001_37_061200

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Preliminary Product Specification 1-800-255-7778 33

OBUF

An OBUF must drive outputs through an external output

por t. The generic output buffer (OBUF) symbol appears in

Figure 37.

The extension to the base name defines which I/O standard

the OBUF uses. With no e xtension specified for t he generic

OBUF symbol, the assumed standard is slew rate limited

LVTTL with 12 mA drive strength.

The LVTTL OBUF addi tio nally can sup port one of two slew

rate mode s to minimize bus transients. By default, the slew

rate f or each output b uff er is reduced to minimiz e po wer bus

transients when switching non-critical signals.

LV T TL output bu ffers have s electable drive strengths.

The f ormat for LVTTL OBUF symbol names is as foll ows.

OBUF_<slew_rate>_<drive_strength>

<slew_rate> is either F (Fast), or S (Slow) and

<driv e_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

The followi ng list details variations of the OBUF symbol.

•OBUF

•OBUF_S_2

•OBUF_S_4

•OBUF_S_6

•OBUF_S_8

•OBUF_S_12

•OBUF_S_16

•OBUF_S_24

•OBUF_F_2

•OBUF_F_4

•OBUF_F_6

•OBUF_F_8

•OBUF_F_12

•OBUF_F_16

•OBUF_F_24

•OBUF_LVCMOS2

•OBUF_PCI33_3

•OBUF_PCI33_5

•OBUF_PCI66_3

•OBUF_GTL

•OBUF_GTLP

•OBUF_HSTL_I

•OBUF_HSTL_III

•OBUF_HSTL_IV

•OBUF_SSTL3_I

•OBUF_SSTL3_II

•OBUF_SSTL2_I

•OBUF_SSTL2_II

•OBUF_CTT

•OBUF_AGP

OBUF placement restrictions require that within a given

VCCO bank each OBUF share the s ame output source drive

voltage. Input buffe rs of any type and ou tput buffers that do

not require VCCO can be placed within any VCCO bank.

Table 16 summarizes the output compatibility requirements.

The LOC property can specify a location for t he OBUF.

OBUFT

The generic 3-state output buffer OBUFT, shown in

Figure 38, typically implements 3-state outputs or bidirec-

tio n al I/O.

The extension to the base name defines which I/O standard

OBUFT uses. With no extension specified for the generic

OBUFT symbol, the assumed standa rd i s slew rate limited

LV TTL with 12 mA drive strengt h.

The LVTTL OBUFT additionally can support one of two slew

rate modes t o m in imize bus transients. By d efault, the slew

rate f or each output buff er is reduced to minimize pow er bus

transients when switching non-cri tical signals.

LVTTL 3-state output buffers have selectable drive

strengths.

The format for LVTTL OB UFT sym bol names is as follows.

OBUFT_<slew_rate>_<drive_strength>

Figure 37: Output Buffer (OBUF) Symbol

OBUF

DS001_38_061200

Table 16: Output Stand ards Compatibility

Requirements

Rule 1 Only outputs with standards which share

compatib le VCCO may be used within the same

bank.

Rule 2 There are no placement restrictions for outputs

with standards that do not require a VCCO.

VCCO Compatible Standards

3.3 LVTTL, SSTL3_I , SSTL3_II , CTT, AG P, GTL,

GTL+, PCI33_ 3, PC I66_3

2.5 SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+

1 .5 H STL_I, H STL_I II, H ST L _IV, G TL , G TL +

Spartan - II 2.5V FP GA Family: Functional Description

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34 1-800-255-7778 Preliminary Product Specification

<slew_rate> can be either F (Fast), or S (Slow) and

<driv e_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

The followi ng list details variations of the OBUFT symbol.

•OBUFT

•OBUFT_S_2

•OBUFT_S_4

•OBUFT_S_6

•OBUFT_S_8

•OBUFT_S_12

•OBUFT_S_16

•OBUFT_S_24

•OBUFT_F_2

•OBUFT_F_4

•OBUFT_F_6

•OBUFT_F_8

•OBUFT_F_12

•OBUFT_F_16

•OBUFT_F_24

•OBUFT_LVCMOS2

•OBUFT_PCI33_3

•OBUFT_PCI33_5

•OBUFT_PCI66_3

•OBUFT_GTL

•OBUFT_GTLP

•OBUFT_HSTL_I

•OBUFT_HSTL_III

•OBUFT_HSTL_IV

•OBUFT_SSTL3_I

•OBUFT_SSTL3_II

•OBUFT_SSTL2_I

•OBUFT_SSTL2_II

•OBUFT_CTT

•OBUFT_AGP

The Versatile I/O OBUFT placement restrictions require that

within a given VCCO bank each OBUFT share the same out-

put source dr ive voltage. Input buffe rs of any type and out-

put buffers that do not require VCCO can be placed within

the same VCCO bank.

The LOC property can specify a location for t he OBUFT.

3-state output buffers and bidirectional buffers can have

either a weak pull-up res istor, a weak pull-down resistor, or

a weak "keeper" circuit. Control this feature by adding the

appropriate symbol to the output net of the OBUFT

(PULLUP, PULLDOW N, or KEEPER).

The weak "keeper" circuit requires the input b uff er within the

IOB t o samp le the I /O signal. S o, OBU FTs programmed for

an I/O standard that requires a VREF have automati c pl ace -

ment of a V REF in the bank with an OBUFT conf igu red with

a weak "k eeper" circuit. This restriction does not af fect most

circuit design as applications using an OBUFT configured

with a weak "keeper" typically implement a bidirectional I/O.

In this case the IBUF (and the corresponding VREF) are

explicitly pla ced.

The LOC property can specify a location for t he OBUFT.

IOBUF

Use the IO BUF s ymb ol for bidirectional signals that requ ire

both an input buffer and a 3-state output buffer with an

active high 3-state pin. The generic input/output buffer

IOBUF appears in Figure 39.

The extension to the base name defines which I/O standard

the IOBUF uses. With no extension specified for the generic

IOBUF symbol, the assumed standard is LVTTL input buffer

and slew rate limited LVTTL with 12 mA drive strength for

the output bu ffer.

The LVTTL IOBUF additionally can support one of two slew

rate modes t o m in imize bus transients. By d efault, the slew

rate f or each output buff er is reduced to minimize pow er bus

transients when switching non-cri tical signals.

LVTTL bidirectional buffers have selectable output drive

strengths.

The format fo r LVTTL IOBUF symbol nam es is as foll ows:

IOBUF_<slew_rate>_<drive_strength>

<slew_rate> can be either F (Fast), or S (Slow) and

<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

Figure 38: 3-State Output Buffer Symbol (OBUFT

IOBUFT

DS001_39_032300

Figure 39: Input/Ou tput Buff er Symbol (IOBUF)

IOBUF

DS001_40_061200

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Preliminary Product Specification 1-800-255-7778 35

The following list details variations of the IOBUF symbol:

•IOBUF

•IOBUF_S_2

•IOBUF_S_4

•IOBUF_S_6

•IOBUF_S_8

•IOBUF_S_12

•IOBUF_S_16

•IOBUF_S_24

•IOBUF_F_2

•IOBUF_F_4

•IOBUF_F_6

•IOBUF_F_8

•IOBUF_F_12

•IOBUF_F_16

•IOBUF_F_24

•IOBUF_LVCMOS2

•IOBUF_PCI33_3

•IOBUF_PCI33_5

•IOBUF_PCI66_3

•IOBUF_GTL

•IOBUF_GTLP

•IOBUF_HSTL_I

•IOBUF_HSTL_III

•IOBUF_HSTL_IV

•IOBUF_SSTL3_I

•IOBUF_SSTL3_II

•IOBUF_SSTL2_I

•IOBUF_SSTL2_II

•IOBUF_CTT

•IOBUF_AGP

When the IOBUF symbol supports an I/O s tandard s uch as

LV T TL, LVC MO S, or PCI33 _5, the I BUF aut om atically con-

figures as a 5V tolerant input buff er unless the VCCO for the

bank is less than 2V. If the single-ended IBUF is placed in a

bank with an HSTL standard (VCCO < 2V), the input buff er is

not 5V tolerant.

The voltage reference signal is "banked" within the

Spartan-II device on a half-edge basis such that f or all pack-

ages there are eight independent VREF banks internally.

See Figure 35, page 32 for a representation of the Spar-

tan-II I/O banks. Within each bank approximately one of

every six I/O pins is automatically configured as a VREF

input.

Additional restrictions on the V ersatile I/O IOBUF placement

require that within a given VCCO bank each IOBUF must

share the same output source drive voltage. Input b uffers of

any type and output buffers that do not require VCCO can be

placed within the same VCCO bank. The LO C proper ty can

specify a location for the IOBUF.

An optional delay element is associated with the inp ut path

in each IOBUF. When the IOBUF drives an input flip-flop

within the IOB, the delay element activates by default to

ensure a zero hold-time requirement. O verride this default

with the NODELAY= TRUE property.

In the case when the IOBUF does not drive an input flip-flop

within t he IOB, the delay element de-activates by default to

provide higher performance. To de lay t he input signal, acti-

vate the delay element with the DELAY=T RUE proper ty.

3-state output buffers and bidirectional buffers can have

either a weak pull-up res istor, a weak pull-down resistor, or

a weak "keeper" circuit. Control this feature by adding the

appropriate symbol to the output net of the IOBUF

(PULLUP, PULLDOW N, or KEEPER).

Versatile I/O Properties

Access to some of the Versatile I/O features (for example,

location constraints, input delay, output dr ive strength, and

slew rate) is available through properties associated with

these features.

Input Delay Properties

An optional delay element is associated with each IBUF.

When the IBUF drives a flip-flop within the IOB, the delay

element activates by default to ensure a zero hold-time

requirement. Use the NODELAY=TRUE property to over-

r ide this default.

In the case when the IBUF does not drive a flip-flop within

the IOB, the delay element by default de-activates to pro-

vide high er performanc e. To delay the input signal , activate

the delay element with the DELAY=T RUE propert y.

IOB Flip-Flop/Latc h Pr operty

The I/O Block (IOB) includes an optional register on the

input path, an optional register on the output p ath, and an

optional register on the 3-state control pin. The design

implementation software automatically takes advantage of

these registers when the following option for the Map pro-

gram is specified:

map -pr b <filename>

Alter natively, the IOB = TRUE proper ty can be plac ed on a

Location Constraints

Specify the location of each Versatile I/O symbol with the

location constraint LOC attached to the Versatile I/O sym-

bol. The external port identifier indicates the value of the

location constrain. The f ormat of the port identifier depends

on the package chosen for the specific design.

The LOC properties use the following form:

LOC=A42

LOC=P37

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36 1-800-255-7778 Preliminary Product Specification

Output Slew Rate Propert y

As mentioned above , a variety of symbol names provide the

option of choosing the des ired slew rate for the output buff-

ers. In the case of the LVTTL output bu ffers (OBUF, OBUFT,

and IOBUF), slew rate control can be alternatively pro-

gramed with the SLEW = proper ty. By default, the slew rate

for each output buffer is reduced to minimize power bus

transients when switching non-critical signals. The SLEW=

property has one of the two following values.

SLEW=SLOW

SLEW=FAST

Output Drive Strength Property

The desired output drive strength can be additionally speci-

fied by choosing the appropr iate librar y sym bol. The Xilinx

library also provides an alternative method for specifying

this feature. For the LVTTL output buffers (OBUF, OBUFT,

and IOBUF, the desired drive strength can be specified with

the DRIVE= proper ty. This property could have one of the

following sev en values.

DRIVE=2

DRIVE=4

DRIVE=6

DRIVE=8

DRIVE=12 (Default)

DRIVE=16

DRIVE=24

Design Considerations

Re feren ce Voltage (VREF) Pin s

Low-voltage I/O sta ndards with a differen tial amplifier input

bu ffer requi re an input ref erence voltage (VREF). Provide the

VREF as an external signal to the device.

The voltage reference signal is "banked" within the device

on a half-edge basis such that for all packages there are

eight independent VREF banks internally. See Figure 35,

page 32 fo r a representation of the I/O banks. Within each

bank approximately one of every six I/O pins is automati-

cally configured as a VREF inpu t.

Within each VREF bank, any input buffers that require a

VREF signal must be of the same type. Output buffers of an y

type and input buffers can be placed without requiring a ref-

erence voltage within the same VREF bank.

Output Drive Source Voltage (VCCO) Pins

Many of the low voltage I/O stand ards s upported by Versa-

tile I/Os require a different output drive source voltage

(VCCO). As a result each device can often have to suppor t

multiple output drive source voltages.

The VCCO supplies are internally tied together for some

packages. The VQ100 and the PQ208 provide one com-

bined VCCO supply. The TQ144 and the CS144 packages

provide four independent VCCO supplies. The FG256 and

the FG456 provide eight independent VCCO supplies.

Output buffers within a given VCCO bank must share the

same o utpu t drive sou rce voltage. Input buffers for LVTTL,

LVCMOS2, PCI33_3, and PCI 66_3 use the VCCO volta ge

for Input VCCO voltage.

Transmission Line Effects

The delay of an electrical signal along a wire is dominated

by the rise and f all times when the signal trav els a short dis-

tance. Transmission line delays vary with inductance and

capacitance, but a well-designed board can experience

delays of approximately 180 ps per in ch.

Transmission line effects, or reflections, typically start at

1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-

tent) termination or changes in the transmission line imped-

ance cause these reflections and can cause additional

delay in longer traces. As system speeds continue to

incre ase, the effect of I/O del ay s ca n beco me a limiting fac -

tor and therefore transmission line termination becomes

incre asingly mo re import ant.

Termination Techniques

A variety of termination techniques reduce the impact of

transmission line effect s .

The following lists output ter mi nation techni ques:

None

Series

Parallel (Shunt)

Ser ies and Paral lel (Serie s-Shun t)

Input ter m ination techniqu es include the following:

None

Parallel (Shunt)

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Preliminary Product Specification 1-800-255-7778 37

These termination techniques can be applied in any combi-

nation. A gener ic ex ample of ea ch combination of ter mina-

tion methods appea rs in Figure 40.

Simult aneous Switching G uidelines

Ground bounce can occur with high-speed digital ICs when

multiple outputs change states simultaneously, causing

undesired transient behavior on an output, or in the internal

logic. This problem is also referred to as the Simultaneous

Switching Output (SSO) problem.

Ground bounce is primarily due to current changes in the

combined inductance of ground pins, bond wires, and

ground metallization. Th e IC internal ground level deviates

from the external system ground le vel f or a short duration (a

few nanoseconds) after multiple outputs change state

simultaneously.

Ground bounce affects stable Low outputs and all inputs

because they interpret the incoming signal by compar ing it

to the internal ground. If the ground bounce amplitude

exceeds the actual instantaneous noise margin, then a

non-changing input can be interpreted as a short pulse with

a polarity oppo site to the grou nd bounc e.

Table 17 provides the guidelines for the maximum number

of simultaneously switching outputs allowed per output

power/ground pair to avoid the effects of ground bounce.

Refer to Table 18 for the number of effective output

power/ground pairs f or each Spartan-II device and package

combination..

Figure 40: O v erview of Standard Input and Output

Ter min ation Methods

DS001_41_032300

Unterminated Double Parallel Terminated

Series-Par allel Terminated Output

Driving a Parallel Terminated Input

Series Terminated Output Driving

a Parallel Terminated Input

Unterminated Output Driving

a Parallel Terminated Input

VTT

VREF

VTT VTT

VTT

Series Terminated Output

VREF

Z=50

Table 17: Maximum Numb er of Simultaneously

Sw i tching Outputs per P owe r/Gr ound Pai r

Package

Standard CS , FG PQ ,

TQ, VQ

LVTTL Slow Slew Rate, 2 mA driv e 68 36

LVTTL Slow Slew Rate, 4 mA driv e 41 20

LVTTL Slow Slew Rate, 6 mA driv e 29 15

LVTTL Slow Slew Rate, 8 mA driv e 22 12

LVTTL Slow Slew Rate, 12 mA driv e 17 9

LVTTL Slow Slew Rate, 16 mA driv e 14 7

LVTTL Slow Slew Rate, 24 mA driv e 9 5

LVTTL Fast Slew Rate, 2 mA drive 40 21

LVTTL Fast Slew Rate, 4 mA drive 24 12

LVTTL Fast Slew Rate, 6 mA drive 17 9

LVTTL Fast Slew Rate, 8 mA drive 13 7

LVTTL Fast Slew Rate, 12 mA drive 10 5

LVTTL Fast Slew Rate, 16 mA drive 8 4

LVTTL Fast Slew Rate, 24 mA drive 5 3

LVCMOS2 10 5

PCI 8 4

GTL 4 4

GTL+ 4 4

HSTL Class I 18 9

HSTL Class III 9 5

HSTL Class IV 5 3

SSTL2 Class I 15 8

SSTL2 Class II 10 5

SSTL3 Class I 11 6

SSTL3 Class II 7 4

CTT 14 7

AGP 9 5

Notes:

1. This analysis assumes a 35 pF load f or each output.

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38 1-800-255-7778 Preliminary Product Specification

Termination Examples

Creating a design with the Versatile I/O features requires

the instantiation of the desired library symbol within the

design code. At t he board l evel, designers need t o know the

termination techniques required f or each I/O standard.

This section describes some common application examples

illustrating the termination techniques recommended by

each of the standards supported by the Versatile I/O fea-

tures. For a full range of accepted val ues f or the DC voltage

specifications for each standard, refer to the table associ-

ated with each figure.

The resistors used in each termination technique example

and the transmission lines depicted represent board level

components and are not meant to represent components

on the dev ice.

GTL

A sample circuit illustrating a v alid termination technique for

GTL is shown in Figure 41. Table 19 lists DC voltage

specifications.

Table 18: Effective Ou tpu t Powe r/G round Pairs for

Spartan-II Devices

Pkg. XC2S

15 XC2S

30 XC2S

50 XC2S

100 XC2S

150 XC2S

200

VQ100 8 8 - - - -

CS144 12 12 - - - -

TQ144 12 12 12 12 - -

PQ208 - 16 16 16 16 16

FG256 - - 16 16 16 16

FG456 - - - 48 48 48 Figure 41: Terminated GTL

Table 19: GTL Voltage S pecificatio ns

Parameter Min Typ Max

VCCO -N/A-

VREF = N × VTT(1) 0.74 0.8 0.86

VTT 1.14 1.2 1.26

VIH ≥ VREF + 0.05 0.79 0.85 -

VIL ≤ VREF – 0.05 - 0.75 0.81

VOH ---

VOL -0.20.4

IOH at VOH (mA) ---

IOL at VOL (mA) at 0.4V 32 - -

IOL at VOL (mA) at 0.2V - - 40

Notes:

1. N mus t be gr eater than or equal to 0.653 and less than or

equal to 0.68.

VREF = 0.8V

VCCO = NA 50Ω

Z = 50

GTL

DS001_43_061200

VTT = 1.2V

50Ω

VTT = 1.2V

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Preliminary Product Specification 1-800-255-7778 39

GTL+

A sample circuit illustrating a valid termination technique for

GTL+ appears in Figure 42. DC voltage specifications

appear in Table 20 .

HSTL Class I

A sample circuit illustrating a v alid termination technique for

HSTL_I appears in Figure 43. DC voltage specifications

appear in Table 21.

Figure 42: Terminated GTL+

Table 20: GTL+ Voltage Specifications

Parameter Min Typ Max

VCCO -- -

VREF = N × VTT(1) 0.88 1.0 1.12

VTT 1.35 1.5 1.65

VIH ≥ VREF + 0 .1 0.9 8 1.1 -

VIL ≤ VREF – 0.1 - 0.9 1.02

VOH -- -

VOL 0.3 0.45 0.6

IOH at VOH (mA) - - -

IOL at VOL (mA) at 0.6V 36 - -

IOL at VOL (mA) at 0.3V - - 48

Notes:

1. N must be greater than or equal to 0.653 and less than or

equal to 0.68.

VREF = 1.0V

VCCO = NA 50Ω

Z = 50

GTL+

DS001_43_061200

VTT = 1.5V

50Ω

VTT = 1.5V

Figure 43: Termi na ted HSTL Class I

Table 21: HSTL Class I Voltag e Specification

Parameter Min Typ Max

VCCO 1.40 1.50 1.60

VREF 0.68 0.75 0.90

VTT -V

CCO × 0.5 -

VIH VREF + 0.1 - -

VIL --V

REF – 0.1

VOH VCCO – 0.4 - -

VOL 0.4

IOH at VOH (mA) −8- -

IOL at VOL (mA) 8 - -

VREF = 0.75V

VCCO = 1.5V 50Ω

Z = 50

HSTL Class I

DS001_44_061200

VTT = 0.75V

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40 1-800-255-7778 Preliminary Product Specification

HTSL Class III

A sample circuit illustrating a valid termination technique for

HSTL_III appears in Figure 44. DC voltage specifications

appear in Table 22.

HTSL Class IV

A sample circuit illustrating a v alid termination technique for

HSTL_IV appears in Figure 45.DC voltage specifications

appear in Table 22

Figure 44: Termi na ted HSTL Class III

Table 22: HST L Class III Voltage Specification

Parameter Min Typ Max

VCCO 1.40 1.50 1.60

VREF (1) -0.90-

VTT -V

CCO -

VIH VREF + 0.1 - -

VIL --V

REF – 0.1

VOH VCCO – 0.4 - -

VOL --0.4

IOH at VOH (mA) −8--

IOL at VOL (mA) 24 - -

Notes:

1. P er EIA/JESD8- 6, "The value of VREF i s to be sele cted by the

user to pr ovide optimum noise margin in the use conditions

specified by the user."

VREF = 0.9V

VCCO = 1.5V 50Ω

Z = 50

HSTL Class III

DS001_45_061200

VTT = 1.5V

Figure 45: Terminated HSTL Class IV

Table 23: HSTL Class IV Voltage Specification

Parameter Min Typ Max

VCCO 1.40 1.50 1.60

VREF -0.90 -

VTT -V

CCO -

VIH VREF + 0.1 - -

VIL --V

REF – 0.1

VOH VCCO – 0.4 - -

VOL --0.4

IOH at VOH (mA) −8- -

IOL at VOL (mA) 48 - -

Notes:

1. P er EIA/J ESD8-6, "The v alue of VREF is to be s electe d b y the

user to provide optimum noise margin in t he use conditions

specified by t he user."

VREF = 0.9V

VCCO = 1.5V 50Ω

Z = 50

HSTL Class IV

DS001_46_061200

VTT = 1.5V

50Ω

VTT = 1.5V

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Preliminary Product Specification 1-800-255-7778 41

SSTL3 Class I

A sample circuit illustrating a valid termination technique for

SSTL3_I appears in Figure 46. DC voltage specifications

appear in Table 24.

SSTL3 Cl a s s II

A sample circuit illustrating a v alid termination technique for

SSTL3_II appears in Figure 47. DC voltage specifications

appear in Table 25.

Figure 46: Termina ted SST L3 Class I

Table 24: SSTL3_I Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF = 0.45 × VCCO 1.3 1.5 1.7

VTT = V REF 1.3 1.5 1.7

VIH ≥ VREF + 0.2 1.5 1. 7 3.9(1)

VIL ≤ VREF – 0.2 −0.3(2) 1.3 1.5

VOH ≥ VREF + 0.6 1.9 - -

VOL ≤ VREF – 0.6 - - 1.1

IOH at VOH (mA) −8--

IOL at VOL (mA) 8 - -

Notes:

1. VIH maximum is VCCO + 0.3.

2. VIL mini m um does not conform to the formul a.

VREF = 1.5V

VCCO = 3.3V 50Ω

Z = 50

SSTL3 Class I

DS001_47_061200

VTT = 1.5V

25Ω

Figure 47: Terminated SSTL3 Class II

Table 25: SSTL3_II Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF = 0.45 × VCCO 1.3 1.5 1.7

VTT = VREF 1.3 1.5 1.7

VIH ≥ VREF + 0.2 1. 5 1.7 3.9(1)

VIL ≤ VREF – 0.2 −0.3(2) 1.3 1.5

VOH ≥ VREF + 0.8 2. 1 - -

VOL ≤ VREF – 0.8 - - 0.9

IOH at VOH (mA) −16 - -

IOL at VOL (mA) 16 - -

Notes:

1. VIH maximum is VCCO + 0.3

2. VIL minimum does not con form to the formula

VREF = 1.5V

VCCO = 3.3V 50Ω

Z = 50

SSTL3 Class II

DS001_48_061200

VTT = 1.5V

50Ω

VTT = 1.5V

25Ω

Spartan - II 2.5V FP GA Family: Functional Description

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42 1-800-255-7778 Preliminary Product Specification

SSTL2_I

A sample circuit illustrating a valid termination technique for

SSTL2_I appears in Figure 48. DC voltage specifications

appear in Table 26

SSTL2 Cl a s s II

A sample circuit illustrating a v alid termination technique for

SSTL2_II appears in Figure 49. DC voltage specifications

appear in Table 27.

Figure 48: Termina ted SST L2 Class I

Table 26: SSTL2_I Voltage Specifications

Parameter Min Typ Max

VCCO 2.3 2.5 2.7

VREF = 0.5 × VCCO 1.15 1.25 1.35

VTT = V REF + N(1) 1.11 1.25 1.39

VIH ≥ VREF + 0.18 1.33 1.43 3.0 (2)

VIL ≤ VREF – 0.18 −0.3(3) 1.07 1.17

VOH ≥ VREF + 0.61 1.76 - -

VOL ≤ VREF – 0.61 - - 0.74

IOH at VOH (mA) −7.6 - -

IOL at VOL (mA) 7.6 - -

Notes:

1. N must be great er than or equal to –0.04 and less than or

equal to 0.04.

2. VIH maximum is VCCO + 0.3.

3. VIL mini m um does not conform to the formul a.

VREF = 1.25V

VCCO = 2.5V 50Ω

Z = 50

SSTL2 Class I

DS001_49_061200

VTT = 1.25V

25Ω

Figure 49: Terminated SSTL2 Class II

Table 27: SSTL2_II Voltage Specifications

Parameter Min Typ Max

VCCO 2.3 2.5 2.7

VREF = 0.5 × VCCO 1.15 1.25 1.35

VTT = VREF + N(1) 1.11 1.25 1.39

VIH ≥ VREF + 0. 18 1.33 1.43 3.0(2)

VIL ≤ VREF – 0.18 −0.3(3) 1.07 1.17

VOH ≥ VREF + 0.8 1. 95 - -

VOL ≤ VREF - 0.8 - - 0.55

IOH at VOH (mA) −15.2 - -

IOL at VOL (mA) 15.2 - -

Notes:

1. N mus t be gr eater than or equal to –0.04 and less than or

equal to 0.04.

2. VIH maximum is VCCO + 0.3.

3. VIL minimum does not con form to the formula.

VREF = 1.25V

VCCO = 2.5V 50Ω

Z = 50

SSTL2 Class II

DS001_50_061200

VTT = 1.25V

50Ω

VTT = 1.25V

25Ω

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Preliminary Product Specification 1-800-255-7778 43

CTT

A sample circuit illustrating a valid termination technique for

CTT appea r in Figure 50. DC voltag e specifications appear

in Table 28 .

PCI33_3 and PCI66_3

PCI33_3 or PCI66_3 require no termination. DC voltage

speci fications appea r in Table 29.

PCI33_5

PCI33_5 requires no termination. DC voltage specifications

appear in Table 30.

F igure 50: Term inated CTT

Table 28: CTT Voltage Spec ifications

Parameter Min Typ Max

VCCO 2.05(1) 3.3 3.6

VREF 1.35 1.5 1.65

VTT 1.35 1.5 1.65

VIH ≥ VREF + 0.2 1.55 1.7 -

VIL ≤ VREF – 0.2 - 1.3 1 .45

VOH ≥ VREF + 0.4 1.7 5 1.9 -

VOL ≤ VREF – 0.4 - 1.1 1 .25

IOH at VOH (mA) −8--

IOL at VOL (mA) 8 - -

Notes:

1. Timing delays are cal culated based on V CCO min of 3.0V.

VREF = 1.5V

VCCO = 3.3V 50Ω

Z = 50

CTT

DS001_51_061200

VTT = 1.5V

Table 29: PCI33_3 and PCI6 6_3 Voltage S pecifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF -- -

VTT -- -

VIH = 0.5 × VCCO 1.5 1.65 VCCO+ 0.5

VIL = 0.3 × VCCO −0.5 0.99 1.08

VOH = 0.9 × VCCO 2.7 - -

VOL = 0.1 × VCCO --0.36

IOH at VOH (mA) Note 1 - -

IOL at VOL (mA) Note 1 - -

Notes:

1. Tested according to the relevant specific ati on.

Table 30: PCI33_5 Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF ---

VTT ---

VIH 1.425 1.5 5.5

VIL −0.5 1.0 1.05

VOH 2.4 - -

VOL - - 0.55

IOH at VOH (mA) N o t e 1 - -

IOL at VOL (mA) Note 1 - -

Notes:

1. Tested according to the relevant specific ati on.

Spartan - II 2.5V FP GA Family: Functional Description

Modu le 2 of 4 www.xilinx.com DS001-2 (v2 .1) March 5, 2001

44 1-800-255-7778 Preliminary Product Specification

LVTTL

LVTTL requires no termination. DC voltage specifications

appears in Table 31.

LVCMOS2

LVCMOS2 requires no termination. DC voltage specifica-

tions appear in Table 32.

AGP-2X

The spe cification fo r the AGP-2X standard does not docu-

ment a recommended termination technique. DC voltage

speci fications appea r in Table 33.

Table 31: LV TTL Volt age Specifi c at io ns

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF ---

VTT ---

VIH 2.0 - 3.6

VIL −0.5 - 0.8

VOH 2.4 - -

VOL --0.4

IOH at VOH (mA) −24 - -

IOL at VOL (mA) 24 - -

Notes:

1. VOL and VOH f or low er drive currents sample t ested.

Table 32: LVCM OS 2 Volt age Specifications

Parameter Min Typ Max

VCCO 2.3 2.5 2.7

VREF ---

VTT ---

VIH 1.7 - 3.6

VIL −0.5 - 0.7

VOH 1.9 - -

VOL --0.4

IOH at VOH (mA) −12 - -

IOL at VOL (mA) 12 - -

Table 33: AGP-2X Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF = N × VCCO(1) 1.17 1.32 1.48

VTT -- -

VIH ≥ VREF + 0.2 1.37 1.52 -

VIL ≤ VREF – 0.2 - 1.12 1.28

VOH ≥ 0.9 × VCCO 2.7 3.0 -

VOL ≤ 0.1 × VCCO - 0.33 0.36

IOH at VOH (mA) Not e 2 - -

IOL at VOL (mA) Note 2 - -

Notes:

1. N mus t be greater t han or equal to 0.39 and less than or

equal to 0.41.

2. Tested according to the relevant specific ati on.

Spartan -II 2.5V FPGA Family: Functional Description

DS001-2 (v2.1) Marc h 5, 2001 www.xilinx.com Module 2 of 4

Preliminary Product Specification 1-800-255-7778 45

Revision History

The Spartan-II Family Data Sheet

DS001-1, Spa r t a n-I I 2.5V FPGA Fami ly: Introduction and Ordering Information (Mo dule 1)

DS001-2, Spartan-II 2.5V FPGA Family: Functional Description (Module 2)

DS001-3, Spa r t a n-I I 2.5V FPGA Fami ly: DC and Switching Characteristics (Module 3)

DS001-4, Spa r t a n-I I 2.5V FPGA Fami ly: Pinout Tables (M odule 4)

Version No. Date Description

2.0 09/18/00 Sectioned the Spartan-II Family data sheet into four modules. Corrected banking description.

2.1 03/05/01 Clarified guideline s fo r applying power to VCCINT and VCCO