AAT1142
DATA SHEET
800mA Voltage-Scaling Step-Down Converter
17
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capacitor with 5.0V DC applied is actually about 6μF.
The maximum input capacitor RMS current is:
⎛⎞
IRMS = IO · · 1 -
⎝⎠
VO
VIN
VO
VIN
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current.
⎛⎞
· 1 - = D · (1 - D) = 0.52 =
⎝⎠
VO
VIN
VO
VIN
1
2
for VIN = 2 · VO
IO
RMS(MAX)
I2
=
The term ⎛⎞
· 1 -
⎝⎠
VO
VIN
VO
VIN appears in both the input voltage
ripple and input capacitor RMS current equations and is
a maximum when VO is twice VIN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT1142. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capacitor
should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the evalu-
ation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
Since the inductance of a short PCB trace feeding the
input voltage is significantly lower than the power leads
from the bench power supply, most applications do not
exhibit this problem.
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic capacitor should be placed in parallel
with the low ESR, ESL bypass ceramic capacitor. This
dampens the high Q network and stabilizes the system.
Output Capacitor
The output capacitor limits the output ripple and provides
holdup during large load transitions. A 4.7μF to 10μF X5R
or X7R ceramic capacitor typically provides sufficient bulk
capacitance to stabilize the output during large load tran-
sitions and has the ESR and ESL characteristics necessary
for low output ripple. A smaller capacitor may result in
slightly increased no load output regulation and output
ripple with input voltages above 5V. This should be veri-
fied under actual operating conditions.
The output voltage droop due to a load transient is dom-
inated by the capacitance of the ceramic output capacitor.
During a step increase in load current, the ceramic output
capacitor alone supplies the load current until the loop
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match the
load current demand. The relationship of the output volt-
age droop during the three switching cycles to the output
capacitance can be estimated by:
COUT =
3 · ΔILOAD
VDROOP · FS
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients.
The internal voltage loop compensation also limits the
minimum output capacitor value to 4.7F. This is due to
its effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
Thermal Calculations
There are three types of losses associated with the
AAT1142 step-down converter: switching losses, conduc-
tion losses, and quiescent current losses. Conduction
losses are associated with the RDS(ON) characteristics of the
power output switching devices. Switching losses are
dominated by the gate charge of the power output switch-
ing devices. At full load, assuming continuous conduction
mode (CCM), a simplified form of the losses is given by:
PTOTAL
IO
2 · (RDS(ON)H · VO + RDS(ON)L · [VIN - VO])
VIN
=
+ (tsw · FS · IO + IQ) · VIN