UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
PRIMARY-SIDE PUSH-PULL OSCILLATOR
WITH DEAD-TIME CONTROL
1
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FEATURES
DPush-Pull Oscillator With Programmable
Deadtime
DHigh-Current Totem-Pole Dual Output Stage
Drives Push-Pull Configuration with 1-A Sink
and 0.5-A Source Capability
DCan be Used in Push-Pull, Half-Bridge, or
Full-Bridge Topologies
DOscillator Synchronization Output
DLow Start-Up Current of 130 μAand1.4-mA
Typical Run Current
DOver-Current Shutdown
DDigitally Controlled Over-Current/Retry
Feature
DUndervoltage Lockout With Hysteresis
APPLICATIONS
DHigh Efficiency Cascaded Converters
DInverters
DElectronic Ballasts
DUninterruptable Power Supplies (UPS)
DAC or DC Links
DESCRIPTION
The UCC28089 is a versatile BiCMOS controller for
dc-to-dc or off-line fixed-frequency switching power
supplies. The UCC28089 has dual alternating output
stages in dual-alternating push-pull configuration. Both
outputs switch at half the oscillator frequency using a
toggle flip-flop and duty cycle is limited to less than 50%.
TYPICAL APPLICATION
2
1
4
3
7
8
5
6
UCC28089
SYNC
DIS
CT
CS
VDD
OUTA
OUTB
GND
+
--
2
4
18
UCC2540
REF
SYNCIN
G1
15
16
14
VDD
PGND
G2
--
BIAS
UDG-04112
RA
RB
CT
VIN =48V
VO=1.2V
+
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Te
x
as Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
2www.ti.com
DESCRIPTION (CONTINUED)
The UCC28089 is optimized for use as the primary-side companion controller for a cascaded converter that has
secondary-side control. The device incorporates dead-time programming. The synchronization output also
provides dead-time information. The retry and soft-start duration scales with the oscillator clock frequency for
high performance fault recovery.
The UCC28089 also provides primary side under-voltage protection (UVLO), and over-current protection. Both
the soft start and retry after fault durations scale with oscillator frequency for high performance. The turn-on/off
UVLO thresholds are 10.5 V/8.0 V.
ORDERING INFORMATION
TEMPER
A
TURE R
A
NGE PACKAGED DEVICES{
T
E
M
P
E
R
A
T
U
R
E
R
A
N
G
E
TA=T
JSOIC--8 (D)
-- 4 0 °C to 105°C UCC28089D
†D (SOIC--8) package is available taped and reeled. Add R suffix to device type (e.g. UCC28089DR) to order quantities of 2,500 devices per reel
(for D).
CONNECTION DIAGRAM
1
2
3
4
8
7
6
5
SYNC
DIS
CT
CS
VDD
OUTA
OUTB
GND
D PACKAGE (SOIC--8)
(TOP VIEW)
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
3
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)†}
PARAMETER SYMBOL RATING UNITS
Supply voltage (IDD <10mA) VDD 15 V
Supply current IDD 20 mA
OUTA/OUTB sink current (peak) IOUT(sink) 1.0
A
OUTA/OUTB source current (peak) IOUT(source) -- 0 . 5
A
SYNC sink current (peak) 50
m
A
SYNC source current (peak) -- 5 0 m
A
Analog inputs (DIS, CT, CS) --0.3toV
DD + 0.3, not to exceed 5 V
Power dissipation at TA=25°C (D package) 650
m
Power dissipation at TA=25°C (DRB package) TBD mW
Junction operating temperature TJ--55 to 150
Storage temperature Tstg --65 to 150 oC
Lead temperature (soldering, 10 sec.) Tsol +300
C
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute--maximum--rated conditions for extended periods may affect device reliability.
‡All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook
for thermal limitations and considerations of packages.
RECOMMENDED OPERATION CONDITIONS
Parameter Symbol MIN TYP MAX UNITS
Supply voltage (IDD <10mA) VDD 8.5 14 V
SYNC sink current (peak) 010 25
m
A
SYNC source current (peak) -- 2 5 -- 1 0 0m
A
Analog inputs (DIS, CT, CS) 0 4 V
Timing capacitor range CT 100 100,000 pF
Timing charge resistor range RA 32 750
k
Ω
Discharge resistor range RB 0250 kΩ
Timing charge current ICHG(RA+RB) 10 300 μA
Switching Frequency fSW 1000 kHz
Junction temperature TJ-- 4 0 105 °C
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
4www.ti.com
ELECTRICAL CHARACTERISTICS:
TA=--40°C to 105°C for UCC28089, VDD =9V(seeNote1),1μF capacitor from VDD to GND, RA = 110 kΩ, RB = 182 Ω, CT = 220 pF, TA=T
J,
(unless otherwise noted).
PARAMETER TEST CONDITION MIN TYP MAX UNITS
Overall Section
Startup current VDD < UVLO start threshold (see Note 2) 130 260 μA
Operating supply current CS = 0 V, (see Note 1, Note 2) 1.4 2.0 mA
Undervoltage Lockout
Start threshold SeeNote1 9.5 10.5 11.5
Minimum operating voltage after start 7.4 8.0 8.4 V
Hysteresis 2.1 2.5 2.9
V
Oscillator
Oscillator frequency 2 x OUTx frequency, Measured at output(s) 180 200 220 kHz
Current Sense
Current Shutdown threshold Resetting current limit 0.650 0.725 0.800 V
CS to output delay CS from 0 mV to 900 mV 45 100 ns
Output
D
e
a
d
T
i
m
e
Measured at OUTA or OUTB 90 100 110
n
s
Dead Time Over temperature 80 125 ns
Minimum duty cycle CS = 0.9 V 0 %
VOL (OUTA or OUTB) IOUT =75mA 0.5 1
V
VOH (OUTA or OUTB) IOUT =--35mA,(VDD–VOUT) 1.0 1.3
V
Output resistance high TA=25°CI
OUT = --1 mA (see Note 4) 70 80 90
TA= full range IOUT = --1 mA (see Note 4) 40 80 135
Ω
Output resistance low TA=25°CI
OUT = 1 mA (see Note 4) 6.5 7.5 8.5 Ω
TA= full range IOUT = 1 mA (see Note 4) 47.5 14
tr, Rise Time CLOAD =1nF 28 50
n
s
tf, Fall Time CLOAD =1nF 13 30 ns
SYNC
SYNC duration Measured at SYNC pin 75 95 115
tr, delay Rising SYNC until falling OUTA or OUTB 08.5 30 ns
tf, delay Falling SYNC until rising OUTA or OUTB 014 50
n
s
SYNC VOH ISYNC = --5 mA (VDD – VSYNC) 0.3 1
V
SYNC VOL ISYNC =5mA 0.3 1
V
tr, Rise Time CLOAD = 100 pF 15 30
n
s
tf, Fall Time CLOAD = 100 pF 15 30 ns
Soft Start & Fault
OUTA/OUTB start delay time Cycles as measured at CT pin 57 59 62
OUTA/OUTB soft start duration First output stage cycle to first full output stage cycle,
CS ≤0.6 V 4 5 7 cycles
NOTES: 1. Set VDD above the start threshold before setting at 9V.
2. Does not include current of the external oscillator network.
3. Ensured by design. Not 100% tested in production.
4. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resisstance is the RDS(ON)
of the MOSFET transistor when the voltage of the driver output is less than the saturation voltage of the bipolar transistor.
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
5
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FUNCTIONAL BLOCK DIAGRAM
OUTPUT LOGIC
UCC28089
6OUTB
7OUTA
8VDD
4
CS
2
DIS
1
SYNC
3
CT
5GND
VDD
UVLO
VDD = 10.5/8.0 V
VDD
OVER
CURRENT
COMP
SS LATCH
0.725 V
SS
COMP
Q
Q
S
R
+
0.2V
56 STEP
START
DELAY
R
GO 7STEPSOFT--
START RAMP
REFGO
VDD/5
SQ
QR
CK
VDD/5
VDD/19.6
QT_
Q
SOFT--START & FAULT
OSCILLATOR
UDG-04101
PIN # NAME I/O FUNCTION
1SYNC O
Active when OUTA and OUTB are active, logic LO at all other times such as during under-voltage
lock-out and over-current shutdown. When active, SYNC is logic HI (VDD) during the discharge time
of the oscillator and logic LO (GND) at all other times. The pulse occur during the dead time.
2 DIS I Separate oscillator timing capacitor discharge pin that allows the dead time to be externally
programmed.
3CT IOscillator timing capacitor connection.
4CS ICurrent sense pin. An over current shutdown event is triggered when the voltage of this pin rises
above 0.75 V.
5GND -- Ground pin. Analog and digital signals reference this pin and output drivers return current through
this pin
6OUTB ODriver output, capable of sinking 1 A and sourcing 0.5 A. OUTB signal alternates with OUTA.
7OUTA ODriver output, capable of sinking 1 A and sourcing 0.5 A. OUTA signal alternates with OUTB.
8VDD IPower input connection for this device.
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
6www.ti.com
APPLICATION INFORMATION
UCC28089 is an alternating dual-driver output oscillator with over-current and under-voltage fault protection.
This feature set is ideal as a start-up controller for isolated power systems where the majority of control functions
are performed on the secondary side. This device is especially useful for dc link for topologies such as the
cascaded buck converter [1], ac link inverter topologies [2], and inexpensive modified square wave inverters.
The UCC28089 has a brief 5 to 7 cycle leading-edge modulated soft-start cycle so that it will not interfere with
secondary-side controlled soft start. Both systems with off-line self bias and auxiliary bias supplies are more
fault tolerant with the UCC28089 because it consistently responds to a fault with a delay of at least 56 oscillator
cycles before retry.
Detailed Functional Description
VDD: Power input connection for this device. Although quiescent VDD current is very low, total supply current
is higher, depending on OUTA and OUTB current and the programmed oscillator frequency. During fault
response, the current drops to a lower level because the oscillator is disabled.
In order to avoid noise problems, position a 1-μF ceramic bypass capacitor, connected from VDD to GND, as
close to the chip as possible. The ceramic bypass capacitor is in addition to any energy storage capacitance
that would be used to hold up the VDD voltage during start-up transients.
GND: Ground pin. Analog signals reference this pin and output drivers return current through this pin. For best
results, use this pin as a local ground point in a star ground configuration.
OUTA and OUTB: Output drivers capable of sinking 1 A and sourcing 0.5 A. The output pulse alternates
between OUTA and OUTB. In addition, a T latch forces the output pulses to alternate in order to reduce flux build
up in a transformer during low duty ratio operation. Each output is capable of driving the gate of a power
MOSFET.
CT and DIS: Oscillator timing capacitor pin and timing capacitor discharge pin. The UCC28089 oscillator tracks
VDD and GND internally in order to minimize oscillator frequency changes due to variations in the voltage of
VDD. Figure 1 shows the oscillator block diagram.
2DIS
3CT
RA
RB
CT
VDD
OSCILLATOR
SQ
QR
D
VROK
CK
VDD
15.7Rx
2.90Rx
Rx
UCC28089
VDD/19.6
VDD/5
V(CT)
CK
Figure 1. Block Diagram for Oscillator
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
7
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APPLICATION INFORMATION
The recommended oscillator frequency range is up to 1 MHz. In order to avoid noise issues, RAand RBshould
be small enough for the oscillator to have at least 10 μA of current. There are two sets of oscillator programming
equations that model the oscillator over its wide programming range. Measure the charge and the discharge
times at the SYNC pin in order to avoid affecting the oscillator with probe impedances or output driver delays.
The approximate first order equations in the table are adequate for switching frequencies below 50 kHz and/or
discharge times that are greater than 1 μs. The specific requirements for using the first order equations versus
the second order equations are related to the timing capacitor size and the discharge resistor. Keep in mind that
the 1st order equations and 2nd order equations are merely approximations that are typically within +/--20% of
the actual operating point. The frequency, charge and discharge times are relatively insensitive to temperature
but larger values of CTand RBexhibit the least sensitivity to temperature. Incidentally, the second order
equations apply for the operating conditions that are in the Electrical Characteristics table. The oscillator
frequency is set according to the following equations:
1ST ORDER EQUATIONS 2ND ORDER EQUATIONS
Condition RA> 300 kΩAND CT> 300 pF 32 kΩ<R
A< 300 kΩOR 100 pF < CT< 300 pF
TCHARGE 0.169RA+RBCT0.175RA+RBCT+40 pF+20 ns
TDISCHARGE 1.36 RBCT(1.37)RB+44CT+14 pF+20 ns
fOSC 5.9
RA+8.0 RBCT
1
TCHARGE +TDISCHARGE
Where RAand RBareinOhms;C
Tis in Farads; fOSC is in Hz; tCHARGE and tDISCHARGE are in seconds.
The oscillator is optimized for a CTtiming capacitor range from 100 pF to 1000 nF and RBmore than 100 Ω.
If the shortest discharge time possible is desired, it is permissible to short DIS to CTfor all recommended CT
values (100 pF to 0.100 μF).
SYNC: This SYNC pin produces an output pulse from 0 to VDD that can be used to synchronize a secondary
side-buck controller to the free running isolating power stage. The proper timing of this signal enables zero
voltage switching on the primary side MOSFETs. The clean signal also solves a problem of getting a
synchronization signal from the secondary side of the transformer, which can have leakage inductance voltage
spikes that may cause false triggering. The SYNC pulse width is the oscillator discharge time, which is
approximately equal to the dead time. Pulse frequency is the oscillator frequency. During fault conditions, the
SYNC pulses are terminated and the SYNC output is held low for at least 56 oscillator cycles. During soft start,
SYNC precedes the first output pulse by at least one oscillator cycle.
CS: Connect the current sense device to this pin. A voltage threshold of 0.725 V triggers a shutdown sequence.
An over-current fault triggers an immediate shutdown. After the fault clears, a total of 64 oscillator cycles are
required for an entire soft start sequence to occur. First, the outputs and SYNC are kept OFF for at least 56
oscillator cycles. Next, after one or two SYNC pulses, the soft start progressively increases the output duty ratio
over the next five to seven oscillator cycles.
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
8www.ti.com
APPLICATION INFORMATION
Using the UCC28089 as the Primary-Side start-up Controller in a Cascaded Push-Pull Buck
Two-Stage Converter
The cascaded push-pull topology is ideal for converting from moderate bus voltages, such as 48-V telecom
buses, to sub 2-V output voltages. The general topology is shown in Figure 2 using the UCC28089 as the
primary-side start-up controller and the UCC2540 as the secondary-side regulator [3].
UDG-04100
CT
RB
RA
10 V
CR1 CR2
VIN =48V VO
1.2 V
2
1
4
3
7
8
5
6
UCC28089
SYNC
DIS
CT
CS
VDD
OUTA
OUTB
GND
+
--
IN OUT
COM
L.REG
2
1
4
3
19
20
17
18
UCC2540
ISET/SD
REF
G2C
SYNCIN
SWS
BST
G1
SW
6
5
8
7
RAMP
GND
VEA--
CEA--
10
9COMP
TR
15
16
13
14
VDD
PGND
G2
VDRV
11
12G2S
SS
+
--
Figure 2. Cascaded Push-Pull Buck Two-Stage Converter
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
9
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APPLICATION INFORMATION
Program the oscillator frequency of the UCC28089 to equal the desired switching frequency of the output post
regulator. The secondary-side controller may also need corresponding switching frequency programming, such
as RAMP and G2C capacitor values for the UCC2540. Program the dead time to be approximately 1/4 of the
resonant period of the equivalent parasitic L--C circuit that is established by the primary leakage inductance of
the transformer and the total drain-source capacitance of the primary-side power MOSFET transistors (COSS
+ stray capacitances). Remember that COSS predictably varies over input line voltage. If the variation is too great
and/or 1/4 the resonant period is less than 100 ns, connect additional capacitance (CR1 and CR2 in Figure 2)
between the drain and source of the primary transistors, which stabilizes the capacitance and raise the total
capacitance value.
If the secondary-side controller is compatible with pulse edges, the pulse edge transformer circuit in Figure 3
can provide an isolated pulse edge signal on the secondary side using a transformer core that is 6-mm diameter
or less. The recommended transformer (COEV #MGBBT--0001101) is compatible with all switching frequencies
and it is smaller than many opto-isolators.
UCC28089
R1
634
C1
680 pF
1
5GND
GND1
Primary Ground Secondary Ground
UCC2540
SYNCIN
REFSYNC
4
2
QCL
2N3904
T1
1:1
RCB
422
RBE
115
L1
15uH
Figure 3. Isolation and clamping the SYNC signal for Cascaded Buck Converters
Notice that the peak-pulse voltage is proportional to the UCC28089 bias voltage. The circuit in Figure 3 is well
suited to the full VDD bias voltage range of the UCC28089 bias voltage because it has a clamp circuit. The clamp
circuit in Figure 3 (RCB,R
BE and QCL)isaV
BE clamp rather than a Zener diode. A VBE clamp is used here
because it has much lower capacitance than typical Zener diodes so that the clamp does not affect the narrow
50-ns pulse width. The clamp may be replaced by a single resistor in applications, as in Figure 2, where the VDD
bias voltage of the UCC28089 is regulated within a +/--5% window.
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
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APPLICATION INFORMATION
Synchronization of Multiple UCC28089 Controllers to an External Signal
In systems where multiple UCC28089 parts need to be synchronized to a common clock, a 3.3-V logic-level
signal can be directly applied to the CT pin (the SYNC pin on UCC28089 only provides output sync signals).
As shown in Figure 4, the externally supplied sync pulse width determines the frequency and the dead time
between OUT A and OUT B. In this configuration, the discharge pin DIS should be grounded since it is not used.
The external sync signal should exceed the oscillator trip level of VDD/5 when high, and pull CT below VDD/20
when low.
UDG-04113
3.3V
OUT A
OUT B
Ext. Sync
DIS
SYNC
CT
CS GND
OUTB
OUTA
VDD
UCC28089
1
2
3
4 5
6
7
8
Ext. Sync
AppliedtoCT
U1
External Sync pulse width defines
output dead time
NC
1μF
VDD
Figure 4. Synchronizing the UCC28089 to an External Signal
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
11
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APPLICATION INFORMATION
Using the UCC28089 as a Modified Square Wave Inverter
Remote or dc-only power systems often require a limited amount of 60-Hz ac line power to supply small
appliances. Compatible loads include universal motors, incandescent lamps, and other electronic devices with
switched mode power supplies to convert the 110-VAC to lower dc voltages. Many of these devices do not require
a perfect sinusoidal line voltage, and acceptable performance can be obtained with a modified square wave
voltage. Using the circuit in Figure 5, the UCC28089 can provide the appropriate waveform along with primary
side over-current protection. Components RA, RB, and CT are selected to program the desired modified square
waveform with the appropriate dead time.
UDG-04105
CT
0.1 μF
RB
27 kΩ
RA
221 kΩ
NC
200 Ω
47 μF
12 V Bias
VIN = 145 VDC
F1
RS
4.7 μF
MPSA42 MPSA42
4.7 μF
--145 V
145 V
0V
VO
110 VAC(rms) 16.7 ms
NOTE: CS signal should be selected to limit peak inrush current to acceptable levels.
1N4003
2
1
4
3
7
8
5
6
UCC28089
SYNC
DIS
CT
CS
VDD
OUTA
OUTB
GND
+
--
6800 pF
6800 pF
50 Ω
200 Ω
200 Ω
50 Ω
200 Ω
20 Ω
Figure 5. Modified Square Wave Inverter
The high-side gate drives of the inverter in Figure 5 are suitable for low frequency applications with relatively
constant duty ratio. The NPN transistors and the charge pump diodes on the high-side gate drives must be rated
for high voltage (at least 145 V + VDD). The gates are protected from excessive negative voltage by the diodes
shown from gate to source.
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
12 www.ti.com
APPLICATION INFORMATION
If desired, the 60-Hz modified square wave inverter frequency could be programmed using an external sync
signal that might originate from a separate oscillator or digital controller. The following diagram in Figure 6 shows
a 50% duty cycle square wave fed into the CT pin, with a frequency of 120 Hz, and the resulting OUTA/OUTB
wave shapes.
3.3 V
OUT A
OUT B
Ext. Sync
DIS
SYNC
CT
CS GND
OUTB
OUTA
VDD
UCC28089
1
2
3
4 5
6
7
8
Ext. Sync
U1
External Sync example with 50% duty cycle
NC
8.33 ms
16.7 ms VDD
1μF
Figure 6. External Synchronization Example with 50% Duty Cycle Square Wave
RELATED PRODUCTS
DEVICE DESCRIPTION
UCC2540 High-Efficiency Secondary-Side Synchronous-Buck PWM Controller
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
13
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TYPICAL CHARACTERISTICS
Figure 7
OSCILLATOR FREQUENCY
vs
TEMPERATURE
fs-- Oscillator Frequency-- kHz
Tj -- Temperature -- °C
--50 50
190
180
25 100
750-- 2 5
185
195
210
200
205
215
220
RA=110kΩ
RB= 182 Ω
CT= 220 pF
Figure 8
Tj -- Temperature -- °C
--50 50 125
98
94
25 100750-- 2 5
96
100
106
102
104
108
110
90
92
OSCILLATOR FREQUENCY
vs
TEMPERATURE
fs-- Oscillator Frequency-- kHz
RA= 221 kΩ
RB=3.32Ω
CT= 220 pF
Figure 9
Tj -- Temperature -- °C
--50 50 125
--1.0%
--2.0%
25 100750-- 2 5
--1.5%
--0.5%
1.0%
0.0%
0.5%
1.5%
2.0%
OSCILLATOR FREQUENCY SHIFT
vs
TEMPERATURE
fs-- Normalized to 25°C-- kHz
RA=110kΩ
RB= 182 Ω
CT= 220 pF
RA= 221 kΩ
RB=3.32Ω
CT= 220 pF
VDD = 9 V
Figure 10
OSCILLATOR FREQUENCY SHIFT
vs
SUPPLY VOLTAGE
f -- Frequency, Normalized -- %
VDD -- Supply Voltage -- V
81215
0.0%
--0.5%
11 1413109
0.5%
1.5%
1.0%
2.0%
RA=110kΩ
RB= 182 Ω
CT= 220 pF
RA= 221 kΩ
RB=3.32Ω
CT= 220 pF
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
14 www.ti.com
TYPICAL CHARACTERISTICS
Figure 11
OSCILATOR FREQUENCY
vs
RA x CT
fOSC -- Oscilator Frequensy -- Hz
RA x CT -- s
10 M
1M
100 K
10 K
1K
100
1M
RA= 76.8 kΩ
RB=0Ω
VDD = 10 V
10 μ100 μ1μ
Figure 12
DISCHARGE TIME
vs
CT
Tdischarge -- Discharge Time-- s
CT-- Farad
100 P 10 n
100 n
10 n
1 n 100 n
RA= 76.8 kΩ
RB=0Ω
VDD = 10 V
1μ
1μ
10 μ
Figure 13
SYNC PULSE WIDTH
vs
TEMPERATURE
SYNC -- Pulse Width-- ns
Tj -- Temperature -- °C
--50 50 125
85
75
25 100750-- 2 5
80
90
105
95
100
110
115
RA=110kΩ
RB= 182 Ω
CT= 220 pF
Figure 14
OUTPUT DEAD TIME
vs
TEMPERATURE
TO-- Output Dead Time -- ns
Tj -- Temperature -- °C
--50 50 125
95
90
25 100750-- 2 5
100
115
105
110
120
125
80
85
RA=110kΩ
RB= 182 Ω
CT= 220 pF
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
15
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Figure 15
PROPAGATION DELAY (SYNC RISE TO OUTPUT FALL)
vs
TEMPERATURE
Tprop(f) -- Propagation Delay-- ns
Tj -- Temperature -- °C
--50 50 125
7
5
25 100750-- 2 5
6
8
11
9
10
12
Figure 16
Tj -- Temperature -- °C
10
5
20
15
25
--50 50 12525 100750-- 2 5
PROPAGATION DELAY (SYNC FALL TO OUTPUT RISE)
vs
TEMPERATURE
Tprop(f) -- Propagation Delay-- ns
Figure 17
OSCILLATOR DISCHARGE ON-RESISTANCE
vs
TEMPERATURE
RDS(on) -- Oscillator Discharge FET On Resistance-- Ω
Tj -- Temperature -- °C
50
45
35
30
25
--50 50 12525 100750-- 2 5
40
vDIS =1.5V
VCT =3.0V
Figure 18
CURRENT SENSE THRESHOLD
vs
TEMPERATURE
CS -- Current Sense Threshold-- mV
Tj -- Temperature -- °C
--50 50 12525 100750-- 2 5
810
770
710
690
650
750
670
730
790
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
16 www.ti.com
TYPICAL CHARACTERISTICS
Figure 19
SUPPLY CURRENT
vs
OSCILLATOR FREQUENCY (NO LOAD)
IDD -- Supply Current -- mA
fOSC -- Oscillator Frequency -- kHz
0 600 K 1 M
1.0
800 K400 K200 K
1.5
2.0
3.0
2.5
3.5
4.0
VDD =14V
VDD =12V
VDD =9V
Figure 20
0 600 K 1 M
6
4
400 K 800 K200 K
8
14
10
12
16
18
0
2
SUPPLY CURRENT
vs
OSCILLATOR FREQUENCY (1 nF LOADS)
IDD -- Supply Current -- mA
fOSC -- Oscillator Frequency -- kHz
VDD =14V
VDD =12V
VDD =9V
Figure 21
t -- Time -- 1 ms/div.
OUTA
OUTB
SYNC
CT
TYPICAL SOFT START WAVEFORMS
Figure 22
t -- Time -- 1 ms/div.
OUTA
OUTB
SYNC
CT
T
Y
PIC
A
LO
V
ER
A
LL ST
A
RT--UP W
A
V
EFORMS
UCC28089
SLUS623A -- SEPTEMBER 2004 -- REVISED AUGUST 2006
17
www.ti.com
REFERENCES
1. Power Supply Seminar SEM--1300 Topic 1: Unique Cascaded Power Converter Topology for High Current
Low Output Voltage Applications, by L. Balogh, C. Bridge and B. Andreycak, Texas Instruments Literature
No. SLUP133
2. Low Cost Inverter Suitable for Medium-Power Fuel Cell Sources, by P.T. Krein and R Balog, IEEE Power
Electronics Specialists Conference Proceedings, 2002, vol. 1, pp. 321--326.
3. Datasheet, UCC2540 High-Efficiency Secondary-Side Synchronous-Buck PWM Controller, Texas
Instruments Literature No. SLUS539
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UCC28089D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28089DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28089DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC28089DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC28089DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC28089DR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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