LTC3805EMSE#TR - Linear Technology Corporation

LTC3805

3805fg

Features

applications

Description

Adjustable Frequency

Current Mode Flyback

DC/DC Controller

The LT C

3805 is a current mode controller for flyback

DC/DC converters designed to drive an N-channel MOSFET

in high input and output voltage converter applications.

Operating frequency and slope compensation can be

programmed by external resistors. Programmable overcur-

rent sensing protects the converter from short-circuits.

Soft-start can be programmed using an external capacitor

and the soft-start capacitor also programs an automatic

restart feature.

The LTC3805 provides ±1.5% output voltage accuracy

and consumes only 360µA of quiescent current during

normal operation and only 40µA during micropower start-

up. Using a 9.5V internal shunt regulator, the LTC3805

can be powered from a high VIN through a resistor or it

can be powered directly from a low impedance DC voltage

of 9V or less.

The LTC3805 is available in the 10-lead MSOP package

and the 3mm × 3mm DFN package.

36V – 72V to 5V/2A Nonisolated Flyback Converter

n VIN and VOUT Limited Only by External Components

n Adjustable Slope Compensation

n Adjustable Overcurrent Protection with Automatic

Restart

n Adjustable Operating Frequency (70kHz to 700kHz)

with One External Resistor

n Synchronizable to an External Clock

n ±1.5% Reference Accuracy

n Current Mode Operation for Excellent Line and Load

Transient Response

n RUN Pin with Precision Threshold and Adjustable

Hysteresis

n Programmable Soft-Start with One External Capacitor

n Low Quiescent Current: 360µA

n Small 10-Lead MSOP and 3mm × 3mm DFN

n Telecom Power Supplies

n 42V and 12V Automotive Power Supplies

n Isolated Electronic Equipment

LTC3805

GND

ITH

RUN GATE

ISENSE

SSFLT

FS FB

VCC

118k

68mΩ

2.2µF

×2

22µF

SYNC

1.33k

8.66k

221k 100k

VIN

36V TO

72V

VOUT

AT 2A

13.7k

71.5k

100µF

× 2

3805 TA01a

0.1µF

20k

470pF LOAD CURRENT (A)

0.01

EFFICIENCY (%)

POWER LOSS (W)

0.1 1

3805 TA01b

100 10

0.1

VIN = 48V

LOSS

EFFICIENCY

Efficiency and Power Loss

vs Load Current; VO = 5V

typical application

L,LT , LT C , LT M , Burst Mode, Linear Technology and the Linear logo are registered trademarks,

No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

LTC3805

3805fg

absolute MaxiMuM ratings

VCC to GND

Low Impedance Source ........................ –0.3V to 8.8V

Current Fed ........................................25mA into VCC*

SYNC ........................................................... –0.3V to 6V

SSFLT........................................................... –0.3V to 5V

FB, ITH, FS ................................................. –0.3V to 3.5V

RUN ........................................................... –0.3V to 18V

(Note 1)

TOP VIEW

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

1GATE

VCC

ISENSE

SYNC

SSFLT

ITH

RUN

TJMAX = 125°C, θJA = 45°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE CONNECTED TO GND

SSFLT

ITH

RUN

GATE

VCC

ISENSE

SYNC

TOP VIEW

MSE PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 150°C, θJA = 45°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE CONNECTED TO GND

OC, ISENSE .................................................... –0.3V to 1V

Operating Junction Temperature Range

(Notes 2, 3) ............................................ –55°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MSE Package .................................................... 300°C

*LTC3805 internal clamp circuit regulates VCC voltage to 9.5V

orDer inForMation

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3805EDD#PBF LTC3805EDD#TRPBF LCJM 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LTC3805IDD#PBF LTC3805IDD#TRPBF LCJM 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LTC3805EMSE#PBF LTC3805EMSE#TRPBF LTCJK 10-Lead Plastic MSOP –40°C to 85°C

LTC3805IMSE#PBF LTC3805IMSE#TRPBF LTCJK 10-Lead Plastic MSOP –40°C to 125°C

LTC3805HMSE#PBF LTC3805HMSE#TRPBF LTCJK 10-Lead Plastic MSOP –40°C to 150°C

LTC3805MPMSE#PBF LTC3805MPMSE#TRPBF LTCJK 10-Lead Plastic MSOP –55°C to 150°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3805EDD LTC3805EDD#TR LCJM 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LTC3805IDD LTC3805IDD#TR LCJM 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LTC3805EMSE LTC3805EMSE#TR LTCJK 10-Lead Plastic MSOP –40°C to 85°C

LTC3805IMSE LTC3805IMSE#TR LTCJK 10-Lead Plastic MSOP –40°C to 125°C

LTC3805HMSE LTC3805HMSE#TR LTCJK 10-Lead Plastic MSOP –40°C to 150°C

LTC3805MPMSE LTC3805MPMSE#TR LTCJK 10-Lead Plastic MSOP –55°C to 150°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

pin conFiguration

LTC3805

3805fg

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VTURNON VCC Turn-On Voltage l7.75 8.4 9 V

VTURNOFF VCC Turn-Off Voltage l3.75 3.95 4.15 V

VHYST VCC Hysteresis 4.5 V

VCLAMP1mA VCC Shunt Regulator Voltage VCC Sinking 1mA, VRUN = 0 l8.8 9.25 9.65 V

VCLAMP25mA VCC Shunt Regulator Voltage VCC Sinking 25mA, VRUN = 0 l8.9 9.5 9.9 V

ICC Input DC Supply Current Normal Operation (fOSC = 200kHz)

(Note 4)

360 µA

VRUN < VRUNON or VCC < VTURNON – 100mV

(Micropower Start-Up)

l40 90 µA

VRUNON RUN Turn-On Voltage VCC Sinking 1mA l1.122 1.207 1.292 V

VRUNOFF RUN Turn-Off Voltage VCC Sinking 1mA l1.092 1.170 1.248 V

IRUN(HYST) RUN Hysteresis Current l4 5 5.8 µA

VFB Regulated Feedback Voltage 0°C ≤ TJ ≤ 85°C (E-Grade) (Note 5)

–40°C ≤ TJ ≤ 85°C (E-Grade) (Note 5)

–40°C ≤ TJ ≤ 125°C (I-Grade) (Note 5)

–40°C ≤ TJ ≤ 150°C (H-Grade) (Note 5)

–55°C ≤ TJ ≤ 150°C (MP-Grade)

0.788

0.780

0.770

0.800

0.812

0.820

IFB VFB Input Current VITH = 1.3V (Note 5) 20 nA

gmError Amplifier Transconductance ITH Pin Load = ±5µA (Note 5) 333 µA/V

∆VO(LINE) Output Voltage Line Regulation VTURNOFF < VCC < VCLAMP1mA (Note 5) 0.05 mV/V

∆VO(LOAD) Output Voltage Load Regulation ITH Sinking 5µA (Note 5)

ITH Sourcing 5µA (Note 5)

mV/µA

fOSC Oscillator Frequency RFS = 350k 70 kHz

RFS = 36k 700 kHz

DCON(MIN) Minimum Switch-On Duty Cycle fOSC = 200kHz 6 9 %

DCON(MAX) Maximum Switch-On Duty Cycle fOSC = 200kHz 70 80 95 %

fSYNC As a Function of fOSC 70kHz < fOSC < 700kHz,

70kHz < fSYNC < 700kHz

67 133 %

VSYNC Minimum SYNC Amplitude 2.9 V

ISS Soft-Start Current –6 µA

IFTO Fault Timeout Current 2 µA

tSS(INT) Internal Soft-Start Time No External Capacitor on SSFLT 1.8 ms

tFTO(INT) Internal Fault Timeout No External Capacitor on SSFLT 4.5 ms

tRISE Gate Drive Rise Time CLOAD = 3000pF 30 ns

tFALL Gate Drive Fall Time CLOAD = 3000pF 30 ns

VI(MAX) Peak Current Sense Voltage RSL = 0 (Note 6) l85 100 115 mV

ISL(MAX) Peak Slope Compensation Output

Current

(Note 7) 10 µA

VOCT Overcurrent Threshold ROC = 0 (Note 8) l85 100 115 mV

IOC Overcurrent Threshold Adjust Current 10 µA

electrical characteristics

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C, VCC = 8V, unless otherwise noted (Note 2).

LTC3805

3805fg

electrical characteristics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3805 is tested under pulsed conditions such that TJ ≈ TA.

The LTC3805E is guaranteed to meet specifications from 0°C to 85°C.

Specifications over the –40°C to 85°C operating junction temperature

range are assured by design, characterization and correlation with

statistical process controls. The LTC3805I is guaranteed over the –40°C to

125°C operating junction temperature range, the LTC3805H is guaranteed

over the full –40°C to 150°C operating junction temperature range, and

the LTC3805MP is tested and guaranteed over the full –55°C to 150°C

operating temperature range. High junction temperatures degrade

operating lifetimes. Operating lifetime is derated at junction temperatures

greater than 125°C. Note that the maximum ambient temperature

consistant with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

resistance and other environmental factors.

Note 3: TJ is calculated from the ambient temperature TA and power

dissipation PD according to the following formula:

TJ = TA + (PD • 45°C/W)

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 5: The LTC3805 is tested in a feedback loop that servos VFB to the

output of the error amplifier while maintaining ITH at the midpoint of the

current limit range.

Note 6: Peak current sense voltage is reduced dependent on duty cycle

and an optional external resistor in series with the SENSE pin. For

details, refer to Programmable Slope Compensation in the Applications

Information section.

Note 7: Guaranteed by design.

Note 8: Overcurrent threshold voltage is reduced dependent on an

optional external resistor in series with the OC pin. For details, refer to

Programmable Overcurrent in the Applications Information section.

LTC3805

3805fg

TEMPERATURE (°C)

–75 –50

788

VFB VOLTAGE (mV)

792

800

808

796

804

812

–25 0 25 50

3805 G01

75 100 125 150

Reference Voltage

vs Temperature

Reference Voltage

vs Supply Voltage

Oscillator Frequency vs RFS

Oscillator Frequency

vs Supply Voltage

Oscillator Frequency

vs Temperature

RUN Undervoltage Lockout

Thresholds vs Temperature

RUN Hysteresis Current

vs Temperature

VCC Undervoltage Lockout

Thresholds vs Temperature

Start-Up ICC Supply Current

vs Temperature

typical perForMance characteristics

RFS (kΩ)

fOSC (kHz)

400

500

600

400

3805 G03

300

200

0100 200 300

100

800

700

VCC (V)

0.799700

(V)

0.799800

0.799900

0.800000

0.800100

0.800200

0.800300

6 85 7 9 10

3805 G02

VCC (V)

201

202

203

3805 G04

200

199

5 6 7 9

198

197

196

fOSC (kHz)

RFS = 124kΩ

TEMPERATURE (°C)

–75 –50

198

OSCILLATOR FREQUENCY (kHz)

199

200

201

202

–25 0 25 50

3805 G05

75 100 125 150

RFS = 124kΩ

TEMPERATURE (°C)

–75 –50

1.170

RUN VOLTAGE (V)

1.175

1.185

1.195

1.180

1.190

1.200

1.205

–25 0 25 50

3805 G06

75 100 125 150

VRUN(ON)

VRUN(OFF)

TEMPERATURE (°C)

–75 –50

4.70

IRUN(HYST)

4.80

5.00

4.90

5.10

5.20

–25 0 25 50

3805 G07

75 100 125 150

TEMPERATURE (°C)

–75 –50

3.50

VCC UNDERVOLTAGE LOCKOUT (V)

4.50

6.50

8.50

5.50

7.50

9.50

–25 0 25 50

3805 G08

75 100 125 150

VTURN(ON)

VTURN(OFF)

TEMPERATURE (°C)

–75 –50

START-UP SUPPLY CURRENT (µA)

–25 0 25 50

3805 G09

75 100 125 150

LTC3805

3805fg

typical perForMance characteristics

External Soft-Start Current

vs Temperature

External Timeout Current

vs Temperature

TEMPERATURE (°C)

–75 –50

4.4

4.5

ISS SOFT-START CURRENT (µA)

4.6

4.8

5.0

4.7

4.9

5.1

5.2

5.3

–25 0 25 50

3805 G15

75 100 125 150

TEMPERATURE (°C)

–75 –50

1.5

IFTO EXTERNAL TIMEOUT CURRENT (µA)

1.6

1.8

2.0

1.7

1.9

2.1

–25 0 25 50

3805 G16

75 100 125 150

Peak Current Sense Voltage

vs Temperature

Overcurrent Threshold

vs Temperature

Internal Soft-Start Time

vs Temperature

TEMPERATURE (°C)

–75 –50

99.0

PEAK CURRENT SENSE VOLTAGE (mV)

99.2

99.6

100.0

99.4

99.8

100.2

100.4

100.8

100.6

–25 0 25 50

3805 G12

75 100 125

150

TEMPERATURE (°C)

–75 –50

OVERCURRENT THRESHOLD (mV)

100

102

104

–25 0 25 50

3805 G13

75 100 125 150

TEMPERATURE (°C)

–75 –50

1.90

INTERNAL SOFT-START TIME (ms)

1.95

2.05

2.15

2.00

2.10

2.20

–25 0 25 50

3805 G14

75 100 125 150

ICC Supply Current

vs Temperature

VCC Shunt Regulator Voltage

vs Temperature

TEMPERATURE (°C)

–75 –50

300

SUPPLY CURRENT (µA)

310

330

320

340

350

–25 0 25 50

3805 G10

75 100 125 150

TEMPERATURE (°C)

–75 –50

9.20

VCLAMP (V)

9.25

9.35

9.45

9.30

9.40

9.50

9.55

9.60

–25 0 25 50

3805 G11

75 100 125

150

VCLAMP25mA

VCLAMP1mA

LTC3805

3805fg

block DiagraM

SSFLT (Pin 1): Soft-Start Pin. A capacitor placed from

this pin to GND (Exposed Pad) controls the rate of rise of

converter output voltage during start-up. This capacitor is

also used for time out after a fault prior to restart.

ITH (Pin 2): Error Amplifier Compensation Point. Normal

operating voltage range is clamped between 0.7V and 1.9V.

FB (Pin 3): Receives the feedback voltage from an external

resistor divider across the output.

RUN (Pin 4): An external resistor divider connects this

pin to VIN and sets the thresholds for converter operation.

FS (Pin 5): A resistor connected from this pin to ground

sets the frequency of operation.

SYNC (Pin 6): Input to synchronize the oscillator to an

external source.

ISENSE (Pin 7): Performs two functions: for current mode

control, it monitors the switch current, using the voltage

across an external current sense resistor. Pin 7 also injects

a current ramp that develops slope compensation voltage

across an optional external programming resistor.

OC (Pin 8): Overcurrent Pin. Connect this pin to the ex-

ternal switch current sense resistor. An additional resistor

programs the overcurrent trip level.

VCC (Pin 9): Supply Pin. A capacitor must closely decouple

VCC to GND (Exposed Pad).

GATE (Pin 10): Gate Drive for the External N-channel

MOSFET. This pin swings from GND to VCC.

GND (Exposed Pad Pin 11): Ground. A capacitor must

closely decouple GND to VCC (Pin 9). The exposed pad

must be soldered to electrical ground on PCB for electrical

contact and rated thermal performance.

–

SLOPE

COMP

CURRENT

RAMP

VCC RUN

GATE

DRIVER GATE

ISENSE

3805 BD

OSCILLATOR

CURRENT

COMPARATOR

OVERCURRENT

COMPARATOR

SHUTDOWN

ITH CLAMPS

20mV

ITH

ERROR

AMPLIFIER

SOFT-START RAMP

10µA

100mV

SWITCHING

LOGIC AND

BLANKING

CIRCUIT

SSFLT

GND

1.2V

2SYNCFS

5 6

9 4

UNDERVOLTAGE

LOCKOUT

800mV

REFERENCE

SOFT-START

FAULT

pin Functions

LTC3805

3805fg

operation

The LTC3805 is a programmable-frequency current mode

controller for flyback, boost and SEPIC DC/DC converters.

The LTC3805 is designed so that none of its pins need

to come in contact with the input or output voltages of

the power supply circuit of which it is a part, allowing the

conversion of voltages well beyond the LTC3805’s absolute

maximum ratings.

Main Control Loop

Please refer to the Block Diagram of this data sheet and

the Typical Application shown on the front page. An ex-

ternal resistive voltage divider presents a fraction of the

output voltage to the FB pin. The divider is designed so

that when the output is at the desired voltage, the FB pin

voltage equals the 800mV internal reference voltage. If

the load current increases, the output voltage decreases

slightly, causing the FB pin voltage to fall below the 800mV

reference. The error amplifier responds by feeding current

into the ITH pin causing its voltage to rise. Conversely, if

the load current decreases, the FB voltage rises above the

800mV reference and the error amplifier sinks current away

from the ITH pin causing its voltage to fall.

The voltage at the ITH pin controls the pulse-width modula-

tor formed by the oscillator, current comparator and SR

latch. Specifically, the voltage at the ITH pin sets the current

comparator’s trip threshold. The current comparator’s

ISENSE input monitors the voltage across an external cur-

rent sense resistor in series with the source of the external

MOSFET. At the start of a cycle, the LTC3805’s oscillator

sets the SR latch and turns on the external power MOSFET.

The current through the external power MOSFET rises as

does the voltage on the ISENSE pin. The LTC3805’s cur-

rent comparator trips when the voltage on the ISENSE pin

exceeds a voltage proportional to the voltage on the ITH pin.

This resets the SR latch and turns off the external power

MOSFET. In this way, the peak current levels through the

external MOSFET and the flyback transformer’s primary

and secondary windings are controlled by the voltage on

the ITH pin. If the current comparator does not trip, the

LTC3805 automatically limits the duty cycle to 80%, resets

the SR latch, and turns off the external MOSFET.

The path from the FB pin, through the error amplifier,

current comparator and the SR latch implements the

closed-loop current mode control required to regulate the

output voltage against changes in input voltage or output

current. For example, if the load current increases, the

output voltage decreases slightly, and sensing this, the

error amplifier sources current from the ITH pin, raising

the current comparator threshold, thus increasing the peak

currents through the transformer primary and secondary.

This delivers more current to the load and restores the

output voltage to the desired level.

The ITH pin serves as the compensation point for the control

loop. Typically, an external series RC network is connected

from ITH to ground and is chosen for optimal response to

load and line transients. The impedance of this RC network

converts the output current of the error amplifier to the

ITH voltage which sets the current comparator threshold

and commands considerable influence over the dynamics

of the voltage regulation loop.

LTC3805

3805fg

Figure 1. Start-Up/Shutdown State Diagram

LTC3805

SHUTDOWN

LTC3805

FAULT

TIMEOUT

3805 F01

VRUN > VRUNON

AND VCC > VTURNON

VRUN < VRUNOFF

VCC < VTURNOFF

VSSFLT < 0.7V VOC > 100mV

LTC3805

ENABLED

operation

Start-Up/Shutdown

The LTC3805 has two shutdown mechanisms to disable

and enable operation: an undervoltage lockout on the VCC

supply pin voltage, and a precision-threshold RUN pin. The

voltage on both pins must exceed the appropriate thresh-

old before operation is enabled. The LTC3805 transitions

into and out of shutdown according to the state diagram

shown in Figure 1. Operation in fault timeout is discussed

in a subsequent section. During shutdown the LTC3805

draws only a small 40µA current.

The undervoltage lockout (UVLO) mechanism prevents

the LTC3805 from trying to drive the external MOSFET

gate with insufficient voltage on the VCC pin. The voltage

at the VCC pin must initially exceed VTURNON = 8.4V to

enable LTC3805 operation. After operation is enabled, the

voltage on the VCC pin may fall as low as VTURNOFF = 4V

before undervoltage lockout disables the LTC3805. This

wide UVLO hysteresis range supports the use of trickle

charger powering schemes. See the Applications Informa-

tion section for more detail.

The RUN pin is connected to the input voltage using a

voltage divider. Converter operation is enabled when the

voltage on the RUN pin exceeds VRUNON = 1.207V and

disabled when the voltage falls below VRUNOFF = 1.170V.

Additional hysteresis is added by a 5µA current source

acting on the voltage divider’s Thevenin resistance. Setting

the input voltage range and hysteresis is further discussed

in the Applications Information section.

Setting the Oscillator Frequency

Connect a frequency set resistor RFS from the FS pin to

ground to set the oscillator frequency over a range from

70kHz to 700kHz. The oscillator frequency is calculated

from:

fOSC =24 •109

RFS −1500

The oscillator may be synchronized to an external clock

using the SYNC input. The rising edge of the external clock

on the SYNC pin triggers the beginning of a switching

period, i.e., the GATE pin going high. The pulse width of

the external clock is quite flexible.

Overcurrent Protection

With the OC pin connected to the external MOSFET’s current

sense resistor, the converter is protected in the event of

an overload or short-circuit on the output. During normal

operation the peak value of current in the external MOS-

FET, as measured by the current sense resistor (plus any

adjustment for slope compensation), is set by the voltage

on the ITH pin operating through the current comparator.

As the output current increases, so does the voltage on

the ITH pin and so does the peak MOSFET current.

LTC3805

3805fg

operation

First, consider operation without overcurrent protection.

For some maximum converter output current, the voltage

on the ITH pin rises to and is clamped at approximately 1.9V.

This corresponds to a 100mV limit on the voltage at the

ISENSE pin. As the output current is further increased, the

duty cycle is reduced as the output voltage sags. However,

the peak current in the external MOSFET is limited by the

100mV threshold at the ISENSE pin.

As the output current is increased further, eventually,

the duty cycle is reduced to the 6% minimum. Since the

external MOSFET is always turned on for this minimum

amount of time, the current comparator no longer limits

the current through the external MOSFET based on the

100mV threshold. If the output current continues to in-

crease, the current through the MOSFET could rise to a

level that would damage the converter.

To prevent damage, the overcurrent pin, OC, is also

connected to the current sense resistor, and a fault is

triggered if the voltage on the OC pin exceeds 100mV. To

protect itself, the converter stops operating as described

in the next section. External resistors can be used to ad-

just the overcurrent threshold to voltages higher or lower

than 100mV as described in the Applications Information

section.

Soft-Start and Fault Timeout Operation

The soft-start and fault timeout of the LTC3805 uses either

a fixed internal timer or an external timer programmed

by a capacitor from the SSFLT pin to GND. The internal

soft-start and fault timeout times are minimums and can

be increased by placing a capacitor from the SSFLT pin

to GND. Operation is shown in Figure 1.

Leave the SSFLT pin open to use the internal soft-start and

fault timeout. The internal soft-start is complete in about

1.8ms. In the event of an overcurrent as detected by the

OC pin exceeding 100mV, the LTC3805 shuts down and

an internal timing circuit waits for a fault timeout of about

4.25ms and then restarts the converter.

Add a capacitor CSS from the SSFLT pin to GND to increase

both the soft-start time and the time for fault timeout. Dur-

ing soft-start, CSS is charged with a 6µA current. When the

LTC3805 comes out of shutdown, the LTC3805 quickly

charges CSS to about 0.7V at which point GATE begins

switching. From that point, GATE continues

switching with

increasing duty cycle until the SSFLT pin reaches about

2.25V at which point soft-start is over and closed-loop

regulation begins. The voltage on the SSFLT pin addition-

ally further charges to about 4.75V.

CSS also performs the timeout function in the event of a

fault. After a fault, CSS is slowly discharged from about

4.75V to about 0.7V by a 2µA current. When the voltage

on the SSFLT pin reaches 0.7V the converter attempts to

restart. More detail on programming the external soft-start

fault timeout is described in the Applications Information

section.

Powering the LTC3805

A built-in shunt regulator from the VCC pin to GND limits

the voltage on the VCC pin to approximately 9.5V as long

as the shunt regulator is not forced to sink more than

25mA. The shunt regulator is always active, even when

the LTC3805 is in shutdown, since it serves the vital func-

tion of protecting the VCC pin from overvoltage. The shunt

regulator permits the use of a wide variety of powering

schemes for the LTC3805 even from high voltage sources

that exceed the LTC3805’s absolute maximum ratings.

Further details on powering schemes are described in the

Applications Information section.

Adjustable Slope Compensation

The LTC3805 injects a 10µA peak current ramp out of

its ISENSE pin which can be used, in conjunction with an

external resistor, for slope compensation in designs that

require it. This current ramp is approximately linear and

begins at zero current at 6% duty cycle, reaching peak

current at 80% duty cycle. Additional details are provided

in the Applications Information section.

LTC3805

3805fg

applications inForMation

Many LTC3805 application circuits can be derived from

the topology shown on the first page of this data sheet

and from the topology shown in Figure 2.

The LTC3805 itself imposes no limits on allowed input volt-

age VIN or output voltage VOUT. These are all determined

by the ratings of the external power components. The

factors are: Q1 maximum drain-source voltage (BVDSS),

on-resistance (RDS(ON)) and maximum drain current, T1

saturation flux level and winding insulation breakdown

voltages, CIN and COUT maximum working voltage, equiva-

lent series resistance (ESR), and maximum ripple current

ratings, and D1 and RSENSE power ratings.

VCC Bias Power

The VCC pin must be bypassed to the GND pin with a

minimum 1µF ceramic or tantalum capacitor located im-

mediately adjacent to the two pins. Proper supply bypassing

is necessary to supply the high transient currents required

by the MOSFET gate driver.

For maximum flexibility, the LTC3805 is designed so that it

can be operated from voltages well beyond the LTC3805’s

absolute maximum ratings. Figure 2 shows the simplest

case, in which the LTC3805 is powered with a resistor

RVCC connected between the input voltage and VCC. The

built-in shunt regulator limits the voltage on the VCC pin

to around 9.5V as long as the internal shunt regulator is

not forced to sink more than 25mA. This powering scheme

has the drawback that the power loss in the resistor re-

duces converter efficiency and the 25mA shunt regulator

maximum may limit the maximum-to-minimum range of

input voltage.

In some cases, the input or output voltage is within the

operational range of VCC for the LTC3805. In this case,

the LTC3805 is operated directly from either the input

or output voltage. Figure 3 shows a 5V output converter

in which RSTART and CVCC form a start-up trickle charger

while D2 powers VCC from the output once the converter

is in normal operation. Note that RSTART need only supply

the very small 40µA micropower start-up current while

Figure 3. Powering the LTC3805 from the Output

LTC3805

ITH

GND

SSFLT

RUN

GATE

ISENSE

SYNC

VCC

RFS

118k

RSLOPE

RSENSE

68mΩ

CIN

2.2µF

× 2 CVCC

22µF

ROC

1.33k

SECPRI

8.66k

221k

RSTART

100k

VIN

36V TO 72V

VOUT

5V AT 2A

RITH

20k

CITH

470pF

CSS

0.1µF

13.7k

71.5k COUT

100µF

× 2

3805 F02

Figure 2. Powering the LTC3805 via the

Internal Shunt Regulator

LTC3805

VCC

RVCC

CVCC

3805 F02

VIN

GND

LTC3805

3805fg

applications inForMation

CVCC is charged to VTURNON. At this point, assuming VRUN

> VRUNON, the converter begins switching the external

MOSFET and ramps up the converter output voltage at

a rate set by the capacitor CSS on the SSFLT pin. Since

RSTART cannot supply enough current to operate the ex-

ternal MOSFET, CVCC begins discharging and VCC drops.

The soft-start must be fast enough and the discharge of

CVCC slow enough so that the output voltage reaches its

target value of 5V before VCC drops to VTURNOFF or the

converter would fail to start.

The typical application circuit in Figure 9 shows a different

flyback converter bias power strategy for a case in which

neither the input or output voltage is suitable for provid-

ing bias power to the LTC3805. A small NPN preregulator

transistor and a Zener diode are used to accelerate the

rise of VCC and reduce the value of the VCC bias capacitor.

The flyback transformer has an additional bias winding to

provide bias power. Note that this topology is very power-

ful because, by appropriate choice of transformer turns

ratio, the output voltage can be chosen without regard to

the value of the input voltage or the VCC bias power for

the LTC3805. The number of turns in the bias winding is

chosen according to

NBIAS =NSEC

VCC

VD4

VOUT −VD1

where NBIAS is the number of turns in the bias winding,

NSEC is the number of turns in the secondary winding,

VCC is the desired voltage to power the LTC3805, VOUT is

the converter output voltage, VD1 is the forward voltage

drop of D1 and VD4 is the forward voltage drop of D4.

Note that since VOUT is regulated by the converter control

loop, VCC is also regulated although not as precisely. The

value of VCC is often constrained since NBIAS and NSEC are

often a limited range of small integer numbers. For proper

operation, the value of VCC must be between VTURNON and

VTURNOFF. Since the ratio of VTURNON to VTURNOFF is over

two to one, this requirement is relatively easy to satisfy.

Figure 9 shows a similar low power nonisolated telecom

converter using a trickle charger.

Transformer Design Considerations

Transformer specification and design is perhaps the

most critical part of applying the LTC3805 successfully.

In addition to the usual list of caveats dealing with high

frequency power transformer design, the following should

prove useful.

Turns Ratios

Due to the use of the external feedback resistor divider

ratio to set output voltage, the user has relative freedom

in selecting transformer turns ratio to suit a given ap-

plication. Simple ratios of small integers, e.g., 1:1, 2:1,

3:2, etc. can be employed which yield more freedom in

setting total turns and transformer inductance. Simple

integer turns ratios also facilitate the use of “off-the-shelf”

configurable transformers. Turns ratio can be chosen on

the basis of desired duty cycle. However, remember that

the input supply voltage plus the secondary-to-primary

referred version of the flyback pulse (including leakage

spike) must not exceed the allowed external MOSFET

breakdown rating.

LTC3805

3805fg

Figure 4. Setting RUN Pin Voltage and Run/Stop Control

LTC3805

RUN

RUN/STOP

CONTROL

(OPTIONAL)

GND 3805 F04

VIN

applications inForMation

Leakage Inductance

Transformer leakage inductance (on either the primary

or secondary) causes a voltage spike to occur after the

MOSFET (Q1) turn-off. This is increasingly prominent at

higher load currents, where more stored energy must be

dissipated. In some cases an RC “snubber” circuit will be

required to avoid overvoltage breakdown at the MOSFET’s

drain node. Application Note 19 is a good reference on

snubber design. A bifilar or similar winding technique is a

good way to minimize troublesome leakage inductances.

However, remember that this will limit the primary-to-

secondary breakdown voltage, so bifilar winding is not

always practical.

Setting Undervoltage and Hysteresis on VIN

The RUN pin is connected to a resistive voltage divider

connected to VIN as shown in Figure 4. The voltage thresh-

old for the RUN pin is VRUNON rising and VRUNOFF falling.

Note that VRUNON – VRUNOFF = 35mV of built-in voltage

hysteresis that helps eliminate false trips.

To introduce further user-programmable hysteresis, the

LTC3805 sources 5µA out of the RUN pin when operation

of LTC3805 is enabled. As a result, the falling threshold

for the RUN pin also depends on the value of R1 and can

be programmed by the user. The falling threshold for VIN

is therefore

VIN(RUN,FALLING) =VRUNOFF •R1

R2 −R1•5µA

where R1(5µA) is the additional hysteresis introduced

by the 5µA current sourced by the RUN pin. When in

shutdown, the RUN pin does not source the 5µA current

and the rising threshold for VIN is simply

VIN(RUN,RISING) =VRUNON •R1

External Run/Stop Control

To implement external run control, place a small N-channel

MOSFET from the RUN pin to GND as shown in Figure 4.

Drive the gate of this MOSFET high to pull the RUN pin

to ground and prevent converter operation.

Selecting Feedback Resistor Divider Values

The regulated output voltage is determined by the resistor

divider across VOUT (R3 and R4 in Figure 2). The ratio of R4

to R3 needed to produce a desired VOUT can be calculated:

R3 =VOUT −0.8V

0.8V R4

Choose resistance values for R3 and R4 to be as large as

possible in order to minimize any efficiency loss due to

the static current drawn from VOUT

, but just small enough

so that when VOUT is in regulation the input current to the

VFB pin is less than 1% of the current through R3 and R4.

A good rule of thumb is to choose R4 to be less than 80k.

LTC3805

3805fg

applications inForMation

Feedback in Isolated Applications

Isolated applications do not use the FB pin and error

amplifier but control the ITH pin directly using an opto-

isolator driven on the other side of the isolation barrier as

shown in Figure 5. A detailed version is shown in Figure

9. For isolated converters, the FB pin is grounded which

provides pull-up on the ITH pin. This pull-up is not enough

to properly bias the opto-isolator which is typically biased

using a resistor to VCC. Since the ITH pin cannot sink the

opto-isolator bias current, a diode is required to block

it from the ITH pin. A low leakage Schottky diode or low

forward voltage PN junction diode should be used to

ensure that the opto-isolator is able to pull ITH down to

its lower clamp.

Oscillator Synchronization

The oscillator may be synchronized to an external clock

by connecting the synchronization signal to the SYNC

pin. The LTC3805 oscillator and turn-on of the switch are

synchronized to the rising edge of the external clock. The

frequency of the external sync signal must be ±33% with

respect to fOSC (as programmed by RFS). Additionally,

the value of fSYNC must be between 70kHz and 700kHz.

Current Sense Resistor Considerations

The external current sense resistor (RSENSE in Figure 2)

allows the user to optimize the current limit behavior for

the particular application. As the current sense resistor

is varied from several ohms down to tens of milliohms,

peak switch current goes from a fraction of an ampere

to several amperes. Care must be taken to ensure proper

circuit operation, especially with small current sense

resistor values.

For example, with the peak current sense voltage of 100mV

on the ISENSE pin, a peak switch current of 5A requires

a sense resistor of 0.020Ω. Note that the instantaneous

peak power in the sense resistor is 0.5W and it must be

rated accordingly. The LTC3805 has only a single sense

line to this resistor. Therefore, any parasitic resistance

in the ground side connection of the sense resistor will

increase its apparent value. In the case of a 0.020Ω sense

resistor, one milliohm of parasitic resistance will cause a

5% reduction in peak switch current. So the resistance of

printed circuit copper traces and vias cannot necessarily

be ignored.

Programmable Slope Compensation

The LTC3805 injects a ramping current through its ISENSE

pin into an external slope compensation resistor RSLOPE.

This current ramp starts at zero right after the GATE pin

has been high for the LTC3805’s minimum duty cycle of

6%. The current rises linearly towards a peak of 10µA at

the maximum duty cycle of 80%, shutting off once the

GATE pin goes low. A series resistor RSLOPE connecting the

ISENSE pin to the current sense resistor RSENSE develops a

ramping voltage drop. From the perspective of the ISENSE

pin, this ramping voltage adds to the voltage across the

sense resistor, effectively reducing the current comparator

threshold in proportion to duty cycle. This stabilizes the

control loop against subharmonic oscillation. The amount

of reduction in the current comparator threshold (∆VSENSE)

can be calculated using the following equation:

∆VSENSE =DutyCycle −6%

80%

10µA •RSLOPE

Note: LTC3805 enforces 6% < Duty Cycle < 80%. A good

starting value for RSLOPE is 3k, which gives a 30mV drop

in current comparator threshold at 80% duty cycle.

Designs that do not operate at greater than 50% duty cycle

do not need slope compensation and may replace RSLOPE

with a direct connection.

Figure 5. Circuit for Isolated Feedback

LTC3805

ITH

VCC

ISOLATION

BARRIER

GND 3805 F05

LTC3805

3805fg

Figure 6. Circuit to Decrease Overcurrent Threshold

LTC3805

GATE

ISENSE

RSENSE

RSLOPE

IOC = 10µA

ISLOPE

GND 3805 F06

ROC

applications inForMation

Overcurrent Threshold Adjustment

Figure 6 shows the connection of the overcurrent pin, OC,

along with the ISENSE pin and the current sense resistor

RSENSE located in the source circuit of the power NMOS

which is driven by the GATE pin. The internal overcurrent

threshold on the OC pin is set at VOCT = 100mV which is the

same as the peak current sense voltage VI(MAX) = 100mV on

the ISENSE pin. The role of the slope compensation adjust-

ment resistor RSLOPE and the slope compensation current

ISLOPE is discussed in the prior section. In combination

with the overcurrent threshold adjust current IOC = 10µA,

an external resistor ROC can be used to lower the overcur-

rent trip threshold from 100mV. This section describes

how to pick ROC to achieve the desired performance. In the

discussion that follows be careful to distinguish between

“current limit” where the converter continues to run with

the ISENSE pin limiting current on a cycle-by-cycle basis

while the output voltage falls below the regulation point

and “overcurrent protection” where the OC pin senses an

overcurrent and shuts down the converter for a timeout

period before attempting an automatic restart.

One overcurrent protection strategy is for the converter

to never enter current limit but to maintain output volt-

age regulation up to the point of tripping the overcurrent

protection. Operation at minimum input voltage VIN(MIN)

hits current limiting for the smallest output current and

is the design point for this strategy.

First, for operation at VIN(MIN), calculate the duty cycle Duty

Cycle VIN(MIN) using the appropriate formula depending on

whether the converter is a boost, flyback or SEPIC. Then

use Duty Cycle VIN(MIN) to calculate ∆VSENSE(VIN(MIN))

using the formula in the prior section. For overcurrent

protection to trip at exactly the point where current limit-

ing would begin set:

ROC(CRIT) =

∆V

SENSE VIN(MIN)

( )

10µA

To find the actual output current that trips overcurrent

protection, calculate the peak switch current IPK(VIN(MIN))

from:

IPK VIN(MIN)

( )

100mV

− ∆

VSENSE VIN(MIN)

( )

RSENSE

Then calculate the converter output current that corre-

sponds to IPK(VIN(MIN)). Again, the calculation depends

both on converter type and the details of converter design

including inductor current ripple. For minimum input volt-

age, ROC(CRIT) produces an overcurrent trip at an output

current just before loss of output voltage regulation and

the onset of current limiting. Note that the output current

that causes an overcurrent trip is higher for higher input

voltages but that an overcurrent trip will always occur

before loss of output voltage regulation. If desired to

meet a specific design target, an increase in ROC above

ROC(CRIT) can be used to reduce the trip threshold and

make the converter trip for a lower output current.

This calculation is based on steady-state operation. De-

pending on design, overcurrent protection can also be

triggered during a start-up transient, particularly if large

output filter capacitors are being charged as output voltage

rises. If that is a problem, output capacitor charging can

LTC3805

3805fg

Figure 7. Circuit to Increase the Overcurrent

Threshold for Small Switch Currents

LTC3805

GATE

ISENSE

RSENSE1

RSENSE2

RSLOPE

GND 3805 F07

IOC = 10µA

ISLOPE

be slowed by using a larger value of SSFLT capacitor. It is

also possible to trip overcurrent protection during a load

step especially if the trip threshold is lowered by making

ROC > ROC(CRIT).

Another overcurrent protection strategy is keep the

converter running as current limiting reduces the duty

cycle and the output voltage sags. In this case, the goal

is often keep the converter in normal operation over as

wide a range as possible, including current limiting, and

to trigger the overcurrent trip only to prevent damage. To

implement this strategy use a value of ROC smaller than

ROC(CRIT). This also reduces sensitivity to overcurrent trips

caused by transient operation. In the limit, set ROC = 0

and connect the OC pin directly to RSENSE. This causes an

overcurrent trip near minimum duty cycle or around 6%.

In some cases it may be desirable to increase the trip

threshold even further. In this strategy, the converter is

allowed to operate all the way down to minimum duty

cycle at which point the cycle-by-cycle current limit of

the ISENSE pin is lost and switch current goes up propor-

tionally to the output current. Figures 7 and 8 show two

ways to do this. Figure 7 is for relatively low currents with

relatively large values of RSENSE. Using this circuit the

overcurrent trip threshold is increased from 100mV to:

VOC =RSENSE1 +RSENSE2

SENSE1

100mV

where it is assumed that the values of RSENSE1 and

RSENSE2 are so small that the IOC = 10µA threshold adjust-

ment current produces a negligible change in VOC.

For larger currents, values of the current sense resistors

must be very small and the circuit of Figure 7 becomes

impractical. The circuit of Figure 8 can be substituted and

the current sense threshold is increased from 100mV to:

VOC =R1+R2

R1 100mV

where the values of R1 and R2 should be kept below 10Ω

to prevent the IOC = 10µA threshold adjustment current

from producing a shift in VOC.

External Soft-Start Fault Timeout

The external soft-start is programmed by a capacitor CSS

from the SSFLT pin to GND. At the initiation of soft-start

the voltage on the SSFLT pin is quickly charged to 0.7V

at which point GATE begins switching. From that point,

a 6µA current charges the voltage on the SSFLT pin until

the voltage reaches about 2.25V at which point soft-start

is over and the converter enters closed-loop regulation.

The soft-start time tSS(EXT) as a function of the soft-start

capacitor, CSS, is therefore:

tSS(EXT) =CSS

2.25−0.7V

6µA

After soft-start is complete, the voltage on the SSFLT

pin continues to charge to about a final value of 4.75V.

Note that choosing a value of CSS less than 5.8nF has

no effect since it would attempt to program an external

soft-start time tSS(EXT) less than the mandatory minimum

Figure 8. Circuit to Increase the Overcurrent

Threshold for Large Switch Currents

LTC3805

GATE

ISENSE

RSLOPE

GND 3805 F08

RSENSE

IOC = 10µA

ISLOPE

applications inForMation

LTC3805

3805fg

Figure 9. Low Power Isolated Telecom Supply with NPN Preregulator

internal soft-start time tSS(IN) = 1.8ms. However, in noisy

environments a small CSS can be valuable to limit jitter

in the oscillator.

If there is an overcurrent fault detected on the OC pin, the

LTC3805 enters a shutdown mode while a 2µA current

discharges the voltage on the SSFLT pin from 4.75V to

about 0.7V. The fault timeout tFTO(EXT) is therefore:

tFTO(EXT) =CSS

4.75V

−

0.7V

2µA

At this point, the LTC3805 attempts a restart.

In the event of a persistent fault, such as a short-circuit

on the converter output, the converter enters a “hiccup”

mode where it continues to try and restart at repetition

rate determined by CSS. If the fault is eventually removed

the converter successfully restarts.

applications inForMation

VIN

COMP

0.6V FB

GND

OPTO

R20

118k

R19

3.01k

C17

1µF

C01

100µF

6.3V

C21

1µF

R12

100k

R14

22.1k

C22

0.47µF

C15

2200pF

250VAC

274Ω

C19

47pF

C20

47nF

R23

221k

C23, 0.1µF

UPS840

BAS516

FDC2512

BAS516

PA1861NL

C18

330pF

VIN

VCC

NOTE: CAN ALSO USE TRICKLE CHARGER AS SHOWN IN FIGURE 10

R16, 1.33k

8.66k

221k

220Ω

R30

51Ω

C16

150pF

200V

PDZ6.8B

6.8V

MMBTA42

3805 TA02a

CIN1

2.2µF

100V

CIN2

2.2µF

100V

VIN+

36V TO

72V

VIN–D6

BAT54CWTIG

R11

6.8k

221k

LTC3805EMSE

ITH

GND

SSFLT

RUN

GATE

ISENSE

SYNCFS

VCC

2Ω

R15

2.0k

C02

100µF

6.3V

C03

100µF

6.3V

RCS

0.068Ω

VOUT+

3.3V

VOUT–

+VOUT

ISO2

NECPS2801-1 U2

LT4430ES6 OPT

LOAD CURRENT (A)

0.01

EFFICIENCY (%)

POWER LOSS (W)

0.1 1

3805 TA02b

100

36V

48V

60V

72V

VIN

Efficiency and Power Loss

vs Load Current and VIN; VO = 3.3V

typical application

LTC3805

3805fg

MSOP (MSE) 0911 REV H

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

1234 5

4.90 ±0.152

(.193 ±.006)

0.497 ±0.076

(.0196 ±.003)

REF

8910

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

1.68 ±0.102

(.066 ±.004)

1.88 ±0.102

(.074 ±.004)

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ±.0015)

TYP

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.68

(.066)

1.88

(.074)

0.1016 ±0.0508

(.004 ±.002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev H)

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.125

TYP

2.38 ±0.10

(2 SIDES)

106

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV C 0310

0.25 ±0.05

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.15 ±0.05

0.50

BSC

0.70 ±0.05

3.55 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50 BSC

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

package Description

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC3805

3805fg

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision history

REV DATE DESCRIPTION PAGE NUMBER

E 04/10 Changes to Typical Application

Updates to Absolute Maximum Ratings

Changes to Electrical Characteristics Tables

Updates to Note 2

Update to Pin 11 in Pin Functions

Edits to Start-Up/Shutdown in Operation Section

Updated Related Parts Table

1, 17

F 05/11 Added MP-grade part. Reflected throughout the data sheet 1-20

G 02/12 VCLAMP1mA comments changed from ICC = 1mA to VCC Sinking 1mA

VCLAMP25mA comments changed from ICC = 25mA to VCC Sinking 25mA

VRUNON comments changed from VCC = VTURNON + 100mA to VCC Sinking 1mA

VRUNOFF comments changed from VCC = VTURNON + 100mA to VCC Sinking 1mA

(Revision history begins at Rev E)

LTC3805

3805fg

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 l FAX: (408) 434-0507 l www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2006

LT 0212 REV G • PRINTED IN USA

relateD parts

typical application

R20

118k

R19

3.01k

C17

10µF

NOTE: CAN ALSO USE NPN PREREGULATOR AS SHOWN IN FIGURE 9

C01

100µF

6.3V

R12

42.2k

C18

330pF

C23, 0.1µF

UPS840

BAS516

FDC2512

PA1861NL

VIN

VCC

R16, 1.33k

8.66k

221k

220Ω

C16

150pF

200V

3805 TA03a

CIN1

2.2µF

100V

VIN+

36V TO 72V

VIN–

LTC3805EMSE

ITH

GND

SSFLT

RUN

GATE

ISENSE

SYNCFS

VCC

C02

100µF

6.3V

C03

100µF

6.3V

RCS

0.068Ω

VOUT+

3.3V

VOUT–

+VOUT

C26

470pF

C25

100pF

R24

20k

R30

51Ω

R14

13.7k

R23

100k

CIN2

2.2µF

100V

Figure 10. Low Power Nonisolated Telecom Supply with Trickle Charger

LOAD CURRENT (A)

0.01

EFFICIENCY (%)

POWER LOSS (W)

0.1 1

3805 TA03b

100

36V

48V

60V

72V

VIN

Efficiency and Power Loss

vs Load Current and VIN; VO = 3.3V

PART NUMBER DESCRIPTION COMMENTS

LT3798 Isolated No Opto-Coupler Flyback Controller with

Active PFC

VIN and VOUT Limited by External Components

LT3748 100V No-Opto Flyback Controller 5V ≤ VIN ≤ 100V, Boundary Mode Operation, MSOP-16 with Extra High

Voltage Pin Spacing

LT3758 Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency,

3mm × 3mm DFN-10 and MSOP-10E

LT3575 No-Opto Isolated Flyback with 60V Integrated Switch 3V ≤ VIN ≤ 40V, Up to 14W, Boundary Mode Operation, TSSOP-16E

LTC3803/LTC3803-3/

LTC3803-5

Flyback DC/DC Controller with Fixed 200kHz or

300kHz Operating Frequency

VIN and VOUT Limited Only by External Components, 6-Pin ThinSOT Package

LTC3873/LTC3873-5 No RSENSE Constant Frequency Flyback, Boost,

SEPIC Controller

VIN and VOUT Limited Only by External Components, 8-Pin ThinSOT or

2mm × 3mm DFN-8 Packages

LT3825 No-Opto Isolated Synchronous Flyback Controller VIN 16V to 75V Limited by External Components, Up to 60W, TSSOP-16E