Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as "Cypress" document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Programmable System-on-Chip (PSoC) General Description PSoC(R) 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm(R) Cortex(R)-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4700S product family, based on this platform, is the industry's first microcontroller with inductive sensing and capacitive sensing technology in a single chip. The inductive sensing (MagSenseTM) technology enables sensing of metal objects and industry's leading capacitive sensing (CapSense(R)) technology enables sensing of non-metallic objects. Features 32-bit MCU Subsystem Serial Communication 48-MHz Arm Cortex-M0+ CPU Up to 32 KB of flash with Read Accelerator Up to 4 KB of SRAM Two independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI, or UART functionality LCD Drive Capability Inductive Sensing LCD segment drive capability on GPIOs Cypress MagSense provides superior noise immunity Reliably detects metal deflection under 190 nm MagSense software component automatically calibrates to compensate for the manufacturing variations Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks Up to 16 sensors Center-aligned, Edge, and Pseudo-random modes Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Capacitive Sensing Cypress CapSense Sigma-Delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance Cypress-supplied software component makes capacitive sensing design easy Automatic hardware tuning (SmartSenseTM) Programmable Analog Timing and Pulse-Width Modulation Up to 36 Programmable GPIO Pins 48-pin TQFP, 24-pin QFN, and 25-ball WLCSP packages Any GPIO pin can be capacitive sensing, analog, or digital; up to 16 pins can be used for inductive sensing. Drive modes, strengths, and slew rates are programmable One single-slope 10-bit ADC function PSoC Creator Design Environment Two current DACs (IDACs) Two low-power comparators that operate in Deep Sleep low-power mode Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing) Applications Programming Interface (API) component for all fixed-function and programmable peripherals Programmable Digital Two SmartIO ports allowing Boolean operations to be performed on port inputs and outputs Industry-Standard Tool Compatibility Low-Power 1.71-V to 5.5-V Operation Deep Sleep mode with operational analog and 2.5 A digital system current Cypress Semiconductor Corporation Document Number: 002-20489 Rev. *C * 198 Champion Court After schematic entry, development can be done with Arm-based industry-standard development tools * San Jose, CA 95134-1709 * 408-943-2600 Revised September 24, 2018 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4: Overview: PSoC Portfolio, PSoC Roadmap Product Selectors: PSoC 4 In addition, PSoC Creator includes a device selection tool. Application notes: Cypress offers a large number of PSoC application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with PSoC 4 are: AN79953: Getting Started With PSoC 4 AN219207: Inductive Sensing Design Guide AN88619: PSoC 4 Hardware Design Considerations AN86439: Using PSoC 4 GPIO Pins AN57821: Mixed Signal Circuit Board Layout (R) AN64846 - Getting Started with CapSense Technical Reference Manual (TRM): Architecture TRM details each PSoC 4 functional block. Registers TRM describes each of the PSoC 4 registers. Development Kits: CY8CKIT-148 PSoC(R) 4700S Inductive Sensing Evaluation Kit is a low-cost hardware platform that enables design and debug of the PSoC 4700S MCU. This kit demonstrates buttons and a proximity sensor using Cypress' brand new inductive-sensing technology, MagSense. In addition, an FPC connector is provided to evaluate various interfaces, such as a rotary encoder. PSoC Creator provides example projects for different product features and usage. Training Videos: Visit www.cypress.com/training for a wide variety of video training resources on PSoC Creator PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100 pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can: 1. Drag and drop component icons to build your hardware 3. Configure components using the configuration tools system design in the main design workspace 4. Explore the library of 100+ components 2. Codesign your application firmware with the PSoC hardware, 5. Review component datasheets using the PSoC Creator IDE C compiler Figure 1. Multiple-Sensor Example Project in PSoC Creator 1 2 3 4 5 Document Number: 002-20489 Rev. *C Page 2 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Contents Block Diagram .................................................................. 4 Functional Description..................................................... 4 Functional Overview ........................................................ 5 CPU and Memory Subsystem ..................................... 5 System Resources ...................................................... 5 Analog Blocks.............................................................. 6 Programmable Digital Blocks ...................................... 6 Fixed Function Digital.................................................. 6 GPIO ........................................................................... 7 Special Function Peripherals....................................... 7 Pinouts .............................................................................. 8 Alternate Pin Functions ............................................... 9 Power............................................................................... 11 Mode 1: 1.8 V to 5.5 V External Supply .................... 11 Mode 2: 1.8 V 5% External Supply.......................... 11 Development Support .................................................... 12 Documentation .......................................................... 12 Online ........................................................................ 12 Tools.......................................................................... 12 Electrical Specifications ................................................ 13 Absolute Maximum Ratings....................................... 13 Document Number: 002-20489 Rev. *C Device Level Specifications....................................... 14 Analog Peripherals .................................................... 17 Digital Peripherals ..................................................... 21 Memory ..................................................................... 24 System Resources .................................................... 24 Ordering Information...................................................... 27 Packaging........................................................................ 29 Package Diagrams .................................................... 30 Acronyms ........................................................................ 32 Document Conventions ................................................. 34 Units of Measure ....................................................... 34 Document History Page ................................................. 35 Sales, Solutions, and Legal Information ...................... 36 Worldwide Sales and Design Support....................... 36 Products .................................................................... 36 PSoC(R) Solutions ...................................................... 36 Cypress Developer Community................................. 36 Technical Support ..................................................... 36 Page 3 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Block Diagram Figure 2. Block Diagram CPU Subsystem Cortex M0+ 32- bit 48 MHz FAST MUL NVIC, IRQMUX System Resources Lite SRAM Controller ROM Controller Peripherals MagSense/ CapSense 5x TCPWM LCD Peripheral Interconnect (MMIO) PCLK IOSS GPIO (5x ports) Test TestMode Entry Digital DFT Analog DFT ROM 8 KB System Interconnect ( Single Layer AHB) Clock Clock Control WDT ILO IMO Reset Reset Control XRES SRAM 4 KB WCO Power Sleep Control POR REF PWRSYS Read Accelerator 2x LP Comparator AHB- Lite FLASH 32 KB 2x SCB-I2C/SPI/ UART PSoC 4700S Architecture High Speed I / O Matrix & 2x Programmable I / O Power Modes Active/ Sleep DeepSleep Document Number: 002-20489 Rev. *C 36x GPIOs, LCD I/O Subsystem Page 4 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Functional Overview CPU and Memory Subsystem CPU The Cortex-M0+ CPU in the PSoC 4700S is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of the Thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the processor from Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode. The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG. The debug configuration used for PSoC 4700S has four breakpoint (address) comparators and two watchpoint (data) comparators. Flash The PSoC 4700S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS) access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. A small section of the Flash memory is used to implement a supervisory Flash for storage or configuration data. Clock System The PSoC 4700S clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that there are no metastable conditions. The clock system for the PSoC 4700S consists of the internal main oscillator (IMO), internal low-frequency oscillator (ILO), a 32 kHz Watch Crystal Oscillator (WCO) and provision for an external clock. Clock dividers are provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to enable granular frequency selections in clocking for use with blocks such as UART. The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals. There are eight clock dividers for the PSoC 4700S, two of those are fractional dividers. The 16-bit capability allows flexible generation of fine-grained frequency values, The system clock (SYSCLK) which is used to clock the CPU, is derived from the HFCLK through a prescaler. All low-frequency operational blocks like watchdog timer (WDT) is clocked by the LFCLK. Figure 3. PSoC 4700S MCU Clocking Architecture WCO Trim IMO SRAM Divide By 2,4,8 HFCLK External Clock 4KB of SRAM are provided with zero wait-state access at 48 MHz. ILO SROM LFCLK A supervisory ROM that contains boot and configuration routines is provided. System Resources Power System The power system is described in detail in the section Power on page 11. It provides assurance that voltage levels are as required for each respective mode and either delays mode entry (for example, on power-on reset (POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detection). The PSoC 4700S operates with a single external supply over the range of either 1.8 V 5% (externally regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which are managed by the power system. The PSoC 4700S provides Active, Sleep, and Deep Sleep low-power modes. All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes 35 s. Document Number: 002-20489 Rev. *C HFCLK SYSCLK Prescaler Integer Dividers Fractional Dividers 5X 16-bit 2X 16.5-bit IMO Clock Source The IMO is the primary source of internal clocking in the PSoC 4700S. It is trimmed during testing to achieve the specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance with Cypress-provided calibration settings is 2%. The IMO has a mode where it can be trimmed using the WCO to achieve a higher precision. ILO Clock Source The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. Page 5 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Watch Crystal Oscillator (WCO) Fixed Function Digital The PSoC 4700S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can be used for precision timing applications. Timer/Counter/PWM (TCPWM) Block Watchdog Timer (WDT) A watchdog timer is implemented in the clock block running from the LFCLK; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is recorded in a Reset Cause register, which is firmware readable. Reset The PSoC 4700S can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled. Voltage Reference The PSoC 4700S reference system generates all internally required references. A 1.2-V voltage reference is provided for the comparator. The IDACs are based on a 5% reference. Analog Blocks Low-power Comparators (LPC) The PSoC 4700S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event. The LPC outputs can be routed to pins. Current DACs The PSoC 4700S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable current ranges. The current DACs are also used for implementation of the MagSense and CapSense. So these DACs are not available if the design implements MagSense or CapSense. Analog Multiplexed Buses The PSoC 4700S has two concentric independent buses that go around the periphery of the chip. These buses (called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal resources (IDACs, comparator, ADC, LPC, CapSense, MagSense) to connect to any pin on the I/O Ports. Programmable Digital Blocks The programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows Boolean functions to be performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as outputs. Document Number: 002-20489 Rev. *C The five TCPWM blocks consist of a 16-bit counter with user-programmable period length. There is a capture register to record the count value at the time of an event (which may be an I/O event), a period register that is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as dead-band programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be shut off immediately with no time for software intervention. Serial Communication Block (SCB) The PSoC 4700S has two serial communication blocks, which can be programmed to have SPI, I2C, or UART functionality. I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multi-master arbitration). This block is capable of operating at speeds of up to 400 kbps (Fast Mode) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that creates a mailbox address range in the memory of the PSoC 4700S and effectively reduces I2C communication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The I2C peripheral is compatible with the I2C Standard-mode and Fast-mode devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. The PSoC 4700S is not completely compliant with the I2C spec in the following respect: GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO. Page 6 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet GPIO CapSense The PSoC 4700S has up to 36 GPIOs. The GPIO block implements the following: CapSense is supported in the PSoC 4700S through a CapSense Sigma-Delta (CSD) block that can be connected to any pins through an analog multiplex bus via analog switches. CapSense function can thus be provided on any available pin or group of pins in a system under software control. A PSoC Creator component is provided for the CapSense block to make it easy for the user. Eight drive modes: Analog input mode (input and output buffers disabled) Input only Weak pull-up with strong pull-down Strong pull-up with weak pull-down Open drain with strong pull-down Open drain with strong pull-up Strong pull-up with strong pull-down Weak pull-up with weak pull-down Input threshold select (CMOS or LVTTL). Individual control of input and output buffer enabling/disabling in addition to the drive strength modes Selectable slew rates for dV/dt related noise control to improve EMI The pins are organized in logical entities called ports, which are 8-bit in width (less for Port 4). During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4700S). Special Function Peripherals MagSense (Inductive Sensing) The MagSense block in the PSoC 4700S device provides reliable contact-less metal-sensing for applications such as buttons (touch-over-metal), proximity detection and measurement, rotary and linear encoders, spring-based position detection, and other applications based on detecting position or distance of the metal object. This block can sense small deflections and can work off a small coin-cell battery enabling battery-powered applications such as mobile devices and smart watches. Cypress provides the component that automatically calibrates the design and compensates for the manufacturing variations, thereby reducing time-to-market, while providing a reliable solution that Just WorksTM in harsh environments. Document Number: 002-20489 Rev. *C Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Proximity sensing can also be implemented. The CapSense block provides a 10-bit Slope ADC function, which can be used in conjunction with the CapSense function. The CapSense block has two IDACs, which can be used for general purposes if CapSense is not being used (both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available). The CapSense block is an advanced, low-noise, programmable block with programmable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and Ground to null out power-supply related noise. LCD Segment Drive The PSoC 4700S has an LCD controller, which can drive up to 8 commons and up to 28 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as Digital Correlation and PWM. Digital Correlation pertains to modulating the frequency and drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port). Page 7 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Pinouts The following table provides the pin list for PSoC 4700S for the 48-pin TQFP, 24-pin QFN, and 25-ball CSP packages. All port pins support GPIO. Pin 11 is a No-Connect in the 48-TQFP. Table 1. PSoC 4700S Pin List 48-TQFP 24-QFN 25-WLCSP Pin Name Pin Name Pin Name 28 P0.0 13 P0.0 D1 P0.0 29 P0.1 14 P0.1 C3 P0.1 30 P0.2 - - - - 31 P0.3 - - - - 32 P0.4 15 P0.4 C2 P0.4 33 P0.5 16 P0.5 C1 P0.5 34 P0.6 17 P0.6 B1 P0.6 35 P0.7 - - B2 P0.7 36 XRES 18 XRES B3 XRES 37 VCCD 19 VCCD A1 VCCD 38 VSSD 20 VSSD A2 VSS 39 VDDD 21 VDD A3 VDD 40 VDDA 21 VDD A3 VDD 41 VSSA 22 VSSA A2 VSS 42 P1.0 - - - - 43 P1.1 - - - - 44 P1.2 23 P1.2 A4 P1.2 45 P1.3 24 P1.3 B4 P1.3 46 P1.4 - - - - 47 P1.5 - - - - 48 P1.6 - - - - 1 P1.7 1 P1.7 A5 P1.7 2 P2.0 2 P2.0 B5 P2.0 3 P2.1 3 P2.1 C5 P2.1 4 P2.2 - - - - 5 P2.3 - - - - 6 P2.4 - - - - 7 P2.5 - - - - 8 P2.6 4 P2.6 D5 P2.6 9 P2.7 5 P2.7 C4 P2.7 10 VSSD - - A2 VSS 12 P3.0 6 P3.0 E5 P3.0 13 P3.1 - - D4 P3.1 14 P3.2 7 P3.2 E4 P3.2 16 P3.3 8 P3.3 D3 P3.3 Document Number: 002-20489 Rev. *C Page 8 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Table 1. PSoC 4700S Pin List (continued) 48-TQFP 24-QFN 25-WLCSP Pin Name Pin Name Pin Name 17 P3.4 - - - - 18 P3.5 - - - - 19 P3.6 - - - - 20 P3.7 - - - - 21 VDDD - - - - 22 P4.0 9 P4.0 E3 P4.0 23 P4.1 10 P4.1 D2 P4.1 24 P4.2 11 P4.2 E2 P4.2 25 P4.3 12 P4.3 E1 P4.3 VDD: Power supply to all sections of the chip Descriptions of the Pin functions are as follows: VSS: Ground for all sections of the chip VDDD: Power supply for the digital section. VDDA: Power supply for the analog section. Alternate Pin Functions VSSD, VSSA: Ground pins for the digital and analog sections respectively. Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin assignments are shown in the following table. VCCD: Regulated digital supply (1.8 V 5%) Table 2. Pin Assignments Port/ Pin Analog Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 Deep Sleep 2 P0.0 lpcomp.in_p[0] - - - tcpwm.tr_in[0] - scb[0].spi_select1:0 P0.1 lpcomp.in_n[0] - - - tcpwm.tr_in[1] - scb[0].spi_select2:0 P0.2 lpcomp.in_p[1] - - - - - scb[0].spi_select3:0 P0.3 lpcomp.in_n[1] - - - - - - P0.4 wco.wco_in - - scb[1].uart_rx:0 scb[2].uart_rx:0 scb[1].i2c_scl:0 scb[1].spi_mosi:1 P0.5 wco.wco_out - P0.6 - - P0.7 - P1.0 - P1.1 - scb[1].uart_tx:0 scb[2].uart_tx:0 scb[1].i2c_sda:0 scb[1].spi_miso:1 srss.ext_clk scb[1].uart_cts:0 scb[2].uart_tx:1 - scb[1].spi_clk:1 - - scb[1].uart_rts:0 - - tcpwm.line[2]:1 scb[0].uart_rx:1 - scb[0].i2c_scl:0 scb[0].spi_mosi:1 - - tcpwm.line_compl[2]:1 scb[0].uart_tx:1 - scb[0].i2c_sda:0 scb[0].spi_miso:1 P1.2 - - tcpwm.line[3]:1 scb[0].uart_cts:1 tcpwm.tr_in[2] scb[2].i2c_scl:0 scb[0].spi_clk:1 P1.3 - - tcpwm.line_compl[3]:1 scb[0].uart_rts:1 tcpwm.tr_in[3] scb[2].i2c_sda:0 scb[0].spi_select0:1 P1.4 - - - - - - scb[0].spi_select1:1 P1.5 - - - - - - scb[0].spi_select2:1 P1.6 - - - - - - scb[0].spi_select3:1 Document Number: 002-20489 Rev. *C scb[1].spi_select0:1 Page 9 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Table 2. Pin Assignments (continued) Port/ Pin Analog Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 Deep Sleep 2 P1.7 - - - - - - - P2.0 - SmartIO[0].io[0] tcpwm.line[4]:0 csd.comp tcpwm.tr_in[4] scb[1].i2c_scl:1 scb[1].spi_mosi:2 P2.1 - SmartIO[0].io[1] tcpwm.line_compl[4]:0 - tcpwm.tr_in[5] scb[1].i2c_sda:1 scb[1].spi_miso:2 P2.2 - SmartIO[0].io[2] - - - - scb[1].spi_clk:2 P2.3 - SmartIO[0].io[3] - - - - scb[1].spi_select0:2 P2.4 - SmartIO[0].io[4] tcpwm.line[0]:1 - - - scb[1].spi_select1:1 P2.5 - SmartIO[0].io[5] tcpwm.line_compl[0]:1 - - - scb[1].spi_select2:1 P2.6 - SmartIO[0].io[6] tcpwm.line[1]:1 - - - scb[1].spi_select3:1 P2.7 - SmartIO[0].io[7] tcpwm.line_compl[1]:1 - - lpcomp.comp[0]:1 - P3.0 - SmartIO[1].io[0] tcpwm.line[0]:0 scb[1].uart_rx:1 - scb[1].i2c_scl:2 scb[1].spi_mosi:0 P3.1 - SmartIO[1].io[1] tcpwm.line_compl[0]:0 scb[1].uart_tx:1 - scb[1].i2c_sda:2 scb[1].spi_miso:0 P3.2 - SmartIO[1].io[2] tcpwm.line[1]:0 scb[1].uart_cts:1 - cpuss.swd_data scb[1].spi_clk:0 P3.3 - SmartIO[1].io[3] tcpwm.line_compl[1]:0 scb[1].uart_rts:1 - cpuss.swd_clk scb[1].spi_select0:0 P3.4 - SmartIO[1].io[4] tcpwm.line[2]:0 - tcpwm.tr_in[6] - scb[1].spi_select1:0 P3.5 - SmartIO[1].io[5] tcpwm.line_compl[2]:0 - tcpwm.tr_in[7] - scb[1].spi_select2:0 P3.6 - SmartIO[1].io[6] tcpwm.line[3]:0 - tcpwm.tr_in[8] - scb[1].spi_select3:0 P3.7 - SmartIO[1].io[7] tcpwm.line_compl[3]:0 - tcpwm.tr_in[9] lpcomp.comp[1]:1 - P4.0 csd.vref_ext - - scb[0].uart_rx:0 tcpwm.tr_in[10] scb[0].i2c_scl:1 scb[0].spi_mosi:0 P4.1 csd.cshieldpads - - scb[0].uart_tx:0 tcpwm.tr_in[11] scb[0].i2c_sda:1 scb[0].spi_miso:0 P4.2 csd.cmodpad - - scb[0].uart_cts:0 - lpcomp.comp[0]:0 scb[0].spi_clk:0 P4.3 csd.csh_tank - - scb[0].uart_rts:0 - lpcomp.comp[1]:0 scb[0].spi_select0:0 Document Number: 002-20489 Rev. *C Page 10 of 36 PRELIMINARY Power PSoC(R) 4: PSoC 4700S Family Datasheet Mode 1: 1.8 V to 5.5 V External Supply The following power system diagram shows the set of power supply pins as implemented for the PSoC 4700S. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the VDD input. Figure 4. Power Supply Connections VDDA VDDD VDDA VSSA Mode 2: 1.8 V 5% External Supply VDDD Analog Domain In this mode, the PSoC 4700S is powered by an external power supply that must be within the range of 1.71 to 1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins are shorted together and bypassed. The internal regulator can be disabled in the firmware. Digital Domain VSSD 1.8 Volt Regulator In this mode, the PSoC 4700S is powered by an external power supply that can be anywhere in the range of 1.8 to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the PSoC 4700S supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be bypassed to ground via an external capacitor (0.1 F; X5R ceramic or better) and must not be connected to anything else. Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-F range, in parallel with a smaller capacitor (0.1 F, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. VCCD An example of a bypass scheme is shown in the following diagram. There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated externally; internal regulator operational). In Mode 2, the supply range is1.8 V 5% (externally regulated; 1.71 V to 1.89 V, internal regulator bypassed). Figure 5. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active Power supply bypass connections example 1.8V to 5.5V VDDD 1 F PSoC 4700S 1.8 V to 5.5 V VDDA F 0.1 F 0.1 F V CCD 0.1 F VSSD Document Number: 002-20489 Rev. *C Page 11 of 36 PRELIMINARY Development Support The PSoC 4700S family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/go/psoc4 to find out more. Documentation A suite of documentation supports the PSoC 4700S family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. Inductive Sensing Design Guide: A guide to designing reliable Inductive Solutions. Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. Document Number: 002-20489 Rev. *C PSoC(R) 4: PSoC 4700S Family Datasheet Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers. The TRM is available in the Documentation section at www.cypress.com/psoc4. Online In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week. Tools With industry standard cores, programming, and debugging interfaces, the PSoC 4700S family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits. Page 12 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Electrical Specifications Absolute Maximum Ratings Table 3. Absolute Maximum Ratings[1] Spec ID# Parameter Description Min Typ Max Units Details/ Conditions V - SID1 VDDD_ABS Digital supply relative to VSS -0.5 - 6 SID2 VCCD_ABS Direct digital core voltage input relative to VSS -0.5 - 1.95 - SID3 VGPIO_ABS GPIO voltage -0.5 - VDD+0.5 - SID4 IGPIO_ABS Maximum current per GPIO -25 - 25 SID5 IGPIO_injection GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS -0.5 - 0.5 BID44 ESD_HBM Electrostatic discharge human body model 2200 - - BID45 ESD_CDM Electrostatic discharge charged device model 500 - - BID46 LU Pin current for latch-up -140 - 140 mA - Current injected per pin V - - mA - Note 1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 002-20489 Rev. *C Page 13 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Device Level Specifications All specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 4. DC Specifications Typical values measured at VDD = 3.3 V and 25 C. Spec ID# Parameter Description Min Typ Max Units V SID53 VDD Power supply input voltage 1.8 - 5.5 SID255 VDD Power supply input voltage (VCCD = VDD= VDDA) 1.71 - 1.89 SID54 VCCD Output voltage (for core logic) - 1.8 - SID55 CEFC External regulator voltage bypass - 0.1 - SID56 CEXC Power supply bypass capacitor - 1 - Details/ Conditions Internally regulated supply Internally unregulated supply - F X5R ceramic or better X5R ceramic or better Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 C. SID10 IDD5 Execute from flash; CPU at 6 MHz - 1.2 2.0 SID16 IDD8 Execute from flash; CPU at 24 MHz - 2.4 4.0 - SID19 IDD11 Execute from flash; CPU at 48 MHz - 4.6 5.9 - mA - Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on) SID22 SID25 IDD17 I2C wakeup WDT, and Comparators on - 1.1 1.6 IDD20 I2C wakeup, WDT, and Comparators on - 1.4 1.9 mA 6 MHz 12 MHz Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed) SID28 SID28A IDD23 I2C wakeup, WDT, and Comparators on - 0.7 0.9 mA 6 MHz IDD23A I2C wakeup, WDT, and Comparators on - 0.9 1.1 mA 12 MHz - 2.5 60 A - - 2.5 60 A - Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on) SID31 IDD26 I2C wakeup and WDT on Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on) SID34 IDD29 I2C wakeup and WDT on Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed) SID37 IDD32 I2C wakeup and WDT on - 2.5 60 A - IDD_XR Supply current while XRES asserted - 2 5 mA - Min Typ Max Units Details/ Conditions DC - 48 MHz s XRES Current SID307 Table 5. AC Specifications Spec ID# SID48 Parameter Description FCPU CPU frequency SID49 TSLEEP Wakeup from Sleep mode - 0 - SID50[3] TDEEPSLEEP Wakeup from Deep Sleep mode - 35 - [3] 1.71 VDD 5.5 - - Notes 2. Guaranteed by characterization. 3. VIH must not exceed VDDD + 0.2 V. Document Number: 002-20489 Rev. *C Page 14 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet GPIO Table 6. GPIO DC Specifications Spec ID# Parameter Description Min Typ Max Units V Details/ Conditions SID57 VIH[4] Input voltage high threshold 0.7 VDDD - - SID58 VIL Input voltage low threshold - - SID241 VIH[4] LVTTL input, VDDD < 2.7 V 0.7 VDDD 0.3 VDDD - - - SID242 VIL LVTTL input, VDDD < 2.7 V - - 0.3 VDDD - SID243 VIH[4] LVTTL input, VDDD 2.7 V 2.0 - - - SID244 VIL LVTTL input, VDDD 2.7 V - - 0.8 - SID59 VOH Output voltage high level VDDD -0.6 - - IOH = 4 mA at 3 V VDDD SID60 VOH Output voltage high level VDDD -0.5 - - IOH = 1 mA at 3 V VDDD SID61 VOL Output voltage low level - - 0.6 IOL = 4 mA at 1.8 V VDDD SID62 VOL Output voltage low level - - 0.6 IOL = 10 mA at 3 V VDDD SID62A VOL Output voltage low level - - 0.4 IOL = 3 mA at 3 V VDDD SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 SID65 IIL Input leakage current (absolute value) - - 2 nA SID66 CIN Input capacitance - - 7 pF mV [5] CMOS Input CMOS Input k - - 25 C, VDDD = 3.0 V - VDDD 2.7 V SID67 VHYSTTL Input hysteresis LVTTL 25 40 - SID68[5] VHYSCMOS Input hysteresis CMOS 0.05 x VDDD - - VDD < 4.5 V SID68A[5] VHYSCMOS5V5 Input hysteresis CMOS 200 - - VDD > 4.5 V [5] SID69 IDIODE Current through protection diode to VDD/VSS - - 100 A - SID69A[5] ITOT_GPIO Maximum total source or sink chip current - - 200 mA - Notes 4. VIH must not exceed VDDD + 0.2 V. 5. Guaranteed by characterization. Document Number: 002-20489 Rev. *C Page 15 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Table 7. GPIO AC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions ns 3.3 V VDDD, Cload = 25 pF SID70 TRISEF Rise time in fast strong mode 2 - 12 SID71 TFALLF Fall time in fast strong mode 2 - 12 SID72 TRISES Rise time in slow strong mode 10 - 60 - 3.3 V VDDD, Cload = 25 pF SID73 TFALLS Fall time in slow strong mode 10 - 60 - 3.3 V VDDD, Cload = 25 pF SID74 FGPIOUT1 GPIO FOUT; 3.3 V VDDD 5.5 V Fast strong mode - - 33 MHz SID75 FGPIOUT2 GPIO FOUT; 1.71 VVDDD3.3 V Fast strong mode - - 16.7 90/10%, 25 pF load, 60/40 duty cycle SID76 FGPIOUT3 GPIO FOUT; 3.3 V VDDD 5.5 V Slow strong mode - - 7 90/10%, 25 pF load, 60/40 duty cycle SID245 FGPIOUT4 GPIO FOUT; 1.71 V VDDD 3.3 V Slow strong mode. - - 3.5 90/10%, 25 pF load, 60/40 duty cycle SID246 FGPIOIN GPIO input operating frequency; 1.71 V VDDD 5.5 V - - 48 90/10% VIO 3.3 V VDDD, Cload = 25 pF 90/10%, 25 pF load, 60/40 duty cycle XRES Table 8. XRES DC Specifications Spec ID# SID77 Parameter Description VIH Input voltage high threshold Min Typ Max Units 0.7 x VDDD - - V Details/ Conditions CMOS Input SID78 VIL Input voltage low threshold - - 0.3 VDDD SID79 RPULLUP Pull-up resistor - 60 - k - SID80 CIN Input capacitance - - 7 pF - SID81 VHYSXRES Input voltage hysteresis - 100 - mV SID82 IDIODE Current through protection diode to VDD/VSS - - 100 A Min Typ Max Units Details/ Conditions [6] Typical hysteresis is 200 mV for VDD > 4.5 V - Table 9. XRES AC Specifications Spec ID# Parameter Description SID83[6] TRESETWIDTH Reset pulse width 1 - - s - BID194[6] TRESETWAKE Wake-up time from reset release - - 2.7 ms - Note 6. Guaranteed by characterization. Document Number: 002-20489 Rev. *C Page 16 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Analog Peripherals Table 10. Low Power Comparator DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions mV - SID84 VOFFSET1 Input offset voltage, Factory trim - - 10 SID85 VOFFSET2 Input offset voltage, Custom trim - - 4 - SID86 VHYST Hysteresis when enabled - 10 35 - SID87 VICM1 Input common mode voltage in normal mode 0 - VDDD - 0.1 SID247 VICM2 Input common mode voltage in low power mode 0 - VDDD - SID247A VICM3 Input common mode voltage in ultra low power mode 0 - VDDD - 1.15 VDDD 2.2 V at -40 C SID88 CMRR Common mode rejection ratio 50 - - SID88A CMRR Common mode rejection ratio 42 - - SID89 ICMP1 Block current, normal mode - - 400 SID248 ICMP2 Block current, low power mode - - 100 - SID259 ICMP3 Block current in ultra low-power mode - 6 28 VDDD 2.2 V at -40 C SID90 ZCMP DC Input impedance of comparator 35 - - V dB Modes 1 and 2 VDDD 2.7V VDDD 2.7V A M - - Table 11. Comparator AC Specifications Spec ID# Parameter Description Min Typ Max Units 38 110 ns SID91 TRESP1 Response time, normal mode, 50 mV overdrive - SID258 TRESP2 Response time, low power mode, 50 mV overdrive - 70 200 SID92 TRESP3 Response time, ultra-low power mode, 200 mV overdrive - 2.3 15 Document Number: 002-20489 Rev. *C Details/ Conditions - - s VDDD 2.2 V at -40 C Page 17 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet CSD (Capacitive Sensing and IDAC block) Table 12. CSD and IDAC Specifications SPEC ID# Parameter Description Min Typ Max Units Details / Conditions SYS.PER#3 VDD_RIPPLE Max allowed ripple on power supply, DC to 10 MHz - - 50 mV VDD > 2 V (with ripple), 25 C TA, Sensitivity = 0.1 pF SYS.PER#16 VDD_RIPPLE_1.8 Max allowed ripple on power supply, DC to 10 MHz - - 25 mV VDD > 1.75V (with ripple), 25 C TA, Parasitic Capacitance (CP) < 20 pF, Sensitivity 0.4 pF SID.CSD.BLK ICSD Maximum block current - - 4000 A Maximum block current for both IDACs in dynamic (switching) mode including comparators, buffer, and reference generator. SID.CSD#15 VREF Voltage reference for CSD and Comparator 0.6 1.2 VDDA - 0.6 V VDDA - 0.06 or 4.4, whichever is lower SID.CSD#15A VREF_EXT External Voltage reference for CSD and Comparator 0.6 - VDDA - 0.6 V VDDA - 0.06 or 4.4, whichever is lower SID.CSD#16 IDAC1IDD IDAC1 (7-bits) block current - - 1750 A - SID.CSD#17 IDAC2IDD IDAC2 (7-bits) block current - - 1750 A - Voltage range of operation 1.71 - 5.5 V 1.8 V 5% or 1.8 V to 5.5 V Voltage compliance range of IDAC 0.6 - VDDA -0.6 V VDDA - 0.06 or 4.4, whichever is lower SID308 VCSD SID308A VCOMPIDAC SID309 IDAC1DNL DNL -1 - 1 LSB - SID310 IDAC1INL INL -2 - 2 LSB INL is 5.5 LSB for VDDA < 2V SID311 IDAC2DNL DNL -1 - 1 LSB - SID312 IDAC2INL INL -2 - 2 LSB INL is 5.5 LSB for VDDA < 2V SID313 SNR Ratio of counts of finger to noise. Guaranteed by characterization 5 - - Ratio Capacitance range of 5 to SID314 IDAC1CRT1 Output current of IDAC1 (7 bits) in low range 4.2 - 5.4 A LSB = 37.5-nA typ. SID314A IDAC1CRT2 Output current of IDAC1(7 bits) in medium range 34 - 41 A LSB = 300-nA typ. SID314B IDAC1CRT3 Output current of IDAC1(7 bits) in high range 275 - 330 A LSB = 2.4-A typ. SID314C IDAC1CRT12 Output current of IDAC1 (7 bits) in low range, 2X mode 8 - 10.5 A LSB = 75-nA typ. SID314D IDAC1CRT22 Output current of IDAC1(7 bits) in medium range, 2X mode 69 - 82 A LSB = 600-nA typ. SID314E IDAC1CRT32 Output current of IDAC1(7 bits) in high range, 2X mode 540 - 660 A LSB = 4.8-A typ. SID315 IDAC2CRT1 Output current of IDAC2 (7 bits) in low range 4.2 - 5.4 A LSB = 37.5-nA typ. SID315A IDAC2CRT2 Output current of IDAC2 (7 bits) in medium range 34 - 41 A LSB = 300-nA typ. SID315B IDAC2CRT3 Output current of IDAC2 (7 bits) in high range 275 - 330 A LSB = 2.4-A typ. SID315C IDAC2CRT12 Output current of IDAC2 (7 bits) in low range, 2X mode 8 - 10.5 A LSB = 75-nA typ. SID315D IDAC2CRT22 Output current of IDAC2(7 bits) in medium range, 2X mode 69 - 82 A LSB = 600-nA typ. Document Number: 002-20489 Rev. *C 35 pF, 0.1-pF sensitivity. All use cases. VDDA > 2 V. Page 18 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Table 12. CSD and IDAC Specifications (continued) SPEC ID# Parameter SID315E IDAC2CRT32 Output current of IDAC2(7 bits) in high range, 2X mode Description Min Typ Max Units 540 - 660 A LSB = 4.8-A typ. SID315F IDAC3CRT13 SID315G Details / Conditions Output current of IDAC in 8-bit mode in low range 8 - 10.5 A LSB = 37.5-nA typ. IDAC3CRT23 Output current of IDAC in 8-bit mode in medium range 69 - 82 A LSB = 300-nA typ. SID315H IDAC3CRT33 Output current of IDAC in 8-bit mode in high range 540 - 660 A LSB = 2.4-A typ. SID320 IDACOFFSET All zeroes input - - 1 LSB SID321 IDACGAIN Full-scale error less offset - - 10 % Polarity set by Source or Sink. Offset is 2 LSBs for 37.5 nA/LSB mode - SID322 IDACMISMATCH1 Mismatch between IDAC1 and IDAC2 in Low mode - - 9.2 LSB LSB = 37.5-nA typ. SID322A IDACMISMATCH2 Mismatch between IDAC1 and IDAC2 in Medium mode - - 5.6 LSB LSB = 300-nA typ. SID322B IDACMISMATCH3 Mismatch between IDAC1 and IDAC2 in High mode - - 6.8 LSB LSB = 2.4-A typ. SID323 IDACSET8 Settling time to 0.5 LSB for 8-bit IDAC - - 10 s Full-scale transition. No external load. SID324 IDACSET7 Settling time to 0.5 LSB for 7-bit IDAC - - 10 s Full-scale transition. No external load. SID325 CMOD External modulator capacitor. - 2.2 - nF 5-V rating, X7R or NP0 cap. Inductive Sensing (MagSense) Table 13. MagSense Specifications Min Typ Max Units Details/Conditions SID500 Spec ID# Nsense Parameter Number of Sensors Description - - 16 - - SID501 Lsamp Sample Rate - - 10 ksps - SID502 Lres Resolution - - 16 bits - SID503 Lfreq Sensor excitation frequency 45 - 3000 kHz - SID505 Lval Inductance Range 1 - 10000 H - SID506 Lprox Proximity detection range - 0.75 x coil diameter - - - Document Number: 002-20489 Rev. *C Page 19 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY CapSense Table 14. 10-bit CapSense ADC Specifications Spec ID# Parameter Description Min Typ Max Units Details/Conditions SIDA94 A_RES Resolution - - 10 bits Auto-zeroing is required every millisecond SIDA95 A_CHNLS_S Number of channels - single ended - - 16 - Defined by AMUX Bus. SIDA97 A-MONO Monotonicity - - - Yes - SIDA98 A_GAINERR Gain error - - 2 % In VREF (2.4 V) mode with VDDA bypass capacitance of 10 F SIDA99 A_OFFSET Input offset voltage - - 3 mV In VREF (2.4 V) mode with VDDA bypass capacitance of 10 F SIDA100 A_ISAR Current consumption - - 0.25 mA - SIDA101 A_VINS Input voltage range - single ended VSSA - VDDA V - SIDA103 A_INRES Input resistance - 2.2 - K - SIDA104 A_INCAP Input capacitance - 20 - pF - SIDA106 A_PSRR Power supply rejection ratio - 60 - dB In VREF (2.4 V) mode with VDDA bypass capacitance of 10 F SIDA107 A_TACQ Sample acquisition time - 1 - s - SIDA108 A_CONV8 Conversion time for 8-bit resolution at conversion rate = Fhclk/(2^(N+2)). Clock frequency = 48 MHz. - - 21.3 s Does not include acquisition time. Equivalent to 44.8 ksps including acquisition time. SIDA108A A_CONV10 Conversion time for 10-bit resolution at conversion rate = Fhclk/(2^(N+2)). Clock frequency = 48 MHz. - - 85.3 s Does not include acquisition time. Equivalent to 11.6 ksps including acquisition time. SIDA109 A_SND Signal-to-noise and Distortion ratio (SINAD) - 61 - dB With 10-Hz input sine wave, external 2.4-V reference, VREF (2.4 V) mode SIDA110 A_BW Input bandwidth without aliasing - - 22.4 kHz 8-bit resolution SIDA111 A_INL Integral Non Linearity. 1 ksps - - 2 LSB VREF = 2.4 V or greater SIDA112 A_DNL Differential Non Linearity. 1 ksps - - 1 LSB Document Number: 002-20489 Rev. *C - Page 20 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Digital Peripherals Timer Counter Pulse-Width Modulator (TCPWM) Table 15. TCPWM Specifications Spec ID SID.TCPWM.1 Parameter ITCPWM1 Description Block current consumption at 3 MHz Min - Typ - Max 45 Units Details/Conditions A All modes (TCPWM) SID.TCPWM.2 ITCPWM2 Block current consumption at 12 MHz - - 155 SID.TCPWM.2A ITCPWM3 Block current consumption at 48 MHz - - 650 SID.TCPWM.3 TCPWMFREQ Operating frequency - - Fc MHz SID.TCPWM.4 TPWMENEXT Input trigger pulse width 2/Fc - - ns SID.TCPWM.5 TPWMEXT Output trigger pulse widths 2/Fc - - Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) outputs SID.TCPWM.5A TCRES Resolution of counter 1/Fc - - Minimum time between successive counts SID.TCPWM.5B PWMRES PWM resolution 1/Fc - - Minimum pulse width of PWM Output SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc - - Minimum pulse width between Quadrature phase inputs All modes (TCPWM) All modes (TCPWM) Fc max = CLK_SYS Maximum = 48 MHz For all trigger events[7] I2C Table 16. Fixed I2C DC Specifications[8] Spec ID Parameter Description Min Typ Max Units A Details/Conditions - SID149 II2C1 Block current consumption at 100 kHz - - 50 SID150 II2C2 Block current consumption at 400 kHz - - 135 SID151 II2C3 Block current consumption at 1 Mbps - - 310 - II2C4 I2C - SID152 enabled in Deep Sleep mode - - - 1.4 Min Typ Max Units - - 1 Msps Table 17. Fixed I2C AC Specifications[8] Spec ID SID153 Parameter FI2C1 Description Bit rate Details/Conditions - Notes 7. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected. 8. Guaranteed by characterization. Document Number: 002-20489 Rev. *C Page 21 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet SPI Table 18. SPI DC Specifications[9] Spec ID Parameter Description Min Typ Max Units Details/Conditions A - SID163 ISPI1 Block current consumption at 1 Mbps - - 360 SID164 ISPI2 Block current consumption at 4 Mbps - - 560 - SID165 ISPI3 Block current consumption at 8 Mbps - - 600 - Min Typ Max Units Details/Conditions - - 8 MHz - ns Table 19. SPI AC Specifications[9] Spec ID SID166 Parameter FSPI Description SPI operating frequency (Master; 6X Oversampling) Fixed SPI Master Mode AC Specifications SID167 TDMO MOSI Valid after SClock driving edge - - 15 SID168 TDSI MISO Valid before SClock capturing edge 20 - - Full clock, late MISO sampling - SID169 THMO Previous MOSI data hold time 0 - - Referred to Slave capturing edge Fixed SPI Slave Mode AC Specifications SID170 TDMI MOSI Valid before Sclock Capturing edge 40 - - SID171 TDSO MISO Valid after Sclock driving edge - - 42 + 3*Tcpu SID171A TDSO_EXT MISO Valid after Sclock driving edge in Ext. Clk mode - - 48 SID172 THSO Previous MISO data hold time 0 - - SID172A TSSELSSCK SSEL Valid to first SCK Valid edge - - 100 ns - TCPU = 1/FCPU - - ns - Note 9. Guaranteed by characterization. Document Number: 002-20489 Rev. *C Page 22 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet UART Table 20. UART DC Specifications[10] Spec ID Parameter Description Min Typ Max Units Details/Conditions SID160 IUART1 Block current consumption at 100 Kbps - - 55 A - SID161 IUART2 Block current consumption at 1000 Kbps - - 312 A - Min Typ Max Units Details/Conditions - - 1 Mbps - Table 21. UART AC Specifications[10] Spec ID SID162 Parameter FUART Description Bit rate LCD Table 22. LCD Direct Drive DC Specifications[10] Spec ID Parameter Description Min Typ Max Units Details/Conditions 16 4 small segment disp. at 50 Hz SID154 ILCDLOW Operating current in low power mode - 5 - A SID155 CLCDCAP LCD capacitance per segment/common driver - 500 5000 pF SID156 LCDOFFSET Long-term segment offset - 20 - mV - SID157 ILCDOP1 LCD system operating current Vbias = 5V - 2 - mA 32 4 segments. 50 Hz. 25 C SID158 ILCDOP2 LCD system operating current Vbias = 3.3 V - 2 - Min Typ Max Units Details/Conditions 10 50 150 Hz - - 32 4 segments. 50 Hz. 25 C Table 23. LCD Direct Drive AC Specifications[10] Spec ID SID159 Parameter FLCD Description LCD frame rate Note 10. Guaranteed by characterization. Document Number: 002-20489 Rev. *C Page 23 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Memory Table 24. Flash DC Specifications Spec ID SID173 Parameter VPE Description Erase and program voltage Min Typ Max Units Details/Conditions 1.71 - 5.5 V - Table 25. Flash AC Specifications Description Min Typ Max Units Details/Conditions SID174 Spec ID TROWWRITE[11] Row (block) write time (erase and program) - - 20 ms Row (block) = 128 bytes SID175 TROWERASE[11] Row erase time - - 16 - SID176 Row program time after erase - - 4 - Bulk erase time (32 KB) - - 35 - SID180[12] TROWPROGRAM[11] TBULKERASE[11] TDEVPROG[11] SID181[12] FEND Flash endurance SID182[12] FRET SID178 Parameter Total device program time - - 7 Seconds - 100 K - - Cycles - Flash retention. TA 55 C, 100 K P/E cycles 20 - - Years - SID182A[12] - Flash retention. TA 85 C, 10 K P/E cycles 10 - - SID256 TWS48 Number of Wait states at 48 MHz 2 - - CPU execution from Flash SID257 TWS24 Number of Wait states at 24 MHz 1 - - CPU execution from Flash Min Typ Max Units - System Resources Power-on Reset (POR) Table 26. Power On Reset (PRES) Spec ID Parameter Description SID.CLK#6 SR_POWER_UP Power supply slew rate 1 - 67 V/ms SID185[12] VRISEIPOR Rising trip voltage 0.80 - 1.5 V SID186[12] VFALLIPOR Falling trip voltage 0.70 - 1.4 Details/Conditions At power-up - - Brown-out Detect Table 27. Brown-out Detect (BOD) for VCCD Min Typ Max Units Details/Conditions SID190[12] Spec ID VFALLPPOR Parameter BOD trip voltage in active and sleep modes Description 1.48 - 1.62 V - SID192[12] VFALLDPSLP BOD trip voltage in Deep Sleep 1.11 - 1.5 - Notes 11. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. 12. Guaranteed by characterization. Document Number: 002-20489 Rev. *C Page 24 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet SWD Interface Table 28. SWD Interface Specifications Min Typ Max Units Details/Conditions SID213 Spec ID F_SWDCLK1 3.3 V VDD 5.5 V - - 14 MHz SWDCLK 1/3 CPU clock frequency SID214 F_SWDCLK2 1.71 V VDD 3.3 V - - 7 SID215[13] T_SWDI_SETUP T = 1/f SWDCLK 0.25*T - - SID216 T_SWDI_HOLD 0.25*T - - - SID217[13] T_SWDO_VALID T = 1/f SWDCLK - - 0.5*T - T_SWDO_HOLD T = 1/f SWDCLK 1 - - - Min Typ Max Units Details/Conditions [13] SID217A [13] Parameter Description T = 1/f SWDCLK SWDCLK 1/3 CPU clock frequency ns - Internal Main Oscillator Table 29. IMO DC Specifications (Guaranteed by Design) Spec ID Parameter Description SID218 IIMO1 IMO operating current at 48 MHz - - 250 A - SID219 IIMO2 IMO operating current at 24 MHz - - 180 A - Table 30. IMO AC Specifications Description Min Typ Max Units Details/Conditions SID223 Spec ID FIMOTOL1 Parameter Frequency variation at 24, 32, and 48 MHz (trimmed) - - 2 % - SID226 TSTARTIMO IMO startup time - - 7 s - SID228 TJITRMSIMO2 RMS jitter at 24 MHz - 145 - ps - Min Typ Max Units Details/Conditions - 0.3 1.05 A - Min Typ Max Units Details/Conditions Internal Low-Speed Oscillator Table 31. ILO DC Specifications (Guaranteed by Design) Spec ID [13] SID231 Parameter IILO1 Description ILO operating current Table 32. ILO AC Specifications Spec ID [13] SID234 Parameter TSTARTILO1 SID236[13] TILODUTY SID237 FILOTRIM1 Description ILO startup time - - 2 ms - ILO duty cycle 40 50 60 % - ILO frequency range 20 40 80 kHz - Note 13. Guaranteed by characterization. Document Number: 002-20489 Rev. *C Page 25 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Watch Crystal Oscillator Table 33. Watch Crystal Oscillator (WCO) Specifications Spec ID# Parameter Description Min Typ Max Units SID398 FWCO Crystal Frequency - 32.768 - kHz SID399 FTOL Frequency tolerance - 50 250 ppm Details / Conditions - With 20-ppm crystal SID400 ESR Equivalent series resistance - 50 - k - SID401 PD Drive Level - - 1 W - SID402 TSTART Startup time - - 500 ms - SID403 CL Crystal Load Capacitance 6 - 12.5 pF - SID404 C0 Crystal Shunt Capacitance - 1.35 - pF - SID405 IWCO1 Operating Current (high power mode) - - 8 A - SID406 IWCO2 Operating Current (low power mode) - - 1 A - External Clock Table 34. External Clock Specifications Min Typ Max Units Details/Conditions SID305[14] ExtClkFreq Spec ID Parameter External clock input frequency 0 - 48 MHz - SID306[14] Duty cycle; measured at VDD/2 45 - 55 % - Min Typ Max Units Details/Conditions 3 - 4 Periods - Min Typ Max Units Details / Conditions - - 1.6 ns - ExtClkDuty Description Block Table 35. Block Specs Spec ID Parameter SID262[14] TCLKSWITCH Description System clock source switching time Smart I/O Table 36. Smart I/O Pass-through Time (Delay in Bypass Mode) Spec ID# SID252 Parameter Description PRG_BYPASS Max delay added by Smart I/O in bypass mode Note 14. Guaranteed by characterization. Document Number: 002-20489 Rev. *C Page 26 of 36 PSoC(R) 4: PSoC 4700S Family Datasheet PRELIMINARY Ordering Information The PSoC 4700S part numbers and features are listed in the following table. Table 37. PSoC 4700S Ordering Information 10-bit CSD ADC LP Comparators TCPWM Blocks SCB Blocks Smart I/Os GPIO WLCSP (0.35-mm pitch) 24-Pin QFN 48-Pin TQFP 4745 MagSense 4744 CapSense 4725 SRAM (KB) 4724 Flash (KB) Category Package Max CPU Speed (MHz) Features CY8C4724FNI-S402 24 16 2 0 1 1 2 5 2 2 21 - - CY8C4724LQI-S401 24 16 2 0 1 1 2 5 2 2 19 - - CY8C4725FNI-S402 24 32 4 0 1 1 2 5 2 4 21 - - CY8C4725LQI-S401 24 32 4 0 1 1 2 5 2 4 19 - - CY8C4744FNI-S402 48 16 2 0 1 1 2 5 2 2 21 - - CY8C4744LQI-S401 48 16 2 0 1 1 2 5 2 2 19 - - CY8C4744AZI-S403 48 32 2 0 1 1 2 5 2 4 36 - - CY8C4745FNI-S402 48 32 4 0 1 1 2 5 2 4 21 - - CY8C4745LQI-S401 48 32 4 0 1 1 2 5 2 4 19 - - CY8C4745AZI-S403 48 32 4 0 1 1 2 5 2 8 36 - - CY8C4745FNI-S412 48 32 4 1 1 1 2 5 2 8 21 - - CY8C4745LQI-S411 48 32 4 1 1 1 2 5 2 8 19 - - CY8C4745AZI-S413 48 32 4 1 1 1 2 5 2 16 36 - - MPN The nomenclature used in the preceding table is based on the following part numbering convention: Field Description Values Meaning CY8C Cypress Prefix 4 Architecture 4 PSoC 4 A Family 7 4700 Family B CPU Speed 2 24 MHz 4 48 MHz C Flash Capacity 4 16 KB 5 32 KB AZ TQFP (0.5-mm pitch) DE Package Code LQ QFN FN CSP F Temperature Range I Industrial S PSoC 4 S-Series S Sub-family Identifier M PSoC 4 M-Series L PSoC 4 L-Series XYZ Attributes Code 000-999 Code of feature set in the specific family Document Number: 002-20489 Rev. *C Page 27 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet The following is an example of a part number: Example CY8C 4 A B C DE F - S XYZ Cypress Prefix Architecture 4: PSoC 4 1: 2: 4200 Family 7: 4100 4700 Family Family within Architecture CPU Speed 4: 48 MHz 5: 32 KB Flash Capacity AZ: TQFP AX: TQFP Package Code I: Industrial Temperature Range Silicon Family Attributes Code Document Number: 002-20489 Rev. *C Page 28 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Packaging The PSoC 4700S will be offered in 48-pin TQFP, 24-pin QFN, and 25-ball WLCSP packages. Package dimensions and Cypress drawing numbers are in the following table. Table 38. Package List Spec ID# Package Description Package Diagram BID20 48-pin TQFP 7 x 7 x 1.4 mm height with 0.5-mm pitch 51-85135 BID34 24-pin QFN 4 x 4 x 0.6 mm height with 0.5-mm pitch 001-13937 BID34F 25-ball WLCSP 2.02 x 1.93 x 0.48 mm height with 0.35-mm pitch 002-09957 Table 39. Package Thermal Characteristics Parameter Description Package Min Typ Max Units TA Operating ambient temperature -40 25 85 C TJ Operating junction temperature -40 - 100 C TJA Package JA 48-pin TQFP - 73.5 - C/Watt TJC Package JC 48-pin TQFP - 33.5 - C/Watt TJA Package JA 24-pin QFN - 21.7 - C/Watt TJC Package JC 24-pin QFN - 5.6 - C/Watt TJA Package JA 25-ball WLCSP - 54.6 - C/Watt TJC Package JC 25-ball WLCSP - 0.5 - C/Watt Table 40. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature All 260 C 30 seconds Table 41. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020 Package MSL All except WLCSP MSL 3 25-ball WLCSP MSL 1 Document Number: 002-20489 Rev. *C Page 29 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Package Diagrams Figure 6. 48-pin TQFP Package Outline 51-85135 *C Figure 7. 24-pin QFN Package Outline 001-13937 *G Document Number: 002-20489 Rev. *C Page 30 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floating and not connected to any other signal. Figure 8. 25-ball WLCSP Package Outline 002-09957 ** Document Number: 002-20489 Rev. *C Page 31 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Acronyms Table 42. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer bus Table 42. Acronyms Used in this Document (continued) Acronym Description ESD electrostatic discharge ETM embedded trace macrocell FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin ALU arithmetic logic unit AMUXBUS analog multiplexer bus HVI high-voltage interrupt, see also LVI, LVD API application programming interface IC integrated circuit APSR application program status register IDAC current DAC, see also DAC, VDAC Arm(R) advanced RISC machine, a CPU architecture IDE integrated development environment ATM automatic thump mode I BW bandwidth CAN Controller Area Network, a communications protocol 2C, or IIC IIR Inter-Integrated Circuit, a communications protocol infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO internal main oscillator, see also ILO CMRR common-mode rejection ratio IMO CPU central processing unit INL integral nonlinearity, see also DNL CRC cyclic redundancy check, an error-checking protocol I/O input/output, see also GPIO, DIO, SIO, USBIO IPOR initial power-on reset DAC digital-to-analog converter, see also IDAC, VDAC IPSR interrupt program status register DFB digital filter block IRQ interrupt request DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. ITM instrumentation trace macrocell DMIPS Dhrystone million instructions per second DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DNU do not use DR port write data registers DSI digital system interconnect DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory LCD liquid crystal display LIN Local Interconnect Network, a communications protocol. LR link register LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt, see also HVI LVTTL low-voltage transistor-transistor logic MAC multiply-accumulate MCU microcontroller unit MISO master-in slave-out NC no connect nonmaskable interrupt EMI electromagnetic interference NMI EMIF external memory interface NRZ non-return-to-zero EOC end of conversion NVIC nested vectored interrupt controller EOF end of frame NVL nonvolatile latch, see also WOL execution program status register opamp operational amplifier EPSR Document Number: 002-20489 Rev. *C Page 32 of 36 PRELIMINARY Table 42. Acronyms Used in this Document (continued) Acronym Description PSoC(R) 4: PSoC 4700S Family Datasheet Table 42. Acronyms Used in this Document (continued) Acronym Description PAL programmable array logic, see also PLD SWD serial wire debug, a test protocol PC program counter SWV single-wire viewer PCB printed circuit board TD transaction descriptor, see also DMA PGA programmable gain amplifier THD total harmonic distortion PHUB peripheral hub TIA transimpedance amplifier PHY physical layer TRM technical reference manual PICU port interrupt control unit TTL transistor-transistor logic PLA programmable logic array TX transmit PLD programmable logic device, see also PAL UART PLL phase-locked loop Universal Asynchronous Transmitter Receiver, a communications protocol PMDD package material declaration data sheet POR power-on reset PRES precise power-on reset PRS pseudo random sequence PS port read data register PSoC(R) Programmable System-on-ChipTM PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I2C serial clock SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset Document Number: 002-20489 Rev. *C UDB universal digital block USB Universal Serial Bus USBIO USB input/output, PSoC pins used to connect to a USB port VDAC voltage DAC, see also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal Page 33 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Document Conventions Units of Measure Table 43. Units of Measure Symbol Unit of Measure C degrees Celsius dB decibel fF femto farad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz k kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second A microampere F microfarad H microhenry s microsecond V microvolt W microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz V volt Document Number: 002-20489 Rev. *C Page 34 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Document History Page Description Title: PSoC(R) 4: PSoC 4700S Family Datasheet Programmable System-on-Chip (PSoC) Document Number: 002-20489 Revision ECN Orig. of Change Submission Date ** 5843084 WKA 09/12/2017 New data sheet. *A 6219085 QVS 06/26/2018 Updated Features: Updated Inductive Sensing: Updated More Information: Updated Electrical Specifications: Updated Analog Peripherals: Updated Inductive Sensing (MagSense): Updated Table 13. Updated Package Diagrams: Spec 001-13937 - Changed revision from *F to *G. Updated to new template. *B 6290288 QVS 08/24/2018 Changed "IndSense" to "MagSense" throughout the document. Updated links in More Information. *C 6318929 QVS 09/24/2018 Updated Features, More Information. Updated Block Diagram. Removed Functional Description and updated Functional Overview. Updated Pinouts. Document Number: 002-20489 Rev. *C Description of Change Page 35 of 36 PRELIMINARY PSoC(R) 4: PSoC 4700S Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R) Solutions Products Arm(R) Cortex(R) Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless (c) Cypress Semiconductor Corporation, 2017-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-20489 Rev. *C Revised September 24, 2018 Page 36 of 36