19-0158; Rev 0; 7/93 Complete, Dual, 12-Bit Multiplying DACs The MX7837/MX7847 are dual, 12-bit, multiplying, voltage-output digital-to-analog converters (DACs). Each DAC has an output amplifier and a feedback resistor. The output amplifier is capable of developing 10V across a 2k load. The amplifier feedback resistor is internally connected to VOUT on the MX7847. No external trims are required to achieve full 12-bit performance over the entire operating temperature range. The MX7847 has a 12-bit parallel data input, whereas the MX7837 operates with a double-buffered 8-bit-bus interface that loads data in two write operations. All logic signals are level triggered and are TTL and CMOS compatible. Fast timing specifications make these DACs compatible with most microprocessors. ________________________Applications Small Component-Count Analog Systems Digital Offset/Gain Adjustments Industrial Process Control Function Generators ____________________________Features Two 12-Bit Multiplying DACs with Buffered Voltage Output Specified with 12V or 15V Supplies No External Adjustments Required Fast Timing Specifications 24-Pin DIP and SO Packages 12-Bit Parallel Interface (MX7847) 8-Bit + 4-Bit Interface (MX7837) ______________Ordering Information ERROR (LSB) PART TEMP. RANGE PIN-PACKAGE MX7837JN 0C to +70C 24 Narrow Plastic DIP 1 MX7837KN MX7837JR MX7837KR MX7837C/D 0C to +70C 0C to +70C 0C to +70C 0C to +70C 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO Dice* 1/2 1 1/2 1 Ordering Information continued on last page. * Contact factory for availability and processing to MIL-STD-883. Automatic Test Equipment Automatic Calibration Machine and Motion Control Systems _________Typical Operating Circuits VDD Waveform Reconstruction Synchro Applications MSB LSB INPUT INPUT LATCH LATCH 4 8 DAC LATCH A 12 _________________Pin Configurations TOP VIEW CS 1 24 DB0/DB8 RFBA 2 23 DB1/DB9 VREFA VREFA 3 22 DB2/DB10 VREFB VOUTA 4 21 DB3/DB11 AGNDA 5 VDD 6 MX7837 20 DB4 19 DB5 VSS 7 18 DB6 AGNDB 8 17 DB7 VOUTB 9 16 A0 VREFB 10 15 A1 DGND 11 14 LDAC RFBB 12 VOUTA DAC A AGNDA RFBB DB0 DB7 LDAC CS WR A0 A1 DAC B CONTROL LOGIC 12 DAC LATCH B 8 4 LSB MSB INPUT INPUT LATCH LATCH VOUTB AGNDB MX7837 13 WR DIP/SO MX7847 on last page. RFBA DGND VSS MX7847 on last page. ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. 1 MX7837/MX7847 _______________General Description MX7837/MX7847 Complete, Dual, 12-Bit Multiplying DACs ABSOLUTE MAXIMUM RATINGS VDD to DGND, AGNDA, AGNDB ............................-0.3V to +17V VSS to DGND, AGNDA, AGNDB (Note 1) ..............+0.3V to -17V VREFA, VREFB to AGNDA, AGNDB .. (VSS - 0.3V) to (VDD + 0.3V) AGNDA, AGNDB to DGND.........................-0.3V to (VDD + 0.3V) VOUTA, VOUTB to AGNDA, AGNDB .....(VSS - 0.3V) to (VDD + 0.3V) RFBA, RFBB to AGNDA, AGNDB .......(VSS - 0.3V) to (VDD + 0.3V) Digital Inputs to DGND ...............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) Narrow Plastic DIP (derate 13.33mW/C above +70C)....1067mW SO (derate 11.76mW/C above +70C) .........................941mW Narrow CERDIP (derate 12.50mW/C above +70C) ..1000mW Operating Temperature Ranges: MX78_7J_/K_ ........................................................0C to +70C MX78_7A_/B_ .................................................. -40C to +85C MX78_7SQ/TQ ............................................... -55C to +125C Storage Temperature Range ............................ -65C to +150C Lead Temperature (soldering, 10sec) .............................+300C Note 1: If VSS is open-circuited with VDD and either AGND applied, the VSS pin will float positive exceeding the Absolute Maximum Ratings. If this possibility exists, a Schottky diode connected between VSS and GND ensures the maximum ratings will be observed. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA = VREFB = +10V, RL = 2k, CL = 100pF, VOUT connected to RFB (MX7837), TA = TMIN to TMAX, unless otherwise noted.) (Note 2) PARAMETER SYMBOL STATIC PERFORMANCE (Note 3) Resolution CONDITIONS MIN N Relative Accuracy INL Differential Nonlinearity DNL Zero-Code Offset Error MAX 12 1 MX78_7K/B/T 1/2 Guaranteed monotonic 1 TA = +25C 2 Loaded with all 0s, MX78_7J/A tempco = 5V/C typ TA = TMIN to TMAX MX78_7K/B MX78_7S/T 4 TA = +25C TA = TMIN to TMAX UNITS Bits MX78_7J/A/S Loaded with all 1s, tempco = 2ppm of FSR/C typ Gain Error TYP 3 LSB LSB mV 5 MX78_7J/A/S 5 MX78_7K/B/T 2 MX78_7J/A/S 7 MX78_7K/B/T 4 LSB REFERENCE INPUTS VREF Input Resistance 8 VREFA, VREFB Resistance Matching 10 13 k 0.5 3 % DIGITAL INPUTS Input High Voltage VINH Input Low Voltage VINL Input Current 2.4 0.8 Digital inputs at 0V and VDD Input Capacitance (Note 4) V 1 A 8 pF ANALOG OUTPUTS DC Output Impedance Short-Circuit Current 2 VOUT connected to AGND 0.2 15 mA _______________________________________________________________________________________ Complete, Dual, 12-Bit Multiplying DACs (VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA = VREFB = +10V, RL = 2k, CL = 100pF, VOUT connected to RFB (MX7837), TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 16.5 V POWER REQUIREMENTS VDD Range VDD VSS Range VSS Positive Supply Current IDD Output unloaded 5 ISS Output unloaded 4 Negative Supply Current Power-Supply Rejection AC CHARACTERISTICS Voltage-Output Settling Time Slew Rate Digital-to Analog Glitch Impulse Channel-to-Channel Isolation (VREFA to VOUTB, VREFB to VOUTA) Multiplying Feedthrough Error Unity-Gain Small-Signal Bandwidth Digital Crosstalk Output Noise Voltage at +25C (0.1Hz to 10Hz) -11.4 -16.5 V 10 mA 6 mA Gain/VDD VDD = 15V 5%, VREF = -10V 0.01 Gain/VSS VSS = -15V 5%, VREF = 10V Gain/VDD VDD = 12V 5%, VREF = -8.9V 0.01 Gain/VSS VSS = -12V 5%, VREF = 8.9V 0.01 tS Settling time to within 1/2LSB of final DAC value; DAC latch alternately loaded will all 0s and all 1s Q DAC latch alternately loaded with 01...11 and 10...00 VREF = 20p-p, 10kHz sine wave, Alternate DAC Latch Loaded with all 0s Full-Power Bandwidth Total Harmonic Distortion 11.4 THD VREF_ = 20Vp-p, 10kHz sine wave, latches loaded with all 0s VREF = 100mVp-p sine wave, DAC latch loaded with all 1s VREF = 20Vp-p Sine wave, DAC latch loaded with all 1s VREF = 6VRMS, 1kHz, DAC latch loaded with all 1s Code transition from all 0s to all 1s; see Typical Operating Characteristics graphs Amplifier noise and Johnson noise of RFB 0.01 % per % 4 s 7 V/s 60 nV-s -95 dB -90 dB 1 MHz 125 kHz -88 dB 10 nV-s 2 VRMS Note 2: The analog outputs can swing to within 2.5V of the supply rails. Hence, for good linearity towards full-scale, |VREFA| and |VREFB| must be at least 2.5V lower than VDD and |VSS|. Tests done with supply voltages below 12.5V are done with VREFA = VREFB = 8.9V. Note 3: Static performance tested at VDD = +15V, VSS = -15V. Performance over supplies guaranteed by PSRR test. Note 4: Guaranteed by design. _______________________________________________________________________________________ 3 MX7837/MX7847 ELECTRICAL CHARACTERISTICS (continued) TIMING CHARACTERISTICS (VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) (Note 5) PARAMETER SYMBOL MX78_7J/K/A/B MIN MAX 0 CONDITIONS MX78_7S/T MIN MAX 0 UNITS CS to WR Setup Time t1 CS to WR Hold Time t2 0 0 ns WR Pulse Width t3 80 80 ns Data to WR Setup Time t4 80 80 ns Data to WR Hold Time t5 10 10 ns Address to WR SetupTime t6 MX7837 only 15 15 ns Address to WR Hold Time t7 MX7837 only 15 15 ns LDAC Pulse Width t8 MX7837 only 80 80 ns ns Note 5: All input signals are specified with tR = tF 5ns. Logic swing is 0V to 5V. __________________________________________Typical Operating Characteristics (TA = +25C, VDD = 15V, VSS = -15V, RL = 2k, CL = 100pF, unless otherwise noted) OUTPUT VOLTAGE SWING vs. RESISTIVE LOAD NOISE SPECTRAL DENSITY SMALL-SIGNAL FREQUENCY RESPONSE 5 25 15 10 5 0 -5 200 10 1k 100 -25 10 10k 100 1k 10k 10k 1k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) MULTIPLYING FEEDTHROUGH ERROR TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (BANDWIDTH = 80kHz) TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (BANDWIDTH > 500kHz) -60 -94 VREFA = 20Vp-p VREFB = AGNDB DAC CODE = 00...00 -45 VREF = 6VRMS DAC CODE = 111...111 -96 VREF = 6VRMS DAC CODE = 111...111 -65 -70 -50 THD (dB) -98 -55 -60 -65 -100 -75 -80 -85 -102 -70 -90 -75 -104 -95 -80 -85 -100 -106 1k 10k 100k FREQUENCY (Hz) 4 100 100k LOAD RESISTANCE () -35 -40 -10 -20 0 0 VREF = 100mVp-p DAC CODE = 11...111 GAIN = -1 -15 100 THD (dB) VOUT (Vp-p) 20 VREF = 0V DAC CODE = 11...111 GAIN = -1 300 GAIN (dB) NOISE SPECTRAL DENSITY (nV/ Hz) VREF = 20Vp-p at 1kHz ATTENUATION (dB) MX7837/MX7847 Complete, Dual, 12-Bit Multiplying DACs 1M 100 1k FREQUENCY (Hz) 10k 100 1k 10k FREQUENCY (Hz) _______________________________________________________________________________________ 100k Complete, Dual, 12-Bit Multiplying DACs LARGE-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE AGNDA A AGNDA A = VOUTA, 50mV/div TIMEBASE = 2s/div VREFA = 100mV SQUARE WAVE A A = VOUTA, 5V/div TIMEBASE = 2s/div VREFA = 10V SQUARE WAVE ______________________________________________________________Pin Description PIN MX7837 MX7847 NAME FUNCTION 1 - CS - 1 CSA Chip-Select Input for DAC A - active-low logic input 2 - RFBA Amplifier Feedback Resistor for DAC A Chip-Select Input for DAC B - active-low logic input Chip Select - active-low logic input - 2 CSB 3 3 VREFA Reference Input Voltage for DAC A 4 4 VOUTA Analog Output Voltage from DAC A 5 5 AGNDA 6 6 VDD Positive Power Supply 7 7 VSS Negative Power Supply 8 8 AGNDB 9 9 VOUTB Analog Output Voltage from DAC B 10 10 VREFB Reference Input Voltage for DAC B 11 11 DGND Digital Ground 12 - RFBB Amplifier Feedback Resistor for DAC B - 12 DB11 Data Bit 11 (MSB) 13 13 WR Analog Ground for DAC A Analog Ground for DAC B Write Input - active-low logic input (MX7837); positive-edge-triggered input used with CSA and CSB (MX7847) 14 - LDAC - 14-24 DB10-DB0 15 - A1 Address Input - most significant address input for input latches Address Input - least significant address input for input latches 16 - A0 17-20 - 21-24 - DB7-DB4 DB3/DB11DB0/DB8 Asynchronous Load - DAC input, active-low Data Bit 10 to Data Bit 0 (LSB) Data Bit 7 to Data Bit 4 Data Bit 3 to Data Bit 0 (LSB), or Data Bit 11 (MSB) to Data Bit 8 _______________________________________________________________________________________ 5 MX7837/MX7847 ____________________________Typical Operating Characteristics (continued) (TA = +25C, VDD = 15V, VSS = -15V, RL = 2k, CL = 100pF, unless otherwise noted.) MX7837/MX7847 Complete, Dual, 12-Bit Multiplying DACs VREF R R Interface Logic Information (MX7847) R 2R 2R 2R 2R 2R 2R C B A S9 S8 S0 2R R/2 VOUT AGND SHOWN FOR ALL 1s ON DAC Figure 2 shows the MX7847 input control logic. The device contains two independent DACs, each with its own CS input and a common WR input. CSA and WR control data loading to the DAC A latch, and CSB and WR control data loading to the DAC B latch. The latches are edge triggered so that input data is latched to the respective latch on WR's rising edge. The same data will be latched to both DACs if CSA and CSB are low and WR is taken high. Table 1 shows the device control-logic truth table, and Figure 3 shows the writecycle timing diagram. Table 1. MX7847 Truth Table CSA CSB X X 1 No Data Transfer 1 1 X No Data Transfer D/A Section 0 1 Data Latched to DAC A Figure 1 shows a simplified circuit diagram for one of the DACs and the output amplifier. Using a segmented scheme, the two MSBs of the 12-bit data word are decoded to drive the three switches (A to C). The remaining 10 bits drive the switches (S0 to S9) in a standard R-2R ladder. Each switch (A to C) directs 1/4 of the total reference current, and the remaining current passes through the R-2R section. The output amplifier and feedback resistor convert current to voltage as follows: VOUT_ = (-D)(VREF_), where D is the fractional representation of the digital word. (D can be set from 0 to 4095/4096.) The output amplifier is capable of developing 10V across a 2k load. It is internally compensated and settles to 0.01% FSR (1/2LSB) in less than 4s. VOUT on the MX7837 is not internally connected to RFB. 1 0 Data Latched to DAC B 0 0 Figure 1. D/A Simplified Circuit Diagram _______________Detailed Description 1 1 X = Don't Care WR Function Data Latched to Both DACs 0 Data Latched to DAC A 0 Data Latched to DAC B 0 Data Latched to Both DACs = Rising Edge Triggered Interface Logic Information (MX7837) The MX7837 input loading structure is configured for interfacing with 8-bit-wide data-bus microprocessors. Each DAC has two 12-bit latches: an input latch, and a DAC latch. Each input latch is subdivided into a leastsignificant 8-bit latch and a most-significant 4-bit latch. The data held in the DAC latches determines the outputs. Figure 4 shows the MX7837 input control logic, and Figure 5 shows the write-cycle timing diagram. CSA, CSB CSA DAC A LATCH t1 WR t3 t2 WR CSB DAC B LATCH t4 DATA Figure 2. MX7847 Input Control Logic 6 t5 VALID DATA Figure 3. MX7847 Write-Cycle Timing Diagram _______________________________________________________________________________________ Complete, Dual, 12-Bit Multiplying DACs DAC A LATCH DAC B LATCH 12 12 CS WR 4 DAC A MS INPUT LATCH A0 A1 A0/A1 ADDRESS VALID t7 t6 CS 4 t1 8 DAC A LS INPUT LATCH 8 t2 t3 WR t5 t4 DATA DAC B MS INPUT LATCH MX7837/MX7847 LDAC VALID DATA t8 DAC B LS INPUT LATCH LDAC Figure 5. MX7837 Write-Cycle Timing Diagram 8 DB7 DB0 Figure 4. MX7837 Input Control Logic CS, WR, A0, and A1 control data loading to the input latches. The eight data inputs accept right-justified data, which can be loaded to the input latches in any sequence. If LDAC is held high, loading data to the input latches will not change the analog output. A0 and A1 determine which input latch will receive the data when CS and WR are low. Table 2 shows the control logic truth table. Table 2. MX7837 Truth Table CS WR A1 A0 LDAC Function and independent of WR. This is useful in many applications, especially in updating multiple MX7837s simultaneously. However, be careful when exercising LDAC during a write cycle; if an LDAC operation overlaps a CS and WR operation, invalid data may be latched to the output. To avoid this, LDAC must remain low after CS or WR have returned high for a period equal to or greater than t8, the minimum LDAC pulse width. Unipolar Binary Operation Figure 6 shows DAC A (MX7837/MX7847) connected for unipolar binary operation. Similar connections apply for DAC B. When VIN is an AC signal, the circuit performs 2-quadrant multiplication. Table 3 shows the code table for this circuit. On the MX7847, the RFB feedback resistor is internally connected to VOUT. 1 X X X 1 No Data Transfer X 1 X X 1 No Data Transfer 0 0 0 0 1 DAC A LS Input Latch Transparent 0 0 0 1 1 DAC A MS Input Latch Transparent 0 0 1 0 1 DAC B LS Input Latch Transparent 1111 1111 1111 0 0 1 1 1 1 1 X X 0 DAC B MS Input Latch Transparent Updated Simultaneously from the Respective Input Latches 4095 -VIN x 4096 1000 0000 0000 2048 1 -VIN x = - VIN 2 4096 0000 0000 0001 1 -VIN x 4096 0000 0000 0000 0V Table 3. Unipolar Code Table DAC Latch Contents MSB LSB X = Don't Care The LDAC input controls 12-bit data transfer from the input latches to the DAC latches. When LDAC is taken low, both DAC latches (thus, both analog outputs) are updated simultaneously. When LDAC is low, the DAC latches are transparent; DAC data is latched on the rising edge of LDAC. The LDAC input is asynchronous Analog Output, VOUT V Note : 1LSB = IN 4096 _______________________________________________________________________________________ 7 MX7837/MX7847 Complete, Dual, 12-Bit Multiplying DACs Bipolar Operation (4-Quadrant Multiplication) Figure 7 shows the MX7837/MX7847 connected for binary operation. The offset-binary coding is shown in Table 4. When VIN is an AC signal, the circuit performs 4-quadrant multiplication. R1, R2, and R3 resistors should be 0.01% ratio matched to maintain gain-error specifications. On the MX7847, the R FB feedback resistor is internally connected to VOUT. Table 4. Bipolar Code Table DAC Latch Contents MSB LSB Analog Output, VOUT 1111 1111 1111 2047 +VIN x 2048 1000 0000 0001 1 +VIN x 2048 1000 0000 0000 0V 0111 1111 1111 1 -VIN x 2048 0000 0000 0000 2048 -VIN x = - VIN 2048 __________Applications Information Ground Management The use of an uninterrupted ground plane is strongly recommended. AC or transient voltages between analog and digital grounds (between AGNDA/AGNDB and DGND) can inject noise into the analog circuitry. Connect the MX7837/MX7847 AGNDs and DGND directly to the ground plane or to a star ground to ensure that they are at the same potential. In complex systems with separate analog and digital ground planes, connect two diodes (1N914 or equivalent) in inverse parallel between the AGND and DGND pins. Power-Supply Decoupling To minimize noise, decouple the VDD and VSS lines to DGND using a 10F capacitor in parallel with a 0.1F ceramic capacitor. Minimize capacitor lead lengths for best noise rejection. Operation with Reduced Power-Supply Voltages The MX7837/MX7847 are specified for operation with V DD/V SS = 11.4V to 16.5V. However, the output amplifier requires 2.5V of headroom, so the reference input should not come within 2.5V of VDD/VSS in order to maintain accuracy at full scale. V Note : 1LSB = IN 2048 VDD VIN VREFA DGND RFBA* VOUTA* DAC A AGNDA VSS VSS VOUT VDD VDD VOUT VIN VREFA MX7837 MX7847 DAC A VSS * INTERNALLY CONNECTED ON MX7847 R2 20k R1 20k VDD DGND AGNDA R3 10k RFBA* VOUTA MX7837 MX7847 VSS VSS Figure 6. Unipolar Binary Operation 8 MAX427 Figure 7. Bipolar Offset Binary Operation _______________________________________________________________________________________ * INTERNALLY CONNECTED ON MX7847 Complete, Dual, 12-Bit Multiplying DACs ____Ordering Information (continued) PART TOP VIEW CSA 1 24 DB0 CSB 2 23 DB1 VREFA 3 22 DB2 VOUTA 4 21 DB3 AGNDA 5 VDD 6 MX7847 20 DB4 19 DB5 VSS 7 18 DB6 AGNDB 8 17 DB7 VOUTB 9 16 DB8 VREFB 10 15 DB9 DGND 11 14 DB10 DB11 12 13 WR DIP/SO Typical Operating Circuits (continued) TEMP. RANGE PIN-PACKAGE ERROR (LSB) MX7837AN -40C to +85C 24 Narrow Plastic DIP 1 MX7837BN MX7837AR MX7837BR MX7837AQ MX7837BQ MX7837SQ MX7837TQ MX7847JN -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 0C to +70C 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow Plastic DIP 1/2 1 1/2 1 1/2 1 1/2 1 MX7847KN MX7847JR MX7847KR MX7847C/D MX7847AN MX7847BN MX7847AR MX7847BR 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO Dice* 24 Narrow Plastic DIP 24 Narrow Plastic DIP 24 Wide SO 24 Wide SO 1/2 1 1/2 1 1 1/2 1 1/2 MX7847AQ MX7847BQ MX7847SQ MX7847TQ -40C to +85C -40C to +85C -55C to +125C -55C to +125C 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow CERDIP 24 Narrow CERDIP 1 1/2 1 1/2 VDD DAC LATCH A VREFA VOUTA DAC A VREFB AGNDA DB0 DB11 DAC B WR CSA CSB CONTROL LOGIC VOUTB DAC LATCH B AGNDB MX7847 DGND VSS _______________________________________________________________________________________ 9 MX7837/MX7847 ______Pin Configurations (continued) MX7837/MX7847 Complete, Dual, 12-Bit Multiplying DACs __________________________________________________________Chip Topographies MX7837 V REFA R FBA MX7847 CS DB0/DB8 DB1/DB9 DB2/DB10 V REFA DB3/ DB11 V OUTA DB4 DB5 AGNDA 0.250" (6.35mm) V DD V SS V SS DB6 DB7 AGNDB V OUTB A0 CSB CSA DB0 DB1 DB2 DB3 V OUTA DB4 DB5 AGNDA 0.250" (6.35mm) V DD V SS V SS AGNDB DB6 DB7 VOUTB DB8 A1 VREFB DGND RFBB WR LDAC 0.140" (3.56mm) TRANSISTOR COUNT: 1240; SUBSTRATE CONNECTED TO V DD. 10 DB9 VREFB DGND DB11 WR DB10 0.140" (3.56mm) TRANSISTOR COUNT: 1240; SUBSTRATE CONNECTED TO V DD. ______________________________________________________________________________________ Complete, Dual, 12-Bit Multiplying DACs DIM A A1 A2 A3 B B1 C D D1 E E1 e eA eB L D1 E E1 D A2 A A3 A1 C B1 eA B eB DIM E MILLIMETERS MIN MAX - 5.08 0.38 - 3.18 3.81 1.40 2.03 0.41 0.56 1.27 1.65 0.20 0.30 31.37 32.13 1.27 2.03 7.62 8.26 6.10 7.11 2.54 BSC 7.62 BSC - 10.16 2.92 3.81 0 15 21-337A L e INCHES MAX MIN 0.200 - - 0.015 0.150 0.125 0.080 0.055 0.022 0.016 0.065 0.050 0.012 0.008 1.265 1.235 0.080 0.050 0.325 0.300 0.280 0.240 0.100 BSC 0.300 BSC 0.400 - 0.150 0.115 15 0 A A1 B C D E e H h L H 24-PIN PLASTIC DUAL-IN-LINE (NARROW) PACKAGE INCHES MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.614 0.598 0.299 0.291 0.050 BSC 0.419 0.394 0.030 0.010 0.050 0.016 8 0 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.35 0.49 0.23 0.32 15.20 15.60 7.40 7.60 1.27 BSC 10.00 10.65 0.25 0.75 0.40 1.27 0 8 21-338A D h x 45 A 0.127mm 0.004in. e B A1 C L 24-PIN PLASTIC SMALL-OUTLINE PACKAGE ______________________________________________________________________________________ 11 MX7837/MX7847 ________________________________________________________Package Information MX7837/MX7847 Complete, Dual, 12-Bit Multiplying DACs ___________________________________________Package Information (continued) DIM S1 S E1 E D A A B B1 C D E E1 e L L1 Q S S1 INCHES MAX MIN 0.200 - 0.023 0.014 0.065 0.038 0.015 0.008 1.280 - 0.310 0.220 0.320 0.290 0.100 BSC 0.200 0.125 - 0.150 0.060 0.015 0.098 - - 0.005 15 0 MILLIMETERS MIN MAX - 5.08 0.36 0.58 0.97 1.65 0.20 0.38 - 32.51 5.59 7.87 7.37 8.13 2.54 BSC 3.18 5.08 3.81 - 0.38 1.52 - 2.49 0.13 - 0 15 21-340B Q L L1 e B1 B C 24-PIN CERAMIC DUAL-IN-LINE (NARROW) PACKAGE Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1993 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.