[ASAHI KASEI] [AK4545] AK4545 AC' 97 Audio CODEC with SRC and DIT Features General Description * AC' 97 Rev. 2.1 Compliant * S/PDIF output * 18bit Resolution A/D and D/A * Exceeds PC99 Performance Requirements: AK4545 (@fs=48k) A/D..................90dBA D/A..................89dBA A-A..................95dBA * Analog Inputs: 4 Stereo Inputs: LINE, CD, VIDEO, AUX Speakerphone and PC BEEP Inputs 2 Independent MIC Inputs * Variable Sampling Rate Support 48k, 44.1k, 32k, 22.05k, 16k, 11.025k, 8k * Analog Output: Stereo LINE Output with volume control True Line Level with volume control Mono Output with volume control * 3D Stereo Enhancement * POP Function & DAC Feed Back Control * EAPD(External Amplifier Powerdown) Support * Power Supplies: Analog 5.0V, Digital 3.3V * Low Power Consumption 215mW(Analog:5V/Digital:3.3V) at full operation * 48 Pin LQFP Package The AK4545 is a 18bit high performance codec which supports variable sampling rate conversion compliant with Audio Codec ' 97 Rev 2.1 requirements. The AK4545 supports S/PDIF output that is digital audio transmitter of IEC958. Audio digital data in PC can be output by this S/PDIF out. The AK4545 provides two pairs of stereo outputs with independent volume controls, a mono output, and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. In addition, the AK4545 has the POP feature suitable for 3D positioning and direct output from DAC for AD monitoring. Sampling frequency is programmable through AC-link as 48k, 44.1k, 32k, 22.05k, 16k, 11.025k, and 8kHz. This setting is done independent to ADC and DAC side while L/R channels are kept identical. The AK4545 provides excellent audio performance, meeting or exceeding PC99 requirements for a PCI audio solution. It has low power consumption, and flexible power-down modes for use in laptops as well as desktop PCs and aftermarket add-in boards. Like the earlier pin-compatible AK4541, AK4543 and AK4544A , the AK4545 is available in a compact 48-lead LQFP package. Reference : Audio Codec ' 97 Revision 2.1 nBlock Diagram Digital Section EAPD PLL Analog Section CD Power Management AUX SYNC ADC SDATA_OUT SDATA_IN AC Link Interface BIT_CLK RESET# TX LINE_IN AC'97 Registers Control Singals and Control Logic Dataslot Controller S/PDIF Clock Out Generator Control Voltage VIDEO MIC1 MIC2 Phone PC_BEEP Output Mixer DAC Clock Generator Input Multiplexer Volume and Mute Control Volume and Mute Control LINE_OUT TRUE_LINE_LEVEL MONO_OUT 3D Stereo Enhancement Reference * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. MS0058-E-00 -12000/11 [ASAHI KASEI] [AK4545] 26 AVdd1 27 AVss1 28 Vref 29 VrefOut 30 AFILTL 31 AFILTR 32 VRAD 33 PLLfilter 34 VRDA 35 3Dcap LINE_OUT_L LINE_OUT_R 36 25 MONO_OUT 37 24 LINE_IN_R AVdd2 38 23 LINE_IN_L LNLVL_OUT_L 39 22 MIC2 NC 40 21 MIC1 LNLVL_OUT_R 41 20 CD_R AVss2 42 19 CD_GND TEST2 43 18 CD_L TEST3 44 17 VIDEO_R NC 45 16 VIDEO_L NC 46 15 AUX_R EAPD 47 14 AUX_L SPDIF_OUT 48 13 PHONE XTL_OUT DVss1 SDATA_OUT BIT_CLK 8 9 10 11 12 PC_BEEP XTL_IN 7 RESET# 6 SYNC 5 DVdd2 4 SDATA_IN 3 DVss2 2 DVdd1 MS0058-E-00 1 -22000/11 [ASAHI KASEI] [AK4545] Pin/Function No. 1 Signal Name DVdd1 I/O - 2 I 3 4 5 6 7 8 9 XTL_IN (MCLKI) XTL_OUT(open) DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 O I O O - 10 11 12 13 14 15 16 17 18 19 SYNC RESET# PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND I I I I I I I I I I 20 21 22 23 24 25 CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R AVdd1 I I I I I - 26 27 AVss1 Vref O 28 29 30 31 32 VrefOut AFILTL AFILTR VRAD PLLfilter O O O O O 33 34 35 36 37 38 VRDA 3Dcap LINE_OUT_L LINE_OUT_R MONO_OUT AVdd2 O O O O O - 39 40 41 42 43 44 45 46 47 48 LNLVL_OUT_L NC LNLVL_OUT_R AVss2 TEST2 TEST3 NC NC EAPD SPDIF_OUT O O I I O O MS0058-E-00 Description Digital power supply; 3.3V(DVdd1 = DVdd2) 0.1uF + 4.7uF capacitors should be connected to digital ground. 24.576MHz(512fs) Crystal is normally connected. If crystal is not connected, external clock can be used. 24.576MHz(512fs) Crystal. If external clock is used, this pin should be open. Digital Ground; 0V. This pin should be directly connected to DVss2 on board. Serial 256-bit AC97 data stream from digital controller 12.288MHz(256fs) serial data clock Digital Ground; 0V. This pin should be directly connected to DVss1 on board. Serial 256-bit AC97 data stream to digital controller Digital power supply; 3.3V(DVdd1 = DVdd2) 0.1uF + 4.7uF capacitors should be connected to digital ground. AC97 Sync Clock, 48kHz(1fs) fixed rate sampling rate AC97 Master Hardware Reset PC Speaker beep pass through From telephony subsystem speakerphone Aux Left Channel Aux Right Channel Video Audio Left Channel Video Audio Right Channel CD Audio Left Channel CD Audio analog ground CD_GND or analog ground should be connected through capacitor. CD Audio Right Channel Desktop Microphone Input Second Microphone Input Line In Left Channel Line In Right Channel Power supply; 5.0V(AVdd1=AVdd2) 0.1uF + 4.7uF capacitors should be connected to AVss1(analog ground). Analog Ground; 0V Reference Voltage Output; 0.1F +4.7F capacitors should be connected to Avss1(analog ground). Reference Voltage Output (2.5V,1.25mA) Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor. Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor. Vref for ADC ; 0.1uF + 4.7uF capacitors should be connected to analog ground. Loop filter for PLL is connected ; 36k resistor and 33nF capacitor in series and 390pF capacitor. Vref for DAC; 0.1uF + 4.7uF capacitors should be connected to analog ground. 3D Enhancement Cap; 27nF capacitor should be connected to analog ground. Line Out Left Channel Line Out Right Channel To telephony subsystem speakerphone Power supply; 5.0V(AVdd1=AVdd2) 0.1uF capacitor should be connected to AVss2(analog ground). True Line Level Out Left Channel No Connection True Line Level Out Right Channel Analog Ground Test pin (This pin should be open for normal operation) :With internal pull-down. Test pin (This pin should be open for normal operation) :With internal pull-down. No Connection No Connection EAPD(External amplified powerdown) SPDIF serial data output -32000/11 [ASAHI KASEI] [AK4545] Absolute Maximum Rating AVss1, AVss2, DVss1, DVss2 =0V (Note 1) Parameter Symbol min Power Supplies (Note 2) Analog(AVdd1 & AVdd2) VA -0.3 Digital(DVdd1 & DVdd2) VD -0.3 Input Current (any pins except for supplies) IIN Analog Input Voltage VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature Ta -10 Storage Temperature Ta -65 Note 1: All voltages with respect to ground . AGND(AVss1, AVss2) and DGND(DVss1, DVss2) should be same voltage. Note 2: Supplying Digital Power, Analog Power should be supplied. max Units 6.0 6.0 10 VA+0.3 VD+0.3 70 150 V V mA V V C C Warning: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes. Recommended Operating Condition AGND, DGND=0V (Note 1) Parameter Power Supplies AK4545 Analog Digital Note 1 : All voltages with respect to ground. MS0058-E-00 Symbol min typ max Units VA VD 4.75 3.135 5.0 3.3 5.25 3.465 V V -42000/11 [ASAHI KASEI] [AK4545] AK4545 Analog Characteristics Ta=25C,AVdd=5.0V,DVdd=3.3V, fs=48kHz unless otherwise specified, Signal Frequency =1kHz All volume setting for ADC/DAC performance measurement is 0dB. Parameter min typ max Audio-ADC Resolution 18 S/N (A weight, fs=48kHz) 83 90 S/N (A weight, fs=44.1kHz) 87 S/(N+D) (fs=48KHz, -1dB analog input) 70 82 Inter Channel Isolation 70 77 Inter Channel Gain Mismatch 0.5 Full Scale Input Voltage 0.88 1.0 1.12 Power Supply Rejection 50 Audio DAC: measured at AOUTL/AOUTR via MIXER path Resolution 18 S/N (A weighted, fs=48kHz) : mixer+DAC measured at AOUT 84 89 S/N (A weighted, fs=44.1kHz) : mixer+DAC measured at AOUT 88 S/(N+D) (fs=48KHz, -1dB digital input) 72 80 Inter Channel Isolation 70 80 Inter Channel Gain Mismatch 1.0 Full Scale Output Voltage 0.88 1.0 1.12 Total Out-of-Band Noise (28.8kHz - 100kHz) -70 Power Supply Rejection 50 MIC Amplifier / MUX Gain : 20dB is selected 18 20 22 Master volume (Mono, Stereo, True Line Level Out) : 1.5dB x 32 step Step Size -1.5 Attenuation Control Range -46.5 0 Load Resistance 10 PC Beep : 3dB x 16 step Step Size -3.0 Attenuation Control Range -45 0 Analog Mixer : 1.5dB x 32 step Step Size -1.5 Gain Control Range -34.5 +12 Record Gain : 1.5dB x 16 step Step Size +1.5 Gain Control Range 0 +22.5 Mixer Input Voltage (except for MIC) 1.0 Input Voltage MIC : Gain = 0dB 1 MIC : Gain = 20dB 0.1 S/N(A weighed) : 0dB setting, 1 path is selected at Mixer CD to AOUT: 88 95 Other analog input to AOUT 95 Input Impedance (Input gain=0dB,Rec_MUTE=off) PC_BEEP only (10) 76 Others(PHONE, LINE, CD, AUX, VIDEO) (10) 40 Input Impedance (MIC1 and MIC2) (10) 20 Output load Resistance 10 (LINE_OUT_L/R, MONO_OUT, LNLVL_OUT_L/R) Vrefout Drivability 1.25 MS0058-E-00 Units Bits dB dB dBFS dB dB Vrms dB Bits dB dB dBFS dB dB Vrms dB dB dB dB dB k dB dB dB dB dB dB Vrms Vrms Vrms dB dB k k k k mA -52000/11 [ASAHI KASEI] [AK4545] Parameter Power Supplies Analog Power Supply Current(AVdd1 & AVdd2) All ON mode(all PR_bits are 0) Cold Reset status(Reset#=L, Vref is ON) All OFF mode(all PR_bits are 1) Digital Power Supply Current(DVdd1 & DVdd2) All ON mode(all PR_bits are 0) at DVDD=3.3V All OFF mode(all PR_bits are 1) min Filter Characteristics Ta=25C,AVdd=5.0V5%,DVdd=3.3V5% , fs=48KHz(fixed) Parameter min ADC Digital Filter (Decimation LPF) Passband (0.2dB) Note) 0 Stopband 28.8 Stopband Attenuation 70 Group Delay ADC Digital Filter (HPF) Frequency Response; -3dB -0.5dB -0.1dB DAC Digital Filter Passband (0.2dB) 0 Stopband 28.8 Group Delay Stopband Rejection 70 DAC Post filter Passband Frequency Response (0 - 19.2kHz) Note) This frequency scales with the sampling frequency ( fs). AK4545 DC Characteristics Ta=-1070C, VD= 3.3V5%, VA=5V5%, 50pF external load Parameter Symbol min H level input voltage C-coupled VIH 0.7xVD (XTAL_IN) direct VIH 0.8xVD L level input voltage C-coupled VIL (XTAL_IN) direct VIL H level input voltage VIH 0.7xVD (RESET#, SYNC, SDATA_OUT) L level input voltage VIL ( RESET#, SYNC, SDATA_OUT) H level output voltage Iout= -1mA VOH VD-0.55 L level output voltage Iout= 1mA VOL Input leakage current(exclude pull up pins) Iin - MS0058-E-00 typ max Units 38 3.7 0 57 8 0.2 mA mA mA 6.9 0 11 0.4 mA mA typ Max Units 19.2 kHz kHz dB ms 0.5 7.5 21 49 Hz 19.2 0.5 0.1 kHz kHz ms dB dB typ - Max - - 0.3xVD 0.2xVD - Units V V V V V - 0.3xVD V - 0.55 10 V V A -62000/11 [ASAHI KASEI] [AK4545] Switching Characteristics Ta=25C, AVdd=5.0V5%, DVdd=3.3V5%, 50pF external load Parameter Symbol Min Master Clock Frequency Note) Fmclk If Crystal is not used. 45 AC link Interface Timing BIT_CLK frequency Fbclk BIT_CLK clock Period(Tbclk=1/Fbclk) Tbclk BIT_BLK low pulse width Tclk_low 36 BIT_BLK low pulse width Tclk_high 36 BIT_CLK rise time Trise_clk BIT_CLK fall time Tfall_clk SYNC frequency SYNC low pulse width Tsync_low SYNC high pulse width SYNC rise time SYNC fall time Setup time(SYNC, SDATA_OUT) Hold time(SYNC, SDATA_OUT) SDATA_IN delay time from BIT_CLK rising edge SDATA_IN rise time SDATA_IN fall time SDATA_OUT rise time SDATA_OUT fall time Cold Rest (SDATA_OUT=L, SYNC=L) RESET# active low pulse width RESET# inactive to BIT_CLK delay Warm Rest Timing SYNC active low pulse width SYNC inactive to BIT_CLK delay Typ 24.576 50 Tsync_high - Trise_sync Tfall_sync Tsetup Thold Tdelay 10 25 - 12.288 81.38 40.7 40.7 48 19.5 (240 cycle) 1.3 (16 cycle) - Trise_din Tfall_din Trise_dout Tfall_dout - max 55 Units MHz % 6 6 15 MHz ns ns ns ns ns kHz s (Tbclk) s (Tbclk) ns ns ns ns ns - 6 6 6 6 ns ns ns ns 1.0 162.8 (2 cycle) - - s ns (Tbclk) Tsync_high 1.0 - Tsync2clk 162.8 (2 cycle) 1.3 (16 cycle) s (Tbclk) ns (Tbclk) Trst_low Trst2clk 45 45 6 6 - AC-link Low Power Mode Timing End of Slot 2 to BIT_CLK, SDATA_IN Ts2_pdwn 1.0 s Low Activate Test Mode Timing Setup to trailing edge of RESET# Tsetup2rst 15.0 ns Hold from RESET# rising edge Thold2rst 100 ns Rising edge of RESET# to Hi-Z Toff 50 ns Falling edge of RESET# to L Tlow 50 ns Note ) The use of a crystal is recommended. If master clock is supplied from controller (or if a external oscillator is used), Master Clock should be input to XTAL_IN, meanwhile XTAL_OUT should be open. MS0058-E-00 -72000/11 [ASAHI KASEI] [AK4545] n Power On Note that AK4545 must be in cold reset at power on and RESET# must be low until master c rystal clock becomes stable, or reset must be done once master clock is stable. Vdd RESET# SDATA_OUT=L SYNC=L BIT_CLK Initialize Registers Trst2clk start up crystal oscillation nCold Reset Timing Note that both SDATA_OUT and SYNC must be low at the rising edge of RESET# for cold reset. The AK4545 initializes all registers including the Powerdown Control Registers, BIT-CLK is reactivated and each analog output is in Hi-Z state except for PC Beep while RESET# pin is low. The PC Beep is directly routed to L & R line outputs when AK4545 is in Cold Reset. At the rising edge of RESET #, the AK4545 starts the initialization of ADC and DAC , which takes 1028TS cycles. After that, the AK4545 is ready for normal operation. Status bit in the slot 0 is 0 (not ready) when the AK4545 is in RESET period ( L) or in initialization process. After initialization cycles, the status bit goes to 1 (ready). Trst_low Trst2clk RESET# VIL SDATA_OUT=L SYNC=L BIT_CLK MS0058-E-00 -82000/11 [ASAHI KASEI] [AK4545] nWarm Reset The AK4545 initiates warm reset process by receiving a single pulse on the sync. The AK4545 clears PR4 bit and PR5 bit in the Powerdown Control Register. However, warm reset does not influence PR0 PR3 or PR6,7 bits in Powerdown Control Register. Note that SYNC signal should synchronize with BIT_CLK after AK4545 starts to output BIT_CLK clock. And if an external clock is used, external clocks should be supplied before issuing a sync pulse for warm reset. ADC and DAC require 1028TS for the initialization. Tsync_high Tsync2clk SYNC VIH BIT_CLK nBIT_CLK Timing Tclk_high Tclk_low BIT_CLK 50% nSYNC Timing Tsync_high Tsync_low SYNC VIH VIL Tsync_period nSetup and Hold Timing Tdelay Tsetup VIH BIT_CLK VIL VIH SDATA_IN VIL Thold VIH SDATA_OUT SYNC MS0058-E-00 VIL -92000/11 [ASAHI KASEI] [AK4545] nSignal Rise and Fall Times (50pF external load : from 10% 90% of DVdd) Trise_clk Tfall_clk Trise_din BIT_CLK Tfall_din SDATA_IN Trise_dout Trise_sync Tfall_sync Tfall_dout SDATA_OUT SYNC nAC-link Low Power Mode Timing Slot 1 Slot 2 Ts2_pdwn BIT_CLK SDATA_OUT Write to 0x26 SDATA_IN Data PR4=1 Dont care Thold nActivate Test Mode VIH RESET# VIH SDATA_OUT Tsetup2rst HI-Z SDATA_IN BIT_CLK Toff Notes:1 1. All AC-link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the rising edge of RESET# causes the AK4545 AC-link outputs to go high impedance which is suitable for ATE in circuit testing. Note that the AK4545 enters in the ATE test mode regardless SYNC is high or low. 2. Once test modes have been entered, the only way to return to the normal operating state is to issue "cold reset" which issues RESET# with both SYNC and SDATA_OUT low. 1 All the following sentences written with small italic font in this document quote the AC' 97 component specification. MS0058-E-00 - 10 2000/11 [ASAHI KASEI] [AK4545] General Description nAC 97 Connection to the Digital AC 97 controller 2 AC `97 communicates with its companion AC `97 controller via a digital serial link, AC-link". All digital audio streams, and command/status information are communicated over this point to point serial interconnect. A breakout of the signals connecting the two is shown in the following figure. AC97 Controller AC97 SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# nDigital Interface The AK4545 incorporates a 5 pin digital serial interface that links it to the AC '97 controller. AC-link is a bi-directional, fixed rate(48kHz), serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. DAC and ADC resolution of the AK4545 is 18 bit resolution. The data streams currently defined by the AC `97 specification include: l PCM Playback 2 output slots 2 channel composite PCM output stream l PCM Record data 2 input slots 2 channel composite PCM input stream l Control 2 output slots Control register write port l Status 2 input slots Control register read port l S/PDIF output data 2 output slots 2 channel composite data output stream SYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-link data, the AK4545 for outgoing data and AC '97 controller for incoming data, samples each serial bit on the falling edges of BIT_CLK.The AK4545 outputs BIT_CLK. The AC-link protocol provides for a special 16-bit slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A "1" in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is "Tagged" invalid, it is the responsibility of the source of the data, (The AK4545 for the input stream, AC '97 controller for the output stream), to stuff all bit positions with 0's during that slot's active time. SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the "Tag Phase". The remainder of the audio frame where SYNC is low is defined as the "Data Phase". Note that SDATA_OUT and SDATA_IN data is delayed one BIT_CLK because AC97 controller causes SYNC signal high at a rising edge of BIT_CLK which initiates a frame. Output stream means the direction from AC 97 controller to the AK4545 , and Input stream means the direction from the AK4545 to AC97 controller 2 All the following sentences written with small italic font in this document quote the AC' 97 component specification. MS0058-E-00 - 11 2000/11 [ASAHI KASEI] Slot [AK4545] 0 1 2 3 4 5 6 All 0 All 0 All 0 All 0 7 8 9 10 11 12 All 0 All 0 All 0 All 0 All 0 All 0 All 0 All 0 SYNC SDATA OUT TAG SDATA IN TAG Command Command PCM(dac) PCM(dac) Address Data Left Right Status Address Status Data PCM(adc) PCM(adc) Left Right Tag Phase SPDIF Out SPDIF Out Channel1 Channel2 All 0 All 0 Data Phase 48kHz AC-link protocol identifies 13slots of data per frame. The frequency of sync is fixed to 48kHz. Only Slot 0, which is the Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections. AC-link Audio Output Frame (SDATA_OUT) a) Slot 0 SYNC BIT_CLK Valid Frame SDATA_OUT Slot3 Slot4 Slot5 Slot6 Slot7 Slot8 Slot9 Slot10 Slot11 Slot12 Slot13 Slot14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1/0 1/0 1/0 1/0 1/0 0 0 0 0 0 0 0 0 Slot1 Bit15 Bit14 Slot2 Bit7 1/0 1/0 0 Slot 0 1 BIT_CLK delay Slot15 Slot 1 The AK4545 checks bit15 (valid frame bit). Note that when the valid frame bit is 1, at least one bit14-7 (slot 1-8) must be valid, bit6-0 will be 0and should be ignored. If bit15 is 0, the AK4545 ignores all following information in the frame. The AK4545 then checks the validity of each bit in the TAG phase (slot 0). Bit14-11,8,7 are valid bits for slot1-4,7,8. If each bit is 0, the AK4545 ignores the slot indicated by 0. On the other hand, if each bit is 1, the slot is valid. A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AK4545 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC '97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AK4545 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. Data should be sent to the AC97 codec with MSB first through the SDATA_OUT. The following table shows the relationship of bit14&13 and the Read/Write operation depending on codec ID configuration. Bit 15 Valid Frame 1 1 1 Bit 14: Slot1 Valid Bit (Command Address) 1 0 1 1 0 MS0058-E-00 Bit 13: Slot 2 Valid Bit (Command Data) 1 1 0 Read/Write Operation of AK4545 Read/Write(Normal Operation) Ignore Read: Normal Operation Write: Ignore 0 Ignore AK4545 Addressing: Slot0 Tag Bits - 12 2000/11 [ASAHI KASEI] [AK4545] b)Slot1:Command Address Port Slot1 gives the address of the command data, which is given in the slot 2. The AK4545 has 26 valid registers of 16bit data. See Page20. BIT_CLK Bit19 Bit18 SDATA_OUT Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 Slot 0 Bit11 Bit10 Bit9 Bit9 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 Slot 1 Bit19 Bit18 Bit17 Bit16 Slot 2 Command Address Port Bit 19: Bit 18:12 Bit 11:0 Read/Write command 1=read, 0=write Control Register Index (see Mixer Registers for the detail) Reserved (0) Bit 18 of this slot1 is equivalent to the most significant bit of the index register address. The AK4545 ignores from bit11 to bit0. These bits will be reserved for future enhancement and must be staffed with 0s by the AC97 controller. c)Slot2:Command Data Port BIT_CLK Bit19 Bit18 SDATA_OUT Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 Slot 1 Bit6 Bit5 Bit4 Bit3 1/0 1/0 0 Slot 2 Bit2 Bit1 Bit0 0 0 0 Bit19 Bit18 Bit17 Bit16 Slot 3 Command Data Port Bit19:4 Bit3:0 Control Register Write Data (if bit 19 of slot 1 is 1, all Bit19:4 should be 0) Reserved(0) If bit19 in slot1 is 0, the AC97 controller must output Command Data Port data in slot 2 of the same frame. If the bit19 in slot1 is 1, the AK4545 will ignore any Command Data Port data in slot2. Bit19 of this slot2 is equivalent to D15 bit of mixer register value. d)Slot3 PCM Playback Left Channel (18bits) The AK4545 uses the playback(DAC) data format in slot3 for left channel. Playback data format is MSB first. Data format is 18bits 2s complement. AC97 controller should stuff bit1-0 with 0. If valid bit (slot3) in the slot 0 is invalid (0), the AK4545 interprets the data as all 0. Bit19:2 Playback data Bit 1:0 0 If Slot3 and 4 of SDATA_OUT are selected for S/PDIF output data, this 18bits data is output through channel1 of S/PDIF out besides DAC. e)Slot4 PCM Playback Right Channel (18bits) The AK4545 uses the playback(DAC) data format in the slot4 for right channel. Playback data format is MSB first. Data format is 18bits 2s complement. AC97 controller should stuff bit1-0 with 0. If valid bit (slot 4) in the slot 0 is invalid (0), the AK4545 interprets the data as all 0. Bit19:2 Playback data Bit 1:0 0 If Slot3 and 4 of SDATA_OUT are selected for S/PDIF output data, this 18bits data is output through channel2 of S/PDIF out besides DAC. f)Slot5,6 Not implemented in the AK4545 The AK4545 ignores these data slot s. MS0058-E-00 - 13 2000/11 [ASAHI KASEI] [AK4545] g)Slot7 S/PDIF output data channel1 (16bits) In case of selecting slot7 and 8 of SDATA_OUT for S/PDIF output data , the AK4545 uses data format in the slot7 for channel1 of S/PDIF output data. This data format is MSB first. Data format is 16bits 2s complement. AC97 controller should stuff bit3-0 with 0. If valid bit (slot7) in the slot 0 is invalid ( 0), the AK4545 interprets the data as all 0. Bit19:4 Output data Bit 3:0 0 h)Slot8 S/PDIF output data channel2 (16bits) In case of selecting slot7 and 8 of SDATA_OUT for S/PDIF output data , the AK4545 uses data format in the slot8 for channel2 of S/PDIF output data. This data format is MSB first. Data format is 16bits 2s complement. AC97 controller should stuff bit3-0 with 0. If valid bit (slot8) in the slot 0 is invalid ( 0), the AK4545 interprets the data as all 0. Bit19:4 Output data Bit 3:0 0 i)Slot9-12 Not implemented in the AK4545 The AK4545 ignores these data slots. MS0058-E-00 - 14 2000/11 [ASAHI KASEI] [AK4545] AC-link Input Frame(SDATA_IN) Each AC-link frame consists of one 16bit tag phase and twelve 20bit slots used for data and control. a)Slot0 Slot0 is a special time frame, and consists of 16bit s. Slot0 is also named the Tag phase. The AK4545 supports Bits 15-11. Each bit indicates 1=valid(normal operation) or ready, 0=invalid(abnormal operation) or not ready. If the first bit in the slot 0 (Bit15) is valid, the AK4545 is ready for normal operation. 3If the Codec Ready bit is invalid, the following bits and remaining slots are all 0. AC97 controller should ignore the following bits in the slot 0 and all other slots. When the ADC sampling rate is set for less than 48kHz, then Bits 12and 11 in slot 0 ( corresponds to slot3 and slot4 respectively ) will be 1 s when valid data is transferred in SDATA_IN, and will be 0 s when no data is transmitted. ( On-demand ) base data transaction ) The next is the extracted description from AC 97 Rev.2.1 ; For variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. Thus, even in variable sample rate mode, the Codec is always the master: for SDATA_IN (Codec to Controller), the Codec sets the TAG bit; for SDATA_OUT (Controller to Codec), the Codec sets the SLOTREQ bit and then checks for the TAG bit in the next frame. AK4545 expects Controller will reply TAG bit in the next frame correctly. Bit 14 means that Slot 1(Status Address) output is valid or invalid. And Bit 13 means that Slot 2(Status Data ) is valid or invalid. The following table shows the relationship between Bit 14,13 and each Status of the AK4545. Bit 15 (Codec Ready) 1 Note Bit 14 (Status Address) 1 Bit 13 (Status Data) 1 Status There is a Read Command in the previous frame. Then both Slot 1 and Slot 2 output normal data. If the access to non-implemented register or odd register is requested, the AK4545 returns valid 7-bit register address in slot 1 and returns valid0000h data in slot 2 on the next AC-link frame. 1 1 0 Prohibited or non-existing 1 0 0 There is no Read Command in the previous frame. Bits 19-12 and Bits 9-0 in Slot 1 are set to 0. And Slot2 outputs All0. 1 0 1 Prohibited or non-existing 1). The above Read sequence is done as response for previous frames read command. That is, if the previous frame is the Write Command, AK4545 outputs bit1 4 =0, bit13 =0 and slot 1&2 = All0, if there is no SLOTREQ. 2). The Bits 14 and 13 in Slot 0 is independent of the SLOTREQ Bits 11 and 10 in Slot 1 which the AK4545 supports. Bit12 means the output of Slot 3( PCM(ADC) Left) is valid or invalid. And Bit 11 means the output of Slot 4(PCM(ADC)Right) is valid or invalid. Bits10-0 are occupied with 0. A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AK4545 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AK4545 transitions SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC '97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. SYNC BIT_CLK SDATA_IN Codec Ready Slot1 Slot2 Slot3 Slot4 Slot6 Slot7 Slot8 Slot11 Slot12 1/0 1/0 1/0 1/0 1/0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 0 Bit8 0 Bit7 0 0 Bit4 Bit3 Slot 0 3 Slot5 0 Bit2 0 0 Bit1 Bit0 Slot 1 When the AC' 97 is not ready for normal operation, output bits are not specified and should be ignored. MS0058-E-00 - 15 2000/11 [ASAHI KASEI] b)Slot1 [AK4545] Status Address Port Audio input frame slot1's stream echoes the control register index, for historical reference, for the data to be returned in slot2. (Assuming that slots1 valid bit and slot2 valid bit in the slot0 had been tagged "valid" by the AK4545) BIT_CLK Bit19 Bit18 SDATA_IN 0 Slot 0 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 1/0 1/0 1/0 1/0 1/0 1/0 1/0 Bit11 Bit10 Bit9 1/0 1/0 0 Bit8 0 Bit7 Bit6 Bit5 0 0 0 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 Slot 1 Bit19 Slot 2 Status Address Port This address shows register index for which data is being returned in the slot2. This address port is the copy of slot1 of the output frame, and index address input to SDATA_OUT is loop ed back to the AC97 controller through SDATA_IN even for non-supported register . For On Demand base data transaction, when the DAC sampling rate is set less than 48kHz, then AK4545 will request new audio data as required by setting the SLOTREQ bits 11 and 10 in Slot1 to 0 s. When no data is required to support the selected sampling rate, these bits will be 1 s. When SLOTREQ bits are asserted as send data request during the current frame on SDATA_IN, AC 97 digital controller should send data onto the corresponding slot in the next frame on SDATA_OUT. If VRA is set 0, SLOTREQ bits show always 0 and sample rate is forced to 48ksps. SLOTREQ Bit 19 18 12 11 10 9 8 7 6 5 40 Description Reserved ( Set to 0 ) Control Register Index ( Set to 0s if tagged invalid ) Slot 3 Request : PCM Left channel 0: send data request, 1: do not send Slot 4 Request : PCM Right channel 0: send data request, 1: do not send Reserved ( Set to 0 ) Slot 6 Request : AK4545 doesnt use slot6. ( Set to 0 ) Slot 7 Request : Slot 7 cant be used at except 48KHz. Set to 0. Slot 8 Request : Slot 8 cant be used at except 48KHz. Set to 0. Slot 9 Request : AK4545 doesnt use slot9. ( Set to 0 ) Reserved ( Set to 0 ) c)Slot2: Status Data Port Status data addressed by command address port of Output Stream is output through SDATA_IN pin. Bit19:4 Control Register Read Data (the contents of indexed address in the slot 1) Bit3:0 0 Note that the address of Status Data Port data are consistent with Status Address Port data of the slot 1 in the same frame. If the read operation is issued in the frame N by AC97 controller, Status Data Port data is output through SDATA_IN in the frame N+1. Note that data is output in only this frame, only one time and that the following frames are invalid if the next read operation is not issued. d)Slot3 PCM Record Left Channel Record(ADC) data format is MSB first. Data format is 2s complement. As the resolution of the AK4545 is 18bit, lower 2 bits are ignored. If ADC block is powered down, slot- 3 valid bit in the slot 0 is invalid ( 0), and data is output as all 0. Bit19:2 Bit1:0 MS0058-E-00 Audio ADC left channel output 0 - 16 2000/11 [ASAHI KASEI] [AK4545] e)Slot4 PCM Record Right Channel Record(ADC) data format is MSB first. Data format is 2s complement. As the resolution of the AK4545 is 18bit, lower 2 bits are ignored. If ADC block is powered down, slot-4 valid bit in the slot 0 is invalid ( 0), and data is output as all 0. Bit19:2 Audio ADC right channel output Bit1:0 0 f)Slot5 Modem Line Codec As the AK4545 does not incorporate modem codec, all bits are stuffed with 0. Bit19:0 0 g)Slot6 Microphone Record Data As the AK4545 does not incorporate 3 rd ADC codec, all bits are stuffed with 0. Bit19:0 0 h)Slots7-12 Bits19:0 MS0058-E-00 Reserved for future enhancement 0 - 17 2000/11 [ASAHI KASEI] [AK4545] nS/PDIF output a) Electrical Characteristics Same as other digital output pins (CMOS level). S/PDIFout pin is supposed to be connected to optical component only. b) Outline of S/PDIF Spec. (1) The channel status of the AK4545 supports consumer mode only. The AK4545 has three-16 bit registers which keep Copyrights-bit, Category-code bits, Generation-bit, etc. These bits can be changed through AClink I/F. (2) SDATA_IN data or SDATA_OUT data is encoded to appropriate bi-phase signal by internal digital audio transmitter (DIT) circuit, and is output through S/ PDIFout pin. One of the following audio data streams can be selected as the input signal to DIT circuit by the setting of internal register. (a) D/A data from SDATA_OUT (slot3/4) (b) A/D data to SDATA_IN (slot 3/4) (c) Slot 7/8 data from SDATA_OUT (In this case, we assume that slot7/8 is original AC-3 encoded data, and that slot 3/4 is down-mixed AC-3 audio data Therefore, the device supposes data rate of slot 7/8 and slot 3/4 to be same and to be 48kHz . ) (3) Even if A/D and D/A sampling frequency (fs) are different, S/PDIFout circuit works correctly. AK4545 BIT_CLK SYNC SDATA_OUT FIFO AC-Link ADC for A/D Interface SDATA_IN RESET# FIFO DAC for D/A Data of Slot7,8 IO S/PDIF OUT Data of Slot3,4 ASLT S/PDIF Out AD CLK DA CLK IO I/O ASLT Data Select 0 0 SDATA_OUT : slot 3, 4 0 1 SDATA_OUT : slot 7, 8 Note 1 X SDATA_IN : slot 3, 4 Note) DAC rate and S/PDIF rate should be same (48kHz). MS0058-E-00 - 18 2000/11 [ASAHI KASEI] [AK4545] c) The Detail of S/PDIF specification The AK4545 uses two times of bit rate clock, and use bi-phase method except of preamble. [Architecture of S/PDIF] Frame formant of S/PDIF is the follwoing. - One frame consists of two sub-frames. - One block consists of 192 frames. - Preamble(B, M, W) for synchronization is added. ( see the following figure.) M Channel 1 W Channel2 B Channel 1 sub-frame Frame 191 Preamble B M W W Channel 2 M sub-frame Frame 0 Preceding symbol : 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 0 0 1 Frame 1 Channel Coding Preceding symbol : 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 1 Definition of sub-frame( note that audio data format is LSB first) bit 0 3 7 8 L Contents Preamble 0 0 0 0 S B Channel 1 27 M S B 1 1 1 28 29 30 31 V U C P V: Valid bit : outputs D15 bit of 70h register U: User bit : always outputs 0 C: Channel Status bit (refer to 72h, 74h registers. The AK4545 outputs the contents of 72h and 74h registers one bit per frame. The AK4545 outputs 0 from 33 frame to 191 frame.) P: Parity bit note that VUC bits of channel 2 are the same as the ones of Channel 1 Channel Status bits items PRO/consumer AUDIO# Copy/Copyright Pre-emphasis Mode Category CODE L:Generation Status Source Num. Channel Num Sample Frequency Clock Accuracy Reserved Bits 0 1 2 3 4-5 6-7 8-14 15 16-19 20-23 24-27 28-29 30-191 fixed Register Register Register fixed fixed Register Register fixed fixed Register fixed fixed " 0" (consumer mode only ) 72h D1 72h D2 72h D3 00 00 72h D8-D14 72h D15 0000 0000 74h D8-D11 00 All 0 Validity Bit : can be set by D15 bit in 70h register User Data : all 0 MS0058-E-00 - 19 2000/11 [ASAHI KASEI] [AK4545] nMixer Registers Each Register is 16 bit wide. Note: The AK4545 outputs valid 0000h if the controller reads an unused or invalid register address . Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 00h 02h Reset Master Volume 0 0 X 1 ML5 0 ML4 1 ML3 1 ML2 0 ML1 0 X 1 X 1 0 0 MR5 MR4 MR3 MR2 04 LNLVL Volume Mute X ML5 ML4 ML3 ML2 ML1 X X MR5 MR4 MR3 MR2 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 26h 28h Master Volume Mono PC_BEEP Volume Phone Volume Mic Volume Line In Volume CD Volume Video Volume Aux Volume PCM Out Volume Record Select Record Gain General Purpose 3D Control Powerdown Ctrl/Stat Extended Audio ID Mute Mute Mute Mute Mute Mute Mute Mute Mute X X X X GL4 GL4 GL4 GL4 GL4 X X X X PR4 X X X X X X GL3 GL3 GL3 GL3 GL3 X GL3 X X PR3 X X X X X X GL2 GL2 GL2 GL2 GL2 SL2 GL2 X X PR2 X X MR5 MR4 MR3 X X X X X X X X X X X X X X X X X X X X X X X X X X X PV3 GN4 GN4 GR4 GR4 GR4 GR4 GR4 X X X X X X X PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 X GR3 X DP3 X X X X X X X X X X X X LPBK X X X X X X X Ext'd audio Stat/Ctrl X X X X X X X X X X X 3D X PR5 X X X X X X GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX X PR1 2Ah X X X X X X X X X X X DFC X PR6 0 X 1 ML 0 ML 0 X X X X GL0 GL0 GL0 GL0 GL0 SL0 GL0 MS X PR0 X X 0 Mute 2Ch 32h 70h 72h 74h 7Ch 7Eh PCM Front DAC Rate PCM LR ADC Rate SPDIF Control SPDIF Channel Status 1 SPDIF Channel Status 2 Vendor ID1 Vendor ID2(AK4545) SR15 SR15 Valid L SR14 SR14 SR13 SR13 SR12 SR12 SR11 SR11 SR10 SR10 SR9 SR9 SR8 SR8 SR7 SR7 SR6 SR6 SR5 SR5 SR4 SR4 SR3 SR3 0 0 0 X 0 0 0 0 X 0 0 1 0 X 0 0 0 0 X 0 0 0 0 X Pre 0 1 0 X Mute POP X PR7 0 X AMAP ASLT X X X X X X CC14 CC13 CC12 CC11 CC10 CC9 CC8 0 1 1 0 0 0 0 0 0 SF3 0 1 SF2 0 1 SF1 0 0 SF0 1 1 20dB D4 D3 REF X X D2 D1 D0 Default 0 0 MR1 MR0 2D50h 8000h MR1 MR0 8000h MR2 MR1 MR0 PV1 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 X PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 X X GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 X DP2 ANL DP1 DAC X X X X DP0 ADC VRA VRA SR2 SR2 SR1 SR1 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h Na 0201h 0000h BB80h BB80h 0000h 9200h 0000h 414Bh 4D07h X SPEN Copy Audio 0 0 1 0 1 1 SR0 SR0 IO 0 0 1 1 *) Vender ID of AKM is AKM :This ID has been approved by Intel. *) The AK4545 outputs X bits as 0. *) A write on Invalid registers will not affect operation of the AK4545 . *) ANL, DAC, ADC Bit in register 26h are all 0 following cold reset. When each section is ready for normal operation, the coresponding bit becomes 1. The Powerdown register(26h) is not affected by a write to Reset register(0h). See Mixer Registers in AC97 specification for details. Vref is controlled only by PR3. nReset Register (Index 00h) <Write> When any value is written to the AK4545 , all registers including 2Ah, 2Ch, and 32h in the AK4545 except for 26h Powerdown/Control Register are reset to default values. The value of this register is not altered. <Read> Reading this register returns 2D50hcomposed of the ID code of the part, a code for the type of 3D enhancement, 18 bit ADC/DAC resolution, and a code for True Line Level Out. *Setting D14 D10 01011 means AKM 3D enhancement which is registered in Audio Codec 97 Component Specification Rev 1.03 and 2.1 . *Setting D8 1 means 18bit ADC resolution and D6 1 means 18bit DAC resolution. *Setting D4 1 means True Line Level Out is supported with Volume Control(Index 04h). MS0058-E-00 - 20 2000/11 [ASAHI KASEI] [AK4545] n Play Master Volume Registers (Index 02h ,06h) and LINVL(True Line Level Out) Volume Register(Index 04h) The following table shows the relationship between bits and the attenuation value with step size of 1.5dB. The AK4545 has a range of 0dB to 46.5dB. The AK4545 does not support the optional MX5 bit. The AK4545 detects when MX5 is set and set all 5 LSBs to 1s. Example: When the driver writes a "01xxxxx" the AK4545 interpret that as "0011111". When this register is read, the return value is "0011111". Mute 0 0 0 0 0 0 0 1 MX5 MX4 MX3 MX2 MX1 MX0 Att. 0 0 0 0 0 0 0dB 0 0 0 0 0 1 -1.5dB 0 0 0 0 1 0 -3.0dB 0 0 0 0 1 1 -4.5dB ------------------------------------------------------------------------0 1 1 1 1 0 -45.0dB 0 1 1 1 1 1 -46.5dB ------------------------------------------------------------------------1 X X X X X -46.5dB ------------------------------------------------------------------------X X X X X X Mute n PC Beep Register (Index 0Ah) The following table shows the relationship between bits and the attenuation value. The attenuation step is 3dB with a range of 0 to 45dB. PC_BEEP of the AK4545 is 0dB at default state. The PC Beep is routed to L & R Line outputs directly when AK4545 is in a RESET State(Reset# is "L") or when the mixer is powerdown with Vref on(PR2="1" and PR3="0"). The PC BEEP isn't routed to True Line Level Out under these states. This is so that Power on Self Test(POST) codes can be heard by the user in case of a hardware problem with the PC. After Reset# goes "H", direct PC beep pass through becomes OFF. Mute PV3 PV2 PV1 PV0 Att. 0 0 0 0 0 0dB 0 0 0 0 1 -3.0dB 0 0 0 1 0 -6.0dB -------------------------------------------------------------0 1 1 1 1 -45.0dB 1 X X X X Mute n Analog Mixer Input Gain Registers (Index 0Ch-18h) The following table shows the relationship between bits and the gain/attenuation value. Attenuation step is 1.5dB with a range of +12dB to 34.5dB. Mute Gx4 Gx3 Gx2 Gx1 Gx0 Att. 0 0 0 0 0 0 +12dB 0 0 0 0 0 1 +10.5dB ----------------------------------------------------------------------0 0 1 0 0 0 0dB 0 0 1 0 0 1 -1.5dB ----------------------------------------------------------------------0 1 1 1 1 0 -33.0dB 0 1 1 1 1 1 -34.5dB 1 X X X X X Mute n Record Select Control Register (Index 1Ah) SR2 0 0 0 0 1 1 1 1 SR1 0 0 1 1 0 0 1 1 MS0058-E-00 SR0 0 1 0 1 0 1 0 1 Att. Mic CD In (R) Video In (R) Aux In (R) Line In (R) Stereo Mix (R) Mono Mix Phone - 21 2000/11 [ASAHI KASEI] [AK4545] n Record Gain Register (Index 1Ch) Mute Gx3 Gx2 Gx1 Gx0 Gain 0 0 0 0 0 0dB 0 0 0 0 1 1.5dB 0 0 0 1 0 3.0dB -------------------------------------------------------------0 1 1 1 1 22.5dB 1 X X X X Mute n General Purpose Register (Index 20h) The following table shows the relationship between the bit and control for several miscellaneous functions of the AK4545. Bit POP D15 DFC D14 3D D13 MIX D9 MS D8 LPBK D7 Function PCM(DAC) Bypass 3D 0= Via 3D Path, 1= 3D Bypass DAC Feed Back Control 0=Mix, 1=DAC only 3D Stereo Enhancement 0=Off, 1=On Mono Output Select 0=Mix, 1=Mic Mic Select 0=Mic1, 1 =Mic2 ADC/DAC Loopback Mode 1= Loopback Comment Controls whether DAC output is mixed with analog inputs before the 3D circuit (POP=0) or after the 3D circuit (POP=1) Controls whether Mix (DFC=0) or DAC only (DFC=1) is sent to the output Controls whether the 3D circuit is bypassed (3D=0) or used (3D=1) Controls whether Full Mix (Mix=0) or Mic inputs (Mix=1) is send to MONO_OUT Selects Mic1 input (MS=0) or Mic2 (MS=1) Selects normal operation (LPBK=0) or loops ADC data directly to DACs (LPBK=1) Relations of control bits D15,14,13 POP X DFC 0 3D 0 Function 3D bypass to Volumes ( Normal ) Mixer a Vol Path at selecting Stereo Mixer record(1Ah register = 0505h) Analog INPUT (Line,CD,Mic..) ADC Mixer DAC 0 0 1 3D output to Volumes Mixer a 3D a Vol Volume Analog INPUT (Line,CD,Mic..) DAC 1 0 1 ( 3D out + DAC ) to Volumes ( Mixer(w/0 DAC) + DAC ) a Vol 3D Analog INPUT (Line,CD,Mic..) Volume 3D Line Out S_DATA_IN ADC Mixer Line Out S_DATA_IN ADC Mixer S_DATA_IN Volume Line Out DAC X 1 X Only DAC fed to Volumes DAC a Vol Then the path from DAC to Mixer is cut. Analog INPUT (Line,CD,Mic..) DAC Mixer ADC Volume S_DATA_IN Line Out D13(3D) will activate the AKM s 3D enhancement. LPBK(ADC/DAC Loopback Mode) bit enables to output ADC data to DAC. While this function is used, the sample rates of ADC and DAC must be set to 48KHz. MS0058-E-00 - 22 2000/11 [ASAHI KASEI] [AK4545] n 3D Control Register (Index 22h) The following table shows the relationship between the bit and 3D Depth. DP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Depth 0% 50% 50% 50% 50% 50% 50% 50% 70% 70% 70% 70% 70% 70% 70% 100% Recommended Application Off Audio Audio Audio Audio Audio Audio Audio Audio Audio Audio Audio Audio Audio Audio Game n Powerdown Control/Status Register (Index 26h ) BitsD0 to D3 are read only. Any write to these bits will not affect the AK4545. These bits are used as status bits to subsections of the AC97 codec. A 1 indicates the subsection is ready or that is capable of performing in a nominal manner. Bit REF D3 ANL D2 DAC D1 ADC D0 Function Vref up to nominal state 0=NOT ready, 1=ready, Analog mixers, etc ready 0=NOT ready, 1=ready DAC section ready to accept data 0=NOT ready, 1=ready ADC section ready to transmit data 0=NOT ready, 1=ready The power down modes are as follows. Bit PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 D8 D9 D10 D11 D12 D13 D14 D15 Function PCM in ADCs & Input Mux Powerdown PCM out DACs Powerdown Analog Mixer Powerdown (Vref still on) Analog Mixer Powerdown (Vref off) Digital Interface (AC-link) Powerdown Internal Clk disable True Line Level Out Powerdown EAPD(External Amplifier Powerdown) When PR3 is set to 1, ADC, DAC, Mixer, True Line Lever Out, and VREF are powered down even if any PRx bit are 0. When PR3 bit is reset to 0, the AK4545 resumes the previous state by referencing previous PRx bit. In this case, the AK4545 outputs corresponding slot-x valid bits in the slot 0 as 0 until the AK4545 is power-up. EAPD(External Amplifier Power Down) bit controls an external audio amplifier. EAPD=0 places a 0(L) on the output pin, enabling an external audio amplifier, EAPD= 1(H) shuts it down. Power-up default is EAPD=0(external audio amplifier enabled). MS0058-E-00 - 23 2000/11 [ASAHI KASEI] [AK4545] n Extended Audio ID(Index 28h) The Extended Audio ID(28h) is a read only register. 2bits D15&D14 can be read for codec identification. As AK4545 operates as only primary CODEC, D15 ,14 are automatically set to 0. The AMAP bit D9 of this read only register for the AK4545 will always be set to 1 indicating that the codec slot DAC mapping conform to AC97 Rev 2.1. Since AK4545 supports variable sample rates, field of D0: VRA is set to 1, indicates Variable Rate PCM Audio is supported. n Extended Audio Status and Control Register (Index 2Ah) Bits D0 to D3, and D11 to D14 are read/write controls, while D6 to D9 are read only data to controller. Function Bit VRA=1 Enables Variable Rate Audio mode in conjunction with Audio Sample Rate (D0) Control Registers and tag-bit/SLOTREQ signaling Because CDAC,LDAC,SDAC, and MICADC are not supported, default value at cold register reset for D11-D14 is set to 0. Internal SRC related circuits are controlled by this VRA bit(2Ah), not by VRA in Extended Audio ID register(28h). n Audio Sample Rate control Registers (Index 2Ch, 32h) Sample Rate controls for DACs, and ADC. 16bit data in D15(MSB) to D0 show unsigned value between 0 to 65535, representing the exact sampling frequency in Hz. These Sample Rate setting is done at VRA=1 of Extended Audio Status and Control Register(2Ah). Data in D15 D0 Sample Rate (kHz) 8.0 1F40 hex 11.025 2B11 hex 16.0 3E80 hex 22.05 5622 hex 32.0 7D00 hex 44.1 AC44 hex 48.0 BB80 hex The AK4545 supports these discrete frequencies. When any other codes is written in this register, the AK4545 works at the sampling rate rounded to the closest one above by decoding of only D15-D12 bits. D15 D12 Sample Rate (kHz) 0,1 8.0 2 11.025 3 16.0 4,5 22.05 6,7,8 32.0 9,Ah 44.1 Bh-Fh 48.0 At VRA=0, 2Ch and 32h are BB80h and cant be written. When VRA is set to 0, 2Ch and 32h register are set to BB80h automatically. And the sample rate changing will be executed on the fly(immediately). It is recommended to set the zero data(no input/no ouput) at the fs changing in order to prevent some noise. MS0058-E-00 - 24 2000/11 [ASAHI KASEI] [AK4545] n S/PDIF Control Register (Index 70h) The following table shows the relationship between the bit and control for S/PDIF out of the AK4545. Bit valid D15 ASLT D14 SPEN D1 IO D0 Function Validity Bit 0 : valid, 1:invalid Alternate Data Slot 0: slot 3/4 of SDATA_OUT 1: slot7/8 of SDATA_OUT S/PDIF powerdown 0: powerdown 1:operation Select signal of S/PDIFout data 0: D/A data 1: A/D data Comment This bit is output to the valid bit in subframe of S/PDIF. In the case of IO=0, the dates of alternated slot of SDATA_OUT are assigned in S/PDIF. See below table. S/PDIF will go into powerdown mode under the following conditions even if SPEN is set to 1. 1) PR3=1 or PR4=1 or PR5=1 2) IO=0 and PR1 = 1 3) IO=1 and PR0 = 1 It is recommended that S/PDIF is powered up from these mode after SPEN is set to 0. Selected dates are output trough S/PDIF out. See below table. S/PDIF Out data are selected by IO and ASLT bits as the following table. IO 1 0 0 ASLT X 0 1 S/PDIF Out data AD data SDATA_OUT Slot3,4 SDATA_OUT Slot7,8 S/PDIF out128fs Clock AD Clock DA Clock DA Clock Note 1. Sample rate should be changed while S/PDIF is powered down. 2. IO and ASLT bits should be changed while S/PDIF is powered down. n S/PDIF Channel Status1 Register (Index 72h) The following table shows the relationship between the bit and the channel status bits for S/PDIF out of the AK4545. Bit Audio D1 Copy D2 Pre D3 CC14-CC8 D14-D8 L D15 Function Bit 1 in the channel status data of consumer mode 0: 2ch Audio Data 1: Digital Data Bit 2 in the channel status data of consumer mode 0: Copyright : yes 1: Copyright : no Bit 3 in the channel status data of consumer mode 0: Pre emphasis OFF 1: Pre emphasis ON Category code:bit8-14 in the channel status data of consumer mode. Default : 0010010 (Digital mixer, original) L:Generation Status: Bit 15 in the channel status data of consumer mode n S/PDIF Channel Status2 Register (Index 74h) The following table shows the relationship between the bit and the channel status bits for S/PDIF out of the AK4545. Bit SF3-SF0 D11-D8 Function Sample Rate (Bit24-27 in the channel status data of consumer mode) SF3 SF2 SF1 SF0 48KHz : 0 0 1 0 44.1KHz : 0 0 0 0 32KHz : 0 0 1 1 n Vendor ID Registers (Index 7Ch , 7Eh) This register is a read only register that is used to determine the specific vendor identification. The ID method is Microsoft Plug and Play Vendor ID code with upper byte of 7Ch register, the first character of that id, lower byte of 7Ch register, the second character and upper byte of 7Eh register the third character. These three characters are ASCII encoded. Lower byte of 7E register is for the Vendor Revision number. AKMs vender ID is AKM, and revision number is 0 7 for AK4545. As ASCII code A is 41h, K is 4Bh, and M is 4Dh, Vendor ID registers are 414Bh and 4D0 7h respectively for AK4545. MS0058-E-00 - 25 2000/11 [ASAHI KASEI] [AK4545] AK4545 3Dcap Block PD 26[10] PD 26[14] AK4545 PC_BEEP PC_VOL(0A[4:1]) Mute(0A[15]) PHONE GAIN (0C[5:0]) Mute(0C[15]) LINE_IN_L LINE_IN_R GAIN(10[12:8]) Mute(10[15]) GAIN (10[4:0]) Mute(10[15]) CD_L CD_GND CD_R GAIN(12[12:8]) Mute(12[15]) GAIN (12[4:0]) Mute(12[15]) VIDEO_L GAIN(14[12:8]) Mute(14[15]) VIDEO_R GAIN (14[4:0]) Mute(14[15]) AUX_L GAIN(16[12:8]) Mute(16[15]) AUX_R GAIN (16[4:0]) Mute(16[15]) GAIN (0E[5:0]) Mute(0E[15]) (0E[6]) MIC1 20dB MIC2 Mixer PD 26[10] PD 26[10] Mixer <Left> PD 26[10] Mixer Mixer <Right> Mixe 3D (R) 22[3:0] Mixe LNLVL_OUT_L LNLVL Volume 04[5:0] Mute 04[15] LNLVL_OUT_R (R) Mixe 1/2 1/2 Mux Master Volume 02[5:0] Mute 02[15] Mux LINE_OUT_R RESET# PD26[10] Mute 06[15] Mux 20[9] (POP 20[15] & 3D 20[13] ) | DFC20[14] LINE_OUT_L Mux Mono Volume 06[5:0] PD 26[10] Mute 02[15] 3D 20[13] DFC20[14] 1/2 Mixer Master Volume 02[13:8] Mux 3D 20[13] DFC20[14] Mux (20[8]) Mute 04[15] RESET# PD26[10] (L) (L) LNLVD Volume 04[13:8] Mute(18[15] GAIN(18[12:8]) DAC.L Mute(18[15] GAIN (18[4:0]) DAC.R MONO_OUT AC97 20[7] PD 26[9] Digital 20[7]Interface Registers SYNC BIT_CLK SDATA_OUT Mux 1A[10:8] Mux 1A[2:0] GAIN 1C[11:8] Mute 1C[15] ADC.L GAIN 1C[3:0] Mute 1C[15] ADC.R PD 26[11] PD 26[8] PD 26[8] Voltage Reference Vref VRAD VRDA VrefOut AVdd1 AVss1 AVdd2 AVss2 NC TEST2 TEST3 NC XTL_IN MS0058-E-00 TX EAPD Dataslot Controller PD 26[13] PD 26[13] RESET# S/PDIF Control 70h, 72h, 74h PLL NC SDATA_IN PD 26[8] XTL_OUT AFILT2 AFILT1 DVss1 PD 26[16] DVdd1 DVss2 DVdd2 - 26 2000/11 [ASAHI KASEI] [AK4545] nPower Management/Low Power Modes The AK4545 is capable of operating at multiple reduced power modes for when no activity is required. The state of power down is controlled by the Powerdown Register (26h). There are 8 separate commands for power down. See the table below for the different modes. As the AK4545 operates at static mode, the registers will not lose their values even if the master clock is stopped only upon power. Powerdown Mode Truth Table ADC DAC Mixer VREF ACLINK PR0="1" PD don't care don't care don't care don't care PR1="1" don't care PD don't care don't care don't care PR2="1" don't care don't care PD don't care don't care (No DAC out) PR3="1" PD PD PD PD don't care PR4="1" PD PD don't care don't care PD PR5="1" PD PD don't care don't care PD PR6="1" don't care don't care don't care don't care don't care PR7="1" don't care don't care don't care don't care don't care *: PD means Powerdown . *: No DAC out means that there is no PCM out because mixer is disabled. Internal CLK don't care don't care don't care LNLVL_OUT don't care don't care PD EAPD don't care don't care don't care don't care don't care PD don't care don't care PD don't care don't care PD don't care don't care don't care don't care don't care PD From normal operation sequential writes to the Powerdown Register are performed to power down subsections of the AK4545 one at a time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC '97 digital interface (AC-link). The part will remain in sleep mode with all its registers holding their static values. To wake up, the AC `97 controller will send a pulse on the sync line issuing a warm reset. This will restart the AK4545 digital (resetting PR4 to zero). The AK4545 can also be woken up with a cold reset. A cold reset will cause a loss of values of the registers as a cold reset will set them to their default states. When a subsection is powered back on the Powerdown Control/Status register (index 26h) should be read to verify that the section is ready (i.e. stable) before attempting any operation that requires its normal operation. And the below figure illustrates one example of procedure to do a complete powerdown/power up of AK4545. PR0=1 PR1=1 ADCs off PR0 Normal PR0=0 & ADC=1 PR2=1 Analog off PR2 or PR3 DACs off PR1 PR1=0 & DAC=1 PR4=1 PR2=0 & ANL=1 Digital I/F off PR4 Shut off AC-Link Warm Reset Cold Reset Default Ready = 1 One example of AK4545 Powerdown/Powerup flow When PR3 bit is set to 1, ADC, DAC, Mixer, True Line Level Out, and VREF will be powered down even if any PRx bit are 0. When PR3 bit is reset to 0, the AK4545 resumes with the previous state by referencing PRx bit. In this case, the AK4545 outputs 0 (invalid) for corresponding slot-x valid bits in the slot 0 until the corresponding block of the AK4545 is power-up. Setting PR4 bit cause the Powerdown mode of AK4545 and AC-Link of AK4545 shut down. In this case, when Warm Reset is executed, PR4 bit is cleared and the AC-Link is reactivated. Meanwhile Cold reset is selected , AK4545 is restored to operation with default register settings. In addition, setting PR5 bit causes the Powerdown mode of AK4545 and the internal clock of AK4545 to be stopped. When a warm reset is done in this case, PR5 bit is cleared to 0 and internal clock and AC-Link are reactivated. When Cold reset is executed, AK4545 is set up to the operation with default register setting, no powerdown modes active. The next figure illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. This is used when the user is playing a CD (or external LINE_IN source) through the AC 97 codec to the speakers but has most of the system in a low power mode. The procedure for this follows the previous except that the analog mixer is never shut down. MS0058-E-00 - 27 2000/11 [ASAHI KASEI] [AK4545] PR0=1 PR1=1 ADCs off PR0 Normal PR0=0 & ADC=1 PR4=1 DACs off PR1 PR1=0 & DAC=1 Digital I/F off PR4 Shut off AC-Link Warm Reset AK4545 Powerdown/Powerup flow with analog still alive nTestability Activating the Test Modes AC `97 has two test modes. One is for ATE in circuit test and the other is for vendor specific tests. AC `97 enters the ATE in circuit test mode regardless of SYNC signal (high or low) if SDATA_OUT is sampled high at the trailing edge of RESET#. AC `97 enters AKM test mode in the case of condition below. These cases will never occur during standard operating conditions. Regardless of the test mode, the AC `97 controller must issue a "Cold" reset to resume normal operation of the AC `97 Codec. Test Mode Functions ATE in circuit test mode When AC `97 is placed in the ATE test mode, its digital AC-link outputs (i.e. BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in circuit testing of the AC `97 controller. MS0058-E-00 - 28 2000/11 [ASAHI KASEI] [AK4545] System Design The following figure shows the system connection diagram. AVDD: 5V DVDD: 3.3V MS0058-E-00 - 29 2000/11 [ASAHI KASEI] [AK4545] 1. Grounding and Power Supply Decoupling AVdd1 and AVdd2 should be connected and derived from same AVdd. And DVdd1 and DVdd2 also should be connected and derived from same DVdd. Analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4545 as possible, with the small value ceramic capacitor being the nearest. No specific power supply sequencing is required on the AK4545. 2. On-chip Voltage Reference The on-chip voltage reference are output on the VRAD ,VRDA and Vref pins for decoupling. A electrolytic capacitor less than 10uF in parallel with a 0.1 uF ceramic capacitor attached to these pins eliminates the effects of high frequency noise. No load current may be drawn from VRAD , VRDA, and Vref pins. All signals, especially clocks, should be kept away from the VRAD , VRDA and Vref pins in order to avoid unwanted coupling into delta-sigma modulators. 3.Analog input Since many analog levels can be as high as 2Vrms, the circuit shown below can be used to attenuate the analog input 2Vrms to 1Vrms which is the maximum voltage allowed for all the stereo line-level inputs. J15 LINE_IN_L J4 LINE_IN_R 4.PC_BEEP If PC_BEEP isnt used, this input pin should be NC(open) or connected to Analog-Ground through capacitor. In this case, the register for PC-Beep(04h,D15) should be set to mute on 1. (Note that the default of PC_BEEP is mute off.) In addition, when PC_BEEP is connected through capacity to Analog-Ground, PC_BEEP is recommended to be separated from other non-used input pins. 5.Microphone Input design VrefOut of AK4545 28pin can be used for Bias of Microphone Input. MS0058-E-00 - 30 2000/11 [ASAHI KASEI] [AK4545] Package 48pin LQFP(Unit:mm) 1.70Max 9.0 0.2 0.13 0.13 7.0 1.40 0.05 25 24 48 13 7.0 37 1 9.0 0.2 36 12 0.145 0.05 0.5 0.22 0.08 0.10 M 0 10 0.10 MS0058-E-00 0.5 0.2 - 31 2000/11 [ASAHI KASEI] [AK4545] Marking AKM AK4545VQ XXXXXXX JAPAN 1 1) 2) 3) 4) 5) MS0058-E-00 Pin #1 indication Date Code : XXXXXXX (7 digits) Marketing Code : AK4545VQ Country of Origin Asahi Kasei Logo - 32 2000/11 [ASAHI KASEI] [AK4545] IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b)A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0058-E-00 - 33 2000/11