ISL2110AR4Z-T - Intersil Corporation

1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL2110, ISL2111

100V, 3A/4A Peak, High Frequency

Half-Bridge Drivers

The ISL2110, ISL2111 are 100V, high frequency, half-bridge

N-Channel power MOSFET driver ICs. They ar e based on

the popular HIP2100, HIP2101 hal f-bridge drivers, but offer

several performance improvements. Peak output pull-up/

pull-down current has been increased to 3A/4A, whic h

significantly reduces switching power losses and eliminates

the need for external totem-pole buffers in many

applications. Also, the low end of the VDD operational supply

range has been extended to 8VDC. The ISL2110 has

additional input hysteresis for superior operation in noisy

environments and the inputs of the ISL2111, like those of the

ISL2110, can now safely swing to the VDD supply rail.

Features

• Drives N-Channel MOSFET Half-Bridge

• SOIC, DFN and TDFN Package Options

• SOIC, DFN and TDFN Packages Compliant with 100V

Conductor Spacing Guidelines per IPC-2221

• Pb-Free (RoHS Compliant)

• Bootstrap Supply Max Voltage to 114VDC

• On-Chip 1W Bootstrap Diode

• Fast Propagation Times for Multi-MHz Circuits

• Drives 1nF Load with Typical Rise/Fall Times of 9ns/7.5ns

• CMOS Compatible Input Thresholds (ISL2110)

• 3.3V/TTL Compatible Input Thresholds (ISL2111)

• Independent Inputs Provide Flexibility

• No Start-Up Problems

• Outputs Unaffected by Supply Glitches, HS Ringing Below

Ground or HS Slewing at High dv/dt

• Low Power Consumption

• Wide Supply Voltage Range (8V to 14V)

• Supply Undervoltage Protection

• 1.6W/1W Typical Output Pull-Up/Pu ll-Down Resistance

Applications

• Telecom Half-Bridge DC/DC Converters

• Telecom Full-Bridge DC/DC Converters

• Two-Switch Forward Converters

• Active-Clamp Forward Converters

• Class-D Audio Amplifiers

Ordering Information

PART

NUMBER

(Notes 1, 2) PART

MARKING

TEMP

RANGE

(°C) PACKAGE

(Pb-Free) PKG.

DWG. #

ISL2110ABZ 2110 ABZ -40 to +125 8 Ld SOIC M8.15

ISL2110AR4Z 211 0AR4Z -40 to +125 12 Ld 4x4 DFN L12.4x4A

ISL2111ABZ 2111 ABZ -40 to +125 8 Ld SOIC M8.15

ISL2111AR4Z 211 1AR4Z -40 to +125 12 Ld 4x4 DFN L12.4x4A

ISL2111ARTZ 211 1ARTZ -40 to +125 10 Ld 4x4 TDFN L10.4x4

ISL2111BR4Z 211 1BR4A -40 to +125 8 Ld 4x4 DFN L8.4x4

NOTES:

1. Add “-T*” suffix for t ape and reel. Please refer to TB347 for details

on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special

Pb-free material sets, molding compounds/die attach materials,

and 100% matte tin plate plus anneal (e3 termination finish, which

is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations). Intersil Pb-free products are MSL classified

at Pb-free peak reflow temperatures that meet or exceed the

Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information

page for ISL2110, ISL2111. For more information on MSL please

see techbrief TB363.

Data Sheet March 8, 2012 FN6295.6

2FN6295.6

March 8, 2012

Application Block Diagram

Pinouts ISL2111ARTZ

(10 LD 4x4 TDFN)

TOP VIEW

ISL2110AR4Z, ISL2111AR4Z

(12 LD 4x4 DFN)

TOP VIEW

ISL2110ABZ, ISL2111ABZ

(8 LD SOIC)

TOP VIEW

ISL2111BR4Z

(8 LD 4x4 DFN)

TOP VIEW

VDD

VSS

VDD

VSS

HS HI

6 7

EPAD*

*EPAD = Exposed PAD

VDD

VSS 2

VDD

VSS

EPAD*

*EPAD = EXPOSED PAD

SECONDARY

CIRCUIT

+100V

CONTROL

CONTROLLER

PWM

HI HO

VDD

+12V

VSS

REFERENCE

AND

ISOLATION

DRIVE

ISL2110

ISL2111

ISL2110, ISL2111

3FN6295.6

March 8, 2012

Functional Block Diagram

UNDER

VOLTAGE

VDD

VSS

DRIVER

LEVEL SHIFT

UNDER

VOLTAGE

EPAD (DFN Package Only)

ISL2111

*EP AD = Exposed Pad. The EPAD is electrically isolated from all other pins. For

best thermal performance connect the EPAD to the PCB power ground plane.

SECONDARY

ISOLATION

PWM

+48V

+12V

CIRCUIT

FIGURE 1. TWO-SWITCH FORWARD CONVERTER

ISL2110

ISL2111

SECONDARY

CIRCUIT

ISOLATION

PWM

+48V

+12V

FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP

ISL2110

ISL2111

ISL2110, ISL2111

4FN6295.6

March 8, 2012

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD, VHB - VHS (Notes 4, 5) . . . . . . . .-0.3V to 18V

LI and HI Voltages (Note 5) . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V

Voltage on LO (Note 5) . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V

Voltage on HO (Note 5) . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V

Voltage on HS (Continuous) (Note 5) . . . . . . . . . . . . . . -1V to 110V

Voltage on HB (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118V

Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . 100mA

Maximum Recommended Operating Conditions

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V

Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V

Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V

V olt age on HB. . . . .V HS+7V to VHS+14V and VDD - 1V to VDD+100V

HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

8 Ld SOIC (Notes 6, 10). . . . . . . . . . . . 95 46

10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . 42 5.5

12 Ld DFN (Notes 7, 8) . . . . . . . . . . . . 40 5.5

8 Ld DFN (Notes 7, 8) . . . . . . . . . . . . . 40 4.0

Max Power Dissip ation at +2 5°C in Free Air

8 Ld SOIC (Notes 6, 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W

10 Ld TDFN (Notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W

12 Ld DFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W

8 Ld DFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W

Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

4. The ISL2110 and ISL2111 are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating

curve for this mode of operation.

5. All voltages referen ced to VSS unless othe rwise specified.

6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.

7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization

and are not production tested.

10. For θJC, the “case temp” location is taken at the package top center.

Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified.

PARAMETERS SYMBOL TEST CONDITIONS

TJ = +25°C TJ = -40°C to +12 5°C

UNITSMIN TYP MAX MIN

(Note 9) MAX

(Note 9)

SUPPLY CURRENTS

VDD Quiescent Current IDD ISL2110; LI = HI = 0V - 0.1 0.25 - 0.3 mA

VDD Quiescent Current IDD ISL2111; LI = HI = 0V - 0.3 0.45 - 0.55 mA

VDD Operating Current IDDO ISL2110; f = 500kHz - 3.4 5.0 - 5.5 mA

VDD Operating Current IDDO ISL2111; f = 500kHz - 3.5 5.0 - 5.5 mA

Total HB Quiescent Current IHB LI = HI = 0V - 0.1 0.15 - 0.2 mA

Total HB Operating Current IHBO f = 500kHz - 3.4 5.0 - 5.5 mA

HB to VSS Current, Quiescent IHBS LI = HI = 0V; VHB = VHS = 114V - 0.05 1.5 - 10 µA

HB to VSS Current, Operating IHBSO f = 500kHz; VHB = VHS = 114V - 1.2 - - - mA

INPUT PINS

Low Level Input Voltage Threshold VIL ISL2110 3.7 4.4 - 3.5 - V

Low Level Input Voltage Threshold VIL ISL2111 1.4 1.8 - 1.2 - V

High Level Input Voltage Threshold VIH ISL2110 - 6.6 7.4 - 7.6 V

High Level Input Voltage Threshold VIH ISL2111 - 1.8 2.2 - 2.4 V

Input Voltage Hysteresis VIHYS ISL2110 - 2.2 - - - V

Input Pull-Down Resistance RI- 210 - 100 500 kΩ

ISL2110, ISL2111

5FN6295.6

March 8, 2012

UNDERVOLTAGE PROTECTION

VDD Rising Threshold VDDR 6.1 6.6 7.1 5.8 7.4 V

VDD Threshold Hysteresis VDDH -0.6- - - V

HB Rising Threshold VHBR 5.5 6.1 6.8 5.0 7.1 V

HB Threshold Hysteresis VHBH -0.6- - - V

BOOT STRAP DIODE

Low Current Forward Voltage VDL IVDD-HB = 100µA - 0.5 0.6 - 0.7 V

High Current Forward Voltage VDH IVDD-HB = 100mA - 0.7 0.9 - 1 V

Dynamic Resistance RDIVDD-HB = 100mA - 0.7 1 - 1.5 Ω

LO GATE DRIVER

Low Level Output Voltage VOLL ILO = 100mA - 0.1 0.18 - 0.25 V

High Level Output Voltage VOHL ILO = -100mA, VOHL = VDD - VLO - 0.16 0.23 - 0.3 V

Peak Pull-Up Current IOHL VLO = 0V - 3 - - - A

Peak Pull-Down Current IOLL VLO = 12V - 4 - - - A

HO GATE DRIVER

Low Level Output Voltage VOLH IHO = 100mA - 0.1 0.18 - 0.25 V

High Level Output Voltage VOHH IHO = -100mA, VOHH = VHB - VHO - 0.16 0.23 - 0.3 V

Peak Pull-Up Current IOHH VHO = 0V - 3 - - - A

Peak Pull-Down Current IOLH VHO = 12V - 4 - - - A

Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. (Continued)

PARAMETERS SYMBOL TEST CONDITIONS

TJ = +25°C TJ = -40°C to +12 5°C

UNITSMIN TYP MAX MIN

(Note 9) MAX

(Note 9)

Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified.

PARAMETERS SYMBOL TEST

CONDITIONS

TJ = +25°C TJ = -40°C

to +125°C

UNITSMIN TYP MAX MIN

(Note 9) MAX

(Note 9)

Lower T urn-Off Propagation De lay (LI Falling to LO Falling) tLPHL - 32 50 - 60 ns

Upper T urn-Off Propagation Delay (HI Falling to HO Falling) tHPHL - 32 50 - 60 ns

Lower Turn-On Prop agation Delay (LI Risin g to LO Risin g) tLPLH - 39 50 - 60 ns

Upper Turn-On Prop a gation Delay (HI Rising to HO Rising ) tHPLH - 38 50 - 60 ns

Delay Matching: Upper Turn-Off to Lower Turn-On tMON 1 8 - - 16 ns

Delay Matching: Lower Turn-Off to Upper Turn-On tMOFF 1 6 - - 16 ns

Either Output Rise Time (10% to 90%) tRC CL = 1nF - 9 - - - ns

Either Output Fall Time (90% to 10%) tFC CL = 1nF - 7.5 - - - ns

Either Output Rise Time (3V to 9V) tR CL = 0.1µF - 0.3 0.4 - 0.5 µs

Either Output Fall Time (9V to 3V) tF CL = 0.1µF - 0.19 0.3 - 0.4 µs

Minimum Input Pulse Width that Changes the Output tPW - - - - 50 ns

Bootstrap Diode Turn-On or Turn-Off Time tBS -10- - - ns

ISL2110, ISL2111

6FN6295.6

March 8, 2012

Timing Diagrams

Pin Descriptions

SYMBOL DESCRIPTION

VDD Positive supply to lower gate driver. Bypass this pin to VSS.

HB High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.

Bootstrap diode is on-chip.

HO High-side output. Connect to gate of high-side power MOSFET.

HS High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this

pin.

HI High-side input.

LI Low-side input.

VSS Chip negative supply, which will generally be ground.

LO Low-side output. Connect to gate of low-side power MOSFET.

NC No Connect.

EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.

FIGURE 3. PROPAGATION DELAYS FIGURE 4. DELAY MATCHING

tHPLH,

tLPLH tHPHL,

tLPHL

HI, LI

LO tMON tMOFF

Typical Performance Curves

FIGURE 5. ISL2110 IDD OPERATING CURRENT vs

FREQUENCY FIGURE 6. ISL2 1 1 1 IDD OPERA TING CURRENT vs

FREQUENCY

0.1

1.0

10.0

FREQUENCY (Hz)

IDDO (mA)

T = +25°C

T = -40°C

T = +125°C

T = +150°C

10k 100k 1.103k10k 100k 1.103k

0.1

1.0

10.0

FREQUENCY (Hz)

IDDO (mA)

T = +25°C

T = -40°C

T = +150°C

T = +125°C

ISL2110, ISL2111

7FN6295.6

March 8, 2012

FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY

FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE FIGURE 10. LOW LEVEL OUTPUT VOL TAGE vs

TEMPERATURE

FIGURE 1 1. UNDERVOL TAGE LOCKOUT THRESHOLD vs

TEMPERATURE FIGURE 12. UNDERVOL TAGE LOCKOUT HYSTERESIS vs

TEMPERATURE

Typical Performance Curves (Continued)

FREQUENCY (Hz)

IHBO (mA)

0.01

1.0

10.0

T = +25°C

T = -40°C

T = +125°C

T = +150°C

10k 100k 1.103k

0.1

FREQUENCY (Hz)

IHBSO (mA)

0.01

1.0

10.0

T = -40°C

T = +125°C

T = +150°C

10k 100k 1.103k

0.1

T = +25°C

-50 0 50 100 150

100

150

200

250

300

TEMPERATURE (°C)

VOHL, VOHH (mV)

VDD = VHB = 12V

VDD = VHB = 14V

VDD = VHB = 8V

-50 0 50 100 150

100

150

200

VOLL, VOLH (mV)

TEMPERATURE (°C)

VDD = VHB = 12V

VDD = VHB = 14V

VDD = VHB = 8V

VDDR, VHBR (V)

-50 0 50 100 150

6.7

TEMPERATURE (°C)

VHBR

VDDR

6.5

6.3

6.1

5.9

5.7

5.5

5.3

VDDH, VHBH (V)

-50 0 50 100 150

0.70

TEMPERATURE (°C)

VHBH

VDDH

0.65

0.60

0.55

0.50

0.45

0.40

ISL2110, ISL2111

8FN6295.6

March 8, 2012

FIGURE 13. ISL21 10 PROP AGA TION DELAYS vs

TEMPERATURE FIGURE 14. ISL21 1 1 PROP AGATION DELAYS vs

TEMPERATURE

FIGURE 15. ISL2110 DELAY MATCHING vs TEMPERATURE FIGURE 16. ISL2111 DELAY MATCHING vs TEMPERATURE

FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT

VOLTAGE

Typical Performance Curves (Continued)

tLPLH, tLPHL, tHPLH, tHPHL (ns)

-50 0 50 100 150

TEMPERATURE (°C)

tLPHL

tHPHL

tLPLH

tHPLH

tLPLH, tLPHL, tHPLH, tHPHL (ns)

-50 0 50 100 150

TEMPERATURE (°C)

tLPHL

tHPHL

tLPLH

tHPLH

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

tMON, tMOFF (ns)

-50 0 50 100 150

TEMPERATURE (°C)

tMOFF

tMON

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

tMON, tMOFF (ns)

-50 0 50 100 150

TEMPERATURE (°C)

tMOFF

tMON

0481012

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VLO, VHO (V)

IOHL, IOHH (A)

26 0481012

1.5

2.0

2.5

3.0

3.5

4.0

4.5

VLO, VHO (V)

IOHL, IOHH (A)

1.0

0.5

ISL2110, ISL2111

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6295.6

March 8, 2012

FIGURE 19. ISL2110 QUIESCENT CURRENT vs VOLTAGE FIGURE 20. ISL2111 QUIESCENT CURRENT vs VOLTAGE

FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE

Typical Performance Curves (Continued)

0 5 10 15 20

100

110

120

VDD, VHB (V)

IDD, IHB (µA)

IHB

IDD

0 5 10 15 20

VDD, VHB (V)

IDD, IHB (µA)

100

120

140

160

180

200

220

240

260

280

300

320

IHB

IDD

0.3 0.4 0.5 0.6 0.7 0.8

1.10-3

0.01

0.10

1.00

FORWARD VOLTAGE (V)

FORWARD CURRENT (A)

1.10-4

1.10-5

1.10-6

12 13 14 15 16

100

120

TO V

VOLTAGE (V)

TO V

VOLTAGE (V)

ISL2110, ISL2111

10 FN6295.6

March 8, 2012

ISL2110, ISL2111

Package Outline Drawing

L10.4x4

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 1/08

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

SIDE VIEW

TOP VIEW

BOTTOM VIEW

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

4.00 2.60

0.15

( 3.80)

(4X)

( 10X 0 . 30 )

( 8X 0 . 8 )

0 .75

BASE PLANE

SEATING PLANE

0.08

0.10

10 X 0.30

SEE DETAIL "X"

0.10

CAMB

INDEX AREA

PIN 1

4.00

PIN #1 INDEX AREA BSC

3.2 REF

8X 0.80

( 10 X 0.60 )

0 . 00 MIN.

0 . 05 MAX.

0 . 2 REF

10X 0 . 40

3.00

( 2.60)

( 3.00 )

0.05 M C

11 FN6295.6

March 8, 2012

ISL2110, ISL2111

Package Outline Drawing

L12.4x4A

12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 3/11

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X "

SIDE VIEW

TOP VIEW

BOTTOM VIEW

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the term inal tip.

Lead width applies to the metalli zed terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

either a mold or mark feature.

Dimensions are in mi llimeters.1.

NOTES:

4.00 1.58

0.15

( 3.80)

(4X)

( 12X 0 . 25)

( 10X 0 . 5 )

1.00 MAX

BASE PLANE

SEATING PLANE

0.08

0.10 C

12 X 0.25

SEE DETAIL "X"

0.10

CAMB

INDEX AREA

PIN 1

4.00

PIN #1 INDEX AREA 3.2 REF

10X 0.50 BSC

( 12 X 0.65 )

0 . 00 MIN.

0 . 05 MAX.

0 . 2 REF

12X 0 . 45

2.80

( 1.58)

( 2.80 )

0.05 M C

12 FN6295.6

March 8, 2012

ISL2110, ISL2111

Package Outline Drawing

M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 3, 3/11

DETAIL "A"

TOP VIEW

INDEX

AREA

123

-C-

SEATING PLANE

x 45°

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1982.

2. Package length does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

3. Package width does not include interlead flash or protrusions. Inte rlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatche d area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater abov e the

seating plane, shall not exceed a maximum value of 0.61mm (0. 024 inch) .

7. Controlling dimension: MILLIMETER. Converted inch dimensions are not

necessarily exact.

8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

SIDE VIEW “A

SIDE VIEW “B”

1.27 (0.050)

6.20 (0.244)

5.80 (0.228)

4.00 (0.157)

3.80 (0.150)

0.50 (0.20)

0.25 (0.01)

5.00 (0.197)

4.80 (0.189) 1.75 (0.069)

1.35 (0.053)

0.25(0.010)

0.10(0.004)

0.51(0.020)

0.33(0.013)

8°

0°

0.25 (0.010)

0.19 (0.008)

1.27 (0.050)

0.40 (0.016)

1.27 (0.050)

5.20(0.205)

TYPICAL RECOMMENDED LAND PATTERN

2.20 (0.087)

0.60 (0. 023)

13 FN6295.6

March 8, 2012

Package Outline Drawing

L8.4x4

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 11/09

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"

SIDE VIEW

TOP VIEW

BOTTOM VIEW

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension applies to the metallized terminal and is measured

Dimens ion s in ( ) for Referen ce O n ly.

Dimensioning and tolerancing conform to ASME Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

4.00 2.50 ± 0.10

0.15

( 3.80)

(4X)

( 8X 0 . 30 )( 6X 0 . 8 )

0 .9 ± 0.10

BASE PLANE

SEATING PLANE

0.08

0.10 C

8 X 0.30

SEE DETAIL "X"

0.10

CAMB

INDEX AREA

PIN 1

4.00

PIN #1 INDEX AREA BSC

2.4 REF

6X 0.80

( 8 X 0.60 )

8X 0 . 40 ± 0.10

3.45 ± 0.10

( 2.50)

( 3.45 )

0.05 M C

0 . 00 MIN.

0 . 05 MAX.

0 . 2 REF

ISL2110, ISL2111