BSS84,215 - NEXPERIA - searchdatasheet.com

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1. Product proﬁle

1.1 General description

P-channel enhancement mode vertical Diffusion Metal-Oxide Semiconductor (DMOS)

transistor in a small Surface-Mounted Device (SMD) plastic package.

[1] /DG: halogen-free

1.2 Features

1.3 Applications

1.4 Quick reference data

BSS84

P-channel enhancement mode vertical DMOS transistor

Rev. 06 — 16 December 2008 Product data sheet

Table 1. Product overview

Type number[1] Package

NXP JEDEC

BSS84 SOT23 TO-236AB

BSS84/DG

nLow threshold voltage nDirect interface to CMOS and

Transistor-Transistor Logic (TTL)

nHigh-speed switching nNo secondary breakdown

nLine current interrupter in telephone sets nRelay, high-speed and line transformer

drivers

nVDS ≤−50 V nID≤−130 mA

nRDSon ≤10 ΩnPtot ≤250 mW

Product data sheet Rev. 06 — 16 December 2008 2 of 11

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

2. Pinning information

3. Ordering information

[1] /DG: halogen-free

4. Marking

[1] /DG: halogen-free

[2] * = -: made in Hong Kong

* = p: made in Hong Kong

* = t: made in Malaysia

* = W: made in China

Table 2. Pinning

Pin Symbol Description Simpliﬁed outline Graphic symbol

1 G gate

SOT23 (TO-236AB)

2 S source

3 D drain

001aaa025

Table 3. Ordering information

Type number[1] Package

Name Description Version

BSS84 TO-236AB plastic surface-mounted package; 3 leads SOT23

BSS84/DG

Table 4. Marking codes

Type number[1] Marking code[2]

BSS84 13*

BSS84/DG ZV*

Product data sheet Rev. 06 — 16 December 2008 3 of 11

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

5. Limiting values

[1] Device mounted on a Printed-Circuit Board (PCB).

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage 25 °C≤Tj≤150 °C-−50 V

VGS gate-source voltage - ±20 V

IDdrain current Tsp =25°C; VGS =−10 V;

see Figure 1 -−130 mA

Tsp = 100 °C;

VGS =−10 V -−75 mA

IDM peak drain current Tsp =25°C; tp≤10 µs;

see Figure 1 -−520 mA

Ptot total power dissipation Tsp =25°C; see Figure 2 [1] - 250 mW

Tstg storage temperature −65 +150 °C

Tjjunction temperature −65 +150 °C

Tsp =25°C

(1) RDSon limitation

Fig 1. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

mld251

VDS (V)

−1−102

−10

−102

−10

−103

(mA)

−1

1 ms

10 ms

100 ms

(1)

tp =

10 µs

100 µs

Product data sheet Rev. 06 — 16 December 2008 4 of 11

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

6. Thermal characteristics

[1] Mounted on a PCB, vertical in still air.

Fig 2. Power derating curve

0 200

300

100

200

mld199

Tamb (°C)

50 100 150

Ptot

(mW)

Table 6. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-a) thermal resistance from

junction to ambient see Figure 3 [1] - - 500 K/W

Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration

103

102

tp (s)

110

mld250

Rth(j-a)

(K/W)

10−1

10−610−510−410−310−2102103

10−1

δ = 0.75

0.1

0.05

0.01

0.02

0.2

0.5

δ =

Product data sheet Rev. 06 — 16 December 2008 5 of 11

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

7. Characteristics

Table 7. Characteristics

=25

C unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source breakdown

voltage ID=−10 µA; VGS =0V −50--V

VGS(th) gate-source threshold

voltage ID=−1 mA; VDS =V

GS;

see Figure 8

Tj=25°C−0.8 - −2V

Tj=−55 °C--−1.8 V

IDSS drain leakage current VDS =−40 V; VGS =0V

Tj=25°C--−100 nA

VDS =−50 V; VGS =0V

Tj=25°C--−10 µA

Tj= 125 °C--−60 µA

IGSS gate leakage current VGS = +20 V; VDS = 0 V - - 100 nA

VGS =−20 V; VDS = 0 V - - 100 nA

RDSon drain-source on-state

resistance VGS =−10 V;

ID=−130 mA;

see Figure 5 and 7

-610Ω

Dynamic characteristics

|Yfs|transfer admittance VDS =−25 V;

ID=−130 mA 50--mS

Ciss input capacitance VGS =0V; V

DS =−25 V;

f = 1 MHz; see Figure 9 - 2545pF

Coss output capacitance - 15 25 pF

Crss reverse transfer

capacitance - 3.5 12 pF

ton turn-on time VDS =−40 V; VGS =0V

to −10 V; ID=−200 mA;

see Figure 10 and 11

-3-ns

toff turn-off time VDS =−40 V;

VGS =−10 V to 0 V;

ID=−200 mA;

see Figure 10 and 11

-7-ns

Product data sheet Rev. 06 — 16 December 2008 6 of 11

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

Tj=25°CT

j=25°C

Fig 4. Output characteristics: drain current as a

function of drain-source voltage; typical

values

Fig 5. Drain-source on-state resistance as a function

of drain current; typical values

Tj=25°C; VDS =−10 V (1) ID=−130 mA; VGS =−10 V

(2) ID=−20 mA; VGS =−2.4 V

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values Fig 7. Normalized drain-source on-state resistance

factor as a function of junction temperature

0−2−10 −12

−600

−200

−400

mld197

−4−6−8VDS (V)

VGS = −10 V −7.5 V −6 V

−5 V

−4 V

−3 V

−2.5 V

(mA)

−1

mld198

−10 −102−103

ID (mA)

RDSon

(Ω)VGS = −2.5 V −3 V

−7.5 V

−10 V

−5 V

−4 V

0−2−4−10

−600

−200

−400

mld196

−6

(mA)

VGS (V)

−80.6

1.0

1.4

1.8

0 50 100 150−50 Tj (°C)

mld194

(1)

(2)

RDSon

RDSon(25°C)

Product data sheet Rev. 06 — 16 December 2008 7 of 11

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

8. Test information

ID=−1 mA; VDS =V

GS VGS =0V; f = 1 MHz

Fig 8. Gate-source threshold voltage as a function of

junction temperature Fig 9. Input, output and reverse transfer

capacitances as a function of drain-source

voltage; typical values

0.6

0.8

1.0

1.2

0 50 100 150

mld195

−50 Tj (°C)

VGSth

VGSth(25°C)

0−10 −20 −30

mld191

(pF)

VDS (V)

Ciss

Coss

Crss

Fig 10. Switching time test circuit Fig 11. Input and output waveforms

mld189

50 Ω

VDS = −40 V

0 V

−10 V

mbb690

10 %

90 %

10 %

ton toff

OUTPUT

INPUT

Product data sheet Rev. 06 — 16 December 2008 8 of 11

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

9. Package outline

Fig 12. Package outline SOT23 (TO-236AB)

UNIT A1

max. bpcDE e1HELpQwv

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

04-11-04

06-03-16

IEC JEDEC JEITA

mm 0.1 0.48

0.38 0.15

0.09 3.0

2.8 1.4

1.2 0.95

1.9 2.5

2.1 0.55

0.45 0.1

0.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15

SOT23 TO-236AB

detail X

vMA

0 1 2 mm

scale

1.1

0.9

Plastic surface-mounted package; 3 leads SOT23

Product data sheet Rev. 06 — 16 December 2008 9 of 11

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

10. Revision history

Table 8. Revision history

Document ID Release date Data sheet status Change notice Supersedes

BSS84_6 20081216 Product data sheet - BSS84_5

Modiﬁcations: •Table 5 “Limiting values”: Ptot ﬁgure reference updated

BSS84_5 20081209 Product data sheet - BSS84_4

BSS84_4 20070717 Product data sheet - BSS84_3

BSS84_3 20030804 Product speciﬁcation - BSS84_2

BSS84_2 19970618 Product speciﬁcation - BSS84_1

BSS84_1 19950407 Product speciﬁcation - -

Product data sheet Rev. 06 — 16 December 2008 10 of 11

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

11. Legal information

11.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

11.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

11.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

11.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

12. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors BSS84

P-channel enhancement mode vertical DMOS transistor

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 December 2008

Document identifier: BSS84_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

13. Contents

1 Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 7

9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

10 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9

11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10

11.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10

11.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

11.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

11.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

12 Contact information. . . . . . . . . . . . . . . . . . . . . 10

13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11