MC74VHCT08AMELG - ON Semiconductor

May, 2011 − Rev. 7

1Publication Order Number:

MC74VHCT08A/D

MC74VHCT08A

Quad 2-Input AND Gate

The MC74VHCT08A is an advanced high speed CMOS 2−input

AND gate fabricated with silicon gate CMOS technology. It achieves

high speed operation similar to equivalent Bipolar Schottky TTL

while maintaining CMOS low power dissipation.

The VHCT inputs are compatible with TTL levels. This device can

be used as a level converter for interfacing 3.3 V to 5.0 V, because it

has full 5.0 V CMOS level output swings.

The VHCT08A input structures provide protection when voltages

between 0 V and 5.5 V are applied, regardless of the supply voltage.

The output structures also provide protection when VCC = 0 V. These

input and output structures help prevent device destruction caused by

supply voltage − input/output voltage mismatch, battery backup, hot

insertion, etc.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V

systems to 3.0 V systems.

Features

•High Speed: tPD = 4.3 ns (Typ) at VCC = 5 V

•Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C

•TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2 V to 5.5 V Operating Range

•Low Noise: VOLP = 0.8 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance: Human Body Model; > 2000 V,

Machine Model; > 200 V

•Chip Complexity: 24 FETs or 6 Equivalent Gates

•These Devices are Pb−Free and are RoHS Compliant

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MARKING

DIAGRAMS

TSSOP−14

DT SUFFIX

CASE 948G

1

SOEIAJ−14

M SUFFIX

CASE 965

SOIC−14

D SUFFIX

CASE 751A

1

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

A = Assembly Location

WL, L = Wafer Lot

Y, YY = Year

WW, W = Work Week

G or G= Pb−Free Package

1

14

VHCT08

ALYWG

VHCT08AG

AWLYWW

1

14

VHCT

08A

ALYWG

G

1

14

(Note: Microdot may be in either location)

MC74VHCT08A

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2

3Y1

1

A1

Figure 1. Logic Diagram

2

B1

6Y2

4

A2

5

B2

8Y3

9

A3

10

B3

11 Y4

12

A4

13

B4

Y = AB

Figure 2. Pinout: 14−Lead Packages

1314 12 11 10 9 8

21 34567

VCC B4 A4 Y4 B3 A3 Y3

A1 B1 Y1 A2 B2 Y2 GND

L

H

L

H

L

H

FUNCTION TABLE

Inputs Output

AB

L

H

Y

(Top View)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Rating

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎ

VCC

ÎÎÎÎÎÎ

–0.5 to +7.0

ÎÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎ

Vin

ÎÎÎÎÎÎ

–0.5 to +7.0

ÎÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎÎ

Vout

ÎÎÎÎÎÎ

–0.5 to VCC +0.5

ÎÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Diode Current

ÎÎÎÎ

IIK

ÎÎÎÎÎÎ

−20

ÎÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Diode Current

ÎÎÎÎ

IOK

ÎÎÎÎÎÎ

±20

ÎÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎ

Iout

ÎÎÎÎÎÎ

±25

ÎÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎ

ICC

ÎÎÎÎÎÎ

±50

ÎÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎ

PD

ÎÎÎÎÎÎ

500

450

ÎÎÎ

mW

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎ

–65 to +150

ÎÎÎ

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or

conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute−maximum−rated conditions is not

implied.

†Derating −SOIC Packages: – 7 mW/°C from 65° to 125°C

TSSOP Package: − 6.1 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎ

VCC

ÎÎÎÎ

4.5

ÎÎÎ

5.5

ÎÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎ

Vin

ÎÎÎÎ

0

ÎÎÎ

5.5

ÎÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎÎ

Vout

ÎÎÎÎ

0

ÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature

ÎÎÎÎ

TA

ÎÎÎÎ

−40

ÎÎÎ

+ 125

ÎÎÎ

°C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 5.0 V ±0.5 V

ÎÎÎÎ

tr, tf

ÎÎÎÎ

0

ÎÎÎ

20

ÎÎÎ

ns/V

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74VHCT08A

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

ÎÎÎ

VCC

(V)

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎ

TA ≤ 85°C

ÎÎÎÎ

TA ≤ 125°C

ÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎ

Min

ÎÎ

Typ

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎÎ

Minimum High−Level Input Voltage

ÎÎÎÎÎ

ÎÎÎÎ

VIH

ÎÎÎ

3.0

4.5

5.5

ÎÎÎ

1.2

2.0

ÎÎ

ÎÎÎ

1.2

2.0

ÎÎÎ

ÎÎ

1.2

2.0

ÎÎÎ

ÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Input Voltage

ÎÎÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎ

3.0

4.5

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

0.53

0.8

ÎÎÎ

0.53

0.8

ÎÎ

ÎÎÎ

0.53

0.8

ÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎ

Minimum High−Level Output Voltage

VIN = VIH or VIL

ÎÎÎÎÎ

VIN = VIH or VIL

IOH = − 50 mA

ÎÎÎÎ

VOH

ÎÎÎ

3.0

4.5

ÎÎÎ

2.9

4.4

ÎÎ

3.0

4.5

ÎÎÎ

2.9

4.4

ÎÎÎ

ÎÎ

2.9

4.4

ÎÎÎ

ÎÎ

V

ÎÎÎÎÎ

VIN = VIH or VIL

IOH = −4 mA

IOH = −8 mA

ÎÎÎ

3.0

4.5

ÎÎÎ

2.58

3.94

ÎÎ

ÎÎÎ

2.48

3.80

ÎÎÎ

ÎÎ

2.34

3.66

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Output Voltage

VIN = VIH or VIL

ÎÎÎÎÎ

VIN = VIH or VIL

IOL = 50 mA

ÎÎÎÎ

VOL

ÎÎÎ

3.0

4.5

ÎÎÎ

ÎÎ

0.0

ÎÎÎ

0.1

ÎÎÎ

0.1

ÎÎ

ÎÎÎ

0.1

ÎÎ

V

ÎÎÎÎÎ

VIN = VIH or VIL

IOL = 4 mA

IOL = 8 mA

ÎÎÎ

3.0

4.5

ÎÎÎ

ÎÎ

ÎÎÎ

0.36

ÎÎÎ

0.44

ÎÎ

ÎÎÎ

0.52

ÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎ

VIN = 5.5 V or

GND

ÎÎÎÎ

IIN

ÎÎÎ

0 to 5.5

ÎÎÎ

ÎÎ

ÎÎÎ

±0.1

ÎÎÎ

±1.0

ÎÎ

ÎÎÎ

±1.0

ÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply Current

ÎÎÎÎÎ

VIN = VCC or GND

ÎÎÎÎ

ICC

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

2.0

ÎÎÎ

20

ÎÎ

ÎÎÎ

40

ÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎ

Quiescent Supply Current

ÎÎÎÎÎ

Input: VIN = 3.4 V

ÎÎÎÎ

ICCT

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

1.35

ÎÎÎ

1.50

ÎÎ

ÎÎÎ

1.65

ÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎ

Output Leakage Current

ÎÎÎÎÎ

VOUT = 5.5 V

ÎÎÎÎ

IOPD

ÎÎÎ

0.0

ÎÎÎ

ÎÎ

ÎÎÎ

0.5

ÎÎÎ

5.0

ÎÎ

ÎÎÎ

10

ÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

ÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎ

TA ≤ 85°C

ÎÎÎÎ

TA ≤ 125°C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎ

Typ

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎ

Max

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay,

Input A or B to Y

ÎÎÎÎÎÎÎÎ

VCC = 3.0 ± 0.3V CL = 15 pF

CL = 50 pF

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎ

ÎÎ

6.2

8.7

ÎÎÎ

8.8

12.3

ÎÎÎ

10.5

14.0

ÎÎ

ÎÎÎ

14.0

17.5

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15 pF

CL = 50 pF

ÎÎÎ

ÎÎ

4.3

5.8

ÎÎÎ

5.9

7.9

ÎÎÎ

7.0

9.0

ÎÎ

ÎÎÎ

9.0

11.0

ÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎ

ÎÎ

4

ÎÎÎ

10

ÎÎÎ

10

ÎÎ

ÎÎÎ

10

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation Capacitance (Note 1)

ÎÎÎÎ

CPD

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Typical @ 25°C, VCC = 5.0V

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

20

ÎÎÎ

pF

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 4 (per gate). CPD is used to determine the

no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.7

NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50pF, VCC = 5.0 V)

Characteristic Symbol

TA = 25°C

Unit

Typ Max

Quiet Output Maximum Dynamic VOL VOLP 0.3 0.8 V

Quiet Output Minimum Dynamic VOL VOLV −0.3 −0.8 V

Minimum High Level Dynamic Input Voltage VIHD 3.5 V

Maximum Low Level Dynamic Input Voltage VILD 1.5 V

MC74VHCT08A

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4

Figure 3. Switching Waveforms

Y

A or B

1.5V

tPLH tPHL

GND

3.0V

1.5V

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 4. Test Circuit

VOH

VOL

ORDERING INFORMATION

Device Package Shipping†

MC74VHCT08ADR2G SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

MC74VHCT08ADTR2G TSSOP−14* 2500 Units / Tape &Reel

MC74VHCT08AMG SOEIAJ−14

(Pb−Free) 50 Units / Rail

MC74VHCT08AMELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*These packages are inherently Pb−Free.

MC74VHCT08A

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5

PACKAGE DIMENSIONS

SOIC−14

D SUFFIX

CASE 751A−03

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

G

P7 PL

14 8

7

1

M

0.25 (0.010) B M

S

B

M

0.25 (0.010) A S

T

−T−

F

RX 45

SEATING

PLANE D14 PL K

C

J

M

_DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

__ __

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

7X

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6

PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V S

T

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

K

K1

ÉÉÉ

DETAIL E

F

M

−W−

0.25 (0.010)

8

14

7

1

PIN 1

IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

−V−

14X REFK

N

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

MC74VHCT08A

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7

PACKAGE DIMENSIONS

SOEIAJ−14

CASE 965−01

ISSUE B

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.004 0.008

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 1.42 --- 0.056

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

D

Z

E

1

14 8

7

eA

b

VIEW P

c

L

DETAIL P

M

A

b

c

D

E

e

L

M

Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

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MC74VHCT08A/D

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