CY7C1350F-100BGC - Cypress Semiconductor

4-Mb (128K x 36) Pipelined SRAM with Nobl™ Architecture

CY7C1350F

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05305 Rev. *A Revised January 19, 2004

1CY7C13 50F

Features

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Byte Write capability

• 128K x 36 common I/O architecture

• Single 3.3V power supply

• 2.5V/3.3V I/O Operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable (OE)

• JEDEC-standard 100 TQFP and 119 BGA packages

• Burst Capability—linear or interleaved burst order

• “ZZ” Sleep mode option

Functional Description[1]

The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1350F is equipped with the advanced

No Bus Latency™ (NoBL™) logic required to enable consec-

utive Read/Write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of the SRAM, especially in systems that require

frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which, when deasserted, suspends operation and extends the

previous clock cycle. Maximum access delay from the clock

rise is 2.8 ns (200-MHz device)

Write operations are controlled by the four Byte Write Select

(BW[A:D]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

A0, A1, A

MODE

CE1

CE2

CE3

OE READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC A0'

A1'

D0 Q1

ADV/LD

INPUT

CLK

WRITE

DRIVERS

SLEEP

CONTROL

Logic Block Diagram

CY7C1350F

Document #: 38-05305 Rev. *A Page 2 of 16

Shaded area contains advance information.

Please contact your local Cypress sales representative for availability of these parts.

Selection Guide

250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit

Maximum Access Time 2.6 2.6 2.8 3.5 4.0 4.5 ns

Maximum Operating Current 325 290 265 240 225 205 mA

Maximum CMOS Standby Current 40 40 40 40 40 40 mA

Pin Configuration

NC / 288M

NC / 144M

NC / 36M

DQP

DDQ

DQP

DDQ

DQP

CLK

CEN

100

ADV/LD

MODE

NC / 72M

NC / 18M

NC / 9M

CY7C1350F

100-Pin TQFP

BYTE B

BYTE A

BYTE C

BYTE D

CY7C1350F

Document #: 38-05305 Rev. *A Page 3 of 16

Pin Configuration (continued)

23 4 56 71

DQA

VDDQ

DQC

DQD

DQC

DQD

AA AANC / 18M VDDQ

CE2A

VDDQ

DQC

DQD

VDD

NC / 72M

DQPD

ADV/LD ACE3NC

VDD AANC

VSS VSS

NC DQPB

DQB

DQA

DQB

DQA

NCNC NC VDDQ

VSS

MODE

CE1VSS

OE VSS VDDQ

BWCNC / 9M

VSS

VDDQ

VDD VSS VDD

VSS

CLK

NC BWA

CEN VSS VDDQ

VSS

NCA

A0 VSS

VDD

DQPCDQB

A NC / 36M

DQCDQB

DQC

DQB

DQA

DQPA

DQD

BWD

119-Ball Bump BGA

BWB

Pin Definitions

Name 119BGA TQFP I/O Description

A0, A1, A P4,N4,A2,

A3,A5,A6,

B3,B5,C2,

C3,C5,C6,

R2,R6,T3,

T4,T5

37,38,32,

33,34,35,

44,45,46,

47,48,49,

50,81,82,

99,10

Input-

Synchronous

Address Inputs used to select one of the 128K address locations.

Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst

counter.

BW[A:D] L5,G5,

G3,L3

93,94,

95,96

Input-

Synchronous

Byte Write Inputs, active LOW. Qualified with WE to conduct writes

to the SRAM. Sampled on the rising edge of CLK.

WE H4 88 Input-

Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK

if CEN is active LOW. This signal must be asserted LOW to initiate a

write sequence.

ADV/LD B4 85 Input-

Synchronous

Advance/Load Input. Used to advance the on-chip address counter

or load a new address. When HIGH (and CEN is asserted LOW) the

internal burst counter is advanced. When LOW, a new address can be

loaded into the device for an access. After being deselected, ADV/LD

should be driven LOW in order to load a new address.

CLK K4 89 Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK

is qualified with CEN. CLK is only recognized if CEN is active LOW.

CE1E4 98 Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.

Used in conjunction with CE2 and CE3 to select/deselect the device.

CE2B2 97 Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.

Used in conjunction with CE1 and CE3 to select/deselect the device.

CE3B6 92 Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.

Used in conjunction with CE1 and CE2 to select/deselect the device.

CY7C1350F

Document #: 38-05305 Rev. *A Page 4 of 16

OE F4 86 Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Combined with

the synchronous logic block inside the device to control the direction of

the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.

When deasserted HIGH, I/O pins are three-stated, and act as input data

pins. OE is masked during the data portion of a write sequence, during

the first clock when emerging from a deselected state, when the device

has been deselected.

CEN M4 87 Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the Clock sig-

nal is recognized by the SRAM. When deasserted HIGH the Clock

signal is masked. Since deasserting CEN does not deselect the device,

CEN can be used to extend the previous cycle when required.

ZZ T7 64 Input-

Asynchronous

ZZ “sleep” Input. This active HIGH input places the device in a

non-time critical “sleep” condition with data integrity preserved. During

normal operation, this pin can be connected to Vss or left floating.

DQs K6,K7,L6,

L7,M6,N6,

N7,P7,D7,

E6,E7,F6,

G6,G7,H6,

H7,D1,E1,

E2,F2,G1,

G2,H1,H2,

K1,K2,L1,

L2,M2,N1,

N2,P1

52,53,56,

57,58,59,

62,63,68,

69,72,73,

74,75,78,

79,2,3,6,

7,8,9,12,

13,18,19,

22,23,23,

24,25,28,

I/O-

Synchronous

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data

deliver the data contained in the memory location specified by the ad-

dress during the clock rise of the read cycle. The direction of the pins

is controlled by OE and the internal control logic. When OE is asserted

LOW, the pins can behave as outputs. When HIGH, DQs and DQPX are

placed in a three-state condition. The outputs are automatically

three-stated during the data portion of a write sequence, during the first

clock when emerging from a deselected state, and when the device is

deselected, regardless of the state of OE.

DQP[A:D] P6,D6,

D2,P2

51,80,

1,30

I/O-

Synchronous

Bidirectional Data Parity I/O Lines. Functionally, these signals are

identical to DQs. During write sequences, DQP[A:D] is controlled by

BW[A:D] correspondingly.

MODE R3 31 Input

Strap pin

Mode Input. Selects the burst order of the device.

When tied to GND selects linear burst sequence. When tied to VDD or

left floating selects interleaved burst sequence.

VDD C4,J2,

J4,J6,R4

15,16,41,

65,66,91

Power Supply Power supply inputs to the core of the device.

VDDQ A1,A7,F1,

F7,J1,J7,

M1,M7,U1,

4,11,14,

20,27,54,

61,70

I/O Power

Supply

Power supply for the I/O circuitry.

VSS D3,D5,E3,

E5,F3,F5

H3,H5,J3,

J5,K3,K5,

M3,M5,N3,

N5,P3,P5

5,10,17,2

1,26,40,5

5,60,67,

71,76,90

Ground Ground for the device.

NC A4,B1,B7,

C1,C7,D4,

G4,L4,R1,

R5,R7,T1,

T2,T6,U6

38,39,42,

43,83,84

No Connects. Not internally connected to the die.

9M, 18M, 36M, 72M, 144M and 288M are address expansion pins in

this device and will be used as address pins in their respective densi-

ties.

Pin Definitions

Name 119BGA TQFP I/O Description

CY7C1350F

Document #: 38-05305 Rev. *A Page 5 of 16

Introduction

Functional Overview

The CY7C1350F is a synchronous-pipelined Burst SRAM

designed specifically to eliminate wait states during

Write/Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous operations

are qualified with CEN. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

access delay from the clock rise (tCO) is 2.8 ns (200-MHz

device).

Accesses can be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

the status of the Write Enable (WE). BW[A:D] can be used to

conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus, provided OE

is active LOW. After the first clock of the read access the output

buffers are controlled by OE and the internal control logic. OE

must be driven LOW in order for the device to drive out the

requested data. During the second clock, a subsequent

operation (Read/Write/Deselect) can be initiated. Deselecting

the device is also pipelined. Therefore, when the SRAM is

deselected at clock rise by one of the chip enable signals, its

output will three-state following the next clock rise.

Burst Read Accesses

The CY7C1350F has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the

SRAM, as described in the Single Read Access section above.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst sequence, and will

wrap around when incremented sufficiently. A HIGH input on

ADV/LD will increment the internal burst counter regardless of

the state of chip enables inputs or WE. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (Read

or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are ALL asserted active, and (3) the Write signal WE

is asserted LOW. The address presented to the address inputs

is loaded into the Address Register. The write signals are

latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically

three-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQs and

DQP[A:D]. In addition, the address for the subsequent access

(Read/Write/Deselect) is latched into the Address Register

(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQs and DQP[A:D]

(or a subset for Byte Write operations, see Write Cycle

Description table for details) inputs is latched into the device

and the write is complete.

The data written during the Write operation is controlled by

BW[A:D] signals. The CY7C1350F provides byte write

capability that is described in the Write Cycle Description table.

Asserting the Write Enable input (WE) with the selected Byte

Write Select (BW[A:D]) input will selectively write to only the

desired bytes. Bytes not selected during a Byte Write

operation will remain unaltered. A synchronous self-timed

write mechanism has been provided to simplify the write

operations. Byte write capability has been included in order to

greatly simplify Read/Modify/Write sequences, which can be

reduced to simple byte write operations.

Because the CY7C1350F is a common I/O device, data should

not be driven into the device while the outputs are active. The

Output Enable (OE) can be deasserted HIGH before

presenting data to the DQs and DQP[A:D] inputs. Doing so will

tri-state the output drivers. As a safety precaution, DQs and

DQP[A:D] are automatically three-stated during the data

portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1350F has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Write operations without reasserting the address inputs.

ADV/LD must be driven LOW in order to load the initial

address, as described in the Single Write Access section

above. When ADV/LD is driven HIGH on the subsequent clock

rise, the chip enables (CE1, CE2, and CE3) and WE inputs are

ignored and the burst counter is incremented. The correct

BW[A:D] inputs must be driven in each cycle of the burst write

in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE1, CE2, and CE3, must remain inactive

for the duration of tZZREC after the ZZ input returns LOW.

CY7C1350F

Document #: 38-05305 Rev. *A Page 6 of 16

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Truth Table[2, 3, 4, 5, 6, 7, 8]

Operation

Address

Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ

Deselect Cycle None H L L X X X L L-H Three-State

Continue

Deselect Cycle

None X L H X X X L L-H Three-State

Read Cycle

(Begin Burst)

External L L L H X L L L-H Data Out (Q)

Read Cycle

(Continue Burst)

Next X L H X X L L L-H Data Out (Q)

NOP/Dummy Read

(Begin Burst)

External L L L H X H L L-H Three-State

Dummy Read

(Continue Burst)

Next X L H X X H L L-H Three-State

Write Cycle

(Begin Burst)

External L L L L L X L L-H Data In (D)

Write Cycle

(Continue Burst)

Next X L H X L X L L-H Data In (D)

NOP/WRITE ABORT

(Begin Burst)

None L L L L H X L L-H Three-State

WRITE ABORT

(Continue Burst)

Next X L H X H X L L-H Three-State

IGNORE CLOCK EDGE

(Stall)

Current X L X X X X H L-H —

SNOOZE MODE None X H X X X X X X Three-State

Notes:

2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx =

Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

3. Write is defined by BW[A:D], and WE. See Write Cycle Descriptions table.

4. When a write cycle is detected, all DQs are three-stated, even during byte writes.

5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.

7. Device will power-up deselected and the DQs in a three-state condition, regardless of OE.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = Three-state

when OE is inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active.

CY7C1350F

Document #: 38-05305 Rev. *A Page 7 of 16

Partial Truth Table for Read/Write[2, 3, 9]

Function WE BWDBWCBWBBWA

Read H X X X X

Write − No bytes written L H H H H

Write Byte A − (DQA and DQPA) LHHHL

Write Byte B − (DQB and DQPB)LHHLH

Write Bytes A, B L H H L L

Write Byte C − (DQC and DQPC)LHLHH

Write Bytes C,A L H L H L

Write Bytes C, B L H L L H

Write Bytes C, B, A L H L L L

Write Byte D − (DQD and DQPD)LLHHH

Write Bytes D, A L L H H L

Write Bytes D, B L L H L H

Write Bytes D, B, A L L H L L

Write Bytes D, C L L L H H

Write Bytes D, C, A L L L H L

Write Bytes D, C, B L L L L H

Write All Bytes L L L L L

Note:

9. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done on which byte write is active.

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Snooze mode standby current ZZ > VDD − 0.2V 40 mA

tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ active to snooze current This parameter is sampled 2tCYC ns

tRZZI ZZ inactive to exit snooze current This parameter is sampled 0 ns

CY7C1350F

Document #: 38-05305 Rev. *A Page 8 of 16

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ..................................... −65°C to +150°C

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V

DC Voltage Applied to Outputs

in Three-State ..........................................−0.5V to VDDQ + 0.5V

DC Input Voltage ....................................... −0.5V to VDD + 0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.................................................... >200 mA

Operating Range

Range

Ambient

Temperature (TA) VDD VDDQ

Com’l 0°C to +70°C 3.3V - 5%/+10% 2.5V - 5%

to VDD

Ind’l −40°C to +85°C

Electrical Characteristics Over the Operating Range[10, 11]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage 2.375 VDD V

VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V

VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA 2.0 V

VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V

VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V

VIH Input HIGH Voltage[10] VDDQ = 3.3V 2.0 VDD + 0.3V V

VDDQ = 2.5V 1.7 VDD + 0.3V V

VIL Input LOW Voltage[10] VDDQ = 3.3V –0.3 0.8 V

VDDQ = 2.5V –0.3 0.7 V

IXInput Load Current

except ZZ and MODE

GND ≤ VI ≤ VDDQ −5 5 µA

Input Current of MODE Input = VSS −30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS −5µA

Input = VDD 30 µA

IOZ Output Leakage

Current

GND ≤ VI ≤ VDDQ, Output Disabled −5 5 µA

IDD VDD Operating Supply

Current

VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC

4-ns cycle, 250 MHz 325 mA

4.4-ns cycle, 225 MHz 290 mA

5-ns cycle, 200 MHz 265 mA

6-ns cycle, 166 MHz 240 mA

7.5-ns cycle, 133 MHz 225 mA

10-ns cycle, 100MHz 205 mA

ISB1 Automatic CE

Power-Down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/tCYC

4-ns cycle, 250 MHz 120 mA

4.4-ns cycle, 225 MHz 115 mA

5-ns cycle, 200 MHz 110 mA

6-ns cycle, 166 MHz 100 mA

7.5-ns cycle, 133 MHz 90 mA

10-ns cycle, 100 MHz 80 mA

Shaded areas contain advance information.

Notes:

10. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).

11. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

CY7C1350F

Document #: 38-05305 Rev. *A Page 9 of 16

ISB2 Automatic CE

Power-Down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

f = 0

All speeds 40 mA

ISB3 Automatic CE

Power-Down

Current—CMOS Inputs

VDD = Max, Device Deselected, or

VIN ≤ 0.3V or VIN > VDDQ – 0.3V

f = fMAX = 1/tCYC

4-ns cycle, 250 MHz 105 mA

4.4-ns cycle, 225 MHz 100 mA

5-ns cycle, 200 MHz 95 mA

6-ns cycle, 166 MHz 85 mA

7.5-ns cycle, 133 MHz 75 mA

10-ns cycle, 100 MHz 65 mA

ISB4 Automatic CE

Power-Down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0

All speeds 45 mA

AC Test Loads and Waveforms

Electrical Characteristics Over the Operating Range[10, 11](continued)

Parameter Description Test Conditions Min. Max. Unit

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDD

GND

90%

10%

90%

10%

≤1 ns ≤1 ns

(c)

OUTPUT

R = 1667Ω

R =1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VL= 1.25V

2.5V ALL INPUT PULSES

VDD

GND

90%

10%

90%

10%

≤1 ns ≤1 ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

Thermal Resistance[12]

Parameter Description Test Conditions

TQFP

Package

BGA

Package Units

ΘJA Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test methods

and procedures for measuring thermal imped-

ance, per EIA / JESD51.

41.83 47.63 °C/W

ΘJC Thermal Resistance

(Junction to Case)

9.99 11.71 °C/W

Capacitance[12]

Parameter Description Test Conditions

TQFP

Package

BGA

Package Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V, VDDQ = 3.3V

5 5 pF

CI/O Input/Output Capacitance 5 7 pF

Note:

12. Tested initially and after any design or process changes that may affect these parameters.

CY7C1350F

Document #: 38-05305 Rev. *A Page 10 of 16

Switching Characteristics Over the Operating Range[17, 18]

250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

tPOWER VDD (typical) to the first

Access[13] 1 1 1 1 11ms

Clock

tCYC Clock Cycle Time 4.0 4.4 5.0 6.0 7.5 10 ns

tCH Clock HIGH 1.7 2.0 2.0 2.5 3.0 3.5 ns

tCL Clock LOW 1.7 2.0 2.0 2.5 3.0 3.5 ns

Output Times

tCO Data Output Valid After CLK

Rise

2.6 2.6 2.8 3.5 4.0 4.5 ns

tDOH Data Output Hold After CLK

Rise

1.0 1.0 1.0 2.0 2.0 2.0 ns

tCLZ Clock to Low-Z[14, 15, 16] 0 0 0 0 0 0 ns

tCHZ Clock to High-Z[14, 15, 16] 2.6 2.6 2.8 3.5 4.0 4.5 ns

tOEV OE LOW to Output Valid 2.6 2.6 2.8 3.5 4.0 4.5 ns

tOELZ OE LOW to Output

Low-Z[14, 15, 16]

0 0 0 0 0 0 ns

tOEHZ OE HIGH to Output

High-Z[14, 15, 16]

2.6 2.6 2.8 3.5 4.0 4.5 ns

Set-up Times

tAS Address Set-up Before CLK

Rise

0.8 1.2 1.2 1.5 1.5 1.5 ns

tALS ADV/LD Set-up Before CLK

Rise

0.8 1.2 1.2 1.5 1.5 1.5 ns

tWES GW, BW[A:D] Set-Up Before

CLK Rise

0.8 1.2 1.2 1.5 1.5 1.5 ns

tCENS CEN Set-up Before CLK Rise 0.8 1.2 1.2 1.5 1.5 1.5 ns

tDS Data Input Set-up Before CLK

Rise

0.8 1.2 1.2 1.5 1.5 1.5 ns

tCES Chip Enable Set-Up Before

CLK Rise

0.8 1.2 1.2 1.5 1.5 1.5 ns

Hold Times

tAH Address Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns

tALH ADV/LD Hold after CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns

tWEH GW, BW[A:D] Hold After CLK

Rise

0.4 0.5 0.5 0.5 0.5 0.5 ns

tCENH CEN Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns

tDH Data Input Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns

tCEH Chip Enable Hold After CLK

Rise

0.4 0.5 0.5 0.5 0.5 0.5 ns

Shaded areas contain advance information.

Notes:

13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation

can be initiated.

14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve Three-state prior to Low-Z under the same system conditions

16. This parameter is sampled and not 100% tested.

17. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

18. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

CY7C1350F

Document #: 38-05305 Rev. *A Page 11 of 16

Switching Waveforms

Read/Write Timing[19, 20, 21]

Notes:

19. For this waveform ZZ is tied LOW.

20. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

21. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

WRITE

D(A1)

123456789

CLK

tCYC

tCL

tCH

tCEH

tCES

CEN

tCENH

tCENS

[A:D]

ADV/LD

tAH

tAS

ADDRESS A1 A2 A3 A4 A5 A6 A7

tDH

tDS

Data

n-Out (DQ)

tCLZ

D(A1) D(A2) D(A5)Q(A4)Q(A3)

D(A2+1)

tDOH tCHZ

tCO

WRITE

D(A2) BURST

WRITE

D(A2+1)

READ

Q(A3) READ

Q(A4) BURST

READ

Q(A4+1)

WRITE

D(A5) READ

Q(A6) WRITE

D(A7) DESELECT

tOEV

tOELZ

tOEHZ tDOH

DON’T CARE UNDEFINED

Q(A6)

Q(A4+1)

CY7C1350F

Document #: 38-05305 Rev. *A Page 12 of 16

NOP, STALL, and DESELECT Cycles[19, 20, 22]

ZZ Mode Timing[23, 24]

Notes:

22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.

23. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

24. DQs are in high-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

READ

Q(A3)

45678910

CLK

CEN

[A:D]

ADV/LD

ADDRESS A3 A4 A5

D(A4)

Data

In-Out (DQ)

Q(A5)

WRITE

D(A4) STALLWRITE

D(A1)

123

READ

Q(A2) STALL NOP READ

Q(A5) DESELECT CONTINUE

DESELECT

DON’T CARE UNDEFINED

CHZ

D(A1) Q(A2) Q(A3)

tZZ

ISUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q) High-Z

DESELECT or READ Only

CY7C1350F

Document #: 38-05305 Rev. *A Page 13 of 16

Shaded areas contain advance information.

Please contact your local Cypress sales representative to order parts that are not listed in the ordering information table.

Ordering Information

Speed

(MHz) Ordering Code

Package

Name Package Type

Operating

Range

250 CY7C1350F-250AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial

CY7C1350F-250BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)

CY7C1350F-250AI A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Industrial

CY7C1350F-250BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)

225 CY7C1350F-225AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial

CY7C1350F-225BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)

CY7C1350F-225AI A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Industrial

CY7C1350F-225BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)

200 CY7C1350F-200AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial

CY7C1350F-200BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)

CY7C1350F-200AI A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Industrial

CY7C1350F-200BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)

166 CY7C1350F-166AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial

CY7C1350F-166BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)

CY7C1350F-166AI A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Industrial

CY7C1350F-166BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)

133 CY7C1350F-133AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial

CY7C1350F-133BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)

CY7C1350F-133AI A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Industrial

CY7C1350F-133BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)

100 CY7C1350F-100AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial

CY7C1350F-100BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)

CY7C1350F-100AI A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Industrial

CY7C1350F-100BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)

CY7C1350F

Document #: 38-05305 Rev. *A Page 14 of 16

Package Diagram

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-*A

CY7C1350F

Document #: 38-05305 Rev. *A Page 15 of 16

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

All product and company names mentioned in this document may be the trademarks of their respective holders.

Package Diagram

51-85115-*B

119-Lead BGA (14 x 22 x 2.4 mm) BG119

CY7C1350F

Document #: 38-05305 Rev. *A Page 16 of 16

Document History Page

Document Title: CY7C1350F 4-Mb (128K x 36) Pipelined SRAM with Nobl™ Architecture

Document Number: 38-05305

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 119828 12/11/02 HGK New Data Sheet

*A 200662 See ECN REF Final Data Sheet