74LVT573PW/AUJ - NXP Semiconductors

1. General description

The 74LVT573 is a high-performance BiCMOS product designed for VCC operation at

3.3 V. This device is an oct al transpare nt latch coupled to eight 3-st ate output buf fers. The

two sections of the de vic e ar e con tr olle d independently by Latch Enable (LE) and Output

Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to

facilitate PC board layout and allow easy interface with microprocessors.

The dat a on the Dn inputs are transferred to the latch output s when the Latch Enab le (LE)

input is High. The latch remains transparent to the data input s while LE is High, and stores

the data that is present one setup time before the High-to-Low enable transition.

The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS

memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all

eight 3-state buffers independent of the latch operation.

When OE is Low, the latched or transparent data appears at the outputs. When OE is

High, the outputs are in the High-impedance “OFF” state, which means they will neither

drive nor load the bus.

2. Features and benefits

Inputs and outputs arranged for easy interfacing to microprocessors

3-state outputs for bus interfacing

Common output enable control

TTL input and output switching levels

Input and output interface capability to systems at 5 V supply

Bus hold data in put s elimina te need for external pull- up resistors to ho ld unused inpu t s

Live insertion an d ex tra ct i on perm i tte d

No bus current loading when output is tied to 5 V bus

Power-up reset

Power-up 3-state

Latch-up protection

JESD78 class II exceeds 500 mA

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115 -A ex ce eds 20 0 V

Specified from 40 C to +85 C

74LVT573

3.3 V octal D-type transparent latch; 3-state

Rev. 8 — 22 November 2011 Product data sheet

Product data sheet Rev. 8 — 22 November 2011 2 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Temperatur e ra nge Name Description Version

74LVT573D 40 C to +85 C SO20 plastic small outline package; 20 leads;

body width 7.5 mm SOT163-1

74LVT573DB 40 C to +85 C SSOP20 plastic shrink small outline package; 20 leads;

body width 5.3 mm SOT339-1

74LVT573PW 40 C to +85 C TSSOP20 plastic thin shrink small outline package; 20 leads;

body width 4.4 mm SOT360-1

74LVT573BQ 40 Cto+85C DHVQFN20 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 20 terminals;

body 2.5 4.5 0.85 mm

SOT764-1

Fig 1. Logic symbol Fig 2. IEC logic symbol

mna807

D7 LE

OE Q0

mna808

11 C1

1EN1

1D 19

Product data sheet Rev. 8 — 22 November 2011 3 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

5. Pinning information

5.1 Pinning

Fig 3. Logic diagra m

mna810

LELELE

LATCH

1LATCH

2LATCH

3LATCH

4LATCH

LE LE LE LE

LATCH

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as a

supply pin or input.

Fig 4. Pin configuration for SO20 and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20

74LVT573

OE VCC

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

GND LE

001aah713

001aah712

74LVT573

Transparent top view

D5 Q5

D4 Q4

D3 Q3

D2 Q2

GND(1)

D1 Q1

D0 Q0

GND

VCC

912

813

714

615

516

417

318

219

terminal 1

index area

Product data sheet Rev. 8 — 22 November 2011 4 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

5.2 Pin description

6. Functional description

6.1 Function table

[1] H = HIGH voltage level;

L = LOW voltage level;

 = HIGH-to-LOW latch enable transition;

h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition;

l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition;

Z = high-impedance OFF-state;

NC = no change;

X = don’t care.

7. Limiting values

Table 2. Pin description

Symbol Pin Description

OE 1 output enable input (active LOW )

D0 to D7 2, 3, 4, 5, 6, 7, 8, 9 data input

GND 10 ground (0 V)

LE 11 latch enable (active HIGH)

Q0 to Q7 19, 18, 17, 16, 15, 14, 13, 12 data output

VCC 20 supply voltage

Table 3. Function table [1]

Operating mode Control OE Control LE Input Dn Internal register Output Qn

Load and read register

enable LHLLL

HHH

Latch and read register L lLL

hHH

Hold L L X NC NC

Disable outputs H L X NC Z

HDnDnZ

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +4.6 V

VIinput voltage [1] 0.5 +7.0 V

VOoutput voltage output in OFF-state or HIGH-state [1] 0.5 +7.0 V

IIK input clamping current VI<0V - 50 mA

IOK output clamping current VO<0V - 50 mA

IOoutput current output in LOW-state - 128 mA

output in HIGH-state - 64 mA

Product data sheet Rev. 8 — 22 November 2011 5 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability.

[3] For SO20 packages: above 70 C derate linearly with 8 mW/K.

For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K.

For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K.

8. Recommended operating conditions

9. Static characteristics

Tstg storage temperature 65 +150 C

Tjjunction temperature [2] - 150 C

Ptot total power dissipation Tamb = 40 C to +85 C[3] - 500 mW

Table 4. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 2.7 - 3.6 V

VIinput voltage 0 - 5.5 V

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8 V

IOH HIGH-level output current - - 32 mA

IOL LOW-level output current - - 32 mA

current duty cycle 50 %; fi1kHz--64mA

Tamb ambient temperature in free air 40 - +85 C

t/V input transition rise and fall rate outputs enabled - - 10 ns/V

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Tamb =40 C to +85 CUnit

Min Typ[1] Max

VIK input clamping voltage VCC = 2.7 V; IIK =18 mA 1.2 0.9 - V

VOH HIGH-level output voltage VCC = 2.7 V to 3.6 V;

IOH =100 AVCC  0.2 VCC  0.1 - V

VCC = 2.7 V; IOH =8mA 2.4 2.5 - V

VCC = 3.0 V; IOH =32 mA 2.0 2.2 - V

VOL LOW-level output voltage VCC = 2.7 V; IOL =100A-0.10.2V

VCC = 2.7 V; IOL =24mA - 0.3 0.5 V

VCC = 3.0 V IOL = 16 mA - 0.25 0.4 V

VCC = 3.0 V IOL =32mA - 0.3 0.5 V

VCC = 3.0 V IOL =64mA - 0.4 0.55 V

VOL(pu) power-up LOW-level

output voltage VCC = 3.6 V; IO=1mA;

VI=GNDorV

[2] - 0.13 0.55 V

Product data sheet Rev. 8 — 22 November 2011 6 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

[1] Typical values are measured at VCC = 3.3 V and Tamb = 25 C.

[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.

[3] Unused pins at VCC or GND.

[4] This is the bus hold overdrive current required to force the input to the opposite logic state.

[5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC =3.3 V 0.3 V

a transition time of 100 s is permitted. This parameter is valid for Tamb =25C only.

[6] ICC is measured with outputs pulled to VCC or GND.

[7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.

IIinput leakage current all input pins;

VCC = 0 V or 3.6 V; VI=5.5V - 1 10 A

control pins;

VCC = 3.6 V; VCC or GND - 0.1 1A

data pins

VCC = 3.6 V; VI=V

CC [3] -0.11A

VCC = 3.6 V; VI=0V 51-A

IOFF power-off leakage current VCC = 0 V; V I or VO= 0 V to 4.5 V - 1 100 A

IBHL bus hold LOW current Dn input; VCC = 3 V; VI=0.8V [4] 75 150 - A

IBHH bus hold HIGH current Dn input; VCC = 3 V; VI=2.0V - 150 75 A

IBHHO bus hold HIGH overdrive current Dn input; VCC = 3.6; VI = 0 V to

3.6 V [4] --500A

IBHLO bus hold LOW overdrive current Dn input; VCC = 3.6; VI = 0 V to

3.6 V 500 - - A

ILO output leakage current Qn output HIGH when

VO= 5.5 Vand VCC =3.0V -60125A

IO(pu/pd) power-up/power-down

output current VCC 1.2 V; VO=0.5Vto V

CC;

VI=GNDorV

CC; OE = don’t care [5] -1100 A

IOZ OFF-state output current VCC = 3.6 V; VI=V

IH or VIL

output HIGH: VO=3.0V - 1 5 A

output LOW: VO=0.5V 51-A

ICC supply current VCC = 3.6 V; VI=GNDorV

CC;

IO=0A

outputs HIGH - 0.13 0.19 mA

outputs LOW - 3 12 mA

outputs disabled [6] - 0.13 0.19 mA

ICC additional supply current per input pin; VCC = 3 V to 3.6 V;

one input at VCC 0.6 V and other

inputs at VCC or GND

[7] -0.10.2mA

CIinput capacitance VI = 0 V or 3.0 V - 4 - p F

COoutput capacitance outputs disabled; VO= 0 V or 3.0 V - 8 - pF

Table 6. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Tamb =40 C to +85 CUnit

Min Typ[1] Max

Product data sheet Rev. 8 — 22 November 2011 7 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

10. Dynamic characteristics

[1] Typical values are at VCC = 3.3 V and Tamb =25 C.

[2] tsu is the same as tsu(L) and tsu(H).

[3] th is the same as th(L) and th(H).

[4] tW is the same as tWL and tWH.

Table 7. Dy namic characteristics

Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 11.

Symbol Parameter Conditions Tamb =40 C to +85 CUnit

Min Typ[1] Max

tPLH LOW to HIGH

propagation delay LE to Qn; see Figure 6

VCC = 3.0 V to 3.6 V 1.6 3.5 5.6 ns

VCC = 2.7 V - - 6.3 ns

Dn to Qn; see Figure 7

VCC = 3.0 V to 3.6 V 1.0 2.5 4.2 ns

VCC = 2.7 V - - 4.7 ns

tPHL HIGH to LOW

propagation delay LE to Qn; see Figure 6

VCC = 3.0 V to 3.6 V 2.5 4.3 6.5 ns

VCC = 2.7 V - - 7.2 ns

Dn to Qn; see Figure 7

VCC = 3.0 V to 3.6 V 1.0 2.7 4.3 ns

VCC = 2.7 V - - 5.2 ns

tPZH OFF-state to HIGH

propagation delay OE to Qn; see Figure 8

VCC = 3.0 V to 3.6 V 1.0 2.8 5.1 ns

VCC = 2.7 V - - 6.2 ns

tPZL OFF-state to LOW

propagation delay OE to Qn; see Figure 9

VCC = 3.0 V to 3.6 V 1.3 3.3 5.5 ns

VCC = 2.7 V - - 6.6 ns

tPHZ HIGH to OFF-state

propagation delay OE to Qn; see Figure 8

VCC = 3.0 V to 3.6 V 2.0 3.7 5.7 ns

VCC = 2.7 V - - 6.7 ns

tPLZ LOW to OFF-state

propagation delay OE to Qn; see Figure 9

VCC = 3.0 V to 3.6 V 1.5 3.0 4.6 ns

VCC = 2.7 V - - 5.1 ns

tsu set-up time Dn to LE; see Figure 10 [2]

VCC = 3.0 V to 3.6 V 0.7 - - ns

VCC =2.7V 0.6 - - ns

thhold time Dn to LE; see Figure 10 [3]

VCC = 3.0 V to 3.6 V 1.6 - - ns

VCC =2.7V 1.8 - - ns

tWpulse width LE input HIGH; see Figure 6 [4]

VCC = 3.0 V to 3.6 V 3.3 - - ns

VCC =2.7V 3.3 - - ns

Product data sheet Rev. 8 — 22 November 2011 8 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

11. Waveforms

Measurement points are given in Table 8. Measurement points are given in Table 8.

Fig 6. Propagation delays latch enable input (LE) to

output (Qn), and latch enable (LE) pulse width Fig 7. Propagation delay data input (Dn) to

output (Qn)

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur

with the output load.

Measurement points are given in Table 8.

Fig 8. Output enable time to HIGH-state and output

disable time fr om HIGH-state Fig 9. Output enable time to LOW-state and outp ut

disable time from LOW-state

Measurement points are given in Table 8.

Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 10. Data setup and hold times for data (Dn) and latch enable (LE) inputs

001aai743

LE input

Qn output

PHL

PLH

0 V

001aai742

Dn input

Qn output

PHL

PLH

0 V

Qn output

001aai745

OE input VM

VOH

0 V

0 V tPZH tPHZ

001aai746

tPZL tPLZ

Qn output

OE input

VOL

3.0 V

0 V

001aai744

th(L)

tsu(L)

th(H)

tsu(H)

0 V

LE input

Dn input

Table 8. Measurement points

Input Output

VMVMVXVY

1.5V 1.5V V

OL + 0.3 V VOH  0.3 V

Product data sheet Rev. 8 — 22 November 2011 9 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

Test data is given in Table 9.

Definitions test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = Test voltage for switching times.

Fig 11. Test circuitry for switching times

VEXT

VCC

VIVO

001aae235

DUT

PULSE

GENERATOR

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

Table 9. Test data

Input Load VEXT

VIfitWtr, tfCLRLtPHZ, tPZH tPLZ, tPZL tPLH, tPHL

2.7 V  10 MHz 500 ns  2.5 ns 50 pF 500 GND 6 V open

Product data sheet Rev. 8 — 22 November 2011 10 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

12. Package outline

Fig 12. Package outline SOT163-1 (SO20)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 13.0

12.6 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT163-1

detail X

0.25

075E04 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.51

0.49 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

vMA

(A )

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

99-12-27

03-02-19

Product data sheet Rev. 8 — 22 November 2011 11 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

Fig 13. Package outline SOT339-1 (SSOP20)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQ(1)

Zywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.38

0.25 0.20

0.09 7.4

7.0 5.4

5.2 0.65 7.9

7.6 0.9

0.7 0.9

0.5 8

0.131.25 0.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

1.03

0.63

SOT339-1 MO-150 99-12-27

03-02-19

detail X

vMA

(A )

110

20 11

0.25

pin 1 index

0 2.5 5 mm

scale

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

max.

Product data sheet Rev. 8 — 22 November 2011 12 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

Fig 14. Package outline SOT360-1 (TSSOP20)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 6.6

6.4 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.5

0.2 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT360-1 MO-153 99-12-27

03-02-19

0.25

110

20 11

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

max.

1.1

Product data sheet Rev. 8 — 22 November 2011 13 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

Fig 15. Package outline SOT764-1 (DHVQFN20)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.6

4.4

3.15

2.85

2.6

2.4 1.15

0.85

3.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT764-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT764-1

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

19 12

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Product data sheet Rev. 8 — 22 November 2011 14 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

BiCMOS Bipolar Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVT573 v.8 20111122 Product data sheet - 74LVT573 v.7

Modifications: •Legal pages updated.

74LVT573 v.7 20110912 Product data sheet - 74LVT573 v.6

74LVT573 v.6 20110727 Product data sheet - 74LVT573 v.5

74LVT573 v.5 20110629 Product data sheet - 74LVT573 v.4

74LVT573 v.4 20080915 Product data sheet - 74LVT573 v.3

74LVT573 v.3 20011217 Product data sheet - 74LVT573 v.2

74LVT573 v.2 19980219 Product specification - -

Product data sheet Rev. 8 — 22 November 2011 15 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

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internal review and subject to formal approval, which may result in

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with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

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data sheet shall define the specification of the product as agreed between

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Product data sheet.

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safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for an y of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer pr oduct

design. It is customer’s sole re sponsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applicat ions and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly object s to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from competent authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the obj ective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 8 — 22 November 2011 16 of 17

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74LVT573

3.3 V octal D-type transparent latch; 3-state

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of rele ase: 22 Novemb er 2011

Document identifier: 74LVT573

Please be aware that important notices concerning this document and the product(s)

described herei n, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 4

6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

16 Contact information. . . . . . . . . . . . . . . . . . . . . 16

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Mouser Electronics

Authorized Distributor

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