Ultra37000 CPLD Family 5V, 3.3V, ISRTM High-Performance CPLDs Features General Description * In-System ReprogrammableTM (ISRTM) CMOS CPLDs -- JTAG interface for reconfigurability -- Design changes do not cause pinout changes -- Design changes do not cause timing changes * High density -- 32 to 512 macrocells -- 32 to 264 I/O pins -- Five dedicated inputs including four clock pins * Simple timing model -- No fanout delays -- No expander delays -- No dedicated vs. I/O pin delays -- No additional delay through PIM -- No penalty for using full 16 product terms -- No delay for steering or sharing product terms * 3.3V and 5V versions * PCI-compatible[1] * Programmable bus-hold capabilities on all I/Os * Intelligent product term allocator provides: -- 0 to 16 product terms to any macrocell -- Product term steering on an individual basis -- Product term sharing among local macrocells * Flexible clocking -- Four synchronous clocks per device -- Product term clocking -- Clock polarity control per logic block * Consistent package/pinout offering across all densities The Ultra37000TM family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs. All of the Ultra37000 devices are electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins, respectively. Because of the superior routability and simple timing model of the Ultra37000 devices, ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance. The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37000 family features user programmable bus-hold capabilities on all I/Os. Ultra37000 5.0V Devices The Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. VCCO connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the VCCO pins to 5V the user insures 5V TTL levels on the outputs. If VCCO is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming. -- Simplifies design migration Ultra37000V 3.3V Devices -- Same pinout for 3.3V and 5.0V devices Devices operating with a 3.3V supply require 3.3V on all VCCO pins, reducing the device's power consumption. These devices support 3.3V JEDEC standard CMOS output levels, and are 5V-tolerant. These devices allow 3.3V ISR programming. * Packages -- 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages -- Lead (Pb)-free packages available Note: 1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V. Cypress Semiconductor Corporation Document #: 38-03007 Rev. *E * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised March 7, 2004 [+] Feedback Ultra37000 CPLD Family Selection Guide 5.0V Selection Guide General Information Speed (tPD) I/O Pins Speed (fMAX) Device Macrocells Dedicated Inputs CY37032 32 5 32 6 200 CY37064 64 5 32/64 6 200 CY37128 128 5 64/128 6.5 167 CY37192 192 5 120 7.5 154 CY37256 256 5 128/160/192 7.5 154 CY37384 384 5 160/192 10 118 CY37512 512 5 160/192/264 10 118 Speed Bins Device 200 167 CY37032 X X X CY37064 X X X CY37128 154 143 125 X 100 X 83 66 X CY37192 X X X CY37256 X X X CY37384 X X CY37512 X X X Device-Package Offering and I/O Count Device 44Lead TQFP 44Lead PLCC CY37032 37 37 CY37064 37 37 44Lead CLCC 84Lead PLCC 37 69 CY37128 84Lead CLCC 100Lead TQFP 160Lead TQFP 160Lead CQFP 208Lead PQFP 133 208Lead CQFP 292Lead PBGA 388Lead PBGA 69 69 69 69 133 CY37192 125 CY37256 133 165 197 CY37384 165 197 CY37512 165 165 197 269 3.3V Selection Guide General Information Device Macrocells Dedicated Inputs I/O Pins Speed (tPD) Speed (fMAX) CY37032V 32 5 32 8.5 143 CY37064V 64 5 32/64 8.5 143 CY37128V 128 5 64/80/128 10 125 CY37192V 192 5 120 12 100 CY37256V 256 5 128/160/192 12 100 CY37384V 384 5 160/192 15 83 CY37512V 512 5 160/192/264 15 83 Document #: 38-03007 Rev. *E Page 2 of 64 [+] Feedback Ultra37000 CPLD Family Speed Bins Device 200 167 154 143 CY37032V X CY37064V X 125 100 83 66 X X CY37128V X X CY37192V X X CY37256V X X CY37384V X X CY37512V X X CY37032V 37 CY37064V 37 400Lead FBGA Device 44Lead TQFP 44Lead CLCC 48Lead FBGA 84Lead CLCC 100Lead TQFP 100Lead FBGA 160Lead TQFP 160Lead CQFP 208Lead PQFP 208Lead CQFP 292Lead PBGA 256Lead FBGA 388Lead PBGA Device-Package Offering and I/O Count 37 37 37 CY37128V 69 69 69 69 85 133 CY37192V 125 CY37256V 133 165 197 CY37384V 165 197 CY37512V 165 Architecture Overview of Ultra37000 Family Programmable Interconnect Matrix The PIM consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations. The inputs to the PIM consist of all I/O and dedicated input pins and all macrocell feedbacks from within the logic blocks. The number of PIM inputs increases with pin count and the number of logic blocks. The outputs from the PIM are signals routed to the appropriate logic blocks. Each logic block receives 36 inputs from the PIM and their complements, allowing for 32-bit operations to be implemented in a single pass through the device. The wide number of inputs to the logic block also improves the routing capacity of the Ultra37000 family. An important feature of the PIM is its simple timing. The propagation delay through the PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM. In fact, all inputs travel through the PIM. As a result, there are no route-dependent timing parameters on the Ultra37000 devices. The worst-case PIM delays are incorporated in all appropriate Ultra37000 specifications. Routing signals through the PIM is completely invisible to the user. All routing is accomplished by software--no hand routing is necessary. Warp(R) and third-party development packages automatically route designs for the Ultra37000 family in a matter of minutes. Finally, the rich routing resources of the Ultra37000 family accommodate last minute logic changes while maintaining fixed pin assignments. Document #: 38-03007 Rev. *E 133 165 197 197 269 269 Logic Block The logic block is the basic building block of the Ultra37000 architecture. It consists of a product term array, an intelligent product-term allocator, 16 macrocells, and a number of I/O cells. The number of I/O cells varies depending on the device used. Refer to Figure 1 for the block diagram. Product Term Array Each logic block features a 72 x 87 programmable product term array. This array accepts 36 inputs from the PIM, which originate from macrocell feedbacks and device pins. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 87 product terms in the array can be created from any of the 72 inputs. Of the 87 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Four of the remaining seven product terms in the logic block are output enable (OE) product terms. Each of the OE product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. In other words, each I/O cell can select between one of two OE product terms to control the output buffer. The first two of these four OE product terms are available to the upper half of the I/O macrocells in a logic block. The other two OE product terms are available to the lower half of the I/O macrocells in a logic block. The next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. The final product term is the product term clock. The set, reset, OE and product term clock have polarity control to realize OR functions in a single pass through the array. Page 3 of 64 [+] Feedback Ultra37000 CPLD Family 2 3 0-16 PRODUCT TERMS 7 0-16 PRODUCT TERMS FROM PIM 36 72 x 87 PRODUCT TERM ARRAY 80 MACROCELL 1 I/O CELL 0 to cells 2, 4, 6 8, 10, 12 PRODUCT TERM ALLOCATOR 0-16 PRODUCT TERMS 0-16 TO PIM MACROCELL 0 2 16 PRODUCT TERMS MACROCELL 14 I/O CELL 14 MACROCELL 15 8 Figure 1. Logic Block with 50% Buried Macrocells Low-Power Option Each logic block can operate in high-speed mode for critical path performance, or in low-power mode for power conservation. The logic block mode is set by the user on a logic block by logic block basis. Product Term Allocator Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing. Product Term Steering Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will "steer" ten product terms to one macrocell and three to the other. On Ultra37000 devices, product terms are steered on an individual basis. Any number between 0 and 16 product terms can be steered to any macrocell. Note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register. Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. The Ultra37000 product term allocator allows sharing across groups of four output macrocells in a Document #: 38-03007 Rev. *E variable fashion. The software automatically takes advantage of this capability--the user does not have to intervene. Note that neither product term sharing nor product term steering have any effect on the speed of the product. All worst-case steering and sharing configurations have been incorporated in the timing specifications for the Ultra37000 devices. Ultra37000 Macrocell Within each logic block there are 16 macrocells. Macrocells can either be I/O Macrocells, which include an I/O Cell which is associated with an I/O pin, or buried Macrocells, which do not connect to an I/O. The combination of I/O Macrocells and buried Macrocells varies from device to device. Buried Macrocell Figure 2 displays the architecture of buried macrocells. The buried macrocell features a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch. The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be set or reset based on an AND expression or an OR expression. Clocking of the register is very flexible. Four global synchronous clocks and a product term clock are available to clock the register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling as well as rising edges (see the Clocking section). Clock polarity is chosen at the logic block level. Page 4 of 64 [+] Feedback Ultra37000 CPLD Family Bus Hold Capabilities on all I/Os The buried macrocell also supports input register capability. The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. For more information, see the application note Understanding Bus-Hold--A Feature of Cypress CPLDs. I/O Macrocell Figure 2 illustrates the architecture of the I/O macrocell. The I/O macrocell supports the same functions as the buried macrocell with the addition of I/O capability. At the output of the macrocell, a polarity control mux is available to select active LOW or active HIGH signals. This has the added advantage of allowing significant logic reduction to occur in many applications. Programmable Slew Rate Control Each output has a programmable configuration bit, which sets the output slew rate to fast or slow. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance. The Ultra37000 macrocell features a feedback path to the PIM separate from the I/O pin input path. This means that if the macrocell is buried (fed back internally only), the associated I/O pin can still be used as an input. I/O MACROCELL FROM PTM FAST 0 1 0-16 PRODUCT TERMS SLEW SLOW C25 P D/T/L 0 1 2 3 C26 0 O O 0 1 Q 1 R 4 C4 DECODE C0 C1 C24 I/O CELL O "0" "1" 0 1 2 3 O C6 C5 1 0 C2 C3 BURIED MACROCELL FROM PTM 0-16 0 1 PRODUCT TERMS C25 0 0 0 1 2 3 O 1 P D/T/L C7 Q R 4 C0 C1 C24 O 1 Q DECODE 1 0 C2 C3 FEEDBACK TO PIM FEEDBACK TO PIM FEEDBACK TO PIM ASYNCHRONOUS BLOCK RESET 4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3) ASYNCHRONOUS 1 ASYNCHRONOUS CLOCK(PTCLK) BLOCK PRESET OE0 OE1 Figure 2. I/O and Buried Macrocells Document #: 38-03007 Rev. *E Page 5 of 64 [+] Feedback Ultra37000 CPLD Family INPUT PIN D 0 1 2 3 FROM CLOCK POLARITY MUXES D Q 0 1 2 3 Q O TO PIM O C12 C13 C10 C11 D Q LE Figure 3. Input Macrocell 0 TO CLOCK MUX ON ALL INPUT MACROCELLS O 1 INPUT/CLOCK PIN C12 0 O 1 FROM CLOCK POLARITY INPUT CLOCK PINS D 0 1 2 3 Q D Q C13, C14, C15 0 1 2 3 O TO PIM O TO CLOCK MUX IN EACH LOGIC BLOCK OR C16 CLOCK POLARITY MUX ONE PER LOGIC BLOCK FOR EACH CLOCK INPUT C10C11 C8 C9 D Q LE Figure 4. Input/Clock Macrocell Clocking Timing Model Each I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchronous product term clock PTCLK. Each input macrocell has access to all four synchronous clocks. One of the most important features of the Ultra37000 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure 5 illustrates the true timing model for the 167-MHz devices in high speed mode. For combinatorial paths, any input to any output incurs a 6.5-ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input set-up time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. These measurements are for any output and synchronous clock, regardless of the logic used. Dedicated Inputs/Clocks Five pins on each member of the Ultra37000 family are designated as input-only. There are two types of dedicated inputs on Ultra37000 devices: input pins and input/clock pins. Figure 3 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered, double-registered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control. Figure 4 illustrates the architecture for the input/clock pins. Like the input pins, input/clock pins can be combinatorial, registered, double-registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock path at the input has user-configurable polarity. Product Term Clocking In addition to the four synchronous clocks, the Ultra37000 family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is available to all 16 macrocells. Each product term clock also supports user configurable polarity selection. Document #: 38-03007 Rev. *E The Ultra37000 features: * No fanout delays * No expander delays * No dedicated vs. I/O pin delays * No additional delay through PIM * No penalty for using 0-16 product terms * No added delay for steering product terms * No added delay for sharing product terms * No routing delays * No output bypass delays The simple timing model of the Ultra37000 family eliminates unexpected performance penalties. Page 6 of 64 [+] Feedback Ultra37000 CPLD Family resources for pinout flexibility, and a simple timing model for consistent system performance. COMBINATORIAL SIGNAL tPD = 6.5 ns INPUT OUTPUT Warp REGISTERED SIGNAL tS = 3.5 ns D,T,L O tCO = 4.5 ns INPUT OUTPUT CLOCK Figure 5. Timing Model for CY37128 JTAG and PCI Standards 5V operation of the Ultra37000 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The 3.3V products meet all PCI requirements except for the output 3.3V clamp, which is in direct conflict with 5V tolerance. The Ultra37000 family's simple and predictable timing model ensures compliance with the PCI AC specifications independent of the design. IEEE 1149.1-compliant JTAG The Ultra37000 family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR. Boundary Scan The Ultra37000 family supports Bypass, Sample/Preload, Extest, Idcode, and Usercode boundary scan instructions. The JTAG interface is shown in Figure 6. TCK TDO JTAG TAP CONTROLLER Bypass Reg. Boundary Scan idcode Usercode ISR Prog. Data Registers Figure 6. JTAG Interface In-System Reprogramming (ISR) In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins. The Ultra37000 family implements ISR by providing a JTAG compliant interface for on-board programming, robust routing Document #: 38-03007 Rev. *E Warp Professional contains several additional features. It provides an extra method of design entry with its graphical block diagram editor. It allows up to 5 ms timing simulation instead of only 2 ms. It allows comparison of waveforms before and after design changes. Warp EnterpriseTM Warp Enterprise provides even more features. It provides unlimited timing simulation and source-level behavioral simulation as well as a debugger. It has the ability to generate graphical HDL blocks from HDL text. It can even generate testbenches. Warp is available for PC and UNIX platforms. Some features are not available in the UNIX version. For further information see the Warp for PC, Warp for UNIX, Warp Professional and Warp Enterprise data sheets on Cypress's web site (www.cypress.com). Third-Party Software Instruction Register TMS Warp is a state-of-the-art compiler and complete CPLD design tool. For design entry, Warp provides an IEEE-STD-1076/1164 VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a graphical finite state machine editor. It provides optimized synthesis and fitting by replacing basic circuits with ones pre-optimized for the target device, by implementing logic in unused memory and by perfect communication between fitting and synthesis. To facilitate design and debugging, Warp provides graphical timing simulation and analysis. Warp ProfessionalTM PCI Compliance TDI Development Software Support Although Warp is a complete CPLD development tool on its own, it interfaces with nearly every third party EDA tool. All major third-party software vendors provide support for the Ultra37000 family of devices. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third-party vendors. Programming There are four programming options available for Ultra37000 devices. The first method is to use a PC with the 37000 UltraISR programming cable and software. With this method, the ISR pins of the Ultra37000 devices are routed to a connector at the edge of the printed circuit board. The 37000 UltraISR programming cable is then connected between the parallel port of the PC and this connector. A simple configuration file instructs the ISR software of the programming operations to be performed on each of the Ultra37000 devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish the programming, reading, verifying, and other ISR functions. For more information on the Cypress ISR Interface, see the ISR Programming Kit data sheet (CY3700i). The second method for programming Ultra37000 devices is on automatic test equipment (ATE). This is accomplished through a file created by the ISR software. Check the Cypress website for the latest ISR software download information. Page 7 of 64 [+] Feedback Ultra37000 CPLD Family The third programming option for Ultra37000 devices is to utilize the embedded controller or processor that already exists in the system. The Ultra37000 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be programmed. The embedded controller then simply directs this ISR stream to the chain of Ultra37000 devices to complete the desired reconfiguring or diagnostic operations. Contact your local sales office for information on availability of this option. Document #: 38-03007 Rev. *E The fourth method for programming Ultra37000 devices is to use the same programmer that is currently being used to program FLASH370i devices. For all pinout, electrical, and timing requirements, refer to device data sheets. For ISR cable and software specifications, refer to the UltraISR kit data sheet (CY3700i). Third-Party Programmers As with development software, Cypress support is available on a wide variety of third-party programmers. All major third-party programmers (including BP Micro, Data I/O, and SMS) support the Ultra37000 family. Page 8 of 64 [+] Feedback Ultra37000 CPLD Family Logic Block Diagrams CY37032/CY37032V Clock/ Input Input 1 TDI TCK TMS 4 36 LOGIC BLOCK A 16 I/Os I/O0-I/O15 36 PIM 16 16 16 LOGIC BLOCK B Input Clock/ Input 4 1 4 4 I/O0-I/O15 LOGIC BLOCK A LOGIC BLOCK B I/O16-I/O31 32 TDI TCK TMS JTAG Tap Controller Document #: 38-03007 Rev. *E 36 36 16 16 36 16 I/Os 16 I/Os I/O16-I/O31 16 CY37064/CY37064V 16 I/Os TDO JTAGEN 4 4 JTAG Tap Controller 16 PIM LOGIC BLOCK D 16 I/Os LOGIC BLOCK C 16 I/Os I/O48-I/O63 36 16 I/O32-I/O47 32 TDO Page 9 of 64 [+] Feedback Ultra37000 CPLD Family Logic Block Diagrams (continued) TDI CY37128/CY37128V CLOCK INPUTS INPUTS 1 4 I/O16-I/O31 I/O32-I/O47 I/O28-I/O63 16 I/Os LOGIC BLOCK 36 A 16 I/Os LOGIC BLOCK B 16 I/Os LOGIC BLOCK C 16 I/Os 36 PIM 16 LOGIC BLOCK D 36 36 16 16 36 36 16 16 36 36 16 16 16 I/Os LOGIC BLOCK 16 I/Os LOGIC BLOCK 16 I/Os LOGIC BLOCK 16 I/Os G I/O112-I/O127 I/O96-I/O111 I/O80-I/O95 F I/O64-I/O79 64 CY37192/CY37192V Input 1 Clock/ Input 4 4 4 JTAG Tap Controller LOGIC BLOCK E TDO JTAGEN H 16 64 TDI TCK TMS Controller TMS 4 INPUT/CLOCK MACROCELLS 4 INPUT MACROCELL I/O0-I/O15 JTAG Tap TCK 10 I/Os I/O0-I/O9 LOGIC BLOCK A 10 I/Os I/O10-I/O19 LOGIC BLOCK B 10 I/Os I/O20-I/O29 LOGIC BLOCK C 10 I/Os I/O30-I/O39 LOGIC BLOCK D 10 I/Os I/O40-I/O49 LOGIC BLOCK E 10 I/Os I/O50-I/O59 LOGIC BLOCK F 60 36 36 16 16 36 36 16 16 36 36 16 16 36 16 PIM 36 16 36 36 16 16 36 36 16 16 LOGIC BLOCK L 10 I/Os I/O110-I/O119 LOGIC BLOCK K 10 I/Os I/O100-I/O109 LOGIC BLOCK J 10 I/Os I/O90-I/O99 LOGIC BLOCK I 10 I/Os I/O80-I/O89 LOGIC BLOCK H 10 I/Os I/O70-I/O79 LOGIC BLOCK G 10 I/Os I/O60-I/O69 60 TDO Document #: 38-03007 Rev. *E Page 10 of 64 [+] Feedback Ultra37000 CPLD Family Logic Block Diagrams (continued) Clock/ Input Input CY37256/CY37256V 1 4 4 4 12 I/Os I/O0-I/O11 LOGIC BLOCK A 12 I/Os I/O12-I/O23 LOGIC BLOCK B 12 I/Os I/O24-I/O35 LOGIC BLOCK C 12 I/Os I/O36-I/O47 LOGIC BLOCK D 12 I/Os I/O48-I/O59 LOGIC BLOCK E 12 I/Os I/O60-I/O71 LOGIC BLOCK F 12 I/Os I/O72-I/O83 LOGIC BLOCK G 12 I/Os LOGIC BLOCK H I/O84-I/O95 TDI TCK TMS JTAG Tap Controller Document #: 38-03007 Rev. *E TDO 96 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 PIM 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 LOGIC BLOCK P 12 I/Os I/O180-I/O191 LOGIC BLOCK O 12 I/Os I/O168-I/O179 LOGIC BLOCK N 12 I/Os I/O156-I/O167 LOGIC BLOCK M 12 I/Os I/O144-I/O155 LOGIC BLOCK L 12 I/Os I/O132-I/O143 LOGIC BLOCK K 12 I/Os I/O120-I/O131 LOGIC BLOCK J 12 I/Os I/O108-I/O119 LOGIC BLOCK I 12 I/Os I/O96-I/O107 96 Page 11 of 64 [+] Feedback Ultra37000 CPLD Family Logic Block Diagrams (continued) Clock/ Input Input CY37384/CY37384V 1 4 4 4 12 I/Os I/O0-I/O11 LOGIC BLOCK AA 12 I/Os LOGIC BLOCK AB I/O12-I/O23 12 I/Os I/O24-I/O35 LOGIC BLOCK AC LOGIC BLOCK AD 12 I/Os I/O36-I/O47 LOGIC BLOCK AE 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 16 PIM 36 16 LOGIC BLOCK AF 36 36 16 16 12 I/Os I/O48-I/O59 LOGIC BLOCK AG 36 36 16 16 12 I/Os I/O60-I/O71 LOGIC BLOCK AH 12 I/Os LOGIC BLOCK AI I/O72-I/O83 LOGIC BLOCK AJ 12 I/Os I/O84-I/O95 LOGIC BLOCK AK LOGIC BLOCK AL TDI TCK TMS 36 JTAG Tap Controller Document #: 38-03007 Rev. *E TDO 96 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 LOGIC BLOCK BL LOGIC BLOCK BK 12 I/Os I/O168-I/O191 LOGIC BLOCK BJ 12 I/Os I/O156-I/O179 LOGIC BLOCK BI 12 I/Os I/O144-I/O167 LOGIC BLOCK BH LOGIC BLOCK BG 12 I/Os I/O132-I/O155 LOGIC BLOCK BF LOGIC BLOCK BE 12 I/Os I/O120-I/O143 LOGIC BLOCK BD 12 I/Os I/O108-I/O131 LOGIC BLOCK BC 12 I/Os I/O96-I/O119 LOGIC BLOCK BB LOGIC BLOCK BA 12 I/Os I/O96-I/O107 96 Page 12 of 64 [+] Feedback Ultra37000 CPLD Family Logic Block Diagrams (continued) CY37512/CY37512V Input Clock/ Input 4 1 4 4 12 I/Os I/O0-I/O11 LOGIC BLOCK AA 12 I/Os I/O12-I/O23 LOGIC BLOCK AB 12 I/Os I/O24-I/O35 LOGIC BLOCK AC LOGIC BLOCK AD 12 I/Os I/O36-I/O47 LOGIC BLOCK AE LOGIC BLOCK AF 12 I/Os I/O48-I/O59 12 I/Os I/O60-I/O71 LOGIC BLOCK AG 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 36 16 16 36 LOGIC BLOCK AH 36 16 16 LOGIC BLOCK AI 16 16 LOGIC BLOCK AJ 36 36 16 16 36 36 16 16 36 36 16 16 36 PIM 36 12 I/Os I/O72-I/O83 LOGIC BLOCK AK 12 I/Os I/O84-I/O95 LOGIC BLOCK AL 36 12 I/Os LOGIC BLOCK AM 36 16 16 36 36 I/O108-I/O119 LOGIC BLOCK AN 16 16 12 I/Os I/O120-I/O131 LOGIC BLOCK AO 36 36 16 16 LOGIC BLOCK AP 36 36 16 16 I/O96-I/O107 12 I/Os 132 TDI TCK TMS 36 JTAG Tap Controller LOGIC BLOCK BP LOGIC BLOCK BO 12 I/Os I/O252-I/O263 LOGIC BLOCK BN 12 I/Os I/O240-I/O251 LOGIC BLOCK BM 12 I/Os I/O228-I/O239 LOGIC BLOCK BL LOGIC BLOCK BK 12 I/Os I/O216-I/O227 LOGIC BLOCK BJ LOGIC BLOCK BI 12 I/Os I/O204-I/O215 LOGIC BLOCK BH LOGIC BLOCK BG 12 I/Os I/O192-I/O203 LOGIC BLOCK BF LOGIC BLOCK BE 12 I/Os I/O180-I/O191 LOGIC BLOCK BD 12 I/Os I/O168-I/O179 LOGIC BLOCK BC 12 I/Os I/O156-I/O167 LOGIC BLOCK BB 12 I/Os I/O144-I/O155 LOGIC BLOCK BA 12 I/Os I/O132-I/O143 132 TDO Document #: 38-03007 Rev. *E Page 13 of 64 [+] Feedback Ultra37000 CPLD Family 5.0V Device Characteristics Maximum Ratings DC Voltage Applied to Outputs in High-Z State................................................-0.5V to +7.0V DC Input Voltage ............................................-0.5V to +7.0V (Above which the useful life may be impaired. For user guidelines, not tested.) DC Program Voltage............................................. 4.5 to 5.5V Current into Outputs .................................................... 16 mA Storage Temperature ................................. -65C to +150C Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied............................................. -55C to +125C Latch-up Current..................................................... > 200 mA Supply Voltage to Ground Potential ............... -0.5V to +7.0V Operating Range[2] Ambient Temperature[2] Junction Temperature Output Condition VCC VCCO 0C to +70C 0C to +90C 5V 5V 0.25V 5V 0.25V 3.3V 5V 0.25V 3.3V 0.3V Industrial -40C to +85C -40C to +105C 5V 5V 0.5V 5V 0.5V 3.3V 5V 0.5V 3.3V 0.3V Military[3] -55C to +125C -55C to +130C 5V 5V 0.5V 5V 0.5V 3.3V 5V 0.5V 3.3V 0.3V Range Commercial 5.0V Device Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage Test Conditions VCC = Min. Min. Typ. IOH = -2.0 mA VOHZ Output HIGH Voltage with Output Disabled[5] VCC = Max. (Mil)[4] V 4.5 V 3.6 V (Ind/Mil)[6] 3.6 V IOL = 16 mA (Com'l/Ind)[4] 0.5 V IOH = 0 A VCC = Min. V 4.2 (Ind/Mil)[6] IOH = -150 A Output LOW Voltage Unit V 2.4 IOH = 0 A (Com'l)[6] IOH = -100 A (Com'l)[6] VOL Max. IOH = -3.2 mA (Com'l/Ind)[4] 2.4 IOL = 12 mA (Mil)[4] 0.5 V Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs[7] 2.0 VCCmax V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs[7] -0.5 0.8 V IIX Input Load Current VI = GND OR VCC, Bus-Hold Disabled -10 10 A IOZ Output Leakage Current VO = GND or VCC, Output Disabled, Bus-Hold Disabled -50 50 A IOS Output Short Circuit Current[5, 8] VCC = Max., VOUT = 0.5V -30 -160 mA IBHL Input Bus-Hold LOW Sustaining Current VCC = Min., VIL = 0.8V +75 A IBHH Input Bus-Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V -75 A IBHLO Input Bus-Hold LOW Overdrive Current VCC = Max. +500 A IBHHO Input Bus-Hold HIGH Overdrive Current VCC = Max. -500 A VIH Notes: 2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000 Family devices, please refer to the Application Note titled "An Introduction to In System Reprogramming with the Ultra37000." 3. TA is the "Instant On" case temperature. 4. IOH = -2 mA, IOL = 2 mA for TDO. 5. Tested initially and after any design or process changes that may affect these parameters. 6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled during ISR programming. Refer to the application note "Understanding Bus-Hold" for additional information. 7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. Document #: 38-03007 Rev. *E Page 14 of 64 [+] Feedback Ultra37000 CPLD Family Inductance[5] 44-Lead 44-Lead 44-Lead 84-Lead 84-Lead 100-Lead 160-Lead 208-Lead TQFP PLCC CLCC PLCC CLCC TQFP TQFP PQFP Unit Parameter Description Test Conditions L Maximum Pin VIN = 5.0V Inductance at f = 1 MHz 2 5 2 8 5 8 9 11 nH Capacitance[5] Parameter Description Test Conditions Max. Unit CI/O Input/Output Capacitance VIN = 5.0V at f = 1 MHz at TA = 25C 10 pF CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz at TA = 25C 12 pF VIN = 5.0V at f = 1 MHz at TA = 25C 16 pF CDP Dual-Function Pins Endurance Characteristics[5] Parameter N [9] Description Test Conditions Minimum Reprogramming Cycles Normal Programming 3.3V Device Characteristics Maximum Ratings Conditions[2] Min. Typ. Unit 1,000 10,000 Cycles DC Voltage Applied to Outputs in High-Z State................................................-0.5V to +7.0V (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Input Voltage ............................................-0.5V to +7.0V DC Program Voltage............................................. 3.0 to 3.6V Current into Outputs ...................................................... 8 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range[2] Range Ambient Temperature[2] Junction Temperature VCC[10] 0C to +70C 0C to +90C 3.3V 0.3V Commercial Industrial -40C to +85C -40C to +105C 3.3V 0.3V Military[3] -55C to +125C -55C to +130C 3.3V 0.3V 3.3V Device Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage Test Conditions VCC = Min. IOH = -3 mA (Mil) VOL Output LOW Voltage VCC = Min. Min. IOH = -4 mA (Com'l)[4] Unit V [4] IOL = 8 mA (Com'l)[4] IOL = 6 mA Max. 2.4 0.5 V (Mil)[4] VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs[7] 2.0 5.5 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs[7] -0.5 0.8 V IIX Input Load Current VI = GND OR VCC, Bus-Hold Disabled -10 10 A IOZ Output Leakage Current VO = GND or VCC, Output Disabled, Bus-Hold Disabled -50 50 A IOS Output Short Circuit Current[5, 8] VCC = Max., VOUT = 0.5V -30 -160 mA IBHL Input Bus-Hold LOW Sustaining Current VCC = Min., VIL = 0.8V +75 IBHH Input Bus-Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V -75 IBHLO Input Bus-Hold LOW Overdrive Current VCC = Max. A A +500 A Input Bus-Hold HIGH Overdrive Current VCC = Max. -500 Notes: 9. Dual pins are I/O with JTAG pins. 10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: VCC is 3.3V 0.16V. A IBHHO Document #: 38-03007 Rev. *E Page 15 of 64 [+] Feedback Ultra37000 CPLD Family Inductance[5] Parameter Description L Test Conditions 44Lead TQFP 44Lead PLCC 44Lead CLCC 84Lead PLCC 84Lead CLCC 100Lead TQFP 160Lead TQFP 2 5 2 8 5 8 9 Maximum Pin VIN = 3.3V Inductance at f = 1 MHz 208Lead PQFP Unit 11 nH Capacitance[5] Parameter Description Test Conditions Max. Unit CI/O Input/Output Capacitance VIN = 3.3V at f = 1 MHz at TA = 25C 8 pF CCLK Clock Signal Capacitance VIN = 3.3V at f = 1 MHz at TA = 25C 12 pF VIN = 3.3V at f = 1 MHz at TA = 25C 16 pF CDP Dual Functional Pins [9] Endurance Characteristics[5] Parameter Description N Test Conditions Minimum Reprogramming Cycles Normal Programming Conditions [2] Min. Typ. Unit 1,000 10,000 Cycles AC Characteristics 5.0V AC Test Loads and Waveforms 238 (COM'L) 319 (MIL) 5V OUTPUT 170 (COM'L) 236 (MIL) 35 pF INCLUDING JIG AND SCOPE 238 (COM'L) 319 (MIL) 5V 3.0V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) (a) 170 (COM'L) GND 236 (MIL) <2 ns ALL INPUT PULSES 90% 90% 10% 10% <2 ns (c) Equivalent to: THEVENIN EQUIVALENT 99 (COM'L) 136 (MIL) 2.08V (COM'L) OUTPUT 2.13V (MIL) 5 OR 35 pF 3.3V AC Test Loads and Waveforms 3.3V 295 (COM'L) 393 (MIL) OUTPUT 35 pF INCLUDING JIG AND SCOPE (a) Equivalent to: OUTPUT 340 (COM'L) 453 (MIL) 295 (COM'L) 393 (MIL) 3.3V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) 3.0V 340 (COM'L) GND 453 (MIL) <2 ns ALL INPUT PULSES 90% 90% 10% 10% <2 ns (c) THEVENIN EQUIVALENT 158 (COM'L) 270 (MIL) 1.77V (COM'L) 1.77V (MIL) 5 OR 35 pF Document #: 38-03007 Rev. *E Page 16 of 64 [+] Feedback Ultra37000 CPLD Family Parameter[11] VX tER(-) 1.5V Output Waveform--Measurement Level VOH tER(+) 0.5V VX 0.5V VX 0.5V VOH 0.5V VOL 2.6V VOL tEA(+) 1.5V VX tEA(-) Vthe VX (d) Test Waveforms Switching Characteristics Over the Operating Range [12] Parameter Description Unit Combinatorial Mode Parameters tPD[13, 14, 15] Input to Combinatorial Output ns tPDL[13, 14, 15] Input to Output Through Transparent Input or Output Latch ns tPDLL [13, 14, 15] Input to Output Through Transparent Input and Output Latches ns tEA[13, 14, 15] Input to Output Enable ns tER[11, 13] Input to Output Disable ns Input Register Parameters tWL Clock or Latch Enable Input LOW Time[8] ns tWH Clock or Latch Enable Input HIGH Time[8] ns tIS Input Register or Latch Set-up Time ns tIH Input Register or Latch Hold Time ns tICO[13, 14, 15] tICOL[13, 14, 15] Input Register Clock or Latch Enable to Combinatorial Output ns Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns Synchronous Clocking Parameters tCO[14, 15] Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output ns tS[13] Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable ns tH Register or Latch Data Hold Time ns Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output Delay (Through Logic Array) ns tSCS[13] Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array) ns tSL[13] Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0 CLK1, CLK2, or CLK3) or Latch Enable ns tHL Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable ns tCO2 [13, 14, 15] Notes: 11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load. 12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load. 13. Logic Blocks operating in Low-Power Mode, add tLP to this spec. 14. Outputs using Slow Output Slew Rate, add tSLEW to this spec. 15. When VCCO = 3.3V, add t3.3IO to this spec. Document #: 38-03007 Rev. *E Page 17 of 64 [+] Feedback Ultra37000 CPLD Family Switching Characteristics Over the Operating Range (continued)[12] Parameter Description Unit Product Term Clocking Parameters tCOPT[13, 14, 15] Product Term Clock or Latch Enable (PTCLK) to Output ns tSPT Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) ns tHPT Register or Latch Data Hold Time ns tISPT[13] Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or Latch Enable (PTCLK) ns tIHPT Buried Register Used as an Input Register or Latch Data Hold Time ns Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) ns tCO2PT [13, 14, 15] Pipelined Mode Parameters tICS[13] Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) ns Operating Frequency Parameters fMAX1 Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[5] MHz fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO)[5] MHz fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)[5] MHz fMAX4 Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS)[5] MHz Reset/Preset Parameters tRW Asynchronous Reset Width[5] ns tRR[13] Asynchronous Reset Recovery Time[5] ns tRO[13, 14, 15] Asynchronous Reset to Output ns tPW Asynchronous Preset Width[5] tPR [13] tPO[13, 14, 15] Asynchronous Preset Recovery ns Time[5] ns Asynchronous Preset to Output ns User Option Parameters tLP Low Power Adder ns tSLEW Slow Output Slew Rate Adder ns t3.3IO 3.3V I/O Mode Timing Adder[5] ns JTAG Timing Parameters tS JTAG Set-up Time from TDI and TMS to TCK[5] tH JTAG Hold Time on TDI and tCO JTAG Falling Edge of TCK to TDO[5] fJTAG Maximum JTAG Tap Controller Frequency Document #: 38-03007 Rev. *E ns TMS[5] ns ns [5] ns Page 18 of 64 [+] Feedback Ultra37000 CPLD Family Switching Characteristics Over the Operating Range [12] Max. Min. Min. 66 MHz Max. 83 MHz Max. Min. Min. 100 MHz Max. 125 MHz Max. 143 MHz Min. Max. 154 MHz Min. Min. Max. 167 MHz Max. Parameter Min. 200 MHz Unit Combinatorial Mode Parameters tPD[13, 14, 15] 6 tPDL[13, 14, 15] tPDLL[13, 14, 15] tEA[13, 14, 15] tER[11, 13] 6.5 7.5 8.5 10 12 15 20 ns 11 12.5 14.5 16 16.5 17 19 22 ns 12 13.5 15.5 17 17.5 18 20 24 ns 8 8.5 11 13 14 16 19 24 ns 8 8.5 11 13 14 16 19 24 ns Input Register Parameters tWL 2.5 2.5 2.5 2.5 tWH 2.5 2.5 2.5 2.5 3 3 4 5 ns tIS 2 2 2 2 2 2.5 3 4 ns tIH 2 2 2 3 2 3 2 4 2.5 5 3 ns 4 ns tICO[13, 14, 15] 11 11 11 12.5 12.5 16 19 24 ns tICOL[13, 14, 15] 12 12 12 14 16 18 21 26 ns 4.5 6 6.5[16] 6.5[17] 8[18] 10 ns Synchronous Clocking Parameters tCO [14, 15] 4 tS[13] 4 tH 0 tCO2[13, 14, 15] tSCS[13] tSL[13] tHL 4 4 5 0 9.5 0 10 5.5[16] 5 0 11 6[17] 0 12 8[18] 0 14 10 0 16 ns 0 19 ns 24 ns 5 6 6.5 7 8[16] 10 12 15 ns 7.5 7.5 8.5 9 10 12 15 15 ns 0 0 0 0 0 0 0 0 ns Product Term Clocking Parameters tCOPT[13, 14, 15] 7 10 10 13 13 13 15 20 ns tSPT 2.5 2.5 2.5 3 5 5.5 6 7 ns tHPT 2.5 2.5 2.5 3 5 5.5 6 7 ns tISPT[13] 0 0 0 0 0 0 0 0 ns tIHPT 6 tCO2PT[13, 14, 6.5 12 15] 6.5 14 7.5 15 9 19 11 19 14 21 19 24 ns 30 ns Pipelined Mode Parameters tICS[13] 5 6 6 7 8[16] 10 12 15 ns Operating Frequency Parameters fMAX1 200 167 154 143 125[16] 100 83 66 MHz fMAX2 200 200 200 167 154 153[17] 125[18] 100 MHz fMAX3 125 125 105 91 83 80[17] 62.5 50 MHz fMAX4 167 167 154 125 118 100 83 66 MHz 8 8 8 10 12 15 20 ns Reset/Preset Parameters tRW 8 tRR[13] 10 10 10 10 12 14 17 22 ns Notes: 16. The following values correspond to the CY37512 and CY37384 devices: tCO = 5 ns, tS = 6.5 ns, tSCS = 8.5 ns, tICS = 8.5 ns, fMAX1 = 118 MHz. 17. The following values correspond to the CY37192V and CY37256V devices: tCO = 6 ns, tS = 7 ns, fMAX2 = 143 MHz, fMAX3 = 77 MHz, and fMAX4 = 100 MHz; and for the CY37512 devices: tS = 7 ns. 18. The following values correspond to the CY37512V and CY37384V devices: tCO = 6.5 ns, tS = 9.5 ns, and fMAX2 = 105 MHz. Document #: 38-03007 Rev. *E Page 19 of 64 [+] Feedback Ultra37000 CPLD Family Switching Characteristics Over the Operating Range (continued)[12] 12 13 13 15 21 Max. Min. Min. 18 66 MHz Max. 83 MHz Max. Min. Min. 14 100 MHz Max. 125 MHz Max. 143 MHz Min. Max. 154 MHz Min. Max. Min. Min. Parameter tRO[13, 14, 15] 167 MHz Max. 200 MHz 26 Unit ns tPW 8 8 8 8 10 12 15 20 ns tPR[13] 10 10 10 10 12 14 17 22 ns tPO[13, 14, 15] 12 13 13 14 15 18 21 26 ns 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns 3 3 3 3 3 3 3 3 ns 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns User Option Parameters tLP tSLEW t3.3IO[19] JTAG Timing Parameters tS JTAG 0 tH JTAG 20 0 0 20 0 20 0 20 0 20 0 20 0 20 ns 20 ns tCO JTAG 20 20 20 20 20 20 20 20 ns fJTAG 20 20 20 20 20 20 20 20 MHz Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT Registered Output with Synchronous Clocking INPUT tS tH SYNCHRONOUS CLOCK tCO REGISTERED OUTPUT tCO2 REGISTERED OUTPUT tWH tWL SYNCHRONOUS CLOCK Note: 19. Only applicable to the 5V devices. Document #: 38-03007 Rev. *E Page 20 of 64 [+] Feedback Ultra37000 CPLD Family Switching Waveforms (continued) Registered Output with Product Term Clocking Input Going Through the Array INPUT tSPT tHPT PRODUCT TERM CLOCK tCOPT REGISTERED OUTPUT Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT tISPT tIHPT PRODUCT TERM CLOCK tCO2PT REGISTERED OUTPUT Latched Output INPUT tSL tHL LATCH ENABLE tPDL tCO LATCHED OUTPUT Document #: 38-03007 Rev. *E Page 21 of 64 [+] Feedback Ultra37000 CPLD Family Switching Waveforms (continued) Registered Input REGISTERED INPUT tIS tIH INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tWH tWL CLOCK Clock to Clock INPUT REGISTER CLOCK tICS tSCS OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT tIS tIH LATCH ENABLE tPDL tICO COMBINATORIAL OUTPUT tWH tWL LATCH ENABLE Document #: 38-03007 Rev. *E Page 22 of 64 [+] Feedback Ultra37000 CPLD Family Switching Waveforms (continued) Latched Input and Output LATCHED INPUT tPDLL LATCHED OUTPUT tICOL tSL tHL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tWH tWL LATCH ENABLE Asynchronous Reset tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK Asynchronous Preset tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK Output Enable/Disable INPUT tER tEA OUTPUTS Document #: 38-03007 Rev. *E Page 23 of 64 [+] Feedback Ultra37000 CPLD Family Power Consumption Typical 5.0V Power Consumption CY37032 60 H ig h S p e e d 50 40 Icc (mA) Low Power 30 20 10 0 0 50 100 150 200 250 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature CY37064 90 80 H ig h S p e e d 70 Icc (mA) 60 50 Low Power 40 30 20 10 0 0 20 40 60 80 100 120 140 160 180 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature Document #: 38-03007 Rev. *E Page 24 of 64 [+] Feedback Ultra37000 CPLD Family Typical 5.0V Power Consumption (continued) CY37128 160 H ig h S p e e d 140 120 Icc (mA) 100 Low Power 80 60 40 20 0 0 20 40 60 80 100 120 140 160 180 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature CY37192 300 250 H ig h S p e e d Icc (mA) 200 Low Power 150 100 50 0 0 20 40 60 80 100 120 140 160 180 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature Document #: 38-03007 Rev. *E Page 25 of 64 [+] Feedback Ultra37000 CPLD Family Typical 5.0V Power Consumption (continued) CY37256 300 H ig h S p e e d 250 200 Icc (mA) Low Power 150 100 50 0 0 20 40 60 80 100 120 140 160 180 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature CY37384 500 450 H ig h S p e e d 400 350 Icc (mA) 300 Low Power 250 200 150 100 50 0 0 20 40 60 80 100 120 140 16 0 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature Document #: 38-03007 Rev. *E Page 26 of 64 [+] Feedback Ultra37000 CPLD Family Typical 5.0V Power Consumption (continued) CY37512 600 H ig h S p e e d 500 Icc (mA) 400 Low Power 300 200 100 0 0 20 40 60 80 100 120 140 160 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature Typical 3.3V Power Consumption CY37032V 30 H igh S p ee d 25 L ow P o w er Icc (mA) 20 15 10 5 0 0 20 40 60 80 100 120 140 160 F re qu e n cy (M H z) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature Document #: 38-03007 Rev. *E Page 27 of 64 [+] Feedback Ultra37000 CPLD Family Typical 3.3V Power Consumption (continued) CY37064V 45 H ig h S p e e d 40 35 Low Power Icc (mA) 30 25 20 15 10 5 0 0 20 40 60 80 100 120 140 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature CY37128V 80 H ig h S p e e d 70 60 Low Power Icc (mA) 50 40 30 20 10 0 0 20 40 60 80 100 120 140 F r e q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature Document #: 38-03007 Rev. *E Page 28 of 64 [+] Feedback Ultra37000 CPLD Family Typical 3.3V Power Consumption (continued) CY37192V 120 H ig h S p e e d 100 80 Icc (mA) Low Power 60 40 20 0 0 20 40 60 80 100 120 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature CY37256V 140 120 H ig h S p e e d 100 Icc (mA) Low Power 80 60 40 20 0 0 20 40 60 80 100 120 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature Document #: 38-03007 Rev. *E Page 29 of 64 [+] Feedback Ultra37000 CPLD Family Typical 3.3V Power Consumption (continued) CY37384V 200 180 H ig h S p e e d 160 140 Low Power Icc (mA) 120 100 80 60 40 20 0 0 10 20 30 40 50 60 70 80 90 F r e q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature CY37512V 250 H ig h S p e e d 200 150 Icc (mA) Low Power 100 50 0 0 10 20 30 40 50 60 70 80 90 F re q u e n c y (M H z ) The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature Document #: 38-03007 Rev. *E Page 30 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] 44-pin TQFP (A44) GND CLK0/I 1 I/O8 I/O9 I/O10 I/O29 I/O28 I/O31 I/O30 I/O1 I/O 0 GND VCCO I/O12 I/O13 /TMS I/O14 I/O15 I/O11 26 8 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 I/O27 /TDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 CLK3/I2 I/O23 I/O22 I/O21 I/O19 /TDO I/O20 CLK2/I0 JTAGEN 44 43 42 41 40 39 38 37 36 35 34 33 32 2 3 31 4 30 5 29 6 28 27 7 1 VCC GND I/O16 I/O17 I/O18 I/O5/TCK I/O6 I/O 7 I/O2 I/O4 I/O3 Top View I/O28 I/O29 I/O31 I/O30 I/O 1 I/O 0 GND VCCO I/O 2 I/O 4 I/O 3 44-pin PLCC (J67) / CLCC (Y67) Top View 6 5 4 3 2 1 44 43 42 41 40 Document #: 38-03007 Rev. *E I/O27 /TDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 CLK3/I2 I/O23 I/O22 I/O21 I/O19 /TDO I/O20 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 VCC GND I/O16 I/O17 I/O18 7 8 9 10 11 12 13 14 15 16 17 I/O12 I/O /TMS 13 I/O14 I/O15 I/O 5/TCK I/O6 I/O7 CLK2/I0 JTAGEN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O 11 Page 31 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) 48-ball Fine-Pitch BGA (BA50) Top View 1 2 3 4 5 6 7 8 A I/O5 TCK VCC I/O3 I/O1 I/O31 I/O30 VCC I/O27 TDI B VCC I/O4 I/O2 I/O0 I/O29 I/O28 I/O26 CLK1/ I4 C CLK2/ I0 I/O7 I/O6 GND GND I/O25 I/O24 I3 D JTAGEN I/O8 I/O9 GND GND I/O22 I/O23 CLK3/ I2 E CLK0/ I1 I/O12 I/O11 I/O10 I/O16 I/O20 I/O21 VCC F I/O13 TMS VCC I/O14 I/O15 I/O17 I/O18 VCC I/O19 TDO Note: 20. For 3.3V versions (Ultra37000V), VCCO = VCC. I/O 8 12 I/O 9 13 75 27 I/O 20 28 I/O 21 29 I/O 22 30 I/O 23 31 GND 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 I/O 53 I/O 55 72 I/O 54 /TDI 71 I/O 53 70 I/O 52 69 I/O 51 68 I/O 50 67 I/O 49 66 I/O 48 65 CLK3/I 4 64 GND 63 VCCO 62 CLK2/I 3 61 I/O 47 60 I/O 46 59 I/O 45 58 I/O 44 57 I/O 43 56 I/O 42 55 I/O 41 54 I/O 40 GND I/O 19 I/O 39 26 GND 73 38 I/O 18 /TDO 25 74 I/O I/O 17 37 24 36 I/O16 I/O 23 I/O CLK1/I 1 35 22 I/O 24 GND I/O 21 34 VCCO I/O 20 33 CLK0/I 0 32 19 I/O I/O 15 I/O 18 [21] I/O 14 VCC 17 GND I/O 13 2 16 VCCO I/O 12 I 15 /TMS 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 11 56 57 1 84 83 82 81 80 79 78 77 76 I/O 59 60 58 I/O I/O I/O 61 I/O 62 I/O I/O I/O 63 JTAGEN 2 GND 3 4 VCC 2 5 V CCO 6 1 I/O 0 7 I/O 3 8 I/O 4 I/O 5 I/O 6 9 14 I/O 25 I/O10 /TCK I/O 7 11 10 I/O I/O GND 84-lead PLCC (J83) / CLCC (Y84) Top View Note: 21. This pin is a N/C, but Cypress recommends that you connect it to VCC to ensure future compatibility. Document #: 38-03007 Rev. *E Page 32 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) NC 56 GND 57 I/O 58 I/O 59 I/O I/O 61 I/O 60 62 I/O I/O I/O 63 VCC N/C GND NC 2 1 I/O 0 VCCO I/O I/O 5 6 7 4 3 I/O I/O I/O I/O VCCO I/O NC 100-lead TQFP (A100) Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 TCK GND I/O 8 I/O 9 I/O 10 1 75 TDI 2 74 VCCO 3 73 I/O 55 4 72 I/O 54 5 71 I/O 53 I/O 11 6 70 I/O 52 I/O 12 7 69 I/O 51 I/O 50 I/O 13 8 68 I/O 14 9 I/O 15 67 10 66 CLK0 /I 0 11 VCCO 65 12 N/C 64 13 63 14 62 GND CLK 1 /I 1 I/O 49 I/O 48 CLK 3 /I 4 GND NC VCCO CLK 2 /I 3 15 I/O16 61 16 60 I/ O47 I/O17 17 59 I/O 46 I/O18 18 58 I/O 45 I/O 44 I/O19 19 I/O20 57 20 I/O21 56 21 55 I/O22 22 54 I/O23 23 53 VCCO 24 52 NC 25 51 I/O 43 I/O 42 I/O 41 I/O 40 GND NC TDO VCCO I/O 38 I/O 39 I/O 35 I/O 36 I/O 37 I/O 33 I/O 34 GND VCC [21 ] I/O 32 NC I2 VCCO I/O 30 I/O 31 I/O 28 I/O 29 I/O 26 I/O 27 I/O 24 I/O 25 TMS Document #: 38-03007 Rev. *E GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 33 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) 100-ball Fine-Pitch BGA (BB100) for CY37064V Top View 1 2 3 4 5 6 7 8 9 10 A NC NC I/O7 I/O5 I/O2 I/O62 I/O60 I/O58 I/O57 I/O56 B I/O9 I/O8 I/O6 I/O4 I/O1 I/O63 VCC I/O59 I/O55 NC C I/O10 TCK VCC I/O3 NC NC I/O61 VCC TDI I/O54 D I/O11 NC I/O12 I/O13 I/O0 NC I/O51 I/O52 CLK3/ I4 I/O53 E I/O14 CLK0/ I0 I/O15 NC GND GND I/O48 I/O49 CLK2/ I3 I/O50 F I/O17 NC NC I/O16 GND GND NC NC I2 I/O47 G I/O22 CLK1/ I1 I/O21 I/O19 I/O18 I/O46 I/O45 I/O44 NC I/O43 H I/O23 TMS VCC I/O20 NC I/O32 I/O42 VCC TDO I/O41 J NC I/O26 I/O28 NC I/O31 I/O33 I/O35 I/O37 I/O39 I/O40 K I/O24 I/O25 I/O27 I/O29 I/O30 I/O34 I/O36 I/O38 NC NC 100-ball Fine-Pitch BGA (BB100) for CY37128V Top View 1 2 3 4 5 6 7 8 9 10 A NC I/O9 I/O8 I/O6 I/O3 I/O76 I/O74 I/O72 I/O71 I/O70 B I/O11 I/O10 I/O7 I/O5 I/O2 I/O77 VCC I/O73 I/O68 I/O69 C I/O12 I/O13 TCK VCC I/O4 I/O1 I/O78 I/O75 VCC I/O67 TDI I/O66 D I/O14 NC I/O15 I/O16 I/O0 I/O79 I/O63 I/O64 CLK3/ I4 I/O65 E I/O17 CLK0/ I0 I/O18 I/O19 GND GND I/O60 I/O61 CLK2/ I3 I/O62 F I/O22 JTAG EN I/O21 I/O20 GND GND I/O59 I/O58 I2 I/O57 G I/O27 CLK1/ I1 I/O26 I/O24 I/O23 I/O56 I/O55 I/O54 NC I/O53 H I/O28 I/O33 TMS VCC I/O25 I/O39 I/O40 I/O52 VCC I/O47 TDO I/O51 J I/O29 I/O32 I/O35 VCC I/O38 I/O41 I/O43 I/O45 I/O48 I/O50 K I/O30 I/O31 I/O34 I/O36 I/O37 I/O42 I/O44 I/O46 I/O49 NC Document #: 38-03007 Rev. *E Page 34 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 VCCO I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCCO GND VCC JTAGEN I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 GND I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND 160-Lead TQFP (A160) / CQFP (U162) for CY37128(V) and CY37256(V) Top View GND I/O16 I/O17 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VCCO I/O111 I/O110 I/O109 I/O108 /TDI I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 CLK3/I4 GND VCCO CLK2/I3 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 GND GND I/O48 I/O49 I/O50 I/O51 I/O52/TMS I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I2 VCCO GND VCC I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I/O79 VCCO 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O18 I/O19 I/O20/TCK I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 CLK0/I0 VCCO GND CLK1/I1 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 VCCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Document #: 38-03007 Rev. *E Page 35 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 VCCO I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCCO GND VCC NC I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 NC GND 160-Lead TQFP (A160) for CY37192(V) Top View GND NC I/O16 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 VCCO I/O104 83 82 81 I/O75 NC GND I/O103 I/O102 TDI I/O101 I/O100 I/O99 I/O98 GND I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 CLK3/I4 GND VCCO CLK2/I3 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 GND I/O81 I/O80 I/O79 I/O78 I/O77 I/O76 Document #: 38-03007 Rev. *E TDO I/O72 I/O73 I/O74 VCCO TMS I/O49 I/O50 I/O51 GND I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I2 VCCO GND VCC I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 I/O66 I/O67 GND I/O68 I/O69 I/O70 I/O71 GND NC I/O46 I/O47 I/O48 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O17 I/O18 TCK I/O19 I/O20 I/O21 GND I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 CLK0/I0 VCCO GND CLK1/I1 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 GND I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 VCCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Page 36 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 VCCO I/O139 I/O138 I/O137 I/O136 I/O135 TDI I/O134 I/O133 I/O132 I/O131 I/O130 GND I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 CLK3/I4 VCC GND VCCO GND CLK2/I3 I/O119 I/O118 I/O117 I/O116 I/O115 NC I/O114 I/O113 I/O112 I/O111 I/O110 GND I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 GND GND I/O60 I/O61 I/O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 I2 VCC0 GND VCC I/O80 I/O81 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 GND I/O90 I/O91 I/O92 I/O93 I/O94 GND TDO I/O95 I/O96 I/O97 I/O98 I/O99 VCC0 GND I/O20 I/O21 I/O22 I/O23 I/O24 TCK I/O25 I/O26 I/O27 I/O28 I/O29 GND I/O30 I/O31 I/O32 I/O33 I/O34 NC I/O35 I/O36 I/O37 I/O38 I/O39 CLK0/I0 VCCO GND NC CLK1/I1 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 GND I/O50 I/O51 I/O52 I/O53 I/O54 NC I/O55 I/O56 I/O57 I/O58 I/O59 VCC0 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VCC VCC0 I/O19 I/O18 I/O17 I/O16 I/O15 NC I/O14 I/O13 I/O12 I/O11 I/O10 GND I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC0 GND VCC NC I/O159 I/O158 I/O157 I/O156 I/O155 NC I/O154 I/O153 I/O152 I/O151 I/O150 GND I/O149 I/O148 I/O147 I/O146 I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 NC GND 208-Lead PQFP (N208) / CQFP (U208) Top View Document #: 38-03007 Rev. *E Page 37 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) 292-Ball PBGA (BG292) Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A GND I/O21 NC I/O16 I/O12 I/O9 I/O7 I/O4 I/O0 I/O190 I/O189 I/O186 I/O182 NC I/O178 I/O175 NC NC I/O169 I/O168 A B I/O23 I/O20 I/O19 I/O18 I/O15 I/O11 I/O8 I/O5 I/O1 I/O191 I/O187 I/O185 I/O181 NC NC I/O174 I/O171 I/O170 NC I/O166 B C NC NC I/O22 NC I/O17 I/O14 I/O10 I/O6 I/O2 NC I/O188 I/O184 I/O180 I/O179 I/O176 I/O173 I/O172 I/O167 I/O165 I/O162 C D I/O24 NC NC GND NC VCCO I/O13 GND I/O3 NC VCC I/O183 GND I/O177 VCCO NC GND I/O164 TDI I/O160 D E I/O27 I/O26 I/O25 NC I/O163 I/O161 I/O159 I/O156 E F I/O30 TCK I/O28 VCCO VCCO I/O158 NC I/O154 F G I/O33 I/O32 I/O31 I/O29 I/O157 I/O155 I/O153 I/O152 G H I/O35 NC I/O34 GND GND GND GND GND GND GND GND I/O151 I/O150 I/O149 H J I/O39 I/O38 I/O37 I/O36 GND GND GND GND GND GND I/O148 I/O147 I/O146 I/O145 J K I/O42 I/O40 I/O41 VCC GND GND GND GND GND GND I/O144 CLK3/I4 NC NC K L I/O43 I/O44 I/O45 I/O46 GND GND GND GND GND GND VCC NC L M I/O47 I/O48 GND GND GND GND GND GND I/O139 I/O140 I/O141 I/O142 M N I/O49 I/O50 I/O51 GND GND GND GND GND GND GND GND I/O136 I/O137 I/O138 N P I/O52 I/O53 I/O55 I/O58 I/O131 I/O133 I/O134 I/O135 P R I/O54 I/O56 I/O59 VCCO VCCO I/O130 NC I/O132 R T I/O57 I/O60 I/O62 I/O65 I/O124 I/O127 I/O128 I/O129 T U I/O61 I/O63 I/O66 GND I/O76 VCCO I/O82 GND I/O91 VCC I/O98 I/O102 GND I/O112 VCCO NC GND I/O123 I/O122 I/O126 U V I/O64 I/O67 I/O69 I/O75 I/O78 I/O81 I/O85 I/O88 I/O92 I2 I/O97 I/O101 I/O105 I/O109 I/O113 TDO I/O114 I/O117 I/O121 I/O125 V W I/O68 I/O70 I/O72 I/O74 I/O79 I/O83 I/O86 I/O89 I/O93 I/O95 I/O96 I/O100 I/O104 I/O107 I/O110 NC NC I/O115 I/O118 I/O120 W Y I/O71 I/O73 I/O77 TMS I/O80 I/O84 I/O87 I/O90 I/O94 NC NC I/O99 I/O103 I/O106 I/O108 I/O111 NC NC I/O116 I/O119 Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK0/I0 CLK1/I1 Document #: 38-03007 Rev. *E CLK2/I3 I/O143 Page 38 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) 256-Ball Fine-Pitch BGA (BB256) Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A GND GND I/O26 I/O24 I/O20 VCC I/O11 GND GND I/O186 VCC I/O177 I/O172 I/O167 GND GND B GND I/O27 I/O25 I/O23 I/O19 I/O15 I/O10 GND GND I/O185 I/O181 I/O176 I/O171 I/O166 I/O165 GND C I/O29 I/O28 NC I/O22 I/O18 I/O14 I/O9 I/O4 I/O191 I/O184 I/O180 I/O175 I/O170 NC I/O163 I/O164 D I/O32 I/O31 I/O30 NC I/O17 I/O13 I/O8 I/O3 I/O190 I/O183 I/O179 I/O174 I/O169 I/O160 I/O161 I/O162 E I/O35 I/O34 I/O33 I/O21 I/O16 I/O12 I/O7 I/O2 I/O189 VCC I/O178 I/O173 I/O168 I/O157 I/O158 I/O159 F VCC I/O38 I/O37 I/O36 TCK VCC I/O6 I/O1 I/O188 I/O182 VCC TDI I/O154 I/O155 I/O156 VCC G I/O43 I/O42 I/O41 I/O40 VCC I/O39 I/O5 I/O0 I/O187 I/O148 I/O149 CLK3 /I4 I/O150 I/O151 I/O152 I/O153 H GND GND I/O47 I/O46 CLK0 /I0 I/O45 I/O44 GND GND I/O144 I/O145 CLK2 /I3 I/O146 I/O147 GND GND J GND GND I/O51 I/O50 NC I/O49 I/O48 GND GND I/O140 I/O141 I2 I/O142 I/O143 GND GND K I/O57 I/O56 I/O55 I/O54 CLK1 /I1 I/O53 I/O52 I/O91 I/O96 I/O101 I/O135 VCC I/O136 I/O137 I/O138 I/O139 L VCC I/O60 I/O59 I/O58 TMS VCC I/O86 I/O92 I/O97 I/O102 VCC TDO I/O132 I/O133 I/O134 VCC M I/O63 I/O62 I/O61 I/O72 I/O77 I/O82 VCC I/O93 I/O98 I/O103 I/O108 I/O112 I/O117 I/O129 I/O130 I/O131 N I/O66 I/O65 I/O64 I/O73 I/O78 I/O83 I/O87 I/O94 I/O99 I/O104 I/O109 I/O113 NC I/O126 I/O127 I/O128 P I/O68 I/O67 NC I/O74 I/O79 I/O84 I/O88 I/O95 I/O100 I/O105 I/O110 I/O114 I/O118 NC I/O124 I/O125 R GND I/O69 I/O70 I/O75 I/O80 I/O85 I/O89 GND GND I/O106 I/O111 I/O115 I/O119 I/O121 I/O123 GND T GND GND I/O71 I/O76 I/O81 VCC I/O90 GND GND I/O107 VCC I/O116 I/O120 I/O122 GND GND Document #: 38-03007 Rev. *E Page 39 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) 388-Lead PBGA (BG388) Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A GND GND I/O19 I/O15 I/O13 I/O34 I/O31 I/O28 I/O25 I/O10 I/O7 I/O4 I/O1 I/O263 I/O260 I/O257 I/O254 I/O239 I/O237 I/O232 I/O229 I/O250 I/O248 I/O244 GND GND B GND I/O8 I/O5 I/O2 C I/O23 I/O38 I/O37 I/O16 I/O12 I/O33 I/O30 I/O27 I/O24 I/O9 I/O6 I/O3 I/O0 I/O262 I/O259 I/O256 I/O253 I/O238 I/O235 I/O233 I/O230 I/O251 I/O247 I/O225 I/O224 I/O227 D I/O39 I/O40 I/O36 NC NC GND GND VCCO VCCO GND GND E I/O42 NC F I/O45 I/O44 I/O43 I/O22 I/O242 I/O219 I/O218 I/O217 G I/O48 I/O47 I/O46 I/O63 I/O241 I/O216 I/O215 I/O214 H I/O49 I/O50 I/O51 VCCO VCCO I/O211 I/O212 I/O213 J I/O52 I/O53 I/O54 VCCO VCCO I/O208 I/O209 I/O210 K I/O55 I/O56 I/O57 L I0 NC TCK I/O18 I/O17 I/O14 I/O35 I/O32 I/O29 I/O26 I/O11 I/O41 NC I/O21 I/O20 VCCO VCCO NC VCCO VCCO I/O236 I/O243 NC NC NC NC NC I/O59 I/O58 GND I/O226 I/O222 I/O223 TDI I/O221 I/O220 I/O205 I/O206 I/O207 GND GND GND GND GND GND GND I/O204 GND GND GND GND GND GND GND GND I/O197 I/O61 I/O60 N I/O64 I/O62 VCCO GND GND GND GND GND GND VCCO I/O201 I/O200 I/O199 P I/O65 I/O66 I/O67 VCCO GND GND GND GND GND GND VCCO I/O196 VCC I/O198 R I/O68 I/O69 I/O70 GND GND GND GND GND GND GND GND I/O193 I/O194 I/O195 T I/O71 I/O84 I/O85 GND GND GND GND GND GND GND GND I/O178 I/O179 I/O192 U I/O88 I/O87 I/O86 V I/O91 I/O90 I/O89 VCCO VCCO I/O174 I/O173 I/O172 W I/O94 I/O93 I/O92 VCCO VCCO I/O171 I/O170 I/O169 Y I/O95 I/O72 I/O73 I/O110 I/O153 I/O190 I/O191 I/O168 AA I/O74 I/O75 I/O76 I/O111 I/O152 I/O187 I/O188 I/O189 AB I/O77 I/O78 I/O79 AC I/O81 I/O80 I/O108 N/C NC NC N/C NC I/O112 I/O113 VCCO VCCO NC GND GND VCCO VCCO GND GND AD I/O109 I/O82 I/O83 I/O117 I/O97 I/O100 I/O102 I/O105 I/O120 I/O123 I/O126 I/O129 NC I2 NC VCCO VCCO I/O150 I/O151 NC I3 I4 M VCC I1 VCC I/O261 I/O258 I/O255 I/O252 I/O234 I/O231 I/O228 I/O249 I/O246 I/O245 I/O240 GND I/O203 I/O202 I/O177 I/O176 I/O175 NC I/O184 I/O185 I/O186 NC I/O155 I/O183 I/O182 I/O133 I/O136 I/O139 I/O142 I/O157 I/O159 I/O161 I/O163 I/O166 I/O146 I/O180 I/O181 I/O154 AE GND I/O115 I/O116 I/O119 I/O98 I/O101 I/O103 I/O106 I/O121 I/O124 I/O127 VCC I/O130 I/O134 I/O137 I/O140 I/O143 I/O160 I/O162 I/O165 I/O144 I/O147 I/O148 AF GND GND I/O114 I/O118 I/O96 I/O99 TMS I/O104 I/O107 I/O122 I/O125 I/O128 I/O131 I/O132 I/O135 I/O138 I/O141 I/O156 I/O158 TDO I/O164 I/O167 I/O145 I/O149 GND GND Document #: 38-03007 Rev. *E NC GND Page 40 of 64 [+] Feedback Ultra37000 CPLD Family Pin Configurations[20] (continued) 400-Ball Fine-Pitch BGA (BB400) Top View A GND GND NC I/O17 I/O16 I/O14 I/O29 VCC I/O11 GND GND I/O257 VCC I/O239 I/O233 I/O232 I/O230 NC GND GND B GND GND GND NC I/O15 I/O13 I/O28 VCC I/O10 GND GND I/O256 VCC I/O238 I/O231 I/O229 NC GND GND GND C NC GND GND GND I/O20 I/O12 I/O27 VCC I/O9 GND GND I/O255 VCC I/O237 I/O228 I/O245 GND GND GND NC D I/O44 NC GND I/O21 I/O19 I/O18 I/O26 I/O25 I/O8 GND GND I/O254 I/O235 I/O236 I/O251 I/O244 I/O243 GND NC I/O227 E I/O46 I/O43 I/O23 I/O22 NC I/O35 I/O34 I/O24 I/O7 I/O4 I/O263 I/O253 I/O234 I/O250 I/O248 I/O241 I/O242 I/O225 I/O226 F I/O47 I/O45 I/O42 I/O41 I/O40 NC I/O33 I/O32 I/O6 I/O3 I/O262 I/O252 I/O249 I/O247 I/O220 I/O221 I/O240 I/O222 I/O223 I/O224 G I/O53 I/O52 I/O51 I/O50 I/O39 I/O38 I/O37 I/O31 I/O5 I/O2 I/O261 I/O217 I/O218 I/O219 I/O212 I/O213 I/O214 I/O215 H VCC VCC VCC I/O49 I/O48 I/O36 TCK VCC I/O30 I/O1 I/O259 I/O260 J I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 VCC I/O62 I/O60 I/O0 K GND GND GND GND I/O65 I/O64 CLK0 /I0 I/O63 I/O61 L GND GND GND GND I/O69 I/O68 NC I/O67 M I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 CLK1 /I1 N VCC VCC VCC I/O91 I/O90 I/O72 P I/O95 I/O94 I/O93 I/O92 I/O75 R I/O80 I/O79 I/O78 I/O108 T I/O82 I/O81 I/O110 U I/O83 NC V NC W Y VCC I/O246 TDI I/O216 I/O210 I/O211 I/O258 I/O202 I/O203 CLK3 /I4 I/O204 I/O205 I/O206 I/O207 I/O208 I/O209 GND GND I/O198 I/O199 CLK2 /I3 I/O200 I/O201 GND GND GND GND I/O66 GND GND I/O193 I/O195 I2 I/O196 I/O197 GND GND GND GND I/O71 I/O70 I/O126 I/O132 I/O192 I/O194 VCC I/O174 I/O175 I/O176 I/O177 I/O178 I/O179 TMS VCC I/O128 I/O127 I/O133 I/O162 TDO I/O180 I/O168 I/O169 I/O74 I/O73 I/O114 I/O77 I/O76 I/O115 I/O117 I/O109 NC I/O116 GND I/O111 I/O112 GND GND GND GND GND GND NC GND GND NC I/O98 VCC VCC VCC VCC VCC VCC VCC I/O129 I/O134 I/O137 I/O163 I/O181 I/O182 I/O183 I/O170 I/O171 I/O172 I/O173 I/O120 I/O130 I/O135 I/O138 I/O164 I/O165 I/O184 I/O185 I/O186 I/O189 I/O191 I/O118 I/O102 I/O121 I/O131 I/O136 I/O139 I/O156 I/O166 I/O167 NC I/O154 I/O155 I/O187 I/O190 I/O119 I/O104 I/O103 I/O122 GND GND I/O140 I/O157 I/O158 I/O150 I/O151 I/O153 GND NC I/O188 I/O113 I/O96 I/O105 VCC I/O123 GND GND I/O141 VCC I/O159 GND GND GND NC I/O97 I/O99 I/O106 VCC I/O124 GND GND I/O142 VCC I/O160 I/O145 I/O147 NC GND GND GND I/O100 I/O101 I/O107 VCC I/O125 GND GND I/O143 VCC I/O161 I/O146 I/O148 I/O149 NC GND GND Document #: 38-03007 Rev. *E VCC VCC NC NC I/O14 4 I/O152 Page 41 of 64 [+] Feedback Ultra37000 CPLD Family Ordering Information CY 37 512 V P400 - 83 BB X C Cypress Semiconductor ID Operating Conditions Commercial 0C to +70C Industrial -40C to +85C Military -55C to +125C Family Type 37 = Ultra37000 Family Lead Free X Lead Free Package Type A = Thin Quad Flat Pack (TQFP) U = Ceramic Quad Flat Pack (CQFP) N = Plastic Quad Flat Pack (PQFP) NT = Thermally Enhanced Plastic Quad Flat Pack (EQFP) J = Plastic Leaded Chip Carrier (PLCC) Y = Ceramic Leaded Chip Carrier (CLCC) BG = Plastic Ball Grid Array (PBGA) BA = Fine-Pitch Ball Grid Array (FBGA) 0.8mm Lead Pitch BB = Fine-Pitch Ball Grid Array (FBGA) 1.0mm Lead Pitch Macrocell Density 32 = 32 Macrocells 256 = 256 Macrocells 64 = 64 Macrocells 384 = 384 Macrocells 128 = 128 Macrocells 512 = 512 Macrocells 192 = 192 Macrocells Operating Reference Voltage V = 3.3V Supply Voltage (5.0V if not specified) Pin Count P44 = 44 Leads P48 = 48 Leads P84 = 84 Leads P100 = 100 Leads P160 = 160 Leads P208 = 208 Leads P256 = 256 Leads P352 = 352 Leads P400 = 400 Leads Speed 200 = 200 MHz 167 = 167 MHz 154 = 154 MHz 143 = 143 MHz 125 = 125 MHz 100 = 100 MHz 83 = 83 MHz 66 = 66 MHz 5.0V Ordering Information Macrocells Speed (MHz) 32 200 154 125 64 200 Ordering Code Package Name Package Type CY37032P44-200AC A44 44-Lead Thin Quad Flat Pack CY37032P44-200AXC A44 44-Lead Lead Free Thin Quad Flat Pack CY37032P44-200JC J67 44-Lead Plastic Leaded Chip Carrier CY37032P44-200JXC J67 44-Lead Lead Free Plastic Leaded Chip Carrier CY37032P44-154AC A44 44-Lead Thin Quad Flat Pack CY37032P44-154JC J67 44-Lead Plastic Leaded Chip Carrier CY37032P44-154AI A44 44-Lead Thin Quad Flat Pack CY37032P44-154AXI A44 44-Lead Lead Free Thin Quad Flat Pack CY37032P44-154JI J67 44-Lead Plastic Leaded Chip Carrier CY37032P44-154JXI J67 44-Lead Lead Free Plastic Leaded Chip Carrier CY37032P44-125AC A44 44-Lead Thin Quad Flat Pack CY37032P44-125AXC A44 44-Lead Lead Free Thin Quad Flat Pack CY37032P44-125JC J67 44-Lead Plastic Leaded Chip Carrier CY37032P44-125JXC J67 44-Lead Lead Free Plastic Leaded Chip Carrier CY37032P44-125AI A44 44-Lead Thin Quad Flat Pack CY37032P44-125JI J67 44-Lead Plastic Leaded Chip Carrier CY37064P44-200AC A44 44-Lead Thin Quad Flat Pack CY37064P44-200AXC A44 44-Lead Lead Free Thin Quad Flat Pack CY37064P44-200JC J67 44-Lead Plastic Leaded Chip Carrier CY37064P44-200JXC J67 44-Lead Lead Free Plastic Leaded Chip Carrier J83 84-Lead Plastic Leaded Chip Carrier CY37064P84-200JC CY37064P100-200AC A100 100-Lead Thin Quad Flat Pack CY37064P100-200AXC A100 100-Lead Lead Free Thin Quad Flat Pack Document #: 38-03007 Rev. *E Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Page 42 of 64 [+] Feedback Ultra37000 CPLD Family 5.0V Ordering Information (continued) Macrocells Speed (MHz) 64 154 Ordering Code Package Type CY37064P44-154AC A44 44-Lead Thin Quad Flat Pack CY37064P44-154JC J67 44-Lead Plastic Leaded Chip Carrier J83 84-Lead Plastic Leaded Chip Carrier CY37064P84-154JC CY37064P100-154AC A100 100-Lead Thin Quad Flat Pack CY37064P44-154AI A44 44-Lead Thin Quad Flat Pack CY37064P44-154AXI A44 44-Lead Lead Free Thin Quad Flat Pack CY37064P44-154JI J67 44-Lead Plastic Leaded Chip Carrier CY37064P44-154JXI J67 44-Lead Lead Free Plastic Leaded Chip Carrier J83 84-Lead Plastic Leaded Chip Carrier CY37064P84-154JI CY37064P100-154AI 125 Package Name A100 Operating Range Commercial Industrial 100-Lead Thin Quad Flat Pack 5962-9951902QYA Y67 44-Lead Ceramic Leadless Chip Carrier Military CY37064P44-125AC A44 44-Lead Thin Quad Flat Pack Commercial CY37064P44-125AXC A44 44-Lead Lead Free Thin Quad Flat Pack CY37064P44-125JC J67 44-Lead Plastic Leaded Chip Carrier CY37064P44-125JXC J67 44-Lead Lead Free Plastic Leaded Chip Carrier CY37064P84-125JC J83 84-Lead Plastic Leaded Chip Carrier CY37064P100-125AC A100 100-Lead Thin Quad Flat Pack CY37064P100-125AXC A100 100-Lead Lead Free Thin Quad Flat Pack CY37064P44-125AI A44 44-Lead Thin Quad Flat Pack CY37064P44-125AXI A44 44-Lead Lead Free Thin Quad Flat Pack CY37064P44-125JI J67 44-Lead Plastic Leaded Chip Carrier CY37064P84-125JI J83 84-Lead Plastic Leaded Chip Carrier CY37064P100-125AI A100 100-Lead Thin Quad Flat Pack CY37064P100-125AXI A100 100-Lead Lead Free Thin Quad Flat Pack 5962-9951901QYA Y67 44-Lead Ceramic Leadless Chip Carrier Document #: 38-03007 Rev. *E Industrial Military Page 43 of 64 [+] Feedback Ultra37000 CPLD Family 5.0V Ordering Information (continued) Macrocells Speed (MHz) 128 167 125 100 Ordering Code 154 125 83 Package Type CY37128P84-167JC J83 84-Lead Plastic Leaded Chip Carrier CY37128P84-167JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier CY37128P100-167AC A100 100-Lead Thin Quad Flat Pack CY37128P100-167AXC A100 100-Lead Lead Free Thin Quad Flat Pack CY37128P160-167AC A160 160-Lead Thin Quad Flat Pack CY37128P160-167AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37128P84-125JC J83 84-Lead Plastic Leaded Chip Carrier CY37128P84-125JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier CY37128P100-125AC A100 100-Lead Thin Quad Flat Pack CY37128P100-125AXC A100 100-Lead Lead Free Thin Quad Flat Pack CY37128P160-125AC A160 160-Lead Thin Quad Flat Pack CY37128P160-125AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37128P84-125JI J83 84-Lead Plastic Leaded Chip Carrier CY37128P84-125JXI J83 84-Lead Lead Free Plastic Leaded Chip Carrier CY37128P100-125AI A100 100-Lead Thin Quad Flat Pack CY37128P100-125AXI A100 100-Lead Lead Free Thin Quad Flat Pack Operating Range Commercial Commercial Industrial CY37128P160-125AI A160 160-Lead Thin Quad Flat Pack CY37128P160-125AXI A160 160-Lead Lead Free Thin Quad Flat Pack 5962-9952102QYA Y84 84-Lead Ceramic Leaded Chip Carrier Military CY37128P84-100JC J83 84-Lead Plastic Leaded Chip Carrier Commercial CY37128P84-100JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier CY37128P100-100AC A100 100-Lead Thin Quad Flat Pack CY37128P100-100AXC A100 100-Lead Lead Free Thin Quad Flat Pack CY37128P160-100AC A160 160-Lead Thin Quad Flat Pack CY37128P160-100AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37128P84-100JI 192 Package Name J83 84-Lead Plastic Leaded Chip Carrier Industrial CY37128P100-100AI A100 100-Lead Thin Quad Flat Pack CY37128P100-100AXI A100 100-Lead Lead Free Thin Quad Flat Pack CY37128P160-100AI A160 160-Lead Thin Quad Flat Pack 5962-9952101QYA Y84 84-Lead Ceramic Leaded Chip Carrier Military CY37192P160-154AC A160 160-Lead Thin Quad Flat Pack Commercial CY37192P160-154AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37192P160-125AC A160 160-Lead Thin Quad Flat Pack CY37192P160-125AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37192P160-125AI A160 160-Lead Thin Quad Flat Pack CY37192P160-125AXI A160 160-Lead Lead Free Thin Quad Flat Pack CY37192P160-83AC A160 160-Lead Thin Quad Flat Pack CY37192P160-83AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37192P160-83AI A160 160-Lead Thin Quad Flat Pack CY37192P160-83AXI A160 160-Lead Lead Free Thin Quad Flat Pack Document #: 38-03007 Rev. *E Commercial Industrial Commercial Industrial Page 44 of 64 [+] Feedback Ultra37000 CPLD Family 5.0V Ordering Information (continued) Macrocells Speed (MHz) 256 154 Ordering Code A160 160-Lead Thin Quad Flat Pack CY37256P160-154AXC A160 160-Lead Lead Free Thin Quad Flat Pack N208 208-Lead Plastic Quad Flat Pack CY37256P256-154BGC BG292 292-Ball Plastic Ball Grid Array CY37256P160-125AC A160 160-Lead Thin Quad Flat Pack CY37256P160-125AXC A160 160-Lead Lead Free Thin Quad Flat Pack N208 208-Lead Plastic Quad Flat Pack CY37256P208-125NC CY37256P256-125BGC BG292 292-Ball Plastic Ball Grid Array CY37256P160-125AI A160 160-Lead Thin Quad Flat Pack CY37256P160-125AXI A160 160-Lead Lead Free Thin Quad Flat Pack N208 208-Lead Plastic Quad Flat Pack CY37256P208-125NI CY37256P256-125BGI 83 Commercial Industrial 292-Ball Plastic Ball Grid Array U162 160-Lead Ceramic Quad Flat Pack Military A160 160-Lead Thin Quad Flat Pack Commercial CY37256P160-83AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37256P208-83NC N208 208-Lead Plastic Quad Flat Pack BG292 292-Ball Plastic Ball Grid Array A160 160-Lead Thin Quad Flat Pack CY37256P160-83AXI A160 160-Lead Lead Free Thin Quad Flat Pack CY37256P208-83NI N208 208-Lead Plastic Quad Flat Pack CY37256P256-83BGI 5962-9952301QZC CY37384P208-125NC CY37384P256-125BGC 83 Commercial 5962-9952302QZC CY37256P160-83AI 125 BG292 Operating Range CY37256P160-83AC CY37256P256-83BGC 384 Package Type CY37256P160-154AC CY37256P208-154NC 125 Package Name CY37384P208-83NC CY37384P256-83BGC CY37384P208-83NI CY37384P256-83BGI Document #: 38-03007 Rev. *E BG292 Industrial 292-Ball Plastic Ball Grid Array U162 160-Lead Ceramic Quad Flat Pack Military N208 208-Lead Plastic Quad Flat Pack Commercial BG292 N208 BG292 N208 BG292 292-Ball Plastic Ball Grid Array 208-Lead Plastic Quad Flat Pack Commercial 292-Ball Plastic Ball Grid Array 208-Lead Plastic Quad Flat Pack Industrial 292-Ball Plastic Ball Grid Array Page 45 of 64 [+] Feedback Ultra37000 CPLD Family 5.0V Ordering Information (continued) Macrocells Speed (MHz) 512 125 100 Ordering Code CY37512P208-125NC N208 CY37512P256-125BGC BG292 CY37512P352-125BGC BG388 CY37512P208-100NC N208 Package Type 208-Lead Plastic Quad Flat Pack BG292 292-Ball Plastic Ball Grid Array BG388 388-Ball Plastic Ball Grid Array N208 BG292 CY37512P352-100BGI BG388 5962-9952502QZC CY37512P208-83NC U208 N208 CY37512P256-83BGC BG292 CY37512P352-83BGC BG388 CY37512P208-83NI N208 208-Lead Plastic Quad Flat Pack Industrial 388-Ball Plastic Ball Grid Array 208-Lead Ceramic Quad Flat Pack Military 208-Lead Plastic Quad Flat Pack Commercial 292-Ball Plastic Ball Grid Array 388-Ball Plastic Ball Grid Array 208-Lead Plastic Quad Flat Pack BG292 292-Ball Plastic Ball Grid Array CY37512P352-83BGI BG388 388-Ball Plastic Ball Grid Array U208 Commercial 292-Ball Plastic Ball Grid Array CY37512P256-83BGI 5962-9952501QZC Commercial 388-Ball Plastic Ball Grid Array 208-Lead Plastic Quad Flat Pack CY37512P352-100BGC CY37512P256-100BGI Operating Range 292-Ball Plastic Ball Grid Array CY37512P256-100BGC CY37512P208-100NI 83 Package Name 208-Lead Ceramic Quad Flat Pack Industrial Military 3.3V Ordering Information Macrocells Speed (MHz) 32 143 100 Ordering Code CY37032VP44-143AC Package Name Package Type A44 44-Lead Thin Quad Flat Pack CY37032VP44-143AXC A44 44-Lead Lead Free Thin Quad Flat Pack CY37032VP48-143BAC BA50 A44 44-Lead Thin Quad Flat Pack CY37032VP44-100AXC A44 44-Lead Lead Free Thin Quad Flat Pack CY37032VP48-100BAC BA50 A44 CY37032VP44-100AXI A44 CY37032VP48-100BAI BA50 Commercial 48-Ball Fine Pitch Ball Grid Array 44-Lead Thin Quad Flat Pack Industrial 44-Lead Lead Free Thin Quad Flat Pack 48-Ball Fine Pitch Ball Grid Array CY37032VP44-100JI J67 44-Lead Plastic Leaded Chip Carrier CY37032VP44-100JXI J67 44-Lead Lead Free Plastic Leaded Chip Carrier Document #: 38-03007 Rev. *E Commercial 48-Ball Fine Pitch Ball Grid Array CY37032VP44-100AC CY37032VP44-100AI Operating Range Page 46 of 64 [+] Feedback Ultra37000 CPLD Family 3.3V Ordering Information (continued) Macrocells Speed (MHz) 64 143 100 128 125 83 192 100 66 Ordering Code Package Name Package Type CY37064VP44-143AC A44 44-Lead Thin Quad Flatpack CY37064VP44-143AXC A44 44-Lead Lead Free Thin Quad Flatpack CY37064VP48-143BAC BA50 48-Ball Fine-Pitch Ball Grid Array CY37064VP100-143AC A100 100-Lead Thin Quad Flatpack CY37064VP100-143AXC A100 100-Lead Lead Free Thin Quad Flatpack CY37064VP100-143BBC BB100 Operating Range Commercial 100-Ball Fine-Pitch Ball Grid Array CY37064VP44-100AC A44 44-Lead Thin Quad Flatpack CY37064VP44-100AXC A44 44-Lead Lead Free Thin Quad Flatpack CY37064VP48-100BAC BA50 48-Ball Fine-Pitch Ball Grid Array CY37064VP100-100AC A100 100-Lead Thin Quad Flatpack CY37064VP100-100AXC A100 100-Lead Lead Free Thin Quad Flatpack CY37064VP100-100BBC BB100 Commercial 100-Ball Fine-Pitch Ball Grid Array CY37064VP44-100AI A44 44-Lead Thin Quad Flatpack CY37064VP44-100AXI A44 44-Lead Lead Free Thin Quad Flatpack CY37064VP48-100BAI BA50 48-Ball Fine-Pitch Ball Grid Array CY37064VP100-100BBI BB100 100-Ball Fine-Pitch Ball Grid Array Industrial CY37064VP100-100AI A100 100-Lead Thin Quad Flatpack CY37064VP100-100AXI A100 100-Lead Lead Free Thin Quad Flatpack 5962-9952001QYA Y67 44-Lead Ceramic Leaded Chip Carrier Military CY37128VP100-125AC A100 100-Lead Thin Quad Flat Pack Commercial CY37128VP100-125AXC A100 100-Lead Lead Free Thin Quad Flat Pack CY37128VP100-125BBC BB100 100-Ball Fine-Pitch Ball Grid Array CY37128VP160-125AC A160 160-Lead Thin Quad Flat Pack CY37128VP160-125AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37128VP160-125AI A160 160-Lead Thin Quad Flat Pack CY37128VP160-125AXI A160 160-Lead Lead Free Thin Quad Flat Pack CY37128VP100-83AC A100 100-Lead Thin Quad Flat Pack CY37128VP100-83AXC A100 100-Lead Lead Free Thin Quad Flat Pack CY37128VP100-83BBC BB100 Industrial Commercial 100-Ball Fine-Pitch Ball Grid Array CY37128VP160-83AC A160 160-Lead Thin Quad Flat Pack CY37128VP160-83AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37128VP100-83AI A100 100-Lead Thin Quad Flat Pack CY37128VP100-83AXI A100 100-Lead Lead Free Thin Quad Flat Pack CY37128VP100-83BBI BB100 Industrial 100-Ball Fine-Pitch Ball Grid Array CY37128VP160-83AI A160 160-Lead Thin Quad Flat Pack CY37128VP160-83AXI A160 160-Lead Lead Free Thin Quad Flat Pack 5962-9952201QYA Y84 84-Lead Ceramic Leaded Chip Carrier Military CY37192VP160-100AC A160 160-Lead Thin Quad Flat Pack Commercial CY37192VP160-100AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37192VP160-66AC A160 160-Lead Thin Quad Flat Pack CY37192VP160-66AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37192VP160-66AI A160 160-Lead Thin Quad Flat Pack Document #: 38-03007 Rev. *E Commercial Industrial Page 47 of 64 [+] Feedback Ultra37000 CPLD Family 3.3V Ordering Information (continued) Macrocells Speed (MHz) 256 100 Ordering Code A160 160-Lead Thin Quad Flat Pack CY37256VP160-100AXC A160 160-Lead Lead Free Thin Quad Flat Pack N208 208-Lead Plastic Quad Flat Pack CY37256VP256-100BGC BG292 292-Ball Plastic Ball Grid Array CY37256VP256-100BBC BB256 256-Ball Fine-Pitch Ball Grid Array CY37256VP160-100AI A160 160-Lead Thin Quad Flat Pack CY37256VP160-100AXI A160 160-Lead Lead Free Thin Quad Flat Pack CY37256VP160-66AC A160 160-Lead Thin Quad Flat Pack CY37256VP160-66AXC A160 160-Lead Lead Free Thin Quad Flat Pack CY37256VP208-66NC N208 208-Lead Plastic Quad Flat Pack CY37256VP256-66BGC BG292 292-Ball Plastic Ball Grid Array CY37256VP256-66BBC BB256 256-Ball Fine-Pitch Ball Grid Array CY37256VP160-66AI 83 292-Ball Plastic Ball Grid Array CY37256VP256-66BBI BB256 256-Ball Fine-Pitch Ball Grid Array U162 160-Lead Ceramic Quad Flat Pack Military N208 208-Lead Plastic Quad Flat Pack Commercial CY37384VP208-83NC CY37384VP208-66NC CY37384VP256-66BGI 66 Commercial 160-Lead Thin Quad Flat Pack CY37384VP208-66NI 83 Industrial A160 CY37384VP256-66BGC 512 Commercial BG292 CY37384VP256-83BGC 66 Operating Range CY37256VP256-66BGI 5962-9952401QZC 384 Package Type CY37256VP160-100AC CY37256VP208-100NC 66 Package Name CY37512VP208-83NC BG292 N208 BG292 N208 BG292 N208 292-Ball Plastic Ball Grid Array 208-Lead Plastic Quad Flat Pack 208-Lead Plastic Quad Flat Pack 208-Lead Plastic Quad Flat Pack CY37512VP352-83BGC BG388 388-Ball Plastic Ball Grid Array CY37512VP400-83BBC BB400 400-Ball Fine-Pitch Ball Grid Array N208 208-Lead Plastic Quad Flat Pack Commercial 292-Ball Plastic Ball Grid Array CY37512VP256-66BGC BG292 CY37512VP352-66BGC BG388 388-Ball Plastic Ball Grid Array CY37512VP400-66BBC BB400 400-Ball Fine-Pitch Ball Grid Array N208 208-Lead Plastic Quad Flat Pack Commercial 292-Ball Plastic Ball Grid Array CY37512VP256-66BGI BG292 CY37512VP352-66BGI BG388 388-Ball Plastic Ball Grid Array CY37512VP400-66BBI BB400 400-Ball Fine-Pitch Ball Grid Array 5962-9952601QZC U208 208-Lead Ceramic Quad Flat Pack Document #: 38-03007 Rev. *E Industrial 292-Ball Plastic Ball Grid Array BG292 CY37512VP208-66NI Commercial 292-Ball Plastic Ball Grid Array CY37512VP256-83BGC CY37512VP208-66NC Industrial Industrial 292-Ball Plastic Ball Grid Array Military Page 48 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams 44-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack A44 51-85064-*B 44-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J67 51-85003-*A Document #: 38-03007 Rev. *E Page 49 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 44-Lead Ceramic Leaded Chip Carrier Y67 51-80014-** Document #: 38-03007 Rev. *E Page 50 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 48-Ball (7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch) Thin BGA BA48D 51-85109-*C 84-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J83 51-85006-*A Document #: 38-03007 Rev. *E Page 51 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 84-Lead Ceramic Leaded Chip Carrier Y84 51-80095-*A Document #: 38-03007 Rev. *E Page 52 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 100-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-*B Document #: 38-03007 Rev. *E Page 53 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100 51-85107-*B Document #: 38-03007 Rev. *E Page 54 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 160-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm) (TQFP) A160 51-85049-*B Document #: 38-03007 Rev. *E Page 55 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 160-Lead Ceramic Quad Flatpack (Cavity Up) U162 25.350.10 (.998.004) TYP. DIMENSION IN MM (INCH) REFERENCE JEDEC: N/A PKG. WEIGHT: 6-7gms PIN 1 0.650(.0256) TYP. 0.300(.012) TYP. R 0.13(.005) MIN. 0-7 28.00 0.10 (1.102 .004) SQ. 0.20 MIN. (.008 MIN.) 0 MIN. 31.20 0.25 (1.228 .010) SQ. SEATING PLANE DETAIL A SEE DETAIL A 2.03(.080) 2.79(.110) 0.15 0.02 (.006 .001) 0.050(.002) 0.500(.020) 0.51 0.20 (.020 .008) 51-80106-*A Document #: 38-03007 Rev. *E Page 56 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 208-Lead Plastic Quad Flatpack N208 51-85069-*B Document #: 38-03007 Rev. *E Page 57 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 208-Lead Ceramic Quad Flatpack (Cavity Up) U208 DIMENSIONS IN MM (INCH) PIN 1 REFERENCE JEDEC: N/A PKG. WEIGHT: 6-7gms 0.50(.0197) TYP. 0.20(.008) TYP. R 0.13(.005) MIN. 0-7 28.00 0.10 (1.102 .008) SQ. 0.20 MIN. (.008 MIN.) 31.22 0.25 (1.229 .010) SQ. 0 MIN. DETAIL A SEE DETAIL A 3.43(.135) 3.94(.155) SEATING PLANE 0.15 0.02 (.006 .001) 0.050(.002) 0.500(.020) 0.51 0.20 (.020 .008) 51-80105-*B Document #: 38-03007 Rev. *E Page 58 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 256-Ball FBGA (17 x 17 mm) BB256 TOP VIEW BOTTOM VIEW O0.05 M C O0.25 M C A B PIN 1 CORNER O0.450.05(256X)-CPLD DEVICES (37K & 39K) PIN 1 CORNER +0.10 -0.05 O0.50 (256X)-ALL OTHER DEVICES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A A B B C D 1.00 C D E E F F G H J K H 15.00 17.000.10 G J K L M 7.50 L M N N P P R R T T 1.00 7.50 0.15 C 0.700.05 0.25 C B 15.00 A 17.000.10 A 0.20(4X) SEATING PLANE +0.10 -0.05 C A1 0.36 0.56 REFERENCE JEDEC MO-192 0.35 A1 A 1.40 MAX. 1.70 MAX. 51-85108-*F Document #: 38-03007 Rev. *E Page 59 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 292-Ball Plastic Ball Grid Array PBGA (27 x 27 x 2.33 mm) BG292 51-85097-*B Document #: 38-03007 Rev. *E Page 60 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 388-Ball Plastic Ball Grid Array PBGA (35 x 35 x 2.33 mm) BG388 51-85103-*C Document #: 38-03007 Rev. *E Page 61 of 64 [+] Feedback Ultra37000 CPLD Family Package Diagrams (continued) 400-Ball FBGA (21 x 21 x 1.4 mm) BB400 51-85111-*A ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trademark of Microsoft Corporation. Warp is a registered trademark, and In-System Reprogrammable, ISR, Warp Professional, Warp Enterprise, and Ultra37000 are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-03007 Rev. *E Page 62 of 64 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback Ultra37000 CPLD Family Addendum 3.3V Operating Range (CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC) Range Commercial Document #: 38-03007 Rev. *E Ambient Temperature[2] Junction Temperature VCC 0C to +70C 0C to +90C 3.3V 0.16V Page 63 of 64 [+] Feedback Ultra37000 CPLD Family Document History Page Document Title: Ultra37000 CPLD Family 5V, 3.3V, ISRTM High-Performance CPLDs Document Number: 38-03007 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106272 04/18/01 SZV Change from Spec number: 38-00475 to 38-03007 *A 124942 03/21/03 OOR Updated 3.3V VCC requirements for -144 speeds Added an Addendum *B 126262 05/09/03 TEH Changed pinout for CY37128V BB100 package *C 128125 07/16/03 HOM Obsoleted following 3.3V PLCC packaged devices: CY37032VP44-143JC CY37032VP44-100JC CY37032VP44-100JI CY37064VP44-143JC CY37064VP84-143JC CY37064VP44-100JC CY37064VP84-100JC CY37064VP44-100JI CY37064VP84-100JI CY37128VP84-125JC CY37128VP84-83JC CY37128VP84-83JI *D 282709 See ECN YDT Changed package diagrams and labels for consistency Added Lead (Pb)-free logo on first page, as well as a note in Features Added Lead (Pb)-free package diagram labels Added Lead-free Parts to Ordering Information CY37032P44-200AXC, CY37032P44-200JXC, CY37032P44-154AXI, CY37032P44-154JXI, CY37032P44-125AXC, CY37032P44-125JXC, CY37064P44-200AXC, CY37064P44-200JXC, CY37064P100-200AXC, CY37064P44-154AXI, CY37064P44-154JXI, CY37064P44-125AXC, CY37064P44-125JXC, CY37064P100-125AXC, CY37064P44-125AXI, CY37064P100-125AXI, CY37128P84-167JXC, CY37128P100-167AXC, CY37128P160-167AXC, CY37128P84-125JXC, CY37128P100-125AXC, CY37128P160-125AXC, CY37128P84-125JXI, CY37128P100-125AXI, CY37128P160-125AXI, CY37128P84-100JXC, CY37128P100-100AXC, CY37128P160-100AXC, CY37128P100-100AXI, CY37192P160-154AXC, CY37192P160-125AXC, CY37192P160-125AXI, CY37192P160-83AXC, CY37192P160-83AXI, CY37256P160-154AXC, CY37256P160-125AXC, CY37256P160-125AXI, CY37256P160-83AXC, CY37256P160-83AXI, CY37032VP44-143AXC, CY37032VP44-100AXC, CY37032VP44-100AXI, CY37032VP44-100JXI, CY37064VP44-143AXC, CY37064VP100-143AXC, CY37064VP44-100AXC, CY37064VP100-100AXC, CY37064VP44-100AXI, CY37064VP100-100AXI, CY37128VP100-125AXC, CY37128VP160-125AXC, CY37128VP160-125AXI, CY37128VP100-83AXC, CY37128VP160-83AXC, CY37128VP100-83AXI, CY37128VP160-83AXI, CY37192VP160-100AXC, CY37192VP160-66AXC, CY37256VP160-100AXC, CY37256VP160-100AXI, CY37256VP160-66AXC *E 321635 See ECN PCX Added Package Diagram BG292 Updated all PBGA package type information (BG292 & BG388) Document #: 38-03007 Rev. *E Page 64 of 64 [+] Feedback