EP82562ETSL7RM - Intel - searchdatasheet.com

82562ET 10/100 Mbps Platform LAN

Connect (PLC)

Networking Silicon

Dat ash e et

Pr oduct Features

■IEEE 802.3 10BASE-T/100BASE-TX

co mplian t physi cal la yer interface

■IEEE 802.3u Auto-Negotiation support

■Digital Adaptive Equalization control

■Link status interrupt ca pability

■XOR tree mode support

■3-port LED support (speed, link and

activity)

■10BASE-T aut o-polarity co rrec tion

■LAN Connect Inte r face

■Diagnostic loopback m ode

■1:1 transmit tra nsformer ratio support

■Low power (less tha n 300 mW in active

transmit mode)

■Reduced power in “unpl ugged mode” (less

than 5 0 m W)

■Automatic detection of “unplugged mode”

■3.3 V device

■48- p in Sh r in k Sm al l O u tl ine Pac ka ge

Revision 1.3

March 2003

Datasheet

Information in this document is provided in connection with Intel® products. No license, e xpress or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating

to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or ch aracteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82562ET PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Current characteriz ed errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are ref erenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

* Other brands and names are the property of their respectiv e owners.

Datasheet iii

Networking Silicon — 82562ET

Revision History

Revision Revision Date Description

1.3 M arch 2003 Adde d product ordering code in Section 1.0.

1.2 October 2001 Removed confidential status.

• Removed sections: “Physical Layer Interface Functionality” and “Platform

LAN Connect”.

• Changed “El ectrical and Ti ming S pecificat ions” sect ion to “Voltage and Tem -

pera ture Specificatio ns” a nd removed timing specificat ions.

1.1 June 2000 Advance Information Datasheet release (Intel Confidential).

• On cover page, r eplace d Boun dary Scan Su pport with XOR tree mode s up-

port. Added bullet for LAN Connec t I/F.

• Pg. 3, added a Solution Bloc k Di agram as included in OR-2338 Pg. 4 b ut

replaced EM with ET in diagram.

• Pg. 11, remo ved Figure 4, “N RZ to MLT-3 Encoding Diag ram”.

• Pg. 35, changed the Rev. number on the 82 562 Pinout symbol to 1.0.

1.0 May 2000 Advance Information Datasheet release (Intel Secret).

• Mo dif ie d Tab le 1 “ 82 56 2ET Har d wa r e Co nf ig ur at ion” t o add o ne r o w for XOR

Tree and include column f or comments.

• Updated t he descrition of t he Act ivity LED signal in Section 3.6, “LED Pins” .

• Rev ised Section 3.7 , “Mi scellaneous Control Pins” to reflect refere nces to

Table 1 “82562ET Hardware Configuration”.

• Updated Secti on 4.0, “Voltage and Temperatur e Sp ecifications”.

• Replaced diagrams in S ection 5.1 , “Package Informat ion”.

0.6 Nov. 1999 • Corrected Figure 4 “NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect

correct signal transi tion s.

• Removed “10BASE-T Error Detection and Reporting” section since the

82562 does not do 10BASE-T error reporting.

0.55 Sept. 1999 Init ial release.

82562ET — Networking Silicon

iv Datasheet

 Datasheet  v
 
Networking Silicon — 82562ET
Contents
0 Introduction.........................................................................................................................1
1 Overview ...............................................................................................................1
2 Features................................................................................................................1
3 References............................................................................................................1
0 82562ET  Architect ural Overview........................................... ............................... ..............3
0 82562ET  Signal Descript ions............................................................ .................................5
1 Signal Type Definitions ..................... ....... ....... ....... .......... ....... ....... ....... ....... ....... ..5
2 Twisted Pair Ethernet (TPE) Pins .........................................................................5
3 Exte r n a l Bi a s Pins  ................................................................................................5
4 Clock Pins ............................................................................................................6
5 Platform LAN Connect Interface Pins....................................................................6
6 LED Pins  ..............................................................................................................7
7 Miscella n eous Control Pi n s ..... .............................................................................7
8 Power and Ground Conn ec tions ...................... ................... .............. ...................8
0 Voltage and Temperat ure S pecifications .............................. .......................... ...................9
1 Absolute Maximum Ratings...................................................................................9
2 DC Characteristics  ...............................................................................................9
2.1 X1 Clock DC Speci fi c a tions .... .... ..... ..... ...................................................9
2.2 LAN Connec t Interface DC Specifications .............................................10
2.3 LED DC Specifications ..........................................................................10
2.4 10BASE-T Voltage and Current DC Specifications ...............................10
2.5 100 BASE-TX Vo ltage and Current DC Specifications  .. ........................11
0 Package and Pi nout Information... .......................... .........................................................13
1 Package Inform ation ...........................................................................................13
2 Pinout Information ............................................. ................... .............. .................14
2.1 8256 2E T Pin Assignment s .... ................................. ...............................14
2.2 8256 2E T Shrink Small Outlying Package Diagram  .............. .................15

82562ET — Networking Silicon

vi Datasheet

Networking Silicon — 82562ET

Datasheet 1

1.0 Introduction

1.1 Overview

The Intel® 82562ET is a highly-integrated Platform LAN Connect device designed for 10 or 100

Mbps Eth ernet syst ems. It is based on the IE EE 10 BAS E-T and 100B AS E-TX sta ndards. The IE EE

802.3u standard for 100BASE-TX def ines networking over two pairs of Categor y 5 unshielded

twisted pair cable or Type 1 shielded twisted pair cable.

The 825 62ET compl ies with th e IEEE 802. 3u Auto- Negoti at ion st andard a nd the IEEE 80 2.3x Full

Duplex Flow Control s tandard. T he 82563ET also includes a PHY inte rface compliant to the

current platform LAN connect interface.

1.2 Features

•IEEE 802.3 10BA S E-T/100BASE-TX compliant physi cal layer interfa ce

•IEEE 802.3u Auto-Negoti ation support

•Dig ital Adaptive Equa liza tion cont r o l

•Link status interrupt capabil ity

•XOR Tree mode support for board testing

•3-port L ED support (speed, link and activity)

•10BASE- T aut o-polarity corre ction

•Diagnostic loopback mode

•1:1 transmit transformer ratio support

•Low power (less than 300 mW in active transmit mode)

•Reduced power in “unplugged mode” (less than 50 mW)

•Automa tic detec tion of “unplugged mode”

•3.3 V device

•48- pin S hrink Smal l Outline P ackage

•Platform LAN connect interface support

1.3 References

•IEEE 802. 3 St anda rd for Local and Metropolitan Area Network s, Institute of Electri ca l and

Electronics Engineers

•82555 10/100 Mbps LAN Physical Layer Interface Datasheet, Intel Corporation

•LAN Connect Interface Specification, Intel Corporation

82562ET — Networking Silicon

2 Datasheet

1.4 Product Code

The pr oduct ordering code for the 82562ET is: DA825 62ET.

Networking Silicon — 82562ET

Datasheet 3

2.0 82562ET Architect ural Overview

The 82562 ET is a highly in tegra ted Plat form LAN Connect de vic e that combin es a 10B ASE-T an d

100BASE-TX physica l layer interface s. The 82562ET supports a single interface fully comp liant

with the IEEE 802.3 standard. Fi gure 1 provides a block diagram of the 82562ET architecture.

The 8252ET is a 3.3 V device in a 48-pin Shrink Small Outline Package (SSOP). This document

des cribes the architec ture of the device in all modes of ope ration.

Four pins, test Enable (TESTEN), Test Clock (IS OL_TCK), Test Input (ISOL_TI), and Test

Exe cute (ISOL_EX) , define the general ope ration of the de vic e. Table 1 shows the pin settings for

the different modes of operation.

NOTE: Combinations not shown in Table 1 are reserved and should not be used.

Figure 1. 82562ET Block Diagram

Equalizer &

BLW correction

CRS/Link 10

Detection

Digital Clock

Rec overy (100)

Digital Clock

Rec overy (10)

Digital

Equalizer

Adaptation

100Base-TX

PCS

Transmit DAC

10/100

Clock

Generator

RDN/RDP

TDN/ TDP

LAN

Connect

Interface

Port LE D

Drivers

LILED

ACTLED

SPEEDLED

Auto-

Negotiation

Control

Registers

10Base-T

PCS

MDI/MDI-X

LAN_RSTSYNC

LAN_TXD[2:0]

LAN_RXD[2:0]

LAN_CLK

Bias & Band-

Gap Voltage

Circuit

X2X1 Crystal

25 MHz

Table 1. 82562ET Hardware Confi gurati on

Mode of Operation TESTEN ISOL_TCK ISOL_TI ISOL_EX Comments

Normal operating

mode 0 0 0 0 The ISOL_TCK, ISOL_TI,

and ISOL_EX pins can

remain floating.

Isolate mode

(Tri-sta te and full

power-down mode)

0111

The device is in tri-state

and pow er-dow n mod e.

1111

The device is in tri-state

and t he full y pow e r ed

down.

XOR Tree 1000

The XOR Tree is used for

boar d tes t in g an d tr i -s tate

mode.

82562ET — Networking Silicon

4 Datasheet

Figure 2. 82562ET Solution Overview

Control

ProcesorVRM Clock

ADDR

DATA

CTRL

Termination

ADDR

DATA

CTRL

ICH2

2 RIMM

Modules

MCH

82562ET

PLC

I D E Pr imary

AMC97

Audio/

Modem

USB Port 2

USB Port 1

IDE

Secondary

PCI Connector 1

PCI Connector 3

PCI Connector 2

PCI Control Bus

PCI Address /Data Bus

82550 LAN

Controller

Game ConnParallelFloppy

Mouse

Keyboard

Serial 1

SIO

UltraDMA/33

USB

AC97 Link

LPC Bus

Address/Data

Networking Silicon — 82562ET

Datasheet 5

3.0 82562ET Sig nal Descriptions

3.1 Signal Type Definitions

3.2 Twisted Pair Ethernet (TPE) Pins

3.3 External Bias Pins

Type Name Description

I Input Input pin to the 82562ET.

O Out put Output pin from the 82562ET.

I/O Input /Output Mu ltiplexed input and output pin to and from the 82562ET.

MLT Multi-lev el

analog I/O Multi-lev el analog pin used for i nput and output.

BBias Bias pin used for ground connection through a resistor or an external voltage

reference.

DPS Digital Power

Supply Digita l power or g rou nd pin for the 82562ET.

APS Analog Power

Supply Analog power or ground pin for the 82562ET.

Pin Name Pin

Number Type Description

TDP

TDN 10

11 MLT Transmit Differential Pair. The transmit differential pair sends serial bit

streams to the unshielded twisted pair (UTP) cable. The differential pair is

a two-level signal in 10BASE-T (Manchester) mode and a three-level

signal in 100BASE-TX mode (ML T-3). These signals directly interface with

the isolation transformer.

RDP

RDN 15

16 MLT Receive Differential Pair. The receive dif ferential pa ir receive the seria l

bit stream from an unshielded twisted pair (UTP) cable. The diff erential

pair is a tw o-level signal in 10BASE-T mode (Manchester) or a three-lev el

signal in 100BASE-TX mode (ML T-3). These signals directly interface with

an isolation t ra nsformer.

Pin Name Pin

Number Type Description

RBIAS10 4 B Bias Reference Resistor 10. T his pin should be con nected to a 549 Ω

pull-down resistor.a

a. 549 Ω for RBIAS10 is only a recommended value and should be fine tuned for v arious designs.

RBIAS100 5 B Bias reference Resistor 100. Th is pin should be co nnected to a 6 19 Ω

pull-down resistor.b

b. 619 Ω for RBIAS100 is only a recommended value and should be fine tuned for various designs.

82562ET — Networking Silicon

6 Datasheet

3.4 Clock Pins

3.5 Platform LAN Con nect Interface Pins

Pin Name Pin

Number Type Description

X1 46 I Crystal Inp ut Clock. X1 and X2 can be driven by an external 25 MHz

crystal of 50 PPM or better. Otherwise, X1 is driven by an external metal-

oxide semiconductor (MOS) level 25 MHz oscillator when X2 is left

floating.

X2 47 O Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz

c rystal of 50 PPM or better.

Pin Name Pin

Number Type Description

LAN_CLK 39 O LAN Connect Clock. The LAN Connect Cloc k is driv en by the 82562ET

on two frequencies depending on oper ation speed. When the 82562ET is

in 100BASE-TX mode, LAN_CLK drives a 50 MHz clock. Otherwise,

LAN_CLK drives a 5 MHz clock for 10BASE-T. The LAN_CLK does not

s top during normal operation.

LAN_

RSTSYNC 42 I Reset/Synchronize. This is a mul tiplexe d pin and is driven by the Media

Access Control (MAC) layer device. Its functions are:

• Reset. When this pin is asserted beyond one LAN Connect clock

period, the 82562ET uses this signal Re set . To ensure reset of the

82562ET, the Reset signal should remain active for at least 500

µseconds.

• Syn chr onize. When this pin is activated synchrono usly, for only one

LAN C on nec t cl oc k pe riod , it i s u se d t o sync hr oni z e th e M A C an d PH Y

on LAN Connect word boundaries.

LAN_

TXD[2:0] 45, 44,

43 ILAN Connect Transmit Data. The LAN Connect transmit pins are used

to transfer data from the MAC device to the 82562ET. These pins are

used to move transmitted data and real time control and management

data. They also transmit out of band control data from the MAC to the

PHY. The pins should be fully synchronous to LAN_CLK.

LAN_

RXD[2:0] 37, 35,

34 OLAN Connect Receive Data. The LAN Connect receive pins are used to

tran s fer da ta fro m the 825 62ET to t h e MAC devi ce. Thes e pins ar e us ed

to move received data and real time control and management data. They

also move out of band control data from the PHY to the MAC. These pins

are synchronous to LAN_CLK.

Networking Silicon — 82562ET

Datasheet 7

3.6 LED Pins

3.7 Miscellaneous Control Pins

Pin Name Pin

Number Type Description

LILED# 27 O Link Integrity LED . The LED is active low and t he Link Inte gri ty LED pin

indicates link status in either 10BASE-T or 100BASE-TX mode. If a link is

present in either mode, the LILED is ass erted.

ACTLED# 32 O Activity LED. The LED i s acti v e l ow an d t he Act ivi ty LED si gn al in di ca tes

either receive or transmit activity. When no activity is present, the LED is

off. The Act iv ity LED will fli cker whe n ac tiv it y is pres en t. The flicker rate

depends on the activity load.

The individual address LED control bit (Word A hexadecimal, bit 4) in the

ICH2 EEPROM can select the ACTLED# behavior. It controls the Activity

LED (ACTLED) functionality in Wake on LAN (WOL) mode.

0 = In WOL mode, the ACTLED is activated by the transmission and

recep tion of broadcast and individua l address mat ch packets.

1 = In WOL mode, the ACTLED is activated by the transmission and

recep tion of individu al address match pac kets only.

This bit is configured by the OEM and is activated by a transmission and

recep tion of individu al address mat c h pac kets.

SPDLED# 31 O Speed LED. The LED is active low and the Speed LED signal indicates

the speed of operation, either 10 Mbps or 100 Mbps. The Speed LED is

on during 100BASE-TX operation and off in 10BASE-T mode.

Pin Name Pin

Number Type Description

ADV10 41 I Advertise 10 Mbps Only. Th e Ad v ertis e 1 0 Mbp s On l y si gnal i s ass erted

high, and the 82562ET adv ertises only 10BASE-T technology during

Auto-Negotiation processes in this state. Otherwise, the 82562ET

advertises all of its technologies.

Not e: A DV10 has an internal pull -down resistor.

ISOL_TCK 30 I Test Clock. The Test Clock signal sets the device into asynchronous test

mode in co njunction with the Test Input, Test Execute an d Test Enable

pins (r efer to Table 1).

In the manufacturing test mode, it acts as the test clock.

Note: ISOL_TCK has an internal pull-down resistor .

ISOL_TI 28 I Test Input. The Test Input signal sets the device into asynchronous t est

mode in co njunction with the Test Cl ock, Test Exec ute and Test Enabl e

pins (r efer to Table 1).

In the manufacturing test mode, it acts as the test data input pin.

Note: ISOL_TI has an internal pull-down resistor.

82562ET — Networking Silicon

8 Datasheet

3.8 Pow er and Ground Connections

ISOL_TEX 29 I Test Exec u te. The Test Ex ecute signal sets the device into asynchronous

test mode in conjunction with the Test Clock, Test Input, and Test Enable

pins (refer to Table 1).

In the manufacturing test mode, it places the command that was entered

through t he TI pin in the instruction register.

Note: ISOL_TEX has an internal pull-down resistor.

TOUT 26 O Test O utput. Th e Test Ou tput pi n i s us ed f or Bou nd ary XO R sca n o utpu t .

In the manufacturing test mode, it acts as the test output port.

TESTEN 21 I Test Ena ble . The Test Ena b l e p in is us ed to en abl e te st mo de an d sh ould

be pulled down to VSS t o al low XO R Tree tes t mo de.

Pin Name Pin

Number Type Description

VCC

VCCP

VCCA

VCCA2

VCCT

1, 25

36, 40

9, 12 ,

14, 17

DPS Digital 3.3 V Po wer. These pins should be connec ted to th e main dig ita l

power supply.

VSS

VSSP

VSSA

VSSA2

8, 13 , 18

24, 48

33, 38

DPS Digital Ground. These pins should be connecte d to t he main digit al

ground.

VCCR 1 9, 23 APS Analog Powe r.

VSSR 20, 22 APS Analog Ground. These pins should not be isolated from the main digital.

Pin Name Pin

Number Type Description

Networking Silicon — 82562ET

Datasheet 9

4.0 Volta ge and Temperature Specifications

4.1 Absolute Maximum Ratings

Maximum ratings are listed below:

Cas e Tempera ture under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 135 C

Sto r age Temper ature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 150 C

Suppl y Voltage with respect to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.45 V

Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 3.45 V

Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 3.45 V

Stresses abo ve the listed absol ute maximum ratings may cause permane nt damage to the 82562ET

device. This is a stress rating only and functional operations of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolu te maximu m rat ing condit ion s for ext ended periods may affe ct de vice rel iabil it y.

4.2 DC Cha racteristics

4.2.1 X1 Clock DC Specifications

NOTES:

1. This characteristic is only characterized, not tested. It is valid for digital pins only.

Table 2. General DC Sp ecifications

Symbol Parameter Condition Min Typical Max Units Notes

VCC Supply Voltage 3.0 3.3 3.45 V

T Temperature Minimum/Maximum Case

Temperature 085C

PPower

Consumption

10/100Mbps (transmitter

on) 300 mW

Reduced Power 50 mW

Auto-Negotiation 200 mW

Table 3. X1 Clock DC Specification s

Symbol Parameter Condition Min Typical Max Units Notes

VIL Input Low V o ltage 0.8 V

VIH Input High

Voltage 2.0 V

IILIH Inp ut Lea kage

Currents 0 < VIN < VCC ±10 µA

CIInput

Capacitance 8pF 1

82562ET — Networking Silicon

10 Datasheet

4.2.2 LAN Connect Interface DC Specifications

NOTES:

1. This characteristic is only characterized, not tested. It is valid f or digital pins only.

4. 2.3 L E D DC Specif icati ons

4.2.4 10BASE-T Voltage and Current DC Specifications

NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3. 3 V.

1. RL i s the r esistive load measured ac ros s the t ransmit differential pins, TDP an d TDN .

Table 4. LAN Con nect Interface DC Specifications

Symbol Parameter Condition Min Typical Max Units Notes

VCCJ Input/Output

Supply Voltage 3.0 3.45 V

VIL Input Low Voltage -0.5 0.3VCCJ V

VIH Input High

Voltage 0.6VCCJ VCCJ +

0.5 V

IIL Input Leakag e

Current 0 < V IN < VCCJ ±10 µA

VOL Output Low

Voltage IOUT = 1 500 µA 0.1VCCJ V

VOH Output High

Voltage IOUT = -500 µA 0.9VCCJ V

CIN Input Pin

Capacitance 8pF1

Table 5. LED DC Specifications

Symbol Parameter Condition Min Typical Max Units Notes

VOLLED Output Low

Voltage IOUT = 1 0 m A 0.7 V

VOHLED Out put High

Voltage IOUT = -10 mA 2.4 V

Table 6. 10BASE-T Transmitter

Symbol Parameter Condition Min Typical Max Units Notes

VOD10 Output Differential

Peak Voltage RL = 100 Ω2.2 2.8 V 1

Networking Silicon — 82562ET

Datasheet 11

NOTES:

1. The input diff erential resistance is measured across the receive differential pins, RDP and RDN.

4.2.5 100BASE-TX Voltage and Current DC Specifications

NOTES:Current is me asured between the transmit differ enti al pins (TDP and TDN ) at 3.3 V.

1. RL is the res istive load measured across the transmit differe nti al pins, TDP and TDN .

NOTES:

1. The input diff erential resistance is measured across the receive differential pins, RDP and RDN.

Table 7. 10BASE-T Receiver

Symbol Parameter Condition Min Typical Max Units Notes

RID10 Input Differential

Resistance DC 10 KΩ1

VIDA10 Input Differential

Accept Peak

Voltage 5 MH z ≤ f ≤ 10 MHz 585 3100 mV

VIDR10 Input Differential

Reject Peak

Voltage 5 MH z ≤ f ≤ 10 MHz 300 mV

VICM10 Input Common

Mode Voltage VCC/2 V

Table 8. 100BASE-TX Trans m itter

Symbol Parameter Condition Min Typical Max Units Notes

VOD100 Output Differential

Peak Voltage RL = 100 Ω0.95 1.0 1.05 V 1

Table 9. 100BASE-TX Receiver

Symbol Parameter Condition Min Typical Max Units Notes

RID100 Input Differential

Resistance DC 10 KΩ1

VIDA100 Input Differential

Accept Peak

Voltage 500 1200 mV

VIDR100 Input Diff erential

Reject Peak

Voltage 100 mV

VICM100 Input Common

Mode Voltage VCC/2 V

82562ET — Networking Silicon

12 Datasheet

Networking Silicon — 82562ET

Datasheet 13

5.0 Package and Pinout Information

5.1 Package Information

The 82562ET is a 48-pin Shrink Small Outlying Package (SSOP). The Package dimensions are

shown in Figure 3. More information on Intel device packa ging is available in the Intel Pac kaging

Handbook, which is av ailable from the Int el L iterature Center or your local s ales of fice.

Figure 3. Dimension Diagram for the 82562ET 48-pin SSOP

82562ET — Network i ng S il i con

14 Datasheet

5.2 Pinout Information

5.2.1 82562ET Pin Assignments

Table 10. 82562ET Pin Assignments

Number Pin Name Pin

Number Pin Nam e Pin

Number Pin Name Pin

Number Pin Name

1 VCC 13 VSS 25 VCC 37 LAN_RXD2

2 VCCA 14 VCCT 26 TOUT 38 VSSP

3 VSSA 15 RDP 27 LILED 39 LAN_CLK

4 RBIAS10 16 RDN 28 ISOL_TI 40 VCCP

5 RBIAS100 17 VCCT 29 ISOL_TEX 41 ADV10

6 VSSA2 18 VSS 30 ISOL_TCK 42 LAN_RSTSYNC

7 VCCA2 19 VCCR 31 SPDLED 43 LAN_TXD0

8 VSS 20 VSSR 32 ACTLED 44 LAN_TXD1

9 VCCT 21 TESTEN 33 VSSP 45 LAN_TXD2

10 TDP 22 VSSR 34 LAN_RXD0 46 X1

11 TDN 23 VCCR 35 LAN_RXD1 47 X2

12 VCCT 24 VSS 36 VCCP 48 VSS

Networking Silicon — 82562ET

Datasheet 15

5.2.2 82562ET Shrink Small Outlying Package Diagram

Figure 4. 82562ET Pin Out Diagram

82562ET

PIN DI AGRA M

SSOP48

Rev 1.0

Top View

17 32

VSSR ( APS)

VCCR (APS)

VCCT (APS)

VSS (DPS)

VSSA (APS)

RBIAS10 (B)

RBIAS100 (B)

VSSA2 ( AP S)

VCCA2 (APS)

TDP (MLT)

VCCA (APS)

LAN_TX D2 (I)

LAN_RXD2 (O)

LAN_RSTSYNC

VSSP (DPS)

X1(I)

X2 (O)

VSS (D P S)

ADV10 (I)

ISOL _TI (I )

LILED# (O)

ACTLED# (O)

SPD LED# ( O)

T DN (ML T)

VCCT (APS)

RDP (MLT)

RDN (MLT)

VCCT (APS)

VCCR (APS)

VSSR ( APS)

VCCT (APS)

VSS (DPS)

VCC (DPS)

LAN_TX D1 (I)

LAN_TX D0 (I)

LAN_RXD1 (O)

LAN_RXD0 (O)

VCCP (DPS)

LAN_CLK (O)

VCCP (DPS)

VSSP (DPS)

VCC (DPS)

ISOL_TEX (I)

TO UT (O)

ISOL _TCK ( I)

TESTEN (I)