TPS53114
www.ti.com
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER
FOR LOW VOLTAGE POWER RAILS
Check for Samples: TPS53114
1FEATURES • Pre-Biased Soft Start
2• D-CAP2™ Mode Control • Selectable Switching Frequency
350 kHz / 700 kHz
– Fast Transient Response • Cycle-By-Cycle Over Current Limiting Control
– No External Parts Required For Loop
Compensation • Thermally Compensated OCP by 4000 ppm/°C
at ITRIP
– Compatible with Ceramic Output
Capacitors APPLICATIONS
• High Initial Reference Accuracy (±1%) • Point-of-Load Regulation in Low Power
• Low Output Ripple Systems for Wide Range of Applications
• Wide Input Voltage Range: 4.5 V to 24 V – Digital TV Power Supply
• Output Voltage Range: 0.76 V to 5.5 V – Networking Home Terminal
• Low-Side RDS(on) Loss-Less Current Sensing – Digital Set Top Box (STB)
• Adaptive Gate Drivers with Integrated Boost – DVD Player / Recorder
Diode – Gaming Consoles
• Adjustable Soft Start
DESCRIPTION
The TPS53114 is a single, adaptive on-time D-CAP2™ mode synchronous buck controller. The TPS53114
enables system designers to complete the suite of various end equipment's power bus regulators with cost
effective low external component count and low standby current solution. The main control loop for the
TPS53114 uses the D-CAP2™ mode control which provides a very fast transient response with no external
components. The TPS53114 also has a circuit that enables the device to adapt to both low equivalent series
resistance (ESR) output capacitors such as POSCAP or SP-CAP and ultra-low ESR ceramic capacitors. The
device provides convenient and efficient operation with input voltages from 4.5 V to 24 V and output voltage from
0.76 V to 5.5 V.
The TPS53114 is available in the 16-pin TSSOP and HTSSOP packages, and is specified from –40°C to 85°C
ambient temperature range.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP2 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS53114PWP
(TSSOP16)
SW
DRVL
DRVH
VBST
EN
VO
VFB
GND
VREG5
TRIP
PGND
C3
C1
10uFx2
L1
R2
R1 C2
0.1uF Q1
Q2
VO1
C5 4.7uF
C6
1uF
R3
116
10
13
14
15
8
11
12
4
6
7
VIN
FSEL
V5FILT 9
CER
5
3SS
VIN
2
C4
VIN
C7
THERMAL
PAD
SGND
SGND
SGND
SGND
PGND
PGND
TPS53114PW
(TSSOP16)
SW
DRVL
DRVH
VBST
EN
VO
VFB
GND
VREG5
TRIP
PGND
C3
C1
10uFx2
L1
R2
R1 C2
0.1uF Q1
Q2
VO1
C5 4.7uF
C6
1uF
R3
1 16
10
13
14
15
8
11
12
4
6
7
VIN
FSEL
V5FILT 9
CER
5
3SS
VIN
2
C4
VIN
C7
SGND
SGND
SGND
SGND
PGND
PGND
TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL APPLICATION CIRCUITS
Figure 1. HTSSOP
Figure 2. TSSOP
2Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS53114
TPS53114
www.ti.com
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
ORDERING INFORMATION(1) (2)
TAPACKAGE(3) ORDERING PART NUMBER PINS OUTPUT SUPPLY ECO PLAN
TPS53114PWPR Tape-and-Reel
HTSSOP
(Thermal Pad）TPS53114PWP Tube Green
–40°C to 85°C 16 (RoHS & no Sb/Br)
TPS53114PWR Tape-and-Reel
TSSOP TPS53114PW Tube
(1) All packaging options have Cu NIPDAU lead/ball finish.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
Operating under free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
VIN, EN –0.3 to 26
VBST –0.3 to 32
Input voltage range V
VBST - SW –0.3 to 6
V5FILT, VFB, TRIP, VO, FSEL, CER –0.3 to 6
DRVH –1 to 32
DRVH - SW –0.3 to 6
Output voltage range SW –2 to 26 V
DRVL, VREG5, SS –0.3 to 6
PGND –0.3 to 0.3
TAOperating ambient temperature range –40 to 85 °C
TSTG Storage temperature range –55 to 150 °C
TJJunction temperature range –40 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE (2 oz. trace and copper pad with solder)
TA< 25°C DERATING FACTOR TA= 85°C
PACKAGE POWER RATING ABOVE TA= 25°C POWER RATING
16-pin HTSSOP (PWP) 2.73 W 27.3 mW/°C 1.09 W
16-pin TSSOP (PW) 0.62 W 6.2 mW/°C 0.25 W
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s) :TPS53114
TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
www.ti.com
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VIN 4.5 24
Supply input voltage range V
V5FILT 4.5 5.5
VBST –0.1 30
VBST - SW –0.1 5.5
Input voltage range VFB, VO, FSEL, CER –0.1 5.5 V
TRIP –0.1 0.3
EN –0.1 24
DRVH –0.1 30
VBST - SW –0.1 5.5
Output Voltage range SW 1.8 24 V
DRVL, VREG5, SS –0.1 5.5
PGND –0.1 0.1
TAOperating free-air temperature –40 85 °C
TJOperating junction temperature –40 125 °C
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN current, TA= 25°C, VREG5 tied to V5FLT, EN = 350 600
IIN VIN supply current mA
5V, VFB = 0.8V, SW = 0.5V
IVINSDN VIN shutdown current VIN current, TA= 25°C, No Load , EN = 0V, VREG5 28 60 mA
= ON
VFB VOLTAGE and DISCHARGE RESISTANCE
VBG Bandgap Initial regulation accuracy TA= 25°C –1.0 1.0 %
TA= 25°C , FSEL = 0 V, CER = V5FILT 755 765 775
VVFBTHL VFB threshold voltage mV
TA= –40°C to 85°C, FSEL = 0V, CER = V5FILT 752 778
TA= 25°C , FSEL = CER = V5FILT 748 758 768
VVFBTHH VFB threshold voltage mV
TA= –40°C to 85°C, FSEL = CER = V5FILT 745 771
IVFB VFB Input Current VFB = 0.8V, TA= 25°C –100 –10 100 nA
RDischg Vo Discharge Resistance EN = 0V, VO = 0.5V, TA= 25°C 40 80 Ω
VREG5 OUTPUT
VVREG5 VREG5 Output Voltage TA=25°C, 5.5V < VIN < 24V, 0 < IVREG5 < 10mA 4.8 5.0 5.2 V
VLN5 Line regulation 5.5V < VIN < 24V, IVREG5 = 10mA 20 mV
VLD5 Load regulation 1mA < IVREG5 < 10mA 40 mV
IVREG5 Output current VIN = 5.5V, VVREG5 = 4.0V, TA= 25°C 170 mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
Source, IDRVH = –100mA 5.5 11
RDRVH DRVH resistance Ω
Sink, IDRVH = 100mA 2.5 5
Source, IDRVL = –100mA 4 8
RDRVL DRVL resistance Ω
Sink, IDRVL = 100mA 2 4
DRVH-low to DRVL-on 20 50 80
TDDead time ns
DRVL-low to DRVH-on 20 40 80
INTERNAL BST DIODE
VFBST Forward Voltage VVREG5-VBST, IF = 10mA, TA= 25°C 0.7 0.8 0.9 V
IVBSTLK VBST Leakage Current VBST = 29V, SW = 24V, TA= 25°C 0.1 1 mA
4Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS53114
TPS53114
www.ti.com
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
ON-TIME TIMER CONTROL
TONL On Time SW = 12V, VO = 1.8V, FSEL = 0V 390 ns
TONH On Time SW = 12V, VO = 1.8V, FSEL = V5FILT 139 ns
TOFFL Min off time SW = 0.7V, TA= 25°C, VFB = 0.7V, FSEL = 0V 285 ns
TOFFH Min off time SW = 0.7V, TA= 25°C, VFB = 0.7V, FSEL = V5FILT 216 ns
SOFT START
Issc SS charge current VSS = 0V , SOURCE CURRENT 1.4 2.0 2.6 mA
Issd SS discharge current VSS = 0.5V , SINK CURRRENT 100 150 mA
UVLO
V5FILT rising 3.7 4.0 4.3 V
VUV5VFILT V5FILT UVLO threshold Hysteresis 0.2 0.3 0.4
LOGIC THRESHOLD
VENH EN H-level threshold voltage EN 2.0 V
VENL EN L-level threshold voltage EN 0.3 V
CURRENT SENSE
ITRIP TRIP source current VTRIP = 0.1V, TA= 25°C 8.5 10 11.5 mA
TCITRIP ITRIP temperature coefficient on the basis of 25°C 4000 ppm/°C
(VTRIP-GND-VPGND-SW) voltage, –10 0 10 mV
VTRIP-GND = 60mV, TA= 25°C
VOCLoff OCP compensation offset (VTRIP-GND-VPGND-SW) voltage, –15 15 mV
VTRIP-GND = 60mV
VRtrip Current limit threshold setting VTRIP-GND voltage 30 200 mV
range
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP Output OVP trip threshold OVP detect 110 115 120 %
TOVPDEL Output OVP prop delay 1.5 ms
UVP detect 65 70 75 %
VUVP Output UVP trip threshold Hysteresis (recovery <20ms) 10 %
TUVPDEL Output UVP delay 17 30 40 ms
TUVPEN Output UVP enable delay UVP enable delay / soft start time X1.4 X1.7 X2.0
THERMAL SHUTDOWN
Shutdown temperature(1) 150 °C
TSDN Thermal shutdown threshold Hysteresis(1) 20
(1) Ensured by design. Not production tested.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s) :TPS53114
VBST
SS
EN
VO
VFB
GND
CER
DRVH
SW
DRVL
PGND
TRIP
VIN
VREG5
V5FILT
FSEL
161
2
3
4
5
6
7
8
10
11
12
13
14
T PS 5 3 1 14
15
9
VBST
SS
EN
VO
VFB
GND
CER
DRVH
SW
DRVL
PGND
TRIP
VIN
VREG5
V5FILT
FSEL
161
2
3
4
5
6
7
8
10
11
12
13
14
T PS 5 3 1 14
15
9
TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
www.ti.com
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
Supply input for high-side NFET driver. Bypass to SW with a high-quality 0.1-mF ceramic capacitor. An external
VBST 16 I schottky diode can be added from VREG5 if forward drop is critical to drive the high-side FET.
EN 7 I Enable. Pull High to enable SMPS.
SS 3 O Soft start programming pin. Connect capacitor from SS pin to GND to program soft start time.
VO 1 I Output voltage input for on-time adjustment and output discharge. Connect directory to the output voltage.
VFB 2 I D-CAP2 feedback input. Connect to output voltage with resistor divider.
GND 4 I Signal ground pin. Connect to PGND and system ground at a single point.
High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and
DRVH 15 O VBST(ON).
SW 14 I/O Switch node connections for both the high-side driver and over current comparator.
DRVL 13 O Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF) and
VREG5(ON).
Power ground connection for both the low-side driver and over current comparator. Connect PGND and GND
PGND 12 I/O strongly together near the IC.
over current threshold programming pin. Connect to GND with a resister to set threshold for low-side RDS(on)
TRIP 11 I current limit.
VIN 9 I Supply Input for 5-V linear regulator. Bypass to GND with a minimum high-quality 0.1-mF ceramic capacitor.
5-V supply input for the control circuitry except the MOSFET drivers. Bypass to GND with a minimum
V5FILT 8 I high-quality 1.0-mF ceramic capacitor. V5FILT is connected to VREG5 via internal 10-Ωresistor.
VREG5 10 O Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum high-quality
4.7-mF ceramic capacitor. VREG5 is connected to V5FILT via internal 10-Ωresistor.
Output capacitor select pin. Connect to GND for ceramic output capacitors. Connect to V5FILT for conductive
CER 5 I polymer electrolyte type output capacitors (SP-CAP, POS-CAP, PXE).
Switching frequency selection pin. Connect to GND for low switching frequency or connect to V5FILT for high
FSEL 6 I switching frequency.
PIN ASSIGNMENT (TOP VIEW)
Figure 3. HTSSOP 16-Pin PWP Figure 4. TSSOP 16-Pin PW
6Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS53114
SW
DRVL
DRVH
VBST
EN
VO
VFB
GND
FSEL
VREG5
TRIP
PGND
VO
7
15
5
12
13
14
6
10
9
11
1
2
4
16
VIN
V5FILT
8
CER
VIN
VIN
5VREG
EN
Logic
LL
PGND
SSLogic
UV
OV
Protection
Logic
Ref SS
UV
OV
UVLO
UVLO
TEST
TESTBLOCK
REF
TSD
Ref
3
SS
PowerGood
FSELECT
FSELECT
-30%
15%
PGND
OCP
GND
10 Am
XCON
ControlLogic
VREG5
0.1 Fm
10x2 Fm
4.7 Fm
1 Fm
PWM
TPS53114
www.ti.com
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
FUNCTIONAL BLOCK DIAGRAM
DETAILED DESCRIPTION
PWM OPERATION
The main control loop of the TPS53114 is an adaptive on-time pulse width modulation (PWM) controller using a
proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. After an internal one-shot timer expires, this
MOSFET is turned off. The one-shot timer is reset and the high-side MOSFET is turned back on when the
feedback voltage falls below the reference voltage. The one shot is set by the converter input voltage VIN, and
the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called
adaptive on-time control. An internal ramp is added to the reference voltage to simulate output ripple, eliminating
the need for ESR induced output ripple from D-CAP mode control.
DRIVERS
The TPS53114 contains two high-current resistive MOSFET gate drivers. The low-side driver is a ground
referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET
whose source is connected to PGND. The high-side driver is a floating SW referenced VBST powered driver
designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the VBST voltage
during the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current
equal to gate charge (Qgat Vgs = 5 V) times switching frequency (fSW).
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFET's body
diodes.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s) :TPS53114
TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
www.ti.com
PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL
TPS53114 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.
TPS53114 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.
Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
5-VOLT REGULATOR
The TPS53114 has an internal 5-V low-dropout (LDO) Regulator to provide a regulated voltage for all both
drivers and the IC's internal logic. A high-quality 4.7-mF or greater ceramic capacitor from VREG5 to GND is
required to stabilize the internal regular. An internal 10-Ωresistor from VREG5 filters the regulator output to the
IC's analog and logic input voltage, V5FILT. An additional high-quality 1.0-mF ceramic capacitor is required from
V5FILT to GND to filter switching noise from VREG5.
SOFT START
The TPS53114 has a programmable soft start . When the EN pin becomes high, 2.0-mA current begins charging
the capacitor which is connected SS pin to GND. Smooth control of the output voltage is maintained during start
up.
PRE-BIAS SUPPORT
The TPS53114 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage (VFB)), then the TPS53114 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the
pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
SWITCHING FREQUENCY SELECTION
The TPS53114 allows the user to select from two different switching frequencies by connecting the FSEL pin to
either GND or V5FILT. Connect FSEL to GND for a switching frequency (fsw) of 350 KHz. Connect FSEL to
V5FILT for a switching frequency of 700 KHz.
OUTPUT DISCHARGE CONTROL
The TPS53114 discharges the outputs when EN is low, or the controller is turned off by the protection functions
(OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-ΩMOSFET which
is connected to VO and PGND. The external low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that, on start,
the regulated voltage always initializes from 0 V.
8Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS53114
V =I R -
TRIP OCL DS(ON)
·( )V-V
IN O VO
VIN
2 1L f· · SW
¾
¾
·
R k =
TRIP ( )WV mV
TRIP ( )
I A
TRIP ( )m
¾
TPS53114
www.ti.com
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
OVER CURRENT PROTECTION
TPS53114 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current by
monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53114 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin
should be connected to GND through a trip voltage setting resistor, according to Equation 1 and Equation 2.
(1)
(2)
The trip voltage should be between 30 mV to 200 mV over all operational temperature, including the
4000 ppm/°C temperature slope compensation for the temperature dependency of the RDS(on). If the load current
exceeds the over current limit, the voltage will begin to drop. If the over current conditions continues, the output
voltage will fall below the under voltage protection threshold and the TPS53114 will shut down.
OVER/UNDER VOLTAGE PROTECTION
TPS53114 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage
is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the
high-side MOSFET driver OFF and the low-side MOSFET driver ON. When the feedback voltage is lower than
70% of the reference voltage, the UVP comparator output goes high and an internal UVP delay counter begins
counting. After 30 ms, TPS53114 latches OFF both top and bottom MOSFET drivers. This function is enabled
approximately 1.7x TSS after power-on. The OVP and UVP latch off is reset when EN goes low level.
UVLO PROTECTION
TPS53114 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin. When
the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF and
output discharge is ON. The UVLO is non-latch protection.
THERMAL SHUTDOWN
The TPS53114 includes an over temperature protection shut-down feature. If the TPS53114 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s) :TPS53114
TJ − Junction Temperature − °C
0
100
200
300
400
500
600
−50 0 50 100 150
ICC − Supply Current − µA
G001
f = 350 kHz
VO = 1.05 V
TJ − Junction Temperature − °C
0
5
10
15
20
25
30
35
40
45
−50 0 50 100 150
IO(sd) − Shutdown Current − µA
G002
VREG5 = ON FSEL = V5FIL T
FSEL = GND
VREG5 Voltage - V
Temperature - °C
TJ − Junction Temperature − °C
0
2
4
6
8
10
12
14
16
−50 0 50 100 150
I(TRIP) − Source Current − µA
G003
4200ppm/°C for RDS(ON) Compensation
TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
VIN SUPPLY CURRENT VIN SHUTDOWN CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 5. Figure 6.
TRIP SOURCE CURRENT
VS
JUNCTION TEMPERATURE VREG5 VOLTAGE
Figure 7. Figure 8.
10 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS53114
4.500
4.600
4.700
4.800
4.900
5.000
5.100
5.200
0 5 10 15 20 25
VREG5 Voltage - V
V - Input Voltage - V
IN
0 . 7 5 0
0 . 7 5 5
0 . 7 6 0
0 . 7 6 5
0 . 7 7 0
0 . 7 7 5
0 . 7 8 0
0 . 7 8 5
0 . 7 9 0
0 . 7 9 5
0 . 8 0 0
-5 0 0 5 0 1 0 0 15 0
VFB Voltage - V
Temperature - °C
FSEL = GND
FSEL = V5FILT
0.740
0.745
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0 5 10 1 5 20 25
VFB Voltage - V
V - Input Voltage - V
IN
FSEL = GND
FSEL = V5FILT
TPS53114
www.ti.com
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
TYPICAL CHARACTERISTICS (continued)
VFB VOLTAGE
VREG5 VOLTAGE vs
vs TEMPERATURE
INPUT VOLTAGE (VO= 1.05 V, IO= 4 A)
Figure 9. Figure 10.
VFB VOLTAGE
vs
INPUT VOLTAGE
Figure 11.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s) :TPS53114
TPS53114 PWP
(HTSSOP 16)
SW
DRV
L
DRV
H
VBST
EN
VO
VFB
GND
VREG 5
TRIP
PGND
C3
C1
10uFL1
SPM6530T
1.5uH
R2
10k
R1
3.69k C2
0.1uF
Q1
FDS8678
Q2
FDS8690
VO1
C5 4.7uF
C6
1uF
R3
3.9k
116
10
13
14
15
8
11
12
4
6
7
VIN
FSEL
V5FILT 9
CER5
3SS
VIN
2
C4
10uF
VIN
C7
4700
THERMAL
PAD
SGND
SGND
SGND
SGND
PGND
PGND
22uFx4
W
W
W
pF
TPS53114PWP
(HTSSOP16)
SW
DRV
L
DRV
H
VBST
EN
VO
VFB
GND
VREG5
TRIP
PGND
C3
C1
10uFL1
SPM6530T
1.5uH
R2
10k
R1
3.81k C2
0.1 uF
Q1
FDS8678
Q2
FDS8690
VO1
C5 4.7uF
C6
1uF
R3
3.9k
116
10
13
14
15
8
11
12
4
6
7
VIN
FSEL
V5FILT 9
CER
5
3SS
VIN
2
C4
10uF
VIN
C7
4700
THERMAL
PAD
SGND
SGND
SGND
SGND
PGND
PGND
22uFx2
W
W
W
pF
TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
www.ti.com
APPLICATION INFORMATION
Figure 12. Typical Application Circuit at 350-kHz Switching Frequency Selection (FSEL pin = GND)
Figure 13. Typical Application Circuit at 700-kHz Switching Frequency Selection (FSEL pin = V5FILT)
12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS53114
VI − Input Voltage − V
300
400
500
600
700
800
0 5 10 15 20 25
f(SW) − Swithing Frequency − kHz
G005
FSEL = V5FILTVO = 1.2 V
VO = 1.05 V
VO = 1.8 V
VO = 3.3 V
VO = 5 V
VI − Input Voltage − V
200
250
300
350
400
450
500
0 5 10 15 20 25
f(SW) − Swithing Frequency − kHz
G004
FSEL = GND
f = 350 kHz
VO = 1.2 V
VO = 1.05 V
VO = 1.8 V VO = 3.3 V VO = 5 V
IO − Output Current − A
200
300
400
500
600
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
f(SW) − Swithing Frequency − kHz
G006
FSEL = GND
VI = 12 V
VO = 1.05 V
VO = 3.3 V
IO − Output Current − A
200
300
400
500
600
700
800
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
f(SW) − Swithing Frequency − kHz
G007
FSEL = V5FILT
VI = 12 V
VO = 3.3 V
VO = 1.05 V
TPS53114
www.ti.com
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
TYPICAL APPLICATION PERFORMANCE
Typical application performance below was taken from specific application circuits Figure 12 and Figure 13.
Figure 14. SWITCHING FREQUENCY (IO= 1 A) vs. Figure 15. SWITCHING FREQUENCY vs. INPUT
INPUT VOLTAGE VOLTAGE
Figure 16. SWITCHING FREQUENCY vs. OUTPUT Figure 17. SWITCHING FREQUENCY vs. OUTPUT
CURRENT CURRENT
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s) :TPS53114
IO − Output Current − A
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VO − Output Voltage − V
G008
FSEL = V5FILT
FSEL = GND
VI = 12 V
VI − Input Voltage − V
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
0 5 10 15 20 25
VO − Output Voltage − V
G009
IO = 3 A
FSEL = V5FILT
FSEL = GND
t − Time − 20 µs/div G010
VO (50mV/div)
Iout1 (2A/div)
FSEL = GND
(350 kHz Selection)
t - Time - 20 m
s/div
G011
VO (50mV/div)
Iout1 (2A/div)
FSEL = V5FILT
(700 kHz Selection)
TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
www.ti.com
Figure 18. 1.05-V OUTPUT VOLTAGE vs. OUTPUT Figure 19. 1.05-V OUTPUT VOLTAGE vs. INPUT
CURRENT VOLTAGE
Figure 20. 1.05-V LOAD TRANSIENT RESPONSE Figure 21. 1.05-V LOAD TRANSIENT RESPONSE
14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS53114
IO − Output Current − A
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
η − Ef ficiency − %
G013
FSEL = GND
350 kHz Selection
VI = 12 V
t − Time − 2 ms/div G012
SS
VO = 1.05 V
CSS = 4700 pF
EN
IO − Output Current − A
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
η − Ef ficiency − %
G014
FSEL = V5FILT
700 kHz Selection
VI = 12 V
TPS53114
www.ti.com
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
Figure 22. STARTUP WAVEFORM Figure 23. 1.05-V EFFICIENCY vs. OUTPUT
CURRENT
Figure 24. 1.05-V EFFICIENCY vs. OUTPUT CURRENT
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s) :TPS53114
L1= ( - 1)V V
IN(max) O
I f
L (ripple) SW1·
·
VO
VIN(max)
=3 ( - 1)·V V
IN(max) O
I f
O SW
1·
·
VO1
VIN(max)
¾
¾
¾
¾
1
IL (ripple)1=V V
IN(max) O
- 1
L f1·SW
·
VO1
VIN(max)
¾
¾
IL (peak)1=VTRIP
RDS(ON)
+IL (ripple)1
¾
IL (RMS)1=ÖI I
O L (ripple)
1+( )
2 2
1
1
¾
12
¾
C1= DI L
load
21·
¾
2 1· ·VODVOS
C1= DI L
load
21·
¾
2· ·KDVUS
K V V=( - 1)
IN O ·
Ton1
¾
T T
ON min(off)
1+
C1= IL (ripple)1
8 1·VO (ripple)
·1
¾
fSW
¾
TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
www.ti.com
COMPONENT SELECTION
CHOOSE INDUCTOR
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation. L1 can
be calculated using Equation 3.
(3)
The inductors current ratings needs to support both the RMS (thermal) current and the peak (saturation) current.
The RMS and peak inductor current can be estimated as follows:
(4)
(5)
(6)
Note:
The calculation above shall serve as a general reference. To further improve transient response, the output
inductance could be reduced further. This needs to be considered along with the selection of the output
capacitor.
CHOOSE OUTPUT CAPACITOR
The capacitor value and ESR determines the amount of output voltage ripple and load transient response.
Recommend to use ceramic output capacitor.
(7)
(8)
Where:
(9)
(10)
Select the capacitance value greater than the largest value calculated from Equation 7,Equation 8 and
Equation 10. The capacitance for C1 should be greater than 66 mF.
Where:
•ΔVOS = The allowable amount of overshoot voltage in load transition
•ΔVUS = The allowable amount of undershoot voltage in load transition
• Tmin(off) = Minimum off time
CHOOSE INPUT CAPACITOR
The TPS53114 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-mF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS53114
R1=()
VO
¾
0.765+ VFB1(ripple)
¾
2
-1 ·R2(FSEL =GND)
1
R1=()
VO
¾
0.758+ VFB1(ripple)
¾
2
-1 ·R2(FSEL = V5FILT)
1
( )
IN O O
TRIP OCL DS(ON)
sw IN
V V V
V = I R
2 L1 V
æ ö
-
- · ·
ç ÷
ç ÷
· · ¦
è ø
TRIP OCLoff
TRIP
TRIP
V (mV) V
R (k ) = I ( A)
-
Wm
TSS =C70.765·
¾
2e-6 ( )s(FSEL =GND)
TSS =C70.758·
¾
2e-6 ( )s(FSEL = V5FILT)
P f CiH CiL VREG V
d SW in(max)
= ( + ) 5· · ·
TPS53114
www.ti.com
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
CHOOSE BOOTSTRAP CAPACITOR
The TPS53114 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side
drivers. A minimum 0.1-mF high-quality ceramic capacitor is recommended. The voltage rating should be greater
than 10.0 V.
CHOOSE VREG5 AND V5FILT CAPACITOR
The TPS53114 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-mF
high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A
minimum 1.0-mF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper
operation. Both of these capacitors' voltage ratings should be greater than 10 V.
CHOOSE OUTPUT VOLTAGE RESISTORS
The output voltage is set with a resistor divider from output voltage node to the VFBx pin. It is recommended to
use 1% tolerance or better resistors. Select R2 between 10 kΩand 100 kΩand use Equation 11 or Equation 12
to calculate R1.
(11)
(12)
Where:
VFB1(ripple) = Ripple voltage at VFB1
CHOOSE RESISTOR SETTING FOR OVER CURRENT LIMIT
(13)
(14)
Where:
• RDS(ON) = Low side FET on-resistance
• ITRIP = TRIP pin source current （≉ 10 mA）
• VOCLoff = Minimum over current limit offset voltage (-20 mV)
• IOCL = over current limit
CHOOSE SOFT START CAPACITOR
Soft start timing equations are as follows:
(15)
(16)
CHOOSE PACKAGE OPTION
TPS53114 power dissipation:
(17)
Where:
• CiH = Input capacitor of high side MOSFET
• CiL = Input capacitor of low side MOSFET
Choose package considering the Dissipation Rating table.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s) :TPS53114
TPS53114
SLVS887B –APRIL 2009–REVISED OCTOBER 2010
www.ti.com
LAYOUT SUGGESTIONS
• Keep the input switching current loop as small as possible.
• Place the input capacitor (C3, C6) close to the top switching FET. The output current loop should also be kept
as small as possible.
• Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin (VFB) of the device.
• Keep analog and non-switching components away from switching components.
• Make a single point connection from the signal ground to power ground.
• Do not allow switching current to flow under the device.
Spacer
REVISION HISTORY
Changes from Original (April 2009) to Revision A Page
• Updated the list of Features .................................................................................................................................................. 1
Changes from Revision A (August 2009) to Revision B Page
• Changed Equation 13 From: IOCL + To: IOCL - ..................................................................................................................... 17
• Updated Equation 14 by adding minus VOCLoff .................................................................................................................... 17
18 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPS53114
PACKAGE OPTION ADDENDUM
www.ti.com 11-Sep-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS53114PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS53114PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS53114PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS53114PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS53114PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS53114PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53114PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
TPS53114PWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated