TPS53114 www.ti.com SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS Check for Samples: TPS53114 FEATURES 1 * 2 * * * * * * * D-CAP2TM Mode Control - Fast Transient Response - No External Parts Required For Loop Compensation - Compatible with Ceramic Output Capacitors High Initial Reference Accuracy (1%) Low Output Ripple Wide Input Voltage Range: 4.5 V to 24 V Output Voltage Range: 0.76 V to 5.5 V Low-Side RDS(on) Loss-Less Current Sensing Adaptive Gate Drivers with Integrated Boost Diode Adjustable Soft Start * * * * Pre-Biased Soft Start Selectable Switching Frequency 350 kHz / 700 kHz Cycle-By-Cycle Over Current Limiting Control Thermally Compensated OCP by 4000 ppm/C at ITRIP APPLICATIONS * Point-of-Load Regulation in Low Power Systems for Wide Range of Applications - Digital TV Power Supply - Networking Home Terminal - Digital Set Top Box (STB) - DVD Player / Recorder - Gaming Consoles DESCRIPTION The TPS53114 is a single, adaptive on-time D-CAP2TM mode synchronous buck controller. The TPS53114 enables system designers to complete the suite of various end equipment's power bus regulators with cost effective low external component count and low standby current solution. The main control loop for the TPS53114 uses the D-CAP2TM mode control which provides a very fast transient response with no external components. The TPS53114 also has a circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP and ultra-low ESR ceramic capacitors. The device provides convenient and efficient operation with input voltages from 4.5 V to 24 V and output voltage from 0.76 V to 5.5 V. The TPS53114 is available in the 16-pin TSSOP and HTSSOP packages, and is specified from -40C to 85C ambient temperature range. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP2 is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009-2010, Texas Instruments Incorporated TPS53114 SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL APPLICATION CIRCUITS VIN 1 R1 VBST VO 16 R2 SGND 2 VFB 3 SS 4 GND Q1 10uFx2 DRVH 15 VO1 (TSSOP16) C7 SGND C3 C2 0.1uF TPS53114PWP SW 14 DRVL THERMAL PAD SGND 5 CER 6 FSEL L1 Q2 13 C1 PGND 12 TRIP 11 R3 7 EN VREG5 10 VIN 9 C5 C6 8 V5FILT VIN C4 1uF SGND PGND 4.7uF PGND Figure 1. HTSSOP VIN 1 VO 2 VFB 3 SS 4 GND R1 R2 SGND VBST 16 DRVH 15 C3 C2 0.1uF Q1 10uFx2 VO1 C7 SGND SW 14 DRVL L1 Q2 13 C1 TPS53114PW SGND 5 CER 6 FSEL PGND 12 (TSSOP16) TRIP 11 R3 7 EN 8 V5FILT VREG5 10 VIN 9 C5 C6 SGND 1uF PGND 4.7uF VIN C4 PGND Figure 2. TSSOP 2 Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 TPS53114 www.ti.com SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 ORDERING INFORMATION (1) TA PACKAGE (3) ORDERING PART NUMBER HTSSOP (Thermal Pad TPS53114PWPR (3) OUTPUT SUPPLY ECO PLAN Tape-and-Reel 16 TPS53114PWR TSSOP (1) (2) PINS TPS53114PWP -40C to 85C (2) TPS53114PW Tube Green (RoHS & no Sb/Br) Tape-and-Reel Tube All packaging options have Cu NIPDAU lead/ball finish. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS Operating under free-air temperature range (unless otherwise noted) (1) VALUE Input voltage range Output voltage range VIN, EN -0.3 to 26 VBST -0.3 to 32 VBST - SW -0.3 to 6 V5FILT, VFB, TRIP, VO, FSEL, CER -0.3 to 6 DRVH -1 to 32 DRVH - SW -0.3 to 6 SW -2 to 26 DRVL, VREG5, SS -0.3 to 6 PGND UNIT V V -0.3 to 0.3 TA Operating ambient temperature range -40 to 85 C TSTG Storage temperature range -55 to 150 C TJ Junction temperature range -40 to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE (2 oz. trace and copper pad with solder) PACKAGE TA < 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 85C POWER RATING 16-pin HTSSOP (PWP) 2.73 W 27.3 mW/C 1.09 W 16-pin TSSOP (PW) 0.62 W 6.2 mW/C 0.25 W Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 3 TPS53114 SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS Supply input voltage range Input voltage range Output Voltage range MIN MAX VIN 4.5 24 V5FILT 4.5 5.5 VBST -0.1 30 VBST - SW -0.1 5.5 VFB, VO, FSEL, CER -0.1 5.5 TRIP -0.1 0.3 EN -0.1 24 DRVH -0.1 30 VBST - SW -0.1 5.5 SW 1.8 24 DRVL, VREG5, SS -0.1 5.5 PGND UNIT V V V -0.1 0.1 TA Operating free-air temperature -40 85 C TJ Operating junction temperature -40 125 C ELECTRICAL CHARACTERISTICS over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT VIN current, TA = 25C, VREG5 tied to V5FLT, EN = 5V, VFB = 0.8V, SW = 0.5V 350 600 VIN current, TA = 25C, No Load , EN = 0V, VREG5 = ON 28 60 mA 1.0 % 765 775 SUPPLY CURRENT IIN VIN supply current IVINSDN VIN shutdown current mA VFB VOLTAGE and DISCHARGE RESISTANCE VBG Bandgap Initial regulation accuracy TA = 25C -1.0 TA = 25C , FSEL = 0 V, CER = V5FILT 755 TA = -40C to 85C, FSEL = 0V, CER = V5FILT 752 TA = 25C , FSEL = CER = V5FILT 748 TA = -40C to 85C, FSEL = CER = V5FILT 745 VVFBTHL VFB threshold voltage VVFBTHH VFB threshold voltage IVFB VFB Input Current VFB = 0.8V, TA = 25C RDischg Vo Discharge Resistance EN = 0V, VO = 0.5V, TA = 25C -100 778 758 768 771 mV mV -10 100 nA 40 80 5.0 5.2 V VREG5 OUTPUT VVREG5 VREG5 Output Voltage TA=25C, 5.5V < VIN < 24V, 0 < IVREG5 < 10mA 4.8 VLN5 Line regulation 5.5V < VIN < 24V, IVREG5 = 10mA 20 mV VLD5 Load regulation 1mA < IVREG5 < 10mA 40 mV IVREG5 Output current VIN = 5.5V, VVREG5 = 4.0V, TA = 25C 170 mA OUTPUT: N-CHANNEL MOSFET GATE DRIVERS RDRVH DRVH resistance RDRVL DRVL resistance TD Dead time Source, IDRVH = -100mA 5.5 11 Sink, IDRVH = 100mA 2.5 5 Source, IDRVL = -100mA 4 8 Sink, IDRVL = 100mA 2 4 DRVH-low to DRVL-on 20 50 80 DRVL-low to DRVH-on 20 40 80 0.7 0.8 0.9 V 0.1 1 mA ns INTERNAL BST DIODE VFBST Forward Voltage VVREG5-VBST, IF = 10mA, TA = 25C IVBSTLK VBST Leakage Current VBST = 29V, SW = 24V, TA = 25C 4 Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 TPS53114 www.ti.com SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT ON-TIME TIMER CONTROL TONL On Time SW = 12V, VO = 1.8V, FSEL = 0V 390 ns TONH On Time SW = 12V, VO = 1.8V, FSEL = V5FILT 139 ns TOFFL Min off time SW = 0.7V, TA = 25C, VFB = 0.7V, FSEL = 0V 285 ns TOFFH Min off time SW = 0.7V, TA = 25C, VFB = 0.7V, FSEL = V5FILT 216 ns SOFT START Issc SS charge current VSS = 0V , SOURCE CURRENT 1.4 2.0 Issd SS discharge current VSS = 0.5V , SINK CURRRENT 100 150 2.6 V5FILT rising 3.7 4.0 4.3 Hysteresis 0.2 0.3 0.4 2.0 mA mA UVLO VUV5VFILT V5FILT UVLO threshold V LOGIC THRESHOLD VENH EN H-level threshold voltage EN VENL EN L-level threshold voltage EN V 0.3 V CURRENT SENSE ITRIP TRIP source current VTRIP = 0.1V, TA = 25C TCITRIP ITRIP temperature coefficient on the basis of 25C VOCLoff VRtrip OCP compensation offset Current limit threshold setting range 8.5 10 11.5 4000 (VTRIP-GND-VPGND-SW) voltage, VTRIP-GND = 60mV, TA = 25C -10 (VTRIP-GND-VPGND-SW) voltage, VTRIP-GND = 60mV -15 15 30 200 VTRIP-GND voltage 0 mA ppm/C 10 mV mV mV OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP Output OVP trip threshold TOVPDEL Output OVP prop delay VUVP Output UVP trip threshold TUVPDEL Output UVP delay TUVPEN Output UVP enable delay OVP detect 110 115 120 1.5 UVP detect 65 Hysteresis (recovery <20ms) UVP enable delay / soft start time 70 % ms 75 % ms 10 % 17 30 40 X1.4 X1.7 X2.0 THERMAL SHUTDOWN TSDN (1) Thermal shutdown threshold Shutdown temperature (1) Hysteresis (1) 150 C 20 Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 5 TPS53114 SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 www.ti.com PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. VBST 16 I Supply input for high-side NFET driver. Bypass to SW with a high-quality 0.1-mF ceramic capacitor. An external schottky diode can be added from VREG5 if forward drop is critical to drive the high-side FET. EN 7 I Enable. Pull High to enable SMPS. SS 3 O Soft start programming pin. Connect capacitor from SS pin to GND to program soft start time. VO 1 I Output voltage input for on-time adjustment and output discharge. Connect directory to the output voltage. VFB 2 I D-CAP2 feedback input. Connect to output voltage with resistor divider. GND 4 I Signal ground pin. Connect to PGND and system ground at a single point. DRVH 15 O High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and VBST(ON). SW 14 I/O Switch node connections for both the high-side driver and over current comparator. DRVL 13 O Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF) and VREG5(ON). PGND 12 TRIP 11 I over current threshold programming pin. Connect to GND with a resister to set threshold for low-side RDS(on) current limit. VIN 9 I Supply Input for 5-V linear regulator. Bypass to GND with a minimum high-quality 0.1-mF ceramic capacitor. V5FILT 8 I 5-V supply input for the control circuitry except the MOSFET drivers. Bypass to GND with a minimum high-quality 1.0-mF ceramic capacitor. V5FILT is connected to VREG5 via internal 10- resistor. VREG5 10 O CER 5 I Output capacitor select pin. Connect to GND for ceramic output capacitors. Connect to V5FILT for conductive polymer electrolyte type output capacitors (SP-CAP, POS-CAP, PXE). FSEL 6 I Switching frequency selection pin. Connect to GND for low switching frequency or connect to V5FILT for high switching frequency. I/O Power ground connection for both the low-side driver and over current comparator. Connect PGND and GND strongly together near the IC. Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum high-quality 4.7-mF ceramic capacitor. VREG5 is connected to V5FILT via internal 10- resistor. PIN ASSIGNMENT (TOP VIEW) 16 VBST VO 1 16 VBST VFB SS 2 15 DRVH 2 15 DRVH 14 SW VFB SS 14 SW GND 4 13 DRVL GND 4 13 DRVL CER FSEL 5 12 PGND 5 12 PGND 11 TRIP CER FSEL 11 TRIP EN 7 10 VREG5 EN 7 10 VREG5 V5FILT 8 9 V5FILT 8 9 3 6 VIN Figure 3. HTSSOP 16-Pin PWP 6 Submit Documentation Feedback 3 6 TPS 531 14 1 TPS 531 14 VO VIN Figure 4. TSSOP 16-Pin PW Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 TPS53114 www.ti.com SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 FUNCTIONAL BLOCK DIAGRAM VIN -30% FSELECT UV VREG5 VBST 16 Control Logic 0.1 mF 15 VO OV 1 XCON 15% 14 13 PGND Ref SS 12 PWM 10 mA VFB 2 SW VO DRVL PGND GND TRIP OCP EN 10x2 mF DRVH EN Logic 7 SS Logic 11 LL PGND VIN VIN SS 9 3 UV GND OV 4 UVLO VREG5 Protection 5VREG 10 Logic 4.7 mF TSD CER Ref 5 REF V5FILT TEST 8 TEST BLOCK FSEL 6 FSELECT PowerGood UVLO 1 mF DETAILED DESCRIPTION PWM OPERATION The main control loop of the TPS53114 is an adaptive on-time pulse width modulation (PWM) controller using a proprietary D-CAP2TM mode control. D-CAP2TM mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. After an internal one-shot timer expires, this MOSFET is turned off. The one-shot timer is reset and the high-side MOSFET is turned back on when the feedback voltage falls below the reference voltage. The one shot is set by the converter input voltage VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP mode control. DRIVERS The TPS53114 contains two high-current resistive MOSFET gate drivers. The low-side driver is a ground referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET whose source is connected to PGND. The high-side driver is a floating SW referenced VBST powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the VBST voltage during the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to gate charge (Qg at Vgs = 5 V) times switching frequency (fSW). To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF between each driver transition. During this time the inductor current is carried by one of the MOSFET's body diodes. Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 7 TPS53114 SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 www.ti.com PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL TPS53114 employs adaptive on-time control scheme and does not have a dedicated on board oscillator. TPS53114 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage. Therefore, when the duty ratio is VOUT/VIN, the frequency is constant. 5-VOLT REGULATOR The TPS53114 has an internal 5-V low-dropout (LDO) Regulator to provide a regulated voltage for all both drivers and the IC's internal logic. A high-quality 4.7-mF or greater ceramic capacitor from VREG5 to GND is required to stabilize the internal regular. An internal 10- resistor from VREG5 filters the regulator output to the IC's analog and logic input voltage, V5FILT. An additional high-quality 1.0-mF ceramic capacitor is required from V5FILT to GND to filter switching noise from VREG5. SOFT START The TPS53114 has a programmable soft start . When the EN pin becomes high, 2.0-mA current begins charging the capacitor which is connected SS pin to GND. Smooth control of the output voltage is maintained during start up. PRE-BIAS SUPPORT The TPS53114 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the low-side driver is held off until the soft start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage (VFB)), then the TPS53114 slowly activates synchronous rectification by limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation. SWITCHING FREQUENCY SELECTION The TPS53114 allows the user to select from two different switching frequencies by connecting the FSEL pin to either GND or V5FILT. Connect FSEL to GND for a switching frequency (fsw) of 350 KHz. Connect FSEL to V5FILT for a switching frequency of 700 KHz. OUTPUT DISCHARGE CONTROL The TPS53114 discharges the outputs when EN is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40- MOSFET which is connected to VO and PGND. The external low-side MOSFET is not turned on during the output discharge operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that, on start, the regulated voltage always initializes from 0 V. 8 Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 TPS53114 www.ti.com SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 OVER CURRENT PROTECTION TPS53114 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current by monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the inductor current is larger than the over current limit (OCL), the TPS53114 delays the start of the next switching cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin should be connected to GND through a trip voltage setting resistor, according to Equation 1 and Equation 2. (VIN - VO) VTRIP = IOCL * RDS(ON) - 3/4 2 * L1 * fSW VTRIP (mV) RTRIP (kW) = 3/4 ITRIP (mA) * V 3/4O VIN (1) (2) The trip voltage should be between 30 mV to 200 mV over all operational temperature, including the 4000 ppm/C temperature slope compensation for the temperature dependency of the RDS(on). If the load current exceeds the over current limit, the voltage will begin to drop. If the over current conditions continues, the output voltage will fall below the under voltage protection threshold and the TPS53114 will shut down. OVER/UNDER VOLTAGE PROTECTION TPS53114 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the high-side MOSFET driver OFF and the low-side MOSFET driver ON. When the feedback voltage is lower than 70% of the reference voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 30 ms, TPS53114 latches OFF both top and bottom MOSFET drivers. This function is enabled approximately 1.7x TSS after power-on. The OVP and UVP latch off is reset when EN goes low level. UVLO PROTECTION TPS53114 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin. When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF and output discharge is ON. The UVLO is non-latch protection. THERMAL SHUTDOWN The TPS53114 includes an over temperature protection shut-down feature. If the TPS53114 die temperature exceeds the OTP threshold (typically 150C), both the high-side and low-side drivers are shut off, the output voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal shutdown is a non-latch protection. Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 9 TPS53114 SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 www.ti.com TYPICAL CHARACTERISTICS VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE VIN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 600 40 IO(sd) - Shutdown Current - A ICC - Supply Current - A 500 45 f = 350 kHz VO = 1.05 V 400 300 200 VREG5 = ON FSEL = V5FILT 35 30 FSEL = GND 25 20 15 10 100 5 0 -50 0 50 100 TJ - Junction Temperature - C 0 -50 150 G001 Figure 6. TRIP SOURCE CURRENT VS JUNCTION TEMPERATURE VREG5 VOLTAGE 100 150 G002 5.110 4200ppm/C for RDS(ON) Compensation 5.100 12 5.090 VREG5 Voltage - V I(TRIP) - Source Current - A 50 Figure 5. 16 14 0 TJ - Junction Temperature - C 10 8 6 5.080 5.070 5.060 4 5.050 2 0 -50 5.040 0 50 100 TJ - Junction Temperature - C 150 -50 G003 Figure 7. 10 0 50 100 150 Temperature - C Figure 8. Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 TPS53114 www.ti.com SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 TYPICAL CHARACTERISTICS (continued) VFB VOLTAGE vs TEMPERATURE (VO = 1.05 V, IO = 4 A) VREG5 VOLTAGE vs INPUT VOLTAGE 5.200 0.800 0.795 5.100 5.000 0.785 VFB Voltage - V VREG5 Voltage - V 0.790 4.900 4.800 0.780 0.775 FSEL = GND 0.770 0.765 4.700 FSEL = V5FILT 0.760 4.600 0.755 4.500 0.750 0 5 10 15 20 25 -5 0 0 VIN - Input Voltage - V 50 100 150 Temperature - C Figure 9. Figure 10. VFB VOLTAGE vs INPUT VOLTAGE 0.790 0.785 0.780 VFB Voltage - V 0.775 FSEL = GND 0.770 0.765 FSEL = V5FILT 0.760 0.755 0.750 0.745 0.740 0 5 10 15 20 25 VIN - Input Voltage - V Figure 11. Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 11 TPS53114 SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 www.ti.com APPLICATION INFORMATION VIN R2 10kW VBST 16 1 VO R1 3.69kW C7 SGND 4700 pF 2 VFB (HTSSOP 16) 3 DRV H 15 C3 10uF VO1 SW 14 SS 4 GND SGND Q1 FDS8678 L1 SPM6530T 1.5uH C2 0.1uF TPS53114 PWP THERMAL PAD SGND 5 CER 6 FSEL DRV L Q2 FDS8690 13 PGND 12 C1 22uFx4 R3 3.9k W TRIP 11 PGND 7 EN VREG 5 10 C5 C6 VIN 8 V5FILT SGND 4.7uF VIN 9 C4 10uF 1uF PGND Figure 12. Typical Application Circuit at 350-kHz Switching Frequency Selection (FSEL pin = GND) VIN 1 R1 3.81k W VBST 16 DRV H 15 C7 SGND 4700pF SGND VFB (HTSSOP16) 3 SS 4 GND SGND 5 CER 6 FSEL 7 EN 8 V5FILT Q1 FDS8678 C2 0 .1 uF TPS53114PWP 2 R2 10kW VO L1 SPM6530T 1.5uH C3 10uF VO1 SW 14 THERMAL PAD DRV L PGND 12 TRIP Q2 FDS8690 13 C1 22uFx2 R3 3.9kW 11 PGND VREG5 10 VIN 9 C5 C6 SGND 1 uF 4.7uF VIN C4 10uF PGND Figure 13. Typical Application Circuit at 700-kHz Switching Frequency Selection (FSEL pin = V5FILT) 12 Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 TPS53114 www.ti.com SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 TYPICAL APPLICATION PERFORMANCE Typical application performance below was taken from specific application circuits Figure 12 and Figure 13. 800 500 400 VO = 5 V VO = 3.3 V VO = 1.8 V f(SW) - Swithing Frequency - kHz 450 f(SW) - Swithing Frequency - kHz VO = 5 V FSEL = GND f = 350 kHz 350 300 VO = 1.05 V VO = 1.2 V 250 700 600 500 VO = 1.05 V VO = 1.8 V 400 VO = 1.2 V FSEL = V5FILT 300 200 0 5 10 15 20 0 25 5 10 15 20 25 VI - Input Voltage - V VI - Input Voltage - V G005 G004 Figure 14. SWITCHING FREQUENCY (IO = 1 A) vs. INPUT VOLTAGE Figure 15. SWITCHING FREQUENCY vs. INPUT VOLTAGE 600 800 FSEL = GND VI = 12 V 700 f(SW) - Swithing Frequency - kHz f(SW) - Swithing Frequency - kHz VO = 3.3 V 500 VO = 3.3 V 400 300 VO = 1.05 V VO = 3.3 V 600 500 VO = 1.05 V 400 300 FSEL = V5FILT VI = 12 V 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 IO - Output Current - A 3.5 4.0 200 0.0 1.0 1.5 2.0 2.5 3.0 3.5 IO - Output Current - A G006 Figure 16. SWITCHING FREQUENCY vs. OUTPUT CURRENT 0.5 4.0 G007 Figure 17. SWITCHING FREQUENCY vs. OUTPUT CURRENT Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 13 TPS53114 SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 www.ti.com 1.10 1.09 1.10 VI = 12 V 1.08 1.07 VO - Output Voltage - V VO - Output Voltage - V 1.08 FSEL = GND 1.06 1.05 1.04 FSEL = V5FILT 1.03 FSEL = V5FILT 1.07 1.06 1.05 1.04 FSEL = GND 1.03 1.02 1.02 1.01 1.01 1.00 0.0 IO = 3 A 1.09 1.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 IO - Output Current - A 0 15 VO (50mV/div) VO (50mV/div) FSEL = GND (350 kHz Selection) FSEL = V5FILT (700 kHz Selection) Iout1 (2A/div) Iout1 (2A/div) 25 G009 t - Time - 20 ms/div G010 Figure 20. 1.05-V LOAD TRANSIENT RESPONSE 20 Figure 19. 1.05-V OUTPUT VOLTAGE vs. INPUT VOLTAGE t - Time - 20 s/div 14 10 VI - Input Voltage - V G008 Figure 18. 1.05-V OUTPUT VOLTAGE vs. OUTPUT CURRENT 5 G011 Figure 21. 1.05-V LOAD TRANSIENT RESPONSE Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 TPS53114 www.ti.com SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 100 90 EN 80 - Efficiency - % 70 SS VO = 1.05 V 60 50 40 30 20 FSEL = GND 350 kHz Selection VI = 12 V 10 CSS = 4700 pF 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 IO - Output Current - A t - Time - 2 ms/div G012 Figure 22. STARTUP WAVEFORM G013 Figure 23. 1.05-V EFFICIENCY vs. OUTPUT CURRENT 100 90 80 - Efficiency - % 70 60 50 40 30 20 FSEL = V5FILT 700 kHz Selection VI = 12 V 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 IO - Output Current - A 3.5 4.0 G014 Figure 24. 1.05-V EFFICIENCY vs. OUTPUT CURRENT Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 15 TPS53114 SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 www.ti.com COMPONENT SELECTION CHOOSE INDUCTOR The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation. L1 can be calculated using Equation 3. (VIN(max) - VO1) L1 = 3/4 IL1(ripple) * fSW * 3 * (VIN(max) - VO1) VO1 3/4 3/4 = VIN(max) IO1 * fSW * VO1 3/4 VIN(max) (3) The inductors current ratings needs to support both the RMS (thermal) current and the peak (saturation) current. The RMS and peak inductor current can be estimated as follows: VIN(max) - VO1 IL1(ripple) = 3/4 L1 * fSW * VO1 3/4 VIN(max) (4) VTRIP 3/4 IL1(peak) = R + IL1(ripple) DS(ON) 3/4 IL1(RMS) = OIO12 + 3/4121 (IL1(ripple))2 (5) (6) Note: The calculation above shall serve as a general reference. To further improve transient response, the output inductance could be reduced further. This needs to be considered along with the selection of the output capacitor. CHOOSE OUTPUT CAPACITOR The capacitor value and ESR determines the amount of output voltage ripple and load transient response. Recommend to use ceramic output capacitor. 2 D Iload * L1 C1 = 23/4 * VO1 * DVOS (7) 2 D Iload * L1 C1 = 23/4 * K * DVUS (8) Where: Ton1 K = (VIN - VO1) * 3/4 TON1 + Tmin(off) (9) IL1(ripple) 1 * 3/4 C1 = 83/4 * VO1(ripple) fSW (10) Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and Equation 10. The capacitance for C1 should be greater than 66 mF. Where: * VOS = The allowable amount of overshoot voltage in load transition * VUS = The allowable amount of undershoot voltage in load transition * Tmin(off) = Minimum off time CHOOSE INPUT CAPACITOR The TPS53114 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A minimum 10-mF high-quality ceramic capacitor is recommended for the input capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage. 16 Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 TPS53114 www.ti.com SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 CHOOSE BOOTSTRAP CAPACITOR The TPS53114 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side drivers. A minimum 0.1-mF high-quality ceramic capacitor is recommended. The voltage rating should be greater than 10.0 V. CHOOSE VREG5 AND V5FILT CAPACITOR The TPS53114 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-mF high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum 1.0-mF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation. Both of these capacitors' voltage ratings should be greater than 10 V. CHOOSE OUTPUT VOLTAGE RESISTORS The output voltage is set with a resistor divider from output voltage node to the VFBx pin. It is recommended to use 1% tolerance or better resistors. Select R2 between 10 k and 100 k and use Equation 11 or Equation 12 to calculate R1. ( ) R1 = ( 3/4 ) 3/4 V1 R1 = 3/4 VFB1 0.765 + 3/4 2 O -1 (ripple) VO 1 -1 VFB1(ripple) 0.758 + 2 * R2 (FSEL = GND) (11) * R2 (FSEL = V5FILT) (12) Where: VFB1(ripple) = Ripple voltage at VFB1 CHOOSE RESISTOR SETTING FOR OVER CURRENT LIMIT ae (VIN - VO ) VO o VTRIP = c IOCL * / * RDS(ON) c 2 * L1 * | sw VIN /o e RTRIP (13) V (mV) - VOCLoff (kW ) = TRIP ITRIP (mA) (14) Where: * RDS(ON) = Low side FET on-resistance * ITRIP = TRIP pin source current 10 mA * VOCLoff = Minimum over current limit offset voltage (-20 mV) * IOCL = over current limit CHOOSE SOFT START CAPACITOR Soft start timing equations are as follows: C7 * 0.765 (s ) TSS = 3/4 -6 2e C7 * 0.758 (s ) TSS = 3/4 -6 2e (FSEL = GND) (15) (FSEL = V5FILT) (16) CHOOSE PACKAGE OPTION TPS53114 power dissipation: Pd = fSW * (CiH + CiL) * VREG5 * Vin(max) (17) Where: * CiH = Input capacitor of high side MOSFET * CiL = Input capacitor of low side MOSFET Choose package considering the Dissipation Rating table. Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 17 TPS53114 SLVS887B - APRIL 2009 - REVISED OCTOBER 2010 www.ti.com LAYOUT SUGGESTIONS * * * * * * Keep the input switching current loop as small as possible. Place the input capacitor (C3, C6) close to the top switching FET. The output current loop should also be kept as small as possible. Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin (VFB) of the device. Keep analog and non-switching components away from switching components. Make a single point connection from the signal ground to power ground. Do not allow switching current to flow under the device. Spacer REVISION HISTORY Changes from Original (April 2009) to Revision A * Page Updated the list of Features .................................................................................................................................................. 1 Changes from Revision A (August 2009) to Revision B Page * Changed Equation 13 From: IOCL + To: IOCL - ..................................................................................................................... 17 * Updated Equation 14 by adding minus VOCLoff .................................................................................................................... 17 18 Submit Documentation Feedback Copyright (c) 2009-2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53114 PACKAGE OPTION ADDENDUM www.ti.com 11-Sep-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS53114PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples TPS53114PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples TPS53114PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples TPS53114PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS53114PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS53114PWR TSSOP PW 16 2000 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53114PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS53114PWR TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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