MC74HC138ADG - ON SEMICONDUCTOR - searchdatasheet.com

July, 2012 − Rev. 12

1Publication Order Number:

MC74HC138A/D

MC74HC138A

1-of-8 Decoder/

Demultiplexer

High−Performance Silicon−Gate CMOS

The MC74HC138A is identical in pinout to the LS138. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

The HC138A decodes a three−bit Address to one−of−eight

active−low outputs. This device features three Chip Select inputs, two

active−low and one active−high to facilitate the demultiplexing,

cascading, and chip−selecting functions. The demultiplexing function

is accomplished by using the Address inputs to select the desired

device output; one of the Chip Selects is used as a data input while the

other Chip Selects are held in their active states.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC

Standard No. 7 A

•Chip Complexity: 100 FETs or 29 Equivalent Gates

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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MARKING

DIAGRAMS

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

16 PDIP−16

N SUFFIX

CASE 648

MC74HC138AN

AWLYYWWG

HC138AG

AWLYWW

138A

ALYWG

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)

MC74HC138A

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7Y6

CS1

CS2

A2 ACTIVE-LOW

OUTPUTS

ADDRESS

INPUTS

CS3

CHIP-

SELECT

INPUTS 5

PIN 16 = VCC

PIN 8 = GND

Inputs Outputs

CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X X H XXXHHHHHHHH

X H X XXXHHHHHHHH

L X X XXXHHHHHHHH

H L L LLL LHHHHHHH

H L L LLHHLHHHHHH

H L L LHLHHLHHHHH

H L L LHHHHHLHHHH

H L L HLLHHHHLHHH

H L L HLHHHHHHLHH

H L L HHLHHHHHHLH

H L L HHHHHHHHHHL

FUNCTION TABLE

H = high level (steady state); L = low level (steady state); X = don’t care

Figure 1. Pin Assignment

CS2

CS1

CS3

GND

VCC

Figure 2. Logic Diagram

ORDERING INFORMATION

Device Package Shipping†

MC74HC138ANG PDIP−16

(Pb−Free)

500 Units / Rail

MC74HC138ADG SOIC−16

(Pb−Free)

48 Units / Rail

MC74HC138ADR2G SOIC−16

(Pb−Free)

2500 / Tape & Reel

MC74HC138ADTR2G TSSOP−16

(Pb−Free)

2500 / Tape & Reel

NLV74HC138ADR2G* SOIC−16

(Pb−Free)

2500 / Tape & Reel

NLV74HC138ADTR2G* TSSOP−16

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable

MC74HC138A

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MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V

Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Iin DC Input Current, per Pin ±20 mA

Iout DC Output Current, per Pin ±25 mA

ICC DC Supply Current, VCC and GND Pins ±50 mA

PDPower Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

750

500

450

Tstg Storage Temperature – 65 to + 150 _C

TLLead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package) 260

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device

reliability.

†Derating −Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 .W/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

TAOperating Temperature, All Package Types – 55 + 125 _C

tr, tfInput Rise and Fall Time VCC = 2.0 V

(Figure 2) VCC = 4.5 V

VCC = 6.0 V

1000

500

400

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HC138A

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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol Parameter Test Conditions

VCC

Guaranteed Limit

Unit

−55_C to 25_Cv 85_Cv 125_C

VIH Minimum High−Level Input

Voltage

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

2.0

3.0

4.5

6.0

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

VIL Maximum Low−Level Input

Voltage

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

2.0

3.0

4.5

6.0

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

VOH Minimum High−Level Output

Voltage

Vin = VIH or VIL

|Iout| v 20 mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL Maximum Low−Level Output

Voltage

Vin = VIH or VIL

|Iout| v 20 mA

2.0

4.5

6.0

0.1

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

3.0

4.5

6.0

0.26

0.33

0.40

Iin Maximum Input Leakage

Current

Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA

ICC Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 mA

6.0 4 40 160 mA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Symbol Parameter

VCC

Guaranteed Limit

Unit

−55_C to 25_Cv 85_Cv 125_C

tPLH,

tPHL

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 4)

2.0

3.0

4.5

6.0

135

170

125

205

165

tPLH,

tPHL

Maximum Propagation Delay, CS1 to Output Y

(Figures 2 and 4)

2.0

3.0

4.5

6.0

110

140

100

165

125

tPLH,

tPHL

Maximum Propagation Delay, CS2 or CS3 to Output Y

(Figures 3 and 4)

2.0

3.0

4.5

6.0

120

150

120

180

150

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 2 and 4)

2.0

3.0

4.5

6.0

110

Cin Maximum Input Capacitance −10 10 10 pF

CPD Power Dissipation Capacitance (Per Package)*

Typical @ 25°C, VCC = 5.0 V

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

MC74HC138A

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Figure 1.

50%

tPHL

tPLH

VCC

GND

Figure 2.

VALID VALID

OUTPUT Y 50%

VCC

GND

tPLH

tTLH

90%

50%

10%

OUTPUT Y

INPUT CS1

tPHL

90%

50%

10%

tTHL

INPUT A

SWITCHING WAVEFORMS

tTHL tTLH

VCC

GND

tPHL tPLH

OUTPUT Y

INPUT

CS2, CS3

90%

50%

10%

90%

50%

10%

Figure 3.

*Includes all probe and jig capacitance

Figure 4. Test Circuit

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

PIN DESCRIPTIONS

ADDRESS INPUTS

A0, A1, A2 (Pins 1, 2, 3)

Address inputs. These inputs, when the chip is selected,

determine which of the eight outputs is active−low.

CONTROL INPUTS

CS1, CS2, CS3 (Pins 6, 4, 5)

Chip select inputs. For CS1 at a high level and CS2, CS3

at a low level, the chip is selected and the outputs follow the

Address inputs. For any other combination of CS1, CS2, and

CS3, the outputs are at a logic high.

OUTPUTS

Y0 − Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)

Active−low Decoded outputs. These outputs assume a

low level when addressed and the chip is selected. These

outputs remain high when not addressed or the chip is not

selected.

MC74HC138A

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CS3

CS2

CS1

EXPANDED LOGIC DIAGRAM

MC74HC138A

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PACKAGE DIMENSIONS

PDIP−16

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

16 PL

SEATING

916

PLANE

−T−

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

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PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45_

8 PLP

−B−

−A−

0.25 (0.010) B S

−T−

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC138A

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PACKAGE DIMENSIONS

TSSOP−16

CASE 948F−01

ISSUE B

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

16 9

DETAIL E

ÉÉÉ

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC138A

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