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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
4M-BIT [512K x 8] SINGLE VOLTAGE
5V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• SinglePowerSupplyOperation
-4.5to5.5voltforread,erase,andprogramoperations
• 524288x8only
• SectorStructure
-64K-Bytex8
• Latch-upprotectedto100mAfrom-1VtoVcc+1V
• CompatiblewithJEDECstandard
-PinoutandsoftwarecompatibletosinglepowersupplyFlash
PERFORMANCE
• HighPerformance
-Accesstime:70/90ns
-Programtime:9us(typical)
-Erasetime:0.7s/sector,4s/chip(typical)
• LowPowerConsumption
-Lowactivereadcurrent:30mA(maximum)at5MHz
-Lowstandbycurrent:1uA(typical)
• Minimum100,000erase/programcycle
• 20yearsdataretention
SOFTWARE FEATURES
• EraseSuspend/EraseResume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
• StatusReply
-Data#Polling&Togglebitsprovidedetectionofprogramanderaseoperationcompletion
PACKAGE
• 32-PinPLCC
• 32-PinTSOP
• All devices are RoHS Compliant
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MX29F040C
Contents
FEATURES .................................................................................................................................................................. 1
GENERALFEATURES ...............................................................................................................................1
SOFTWAREFEATURES ............................................................................................................................1
PACKAGE ..................................................................................................................................................1
PIN CONFIGURATIONS .............................................................................................................................................. 4
PIN DESCRIPTION ...................................................................................................................................................... 5
LOGICSYMBOL .........................................................................................................................................5
BLOCK DIAGRAM ....................................................................................................................................................... 6
Table 1. SECTOR STRUCTURE ................................................................................................................................. 7
MX29F040CSECTORADDRESSTABLE .................................................................................................. 7
Table 2. BUS OPERATION ..........................................................................................................................................7
REQUIREMENTSFORREADINGARRAYDATA ......................................................................................8
WRITECOMMANDS/COMMANDSEQUENCES .......................................................................................8
AUTOMATICSELECTOPERATION ..........................................................................................................8
DATAPROTECTION ...................................................................................................................................9
WRITEPULSE"GLITCH"PROTECTION ..................................................................................................9
LOGICALINHIBIT .......................................................................................................................................9
POWER-UPSEQUENCE ...........................................................................................................................9
POWER-UPWRITEINHIBIT ......................................................................................................................9
POWERSUPPLYDECOUPLING ...............................................................................................................9
TABLE 3. MX29F040C COMMAND DEFINITIONS ................................................................................................... 10
RESET ..................................................................................................................................................... 11
AUTOMATICSELECTCOMMANDSEQUENCE ..................................................................................... 11
AUTOMATICPROGRAMMING ................................................................................................................12
CHIPERASE ...........................................................................................................................................13
SECTORERASE ......................................................................................................................................13
SECTORERASESUSPEND ....................................................................................................................14
SECTORERASERESUME ......................................................................................................................14
ABSOLUTE MAXIMUM STRESS RATINGS ............................................................................................................. 15
OPERATING TEMPERATURE AND VOLTAGE ........................................................................................................ 15
DC CHARACTERISTICS ........................................................................................................................................ 16
SWITCHING TEST CIRCUITS ................................................................................................................................... 17
AC CHARACTERISTICS ......................................................................................................................................... 18
Figure1.COMMANDWRITEOPERATION .............................................................................................19
READ/RESET OPERATION ...................................................................................................................................... 20
Figure2.READTIMINGWAVEFORMS ...................................................................................................20
ERASE/PROGRAM OPERATION ............................................................................................................................. 21
Figure3.AUTOMATICCHIPERASETIMINGWAVEFORM ....................................................................21
Figure4.AUTOMATICCHIPERASEALGORITHMFLOWCHART ..........................................................22
Figure5.AUTOMATICSECTORERASETIMINGWAVEFORM ..............................................................23
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MX29F040C
Figure6.AUTOMATICSECTORERASEALGORITHMFLOWCHART ..................................................24
Figure7.ERASESUSPEND/RESUMEFLOWCHART ............................................................................25
Figure8.AUTOMATICPROGRAMTIMINGWAVEFORMS .....................................................................26
Figure9.CE#CONTROLLEDWRITETIMINGWAVEFORM ..................................................................27
Figure10.AUTOMATICPROGRAMMINGALGORITHMFLOWCHART .................................................28
Figure11.SILICONIDREADTIMINGWAVEFORM ................................................................................29
WRITE OPERATION STATUS ................................................................................................................................... 30
Figure12.DATA#POLLINGTIMINGWAVEFORMS(DURINGAUTOMATICALGORITHMS) ................ 30
Figure13.DATA#POLLINGALGORITHM ...............................................................................................31
Figure14.TOGGLEBITTIMINGWAVEFORMS(DURINGAUTOMATICALGORITHMS) .....................32
Figure15.TOGGLEBITALGORITHM ...................................................................................................33
RECOMMENDED OPERATING CONDITIONS ......................................................................................................... 34
FigureA.ACTimingatDevicePower-Up .................................................................................................34
ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 35
DATA RETENTION .................................................................................................................................................... 35
LATCH-UP CHARACTERISTICS .............................................................................................................................. 35
ORDERING INFORMATION ...................................................................................................................................... 36
PACKAGE INFORMATION ........................................................................................................................................38
REVISION HISTORY ................................................................................................................................................. 40
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MX29F040C
PIN CONFIGURATIONS
32 PLCC
32 TSOP (Standard Type) (8mm x 20mm)
1
4
5
9
13
14 17 20
21
25
29
32 30 A14
A13
A8
A9
A11
OE#
A10
CE#
Q7
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
Q3
Q4
Q5
Q6
A12
A15
A16
A18
VCC
WE#
A17
MX29F040C
A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX29F040C
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MX29F040C
LOGIC SYMBOL
SYMBOL PIN NAME
A0~A18 AddressInput
Q0~Q7 DataInput/Output
CE# ChipEnableInput
WE# WriteEnableInput
OE# OutputEnableInput
GND GroundPin
VCC +5.0Vsinglepowersupply
PIN DESCRIPTION
8
Q0-Q7
A0-A18
CE#
OE#
WE#
19
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MX29F040C
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q7
A0-AM
AM: MSB address
CE#
OE#
WE#
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MX29F040C
Sector Sector Address Address Range
A18 A17 A16
SA0 000 00000h-0FFFFh
SA1 001 10000h-1FFFFh
SA2 010 20000h-2FFFFh
SA3 011 30000h-3FFFFh
SA4 100 40000h-4FFFFh
SA5 101 50000h-5FFFFh
SA6 110 60000h-6FFFFh
SA7 111 70000h-7FFFFh
Note: Allsectorsare64Kbytesinsize.
Table 1. SECTOR STRUCTURE
MX29F040C SECTOR ADDRESS TABLE
Table 2. BUS OPERATION
Notes:
1.Vhvistheveryhighvoltage,11.5Vto12.5V.
2.Xmeansinputhigh(Vih)orinputlow(Vil).
Mode Pins CE# OE# WE# A0 A1 A6 A9 Q0 ~ Q7
ReadSiliconID
ManufactureCode L L H L L XVhv C2H
ReadSiliconID
DeviceCode L L H H L XVhv A4H
Read L L H A0 A1 A6 A9 DOUT
Standby H XXXXXX HIGHZ
OutputDisable L H H XXXX HIGHZ
Write L H L A0 A1 A6 A9 DIN
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MX29F040C
REQUIREMENTS FOR READING ARRAY DATA
Readarrayactionistoreadthedatastoredinthearrayout.Whilethememorydeviceisinpowereduporhas
beenreset,itwillautomaticallyenterthestatusofreadarray.Ifthemicroprocessorwantstoreadthedatastored
inarray,ithastodriveCE#(deviceenablecontrolpin)andOE#(Outputcontrolpin)asVil,andinputtheaddress
ofthedatatobereadintoaddresspinatthesametime.Afteraperiodofreadcycle(TceorTaa),thedatabeing
readoutwillbedisplayedonoutputpinformicroprocessortoaccess.IfCE#orOE#isVih,theoutputwillbein
tri-state,andtherewillbenodatadisplayedonoutputpinatall.
Afterthememorydevicecompletesembeddedoperation(automaticEraseorProgram),itwillautomaticallyre-
turntothestatusofreadarray,andthedevicecanreadthedatainanyaddressinthearray.Intheprocessof
erasing,if thedevice receivesthe Erasesuspend command,erase operationwill bestopped aftera periodof
timenomorethanTreadyandthedevicewillreturntothestatusofreadarray.Atthistime,thedevicecanread
thedatastoredinanyaddressexceptthesectorbeingerasedinthearray.Inthestatusoferasesuspend,ifuser
wantstoreadthedatainthesectorsbeingerased,thedevicewilloutputstatusdataontotheoutput.Similarly,if
programcommandisissuedaftererasesuspend,afterprogramoperationiscompleted,systemcanstillreadar-
raydatainanyaddressexceptthesectorstobeerased.
Thedeviceneedstoissueresetcommandtoenablereadarrayoperationagaininordertoarbitrarilyreadthe
datainthearrayinthefollowingtwosituations:
1.Inprogramoreraseoperation,theprogrammingorerasingfailurecausesQ5togohigh.
2.Thedeviceisinautoselectmode.
Inthe twosituationsabove, ifresetcommand isnot issued,thedevice isnot inreadarray modeandsystem
mustissueresetcommandbeforereadingarraydata.
WRITE COMMANDS/COMMAND SEQUENCES
Towriteacommandtothedevice,systemmustdriveWE#andCE#toVil,andOE#toVih.Inacommandcycle,
alladdress arelatchedat thelaterfalling edgeof CE#andWE#, andall dataarelatched attheearlier rising
edgeofCE#andWE#.
"Figure 1. COMMAND WRITE OPERATION"illustratestheACtimingwaveformofawritecommand,and"TA-
BLE 3. MX29F040C COMMAND DEFINITIONS"denesallthevalidcommandsetsofthedevice.Systemisnot
allowedtowriteinvalidcommandsnotdenedinthisdatasheet.Writinganinvalidcommandwillbringthedevice
toanundenedstate.
AUTOMATIC SELECT OPERATION
Whenthedevice isinRead arraymodeor erase-suspended readarray mode, usercanissue readsiliconID
commandtoenterreadsiliconIDmode.AfterenteringreadsiliconIDmode,usercanqueryseveralsiliconIDs
continuouslyanddoes notneedto issuereadsilicon ID modeagain. WhenA0 isLow,device will outputMa-
cronixManufactureIDC2.WhenA0ishigh,devicewilloutputDeviceID.InreadsiliconIDmode,issuingreset
commandwillresetdevicebacktoreadarraymodeorerase-suspendedreadarraymode.
AnotherwaytoenterreadsiliconIDistoapplyhighvoltageonA9pinwithCE#,OE#andA1atVil.Whilethe
highvoltageofA9pinisdischarged,devicewillautomaticallyleavereadsiliconIDmodeandgobacktoread
arraymodeorerase-suspendedreadarraymode.WhenA0isLow,devicewilloutputMacronixManufactureID
C2.WhenA0ishigh,devicewilloutputDeviceID.
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DATA PROTECTION
Toavoidaccidentalerasureorprogrammingofthedevice,thedeviceisautomaticallyresettoreadarraymode
duringpowerup.Besides,onlyaftersuccessfulcompletionofthespeciedcommandsetswillthedevicebegin
itseraseorprogramoperation.
Otherfeaturestoprotectthedatafromaccidentalalternationaredescribedasfollowed.
WRITE PULSE "GLITCH" PROTECTION
CE#,WE#,OE#pulsesshorterthan5ns aretreatedasglitchesandwillnot beregardedasaneffectivewrite
cycle.
LOGICAL INHIBIT
AvalidwritecyclerequiresbothCE#andWE#atVilwithOE#atVih.WritecycleisignoredwheneitherCE#at
Vih,WE#aVih,orOE#atVil.
POWER-UP SEQUENCE
Uponpowerup,MX29F040Cisplacedinreadarraymode.Furthermore,programoreraseoperationwillbegin
onlyaftersuccessfulcompletionofspeciedcommandsequences.
POWER-UP WRITE INHIBIT
WhenWE#,CE#isheldatVilandOE#isheldatVihduringpowerup,thedeviceignorestherstcommandon
therisingedgeofWE#.
POWER SUPPLY DECOUPLING
A0.1uFcapacitorshouldbeconnectedbetweentheVccandGNDtoreducethenoiseeffect.
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TABLE 3. MX29F040C COMMAND DEFINITIONS
Notes:
1.DeviceID:A4H.
2. Itisnotallowedtoadoptanyothercodewhichisnotintheabovecommanddenitiontable.
Command Read
Mode
Reset
Mode
AutomaticSelect Program Chip
Erase
Sector
Erase
Erase
Suspend
Erase
Resume
ManufacturerID DeviceID
1stBus
Cycle
Addr Addr XXX 555 555 555 555 555 XXX XXX
Data Data F0 AA AA AA AA AA B0 30
2ndBus
Cycle
Addr 2AA 2AA 2AA 2AA 2AA
Data 55 55 55 55 55
3rdBus
Cycle
Addr 555 555 555 555 555
Data 90 90 A0 80 80
4thBus
Cycle
Addr X00 X01 Addr 555 555
Data C2 ID Data AA AA
5thBus
Cycle
Addr 2AA 2AA
Data 55 55
6thBus
Cycle
Addr 555 Sector
Data 10 30
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RESET
Inthefollowingsituations,executingresetcommandwillresetdevicebacktoreadarraymode:
• Amongerasecommandsequence(beforethefullcommandsetiscompleted)
• Sectorerasetime-outperiod
• Erasefail(whileQ5ishigh)
• Amongprogramcommand sequence(beforethefullcommandsetiscompleted,erase-suspendedprogram
included)
• Programfail(whileQ5ishigh,anderase-suspendedprogramfailisincluded)
• ReadsiliconIDmode
Whiledeviceisatthestatusofprogramfailorerasefail(Q5ishigh),usermustissueresetcommandtoreset
devicebacktoreadarraymode.WhilethedeviceisinreadsiliconIDmode,usermustissueresetcommandto
resetdevicebacktoreadarraymode.
Whenthedeviceisintheprogressofprogramming(notprogramfail)orerasing(noterasefail),devicewillig-
noreresetcommand.
AUTOMATIC SELECT COMMAND SEQUENCE
AutomaticSelectmodeisusedtoaccessthemanufacturerID,deviceID.Theautomaticselectmodehasfour
command cycles. The rst two are unlock cycles, and followed by a specic command.The fourth cycle is a
normalreadcycle,andusercanreadatanyaddressanynumberoftimeswithoutenteringanothercommand
sequence.TheresetcommandisnecessarytoexittheAutomaticSelectmodeandbacktoreadarray.Thefol-
lowingtableshowstheidenticationcodewithcorrespondingaddress.
Address Data (Hex)
ManufacturerID X00 C2
DeviceID X01 A4
Thereisanalternativemethodtothatshownin"Table 2. BUS OPERATION",whichisintendedforEPROMpro-
grammersandrequiresVhvonaddressbitA9.
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MX29F040C
AUTOMATIC PROGRAMMING
TheMX29F040Ccanprovidetheuserprogramfunction.Aslongastheusersentertherightcycledenedinthe
"TABLE 3. MX29F040C COMMAND DEFINITIONS"(including2unlockcyclesandA0H),anydatauserinputs
willautomaticallybeprogrammedintothearray.
Once the program function is executed, the internal write state controller will automatically execute the algo-
rithms and timings necessary for program and verication, which includes generating suitable program pulse,
verifyingwhetherthethresholdvoltageoftheprogrammedcellishighenoughandrepeatingtheprogrampulse
ifanyofthecellsdoesnotpassverication.Meanwhile,theinternalcontrolwillprohibittheprogrammingtocells
thatpassvericationwhiletheothercellsfailinvericationinordertoavoidover-programming.
Programmingwillonlychangethebitstatusfrom"1"to"0".Thatistosay,itisimpossibletoconvertthebitstatus
from"0"to"1"byprogramming.Meanwhile,theinternalwritevericationonlydetectstheerrorsofthe"1"thatis
notsuccessfullyprogrammedto"0".
Anycommandwrittentothedeviceduringprogrammingwillbeignoredexcepthardwarereset,whichwilltermi-
natetheprogramoperationafteraperiodoftimenomorethanTready.Whentheembeddedprogramalgorithm
iscompleteortheprogramoperationisterminatedbyhardwarereset,thedevicewillreturntothereadingarray
datamode.
Withtheinternalwritestatecontroller,thedevicerequirestheusertowritetheprogramcommandanddataonly.
ThetypicalchipprogramtimeatroomtemperatureoftheMX29F040Cis4.5seconds.
Whentheembeddedprogramoperationisongoing,usercanconrmiftheembeddedoperationisnishedor
notbythefollowingmethods:
*1:Thestatus"inprogress"meansbothprogrammodeanderase-suspendedprogrammode.
Status Q7 Q6 Q5
Inprogress*1 Q7# togging 0
Finished Q7 Stoptoggling 0
Exceedtimelimit Q7# Toggling 1
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MX29F040C
SECTOR ERASE
SectorEraseistoeraseallthedatainasectorwith"1"and"0"asall"1".Itrequiressixcommandcyclestois-
sue.Thersttwocyclesare"unlockcycles",thethirdoneisacongurationcycle,thefourthandftharealso
"unlockcycles"andthesixthcycleisthesectorerasecommand.Afterthesectorerasecommandsequenceis
issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector ad-
dressandsectorerasecommandcanbewrittenmultiply.Onceuserentersanothersectorerasecommand,the
time-outperiodof50usisrecounted.Ifuserentersanycommandotherthansectoreraseorerasesuspenddur-
ingtime-outperiod,theerasecommandwouldbeabortedandthedeviceisresettoreadarraycondition.The
numberofsectorscouldbefromonesectortoallsectors.Aftertime-outperiodpassingby,additionalerasecom-
mandisnotacceptedanderaseembeddedoperationbegins.
Duringsectorerasing,allcommandswillnotbeacceptedexcepthardwareresetanderasesuspendanduser
cancheckthestatusaschiperase.
Status Q7 Q6 Q5 Q2
Inprogress 0Togging 0Toggling
Finished 1Stoptoggling 0 1
Exceedtimelimit 0Toggling 1Toggling
Whentheembeddederaseoperationisongoing,usercanconrmiftheembeddedoperationisnishedornot
bythefollowingmethods:
Status Q7 Q6 Q5 Q3 Q2
Time-outperiod 0Toggling 0 0 Toggling
Inprogress 0Togging 0 1 Toggling
Finished 1Stoptoggling 011
Exceedtimelimit 0Toggling 1 1 Toggling
CHIP ERASE
ChipEraseistoeraseallthedatawith"1"and"0"asall"1".Itneeds6cyclestowritetheactionin,andtherst
twocyclesare"unlock"cycles,thethirdoneisacongurationcycle,thefourthandftharealso"unlock"cycles,
andthesixthcycleisthechiperaseoperation.
Duringchiperasing,allthecommandswillnotbeacceptedexcepthardwarerestsortheworkingvoltageistoo
lowthatchiperasewillbeinterrupted.AfterChipErase,thechipwillreturntothestateofReadArray.
Whentheembeddedchiperaseoperationisongoing,usercanconrmiftheembeddedoperationisnishedor
notbythefollowingmethods:
*1:ThestatusQ3isthetime-outperiodindicator.WhenQ3=0,thedeviceisintime-outperiodandisacceptible
toanothersectoraddresstobeerased.WhenQ3=1,thedeviceisineraseoperationandonlyerasesuspendis
valid.
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MX29F040C
When the device has suspended erasing, user can execute the command sets except sector erase and chip
erase,suchasreadsiliconID,program,anderaseresume.
SECTOR ERASE RESUME
Sectoreraseresumecommandisvalidonlywhenthedeviceisinerasesuspendstate.Aftereraseresume,user
canissueanothererasesuspendcommand,butthereshould bea400usintervalbetweeneraseresume and
thenexterasesuspend.Ifuserissueinnitesuspend-resumeloop,orsuspend-resumeexceeds1024times,the
timeforerasingwillincrease.
Status Q7 Q6 Q5 Q3 Q2
Erasesuspendreadinerasesuspendedsector 1Notoggle 0N/A toggle
Erasesuspendreadinnon-erasesuspendedsector Data Data Data Data Data
Erasesuspendprograminnon-erasesuspendedsector Q7# Toggle 0N/A N/A
SECTOR ERASE SUSPEND
Duringsectorerasure,sectorerasesuspendistheonlyvalidcommand.Ifuserissueerasesuspendcommand
inthetime-outperiodofsectorerasure,devicetime-outperiodwillbeoverimmediatelyandthedevicewillgo
backtoerase-suspendedreadarraymode.Ifuserissueerasesuspendcommandduringthesectoreraseisbe-
ingoperated,devicewillsuspendtheongoingeraseoperation,andaftertheTready1(<=20us)suspendnishes
andthedevicewillentererase-suspendedreadarraymode.Usercanjudgeifthedevicehasnishederasesus-
pendthroughQ6,andQ7.
Afterdevicehasenterederase-suspendedreadarraymode,usercanreadothersectorsnotaterasesuspend
bythespeedofTaa;whilereadingthesectorinerase-suspendmode,devicewilloutputitsstatus.Usercanuse
Q6andQ2tojudgethesectoriserasingortheeraseissuspended.
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MX29F040C
ABSOLUTE MAXIMUM STRESS RATINGS
SurroundingTemperaturewithBias.................................................-65oCto+125oC
StorageTemperature............................................................-65oCto+150oC
VoltageRange
Vcc........................................................................-0.5Vto+7.0V
A9.......................................................................-0.5Vto+13.5V
Theotherpins.............................................................-0.5VtoVcc+0.7V
OutputShortCircuitCurrent(lessthanonesecond)......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200mA
Note:
1.Minimumvoltagemayundershootto-2Vduringtransitionandforlessthan20nsduringtransitions.
2.MaximumvoltagemayovershoottoVcc+2Vduringduringtransitionandforlessthan20nsduringtransitions.
OPERATING TEMPERATURE AND VOLTAGE
Commercial (C) Grade
SurroundingTemperature(TA)........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°Cto+70°C
Industrial (I) Grade
SurroundingTemperature(TA)......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°Cto+85°C
VCC Supply Voltages
VCC range........................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5Vto5.5V
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MX29F040C
DC CHARACTERISTICS
Symbol Description Min Typ Max Remark
Iilk InputLeak ± 1.0uA
Iolk OutputLeak 10uA
Icr1 ReadCurrent(10MHz) 50mA CE#=Vil,OE#=Vih
Icr2 ReadCurrent(5MHz) 40mA CE#=Vil,OE#=Vih
Icw WriteCurrent 15mA 30mA CE#=Vil,OE#=Vih,WE#=ViL
Isb1 StandbyCurrent(TTL) 1mA Vcc=Vccmax,CE#=Vih
otherpindisable
Isb2 Standbycurrent(CMOS) 1uA 5uA Vcc=Vcc max, CE#=vcc +0.3V,
otherpindisable
Vil InputLowVoltage -0.3V 0.8V
Vih InputHighVoltage 0.7xVcc Vcc+0.3V
Vhv VeryHighVoltageforAutoSelect 11.5V 12V 12.5V
Vol OutputLowVoltage 0.45V Iol=2.1mA,Vcc=Vccmin
Voh1 OuputHighVoltage(TTL) 2.4V Ioh1=-2mA
Voh2 OuputHighVoltage(CMOS) Vcc-0.4V Ioh2=-100uA
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
SWITCHING TEST CIRCUITS
TestCondition
OutputLoad:1TTLgate
OutputLoadCapacitance,CL:100PFfor90ns,30PFfor70ns
Rise/FallTimes:10nS
Input/Outputreferencelevels:0.8V,2.0V
SWITCHING TEST WAVEFORMS
R1=6.2Kohm
R2=2.7Kohm
TESTED DEVICE
DIODES=IN3064
OR EQUIVALENT
CL
R1
Vcc
0.1uF
R2
Vcc
2.0V 2.0V
0.8V
0.8V
TEST POINTS
0.7xVCC
0.45V
OUTPUT
INPUT
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MX29F040C
AC CHARACTERISTICS
Symbol Description Speed Option -70/90 Unit
Min Typ Max
Taa Validdataoutputafteraddress 70/90 ns
Tce ValiddataoutputafterCE#low 70/90 ns
Toe ValiddataoutputafterOE#low 30/35 ns
Tdf DataoutputoatingafterOE#highorCE#high 20 ns
Toh Outputholdtimefrom theearliestrisingedgeofAddrss,
CE#,OE#
0ns
Trc Readperiodtime 70/90 ns
Twp WE#pulsewidth 35 ns
Twph WE#pulsewithhigh 30 ns
Tghwl Readrecovertimebeforewrite 0ns
Twc Writeperiodtime 70/90 ns
Tcwc Commandwriteperiodtime 70/90 ns
Tas Addresssetuptime 0ns
Tah Addressholdtime 45 ns
Tds Datasetuptime 30/45 ns
Tdh Dataholdtime 0ns
Tcs CE#Setuptime 0ns
Tch CE#holdtime 0ns
Toes OE#setuptime 0ns
Tcep CE#pulsewidth 35/45 ns
Tceph CE#pulsewidthhigh 20 ns
Tavt Programoperation 9 300 us
Taetc ChipEraseOperation 432 sec
Taetb SectorEraseOperation 0.7 8 sec
Tbal SectorAddressholdtime 50 us
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 1. COMMAND WRITE OPERATION
Addresses
CE#
OE#
WE#
DIN
Tds
Tah
Data
Tdh
Tcs Tc h
Tcwc
Toes
Tas
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
VA
VA: Valid Address
Twp Twph
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORMS
Addresses
CE#
OE#
Taa
WE#
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh
Vol
HIGH Z HIGH Z
DATA Valid
Toe Tdf
Tce
Outputs
Toh
ADD Valid
Trc
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MX29F040C
ERASE/PROGRAM OPERATION
Figure 3. AUTOMATIC CHIP ERASE TIMING WAVEFORM
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MX29F040C
Figure 4. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
YES
NO Data=FFh ?
Write Data 10H Address 555H
Write Data 55H Address 2AAH
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Chip Erase Completed
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 5. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Twc
Address
OE#
CE#
55h
2AAh Sector
Address 1
Sector
Address 0
30h
In
Progress Complete
VA VA
30h
Sector
Address n
Tas
Tah
Tbal
Tch
Tds Tdh
Taetb
Read Status
Last 2 Erase Command Cycle
Tcs
WE#
Data
30h
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 6. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
Write Data 30H Sector Address
Write Data 55H Address 2AAH
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Sector Erase Completed
NO
Last Sector
to Erase
YES
YES
NO
Data=FFh
25
P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 7. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
Toggle Bit checking Q6
not toggled
ERASE SUSPEND
YES
NO
Write Data 30H
Continue Erase
Reading or
Programming End
Read Array or
Program
Another
Erase Suspend ? NO
YES
YES
NO
ERASE RESUME
26
P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 8. AUTOMATIC PROGRAM TIMING WAVEFORMS
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Ta h
Tch
Tds Tdh
Tavt
Last 2 Read Status CycleLast 2 Program Command Cycle
Tcs
WE#
Data
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 9. CE# CONTROLLED WRITE TIMING WAVEFORM
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Ta h
Tghwl
Tcep
Tds Tdh
Tavt or Taetb
Tceph
WE#
Data
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 10. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Program Data/Address
Write Data A0H Address 555H
YES
Read Again Data:
Program Data?
YES
Auto Program Completed
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
Last Byte to be
Programed
No
No
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 11. SILICON ID READ TIMING WAVEFORM
Taa
Tce
Taa
Toe
Toh To h
Tdf
DATA OUT
C2H A4H
Vhv
Vih
Vil
A9
ADD
CE#
A1
OE#
WE#
A0
DATA OUT
DATA
Q0-Q7
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
30
P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
WRITE OPERATION STATUS
Figure 12. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tdf
Tce
Tch
Toe
Toh
CE#
OE#
WE#
Q7
Q0-Q6 Status Data Status Data
ComplementComplement True Valid Data
Taa
Address VAVA
High Z
High Z
Valid DataTrue
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 13. DATA# POLLING ALGORITHM
Read Q7~Q0 at valid address
(Note 1)
Read Q7~Q0 at valid address
Start
Q7 = Data# ?
Q5 = 1 ?
Q7 = Data# ?
(Note 2)
FAIL Pass
No
No
No
Yes
Yes
Yes
Notes:
1.Forprogramming,validaddressmeasprogramaddress.
Forerasing,validaddressmeaserasesectorsaddress.
2.Q7shouldberecheckedevenQ5="1"becauseQ7maychangesimultaneouslywithQ5.
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 14. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tdf
Tce
Tch
Toe
Taa
Toh
Address
CE#
OE#
WE#
Q6/Q2 Valid Status
(first read)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
Notes:
1. VA : Valid Address
2. CE# must be toggled when toggle bit is toggling.
VA
Valid Data
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
Figure 15. TOGGLE BIT ALGORITHM
Notes:
1.Readtogglebittwicetodeterminewhetherornotitistoggling.
2.RechecktogglebitbecauseitmaystoptogglingasQ5changesto"1".
Read Q7-Q0 Twice
Q5 = 1?
Read Q7~Q0 Twice
Program/Erase fail
Write Reset CMD Program/Erase Complete
Q6 Toggle ?
Q6 Toggle ?
NO
(Note1)
(Note1, 2)
YES
NO
NO
YES
YES
Start
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
ACtimingillustratedin"Figure A. AC Timing at Device Power-Up"isrecommendedforthesupplyvoltagesand
thecontrolsignalsatdevicepower-up.Ifthetiminginthegureisignored,thedevicemaynotoperatecorrectly.
Figure A. AC Timing at Device Power-Up
Vcc
ADDRESS
CE#
WE#
OE#
DATA
Tvr
Taa
Tr or Tf Tr or Tf
Tce
Tf
Vcc(min)
GND
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh
High Z
Vol
Valid
Ouput
Valid
Address
Tr
Toe
Tf Tr
Symbol Parameter Min. Max. Unit
Tvr VccRiseTime 20 500000 uS/V
Tr InputSignalRiseTime 20 uS/V
Tf InputSignalFallTime 20 uS/V
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
LATCH-UP CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE
Parameter Symbol Parameter Description Test Set TYP MAX UNIT
CIN2 ControlPinCapacitance VIN=0 12 pF
COUT OutputCapacitance VOUT=0 12 pF
CIN InputCapacitance VIN=0 8 pF
TSOP AND PLCC PIN CAPACITANCE
PARAMETER LIMITS
MIN. TYP. MAX. UNITS
ByteProgrammingTime 9 300 us
SectorEraseTime 0.7 8 sec
ChipEraseTime 432 sec
ChipProgrammingTime 4.5 13.5 sec
Erase/ProgramCycles 100,000 Cycles
Note: 1.Typicalconditionmeans25°C, 5V.
2.Maximumconditionmeans90°C,4.5V,100Kcycles.
MIN. MAX.
InputVoltagedifferencewithGNDonallpinsexceptI/Opins -1.0V 13.5V
InputVoltagedifferencewithGNDonallI/Opins -1.0V VCC+1.0V
VccCurrent -100mA +100mA
IncludesallpinsexceptVCC.Testconditions:VCC=5V,onepinpertesting
DATA RETENTION
PARAMETER Condition Min. Max. UNIT
Dataretention 55˚C 20 years
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P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
ORDERING INFORMATION
PART NO. Access
Time (ns)
Operating
Current
MAX.(mA)
Standby
Current
MAX.(uA)
Temperature
Range
PACKAGE Remark
MX29F040CQC-70G 70 30 5 0oC~70oC32PinPLCC
MX29F040CQC-90G 90 30 5 0oC~70oC32PinPLCC
MX29F040CTC-70G 70 30 5 0oC~70oC32PinTSOP
(NormalType)
MX29F040CTC-90G 90 30 5 0oC~70oC32PinTSOP
(NormalType)
MX29F040CQI-70G 70 30 5 -40oC~85oC32PinPLCC
MX29F040CQI-90G 90 30 5 -40oC~85oC32PinPLCC
MX29F040CTI-70G 70 30 5 -40oC~85oC32PinTSOP
(NormalType)
MX29F040CTI-90G 90 30 5 -40oC~85oC32PinTSOP
(NormalType)
37
P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
PART NAME DESCRIPTION
MX 29 F 70C T I G
OPTION:
G: RoHS Compliant package
blank: normal
SPEED:
70:70ns
90: 90ns
TEMPERATURE RANGE:
I: Industrial (-40C to 85C)
PACKAGE:
Q: PLCC
T: TSOP
REVISION:
C
DENSITY & MODE:
040: 4M, x8 Equal Sector
TYPE:
F: 5V
DEVICE:
29: Flash
040
.
38
P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
PACKAGE INFORMATION
39
P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
40
P/N:PM1201 REV. 2.2, DEC. 04, 2012
MX29F040C
REVISION HISTORY
Revision No. Description Page Date
1.0 1.Removed"Preliminary"title P1 DEC/20/2005
2.Removedcommercialgrade All
3.Addedaccesstime:55ns;Removedaccesstime:120ns All
1.1 1.Removedaccesstime:55ns P1,13,15,16 JUN/21/2006
P29,30
2.Removedsectorprotect/chipunprotectfeature P1,5~7,10,12
P26~29
3.Addeddata#polling,togglebitalgorithm P20,21
1.2 1.DataSheetformatchanged All AUG/15/2006
1.3 1.Datamodication All AUG/17/2006
1.4 1.Addedstatement P40 NOV/06/2006
1.5 1.RemovedPDIPpackageoption P1,2,34,35 JAN/18/2007
2.AddedrecommedationfornonRoHScompliantdevices P1,34
1.6 1.Addednote1into"TABLE 3. MX29F040C COMMAND DEFINITIONS"P8 JAN/17/2008
1.7 1.Modied"Figure 9. CE# CONTROLLED WRITE TIMING WAVEFORM"P25 FEB/21/2008
1.8 1.RemovednonPb-freeEPNs P1,34,35 SEP/15/2008
2.AddedC-gradeEPNs P34,35
1.9 1.ModiedFigure10.CE#ControlledWriteTimingWaveform P25 MAR/09/2009
(Changed"Twhwh1orTwhwh2"into"TavtorTaetb")
2.
Modied"Figure 12. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)"P28
2.0 1.AddedNoteofmaximum/minimumvoltageduringtransition P13 MAY/26/2009
intoDCcharacteristics
2.AddedDC:IcwspecandmodifyMax.Icr1 P14
3.AddedAC:Twp/Twph/Tghwlspec P16
2.1 1.Added"DATA RETENTION"table P33 JUN/30/2009
2.Modiedthesectorerasetimemaxfrom15sto8s P16,33
2.2 1. ModieddescriptionforRoHScompliance P1,36,37 DEC/04/2012
2.ModiedOutputLoadCapatitance P17
MX29F040C
41
Exceptfor customizedproducts whichhas beenexpressly identiedin the applicableagreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
householdapplicationsonly,andnotforuseinanyapplicationswhichmay,directlyorindirectly,causedeath,
personalinjury,orseverepropertydamages.IntheeventMacronixproductsareusedincontradictedtotheir
targetusageabove,thebuyershalltakeanyandallactionstoensuresaidMacronix'sproductqualiedforits
actualuseinaccordancewiththeapplicablelawsandregulations;andMacronixaswellasit’ssuppliersand/or
distributorsshallbereleasedfromanyandallliabilityarisentherefrom.
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tradenamethereof,suchasMacronix,MXIC,MXICLogo,MXLogo,IntegratedSolutionsProvider,NBit,Nbit,
NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech,MXSMIO,MacronixvEE,MacronixMAP,RichAudio,RichBook,RichTV,andFitCAM.Thenames
andbrandsofthirdpartyreferredthereto(ifany)areforidenticationpurposesonly.
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