This ispreliminary information ona new product indevelopment orundergoing evaluation. Details aresubject to change without notice.
version 4.5
April 2002 ADCS 7155031 1/18
STV7610A
PLASMA DISPLAY PANEL DATA DRIVER
FEATURES
■96 Output- Plasma Display Driver
■100 V Absolute Maximum Rating
■5 V Supply for Logic
■-70/+90 mA Source/sinkOutput MOS
■6 bit Cascadable Data Bus (20 MHz)
■Blank, Polarity Control
■BCD Technology
■Packaging TQFP144 or Dice
DESCRIPTION
The STV7610A is a BCD data driver for Plasma
Display Panel (PDP). Using a 6-bit wide cascada-
ble data bus, it addresses 96 high current & high
voltage outputs. By serially connecting several
STV7610A, any horizontal pixel definition can be
performed. The 20MHz shift clock gives an equiv-
alent 120 MHz shift register. The STV7610A is
supplied with a separated 90 V power output sup-
ply anda5 Vlogic supply. All command inputs are
CMOS compatible.
TQFP144 (20 x 20 x 1.4 mm)
(Thin Plastic Quad Flat Pack)
ORDER CODE: STV7610A
DIE
ORDER CODE: STV7610A/WAF(1)
(1): Unsawn tested wafer
1
Table of Contents
2
2/18
PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................. 3
PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................. 4
PIN LIST . . . . . ................................................................. 5
PAD COORDINATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................ 6
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CIRCUIT DESCRIPTION . ....................................................... 10
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... 11
THERMAL DATA . . . . . . . . . . . . . . ................................................ 11
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC TIMINGS REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC TIMINGS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
INPUT/OUTPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TESTED WAFER DISCLAIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................ 16
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . ................................ 17
2
STV7610A
ADCS 7155031 3/18
PIN CONNECTIONS
(DIE Pinout)
VPP
OUT33
OUT32
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1OUT96
OUT95
OUT94
OUT93
OUT92
OUT91
OUT90
OUT89
OUT88
OUT87
OUT86
OUT85
OUT84
OUT83
OUT82
OUT81
OUT80
OUT79
OUT78
OUT77
OUT76
OUT75
OUT74
OUT73
OUT72
OUT71
OUT70
OUT69
OUT68
OUT67
OUT66
OUT65
OUT64
VPP
OUT63
OUT62
OUT61
OUT60
OUT59
OUT58
OUT57
OUT56
OUT55
OUT54
OUT53
OUT52
OUT51
OUT50
OUT49
OUT48
OUT47
OUT46
OUT45
OUT44
OUT43
OUT42
OUT41
OUT40
OUT39
OUT38
OUT37
OUT36
OUT35
OUT34
VSSP
VSSP
VSSP
VPP
B6
B5
B4
B3
B2
B1
BLK
F/R
POL
VCC
VSSLOG
VSSSUB
CLK
STB
A1
A2
A3
A4
A5
A6
VPP
VSSP
STV7610A
Bare Die
VPP VPP
(0,0)
Y
X
3
STV7610A
4/18 ADCS 7155031
PIN CONNECTIONS
(TQFP Pinout)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VPP
OUT33
OUT32
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1OUT96
OUT95
OUT94
OUT93
OUT92
OUT91
OUT90
OUT89
OUT88
OUT87
OUT86
OUT85
OUT84
OUT83
OUT82
OUT81
OUT80
OUT79
OUT78
OUT77
OUT76
OUT75
OUT74
OUT73
OUT72
OUT71
OUT70
OUT69
OUT68
OUT67
OUT66
OUT65
OUT64
VPP
OUT63
OUT62
OUT61
OUT60
OUT59
OUT58
OUT57
OUT56
OUT55
OUT54
OUT53
OUT52
OUT51
OUT50
OUT49
OUT48
OUT47
OUT46
OUT45
OUT44
OUT43
OUT42
OUT41
OUT40
OUT39
OUT38
OUT37
OUT36
OUT35
OUT34
VSSP
NC
NC
NC
NC
VSSP
NCNC
NC
NC
NC
VSSP
VPP
NC
NC
B6
B5
B4
B3
B2
B1
BLK
F/R
POL
VCC
VSSLOG
VSSSUB
CLK
STB
A1
A2
A3
A4
A5
A6
NC
VPP
NC
VSSP
NC
NC
NC
NC
STV7610A
TQFP144
NC
VPP VPP
3
STV7610A
ADCS 7155031 5/18
PIN LIST
(TQFP144)
PIN LIST (Power outputs)
Pin N°Symbol Type Description
3-37-38-39-41-43-48-65-67-69-
70-71-72-106-110-111-142-143 -NC
1-2-42-66-107-108 VPP Supply High Voltage Supply of Power Outputs
53 VCC Ground 5V Logic Supply
40-68-109-144 VSSP Ground Ground of Power Outputs
54 VSSLOG Ground Logic Ground
55 VSSSUB Output Substrate Ground
73 to 105 OUT 1 toOUT 33 Output Power Output
112 to 141 OUT 34 to OUT 63 Input Power Output
4 to 36 OUT 64 to OUT 96 Input Power Output
50 BLK Input Blanking Input
51 POL Input Polarity Input
52 F/R Input Selection of Shift Direction
56 CLK Input Clock of data Shift Register
57 STB Input Latch of data to Outputs
59 to 64 A1 to A6 Input/Output Forward Shift Register Input
44 to 49 B6 to B1 Input/Output Forward Shift Register Output
Output N°Pin N°Output N°Pin N°Output N°Pin N°Output N°Pin N°
1 73 25 97 49 127 73 13
2 74 26 98 50 128 74 14
3 75 27 99 51 129 75 15
4 76 28 100 52 130 76 16
5 77 29 101 53 131 77 17
6 78 30 102 54 132 78 18
7 79 31 103 55 133 79 19
8 80 32 104 56 134 80 20
9 81 33 105 57 135 81 21
10 82 34 112 58 136 82 22
11 83 35 113 59 137 83 23
12 84 36 114 60 138 84 24
13 85 37 115 61 139 85 25
14 86 38 116 62 140 86 26
15 87 39 117 63 141 87 27
3
STV7610A
6/18 ADCS 7155031
PAD COORDINATES
(in µm)
Pad positions from the middle of the top side
Pad positions along the right side
16 88 40 118 64 4 88 28
17 89 41 119 65 5 89 29
18 90 42 120 66 6 90 30
19 91 43 121 67 7 91 31
20 92 44 122 68 8 92 32
21 93 45 123 69 9 93 33
22 94 46 124 70 10 94 34
23 95 47 125 71 11 95 35
24 96 48 126 72 12 96 36
Output N°Pin N°Output N°Pin N°Output N°Pin N°Output N°Pin N°
Name Center Size
XYXY
OUT 48 74.0 3034.0 80.0 90.0
OUT 47 210.0 3034.0 80.0 90.0
OUT 46 346.0 3034.0 80.0 90.0
OUT 45 482.0 3034.0 80.0 90.0
OUT 44 618.0 3034.0 80.0 90.0
OUT 43 754.0 3034.0 80.0 90.0
OUT 42 890.0 3034.0 80.0 90.0
OUT 41 1026.0 3034.0 80.0 90.0
OUT 40 1162.0 3034.0 80.0 90.0
OUT 39 1298.0 3034.0 80.0 90.0
OUT 38 1434.0 3034.0 80.0 90.0
OUT 37 1570.0 3034.0 80.0 90.0
OUT 36 1706.0 3034.0 80.0 90.0
OUT 35 1842.0 3034.0 80.0 90.0
OUT 34 1993.0 3034.0 80.0 90.0
Name Centre Size
XYXY
V
SSP 2116.0 2795.0 90.0 80.0
VPP 2029.8 2496.5 90.0 90.0
VPP 2041.5 1843.0 90.0 80.0
OUT 33 2117.0 1580.0 90.0 80.0
OUT 32 2117.0 1444.0 90.0 80.0
OUT 31 2117.0 1308.0 90.0 80.0
OUT 30 2117.0 1172.0 90.0 80.0
OUT 29 2117.0 1036.0 90.0 80.0
OUT 28 2117.0 900.0 90.0 80.0
OUT 27 2117.0 764.0 90.0 80.0
OUT 26 2117.0 628.0 90.0 80.0
OUT 25 2117.0 492.0 90.0 80.0
OUT 24 2117.0 356.0 90.0 80.0
OUT 23 2117.0 220.0 90.0 80.0
OUT 22 2117.0 84.0 90.0 80.0
OUT 21 2117.0 -52.0 90.0 80.0
OUT 20 2117.0 -188.0 90.0 80.0
OUT 19 2117.0 -324.0 90.0 80.0
OUT 18 2117.0 -460.0 90.0 80.0
OUT 17 2117.0 -596.0 90.0 80.0
OUT 16 2117.0 -732.0 90.0 80.0
OUT 15 2117.0 -868.0 90.0 80.0
OUT 14 2117.0 -1004.0 90.0 80.0
OUT 13 2117.0 -1140.0 90.0 80.0
OUT 12 2117.0 -1276.0 90.0 80.0
OUT 11 2117.0 -1412.0 90.0 80.0
Name Centre Size
XYXY
3
STV7610A
ADCS 7155031 7/18
Pad positions along the bottom side
OUT 10 2117.0 -1548.0 90.0 80.0
OUT 9 2117.0 -1684.0 90.0 80.0
OUT 8 2117.0 -1820.0 90.0 80.0
OUT 7 2117.0 -1956.0 90.0 80.0
OUT 6 2117.0 -2092.0 90.0 80.0
OUT 5 2117.0 -2228.0 90.0 80.0
OUT 4 2117.0 -2364.0 90.0 80.0
OUT 3 2117.0 -2500.0 90.0 80.0
OUT 2 2117.0 -2636.0 90.0 80.0
OUT 1 2117.0 -2832.0 90.0 80.0
Name Centre Size
XYXY
V
SSP 1904.0 -3034.0 80.0 90.0
VPP 1698.0 -3034.0 80.0 90.0
A6 1499.0 -3034.0 80.0 90.0
A5 1349.0 -3034.0 80.0 90.0
A4 1199.0 -3034.0 80.0 90.0
Name Centre Size
XYXY
A3 1049.0 -3034.0 80.0 90.0
A2 899.0 -3034.0 80.0 90.0
A1 749.0 -3034.0 80.0 90.0
STB 449.0 -3034.0 80.0 90.0
CLK 299.0 -3034.0 80.0 90.0
GNDsub 156.5 -3034.0 80.0 90.0
GND 3.0 -3034.0 80.0 90.0
VCC -158.0 -3034.0 80.0 90.0
F/R -299.0 -3034.0 80.0 90.0
POL -449.0 -3034.0 80.0 90.0
BLK -599.0 -3034.0 80.0 90.0
B1 -749.0 -3034.0 80.0 90.0
B2 -899.0 -3034.0 80.0 90.0
B3 -1049.0 -3034.0 80.0 90.0
B4 -1199.0 -3034.0 80.0 90.0
B5 -1349.0 -3034.0 80.0 90.0
B6 -1499.0 -3034.0 80.0 90.0
VPP -1698.0 -3034.0 80.0 90.0
VSSP -1904.0 -3034.0 80.0 90.0
Name Centre Size
XYXY
3
STV7610A
8/18 ADCS 7155031
Pad Positions along the left side
Pad Positions along the top side
Name Centre Size
XYXY
OUT 96 -2117.0 -2832.0 90.0 80.0
OUT 95 -2117.0 -2636.0 90.0 80.0
OUT 94 -2117.0 -2500.0 90.0 80.0
OUT 93 -2117.0 -2364.0 90.0 80.0
OUT 92 -2117.0 -2228.0 90.0 80.0
OUT 91 -2117.0 -2092.0 90.0 80.0
OUT 90 -2117.0 -1956.0 90.0 80.0
OUT 89 -2117.0 -1820.0 90.0 80.0
OUT 88 -2117.0 -1684.0 90.0 80.0
OUT 87 -2117.0 -1548.0 90.0 80.0
OUT 86 -2117.0 -1412.0 90.0 80.0
OUT 85 -2117.0 -1276.0 90.0 80.0
OUT 84 -2117.0 -1140.0 90.0 80.0
OUT 83 -2117.0 -1004.0 90.0 80.0
OUT 82 -2117.0 -868.0 90.0 80.0
OUT 81 -2117.0 -732.0 90.0 80.0
OUT 80 -2117.0 -596.0 90.0 80.0
OUT 79 -2117.0 -460.0 90.0 80.0
OUT 78 -2117.0 -324.0 90.0 80.0
OUT 77 -2117.0 -188.0 90.0 80.0
OUT 76 -2117.0 -52.0 90.0 80.0
OUT 75 -2117.0 84.0 90.0 80.0
OUT 74 -2117.0 220.0 90.0 80.0
OUT 73 -2117.0 356.0 90.0 80.0
OUT 72 -2117.0 492.0 90.0 80.0
OUT 71 -2117.0 628.0 90.0 80.0
OUT 70 -2117.0 764.0 90.0 80.0
OUT 69 -2117.0 900.0 90.0 80.0
OUT 68 -2117.0 1036.0 90.0 80.0
OUT 67 -2117.0 1172.0 90.0 80.0
OUT 66 -2117.0 1308.0 90.0 80.0
OUT 65 -2117.0 1444.0 90.0 80.0
OUT 64 -2117.0 1580.0 90.0 80.0
VPP -2041.5 1843.0 90.0 80.0
VPP -2029.8 2496.5 90.0 80.0
VSSP -2116.0 2795.0 90.0 80.0
Name Centre Size
XYXY
OUT 63 -1980.0 3034.0 80.0 90.0
OUT 62 -1830.0 3034.0 80.0 90.0
OUT 61 -1694.0 3034.0 80.0 90.0
OUT 60 -1558.0 3034.0 80.0 90.0
OUT 59 -1422.0 3034.0 80.0 90.0
OUT 58 -1286.0 3034.0 80.0 90.0
OUT 57 -1150.0 3034.0 80.0 90.0
OUT 56 -1014.0 3034.0 80.0 90.0
OUT 55 -878.0 3034.0 80.0 90.0
OUT 54 -742.0 3034.0 80.0 90.0
OUT 53 -606.0 3034.0 80.0 90.0
OUT 52 -470.0 3034.0 80.0 90.0
OUT 51 -334.0 3034.0 80.0 90.0
OUT 50 -198.0 3034.0 80.0 90.0
OUT 49 -62.0 3034.0 80.0 90.0
Name Centre Size
XYXY
3
STV7610A
ADCS 7155031 9/18
BLOCK DIAGRAM
LOGIC
16-BIT SHIFT REGISTER
P1 P91
16-BIT SHIFT REGISTER
P2 P92
16-BIT SHIFT REGISTER
16-BIT SHIFT REGISTER
P4 P94
16-BIT SHIFT REGISTER
P5 P95
16-BIT SHIFT REGISTER
P6 P96
LATCH
Q1 Q96
P3 P93
Q2 Q95
P96P95P6P1
52
53
56
59 49
60 48
61 47
62 46
63 45
64 44
57 54
55
50
51
73 36
VSSP
Pins 40-68-109-144
VPP
Pins 1-2-42-66-107-108
VCC
VSSSUB
VSSLOG
B6
B5
B4
B3
B2
B1A1
A2
A3
A4
A5
A6
STB
POL
BLK
FOR/REVCLK
OUT1 OUT96
STV7610A
VCC
VCC
VCC
3
STV7610A
10/18 ADCS 7155031
CIRCUIT DESCRIPTION
The STV7610A contains all the logic and the pow-
er circuits necessary to drive the columns of a
Plasma Display Panel (P. D. P.). The binary value
of eachpixelofthe displayedlineis loadedinto the
shift register. Data are input in a 6-bit wide data
bus to A1 - A6 input (case of forward shift mode).
Data are shifted at each low to high transition of
the CLKshift clock. After 16 shifts the first data are
available on B1 - B6 outputs. These B1 - B6 out-
puts can be used to cascade several drivers to
perform any horizontal resolution. The forward/
(F/R) input is used to select the direc-
tion of the shift register, A1 - A6 and B1 - B6 data
bus input/output status is set according to the se-
lected direction. F/R= H, A is an input and B is an
output.
Serial inputs,CLK, STB inputs are Smith trigger in-
puts. If not used in the application, Blanking (BLK),
Polarity (POL are internally pulled to level “H”. The
maximum frequency of the shift clock is 20 MHz.
This leads to an equivalent 120 MHz serial shift
register.
On low level of STB, data is transferred from shift
register to the latch stage. Data will not be re-
freshed as long as STB is kept high.
Blanking input (BLK) forces the power outputs to
low level when pulled low. All the power outputs
are set at high level when the Polarity command
(POL) is pulled low and the Blanking (BLK) input is
at high level.
VSSSUB and VSSLOG must be connected as close
as possible to the logical reference ground of the
application.
Shift Register Truth Table
Power Output Truth Table
Note 1 Qn+1 = A1, Qn + 2 = A2, Qn + 3 = A3, Qn + 4 = A4, Qn + 5 = A5, Qn + 6 = A6, n = [0,6,12,18,...,90]
reverse
Input Input/Output Shift Register
Function
F/R CLK A B Output Q
H Rise IN OUT Forward shift
H H or L IN OUT Steady
L Rise OUT IN Reverse shift
L H or L OUT IN Steady
Qn STB BLK POL Driver
Output Comments
X X L X L Output low
X X H L H Output high
X H H H Qn Data latched
L L H H L Data copied
H L H H H Data copied
3
STV7610A
ADCS 7155031 11/18
ABSOLUTE MAXIMUM RATINGS
Note 2 Through one power output (all power outputs).
Note 3 Through one power output for all power outputs (see Test Diagram) with Junction temperature lower or equal
than Tjmax.
Note 4 These parameters are measured during ST’s internal qualification which includes temperature characterisation
on standard batches and on corners batches of the process. These parameters are not tested on the parts.
Note 5 Transient current. Spike current duration inferior to 300ns.
THERMAL DATA
Symbol Parameter Value Unit
VCC Logic Supply Range (Pin 53) -0.3, +7 V
OUTi Output Pins (4 to 36, 73 to 105, 112 to 141) -0.3, +100 V
VIN Logic Input Voltage (Pins 50, 51, 52, 56, 57, 59 to 64) -0.3, +VCC +0.3 V
VOUT Logic Output Voltage (Pin 44 to 49) -0.3, +VCC +0.3 V
I
POUT Driver Output Current ( Note 2) ( Note 4) ( Note 5) -150/ +150 mA
IDOUT Diode Output Current ( Note 3) ( Note 4) ( Note 5) -200/ +300 mA
TjJunction Temperature +150 °C
Toper Operating Temperature -20, +85 °C
Tstg Storage Temperature -50, +150 °C
Symbol Parameter Value Unit
Rth(j-a) Junction-ambient Thermal Resistance Typ. 41 °C/W
3
STV7610A
12/18 ADCS 7155031
ELECTRICAL CHARACTERISTICS
(VCC =5V,V
PP =90V,V
SSP =0V,V
SSLOG =0V,V
SSSUB =0V,T
amb =25°C, fCLK = 20 MHz,
unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
SUPPLY
VCC Logic Supply Voltage 4.5 5 5.5 V
ICCH Logic Supply Current (all inputs high) - - 100 µA
ICCL Logic Dynamic Supply Current fCLK =20MHz - 26 - mA
V
PP Power Output Supply Voltage 15 - 90 V
IPPH Power Output Supply Current
(steady outputs) - - 100 µA
OUTPUT (VPP = 15 V to 90 V)
OUT 1- OUT 96
VPOUTH Power Output Voltage Drop
(High Level) (versus VPP)IPOUTH = - 30 mA
IPOUTH = - 45mA -
-4.0
4.5 6.0
6.5 V
V
VPOUTL Power Output Voltage Drop
(Low Level) IPOUTL = + 30 mA - 1.6 4 V
VDOUTH Output Diode Voltage (High Level) IDOUTH = +45 mA (Figure 2) - 1.05 4 V
VDOUTL Output Diode Low Level IDOUTL = - 30mA (Figure 2) - -0.95 -4 V
A1-A6, B1-B6
VOH Logic Output (High Level) IOH = -1 mA 4 4.2 - V
VOL Logic Output (Low Level) IOL = +1 mA - 0.12 0.4 V
INPUT
CLK, F/R, STB, POL, BLK, A1-A6, B1-B6
VIH Input Voltage (High Level) 0.8 VCC --V
V
IL Input Voltage (Low Level) - - 0.2VCC V
IIH High Level Input Current VIH =V
CC --10µA
I
IL Low Level Input Current
CLK, A1-A6, B1-B6, STB,
F/R, BLK, POL
VIL =0V -
--
--10
-40 µA
µA
3
STV7610A
ADCS 7155031 13/18
AC TIMINGS REQUIREMENTS
(VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, inputsignals max leading edge & trailing edge (tR,t
F
) = 10 ns)
AC TIMINGS CHARACTERISTICS
(VCC =5V,V
PP =90V
,V
SPP =0V,V
SSLOG =0V,V
SSSUB =0V,T
amb =25°C)
(VIL(Max.) = 0.2 Vcc, VIH(Min.) = 0.8 VCC,V
OH = 4.0V, VOL = 0.4 V, unless otherwise specified)
Note 6 For IC in cascading configuration and in case a time delay is inserted on the clock signal of the cascaded IC, the
maximum value of this time delay must be set at the minimum value of tPHL1, tPLH1 (Figure 7).
Note 7 One output among 96, loading capacitor CL= 50pF, other outputs at low level.
Symbol Parameter Min. Typ. Max. Unit
tWHCLK Duration of clock (CLK) pulse at high level 15 - - ns
tWLCLK Duration of clock (CLK) pulse at low level 15 - - ns
tSDAT Set-up Time of data input before clock (low to high) transition 10 - - ns
tHDAT Hold Time of data input after clock (low to high) transition 10 - - ns
tSFR Forward/ (F/R) Set-up Time before clock
(low to high) transition 100 - - ns
tDSTB Minimum Delay to latch STB after clock (low to high) transition 10 - - ns
tSSTB Minimum Delay to latch STB before clock (low to high) transition 10 - - ns
tSTB Latch STB Low Level Pulse Duration 20 - - ns
tBLK Blanking BLK Pulse Duration 500 - - ns
tPOL Polarity POL Pulse Duration 500 - - ns
Symbol Parameter Min. Typ. Max. Unit
tCLK Data clock Period 50 - - ns
tRDAT Logical Data Output Rise Time (CL=10pF) - 12 20 ns
tFDAT Logical Data Output Fall Time (CL=10pF) - 11 20 ns
tPHL1
tPLH1 Delay oflogic data output (high to low transition) after clock (CLK) transition Note 6
Delay oflogic data output (low to high transition) after clock (CLK) transition Note 6 15
15 35
35 50
50 ns
ns
tPHL2
tPLH2
Delay of power output change (high to low transition) after clock (CLK) transition
Delay of power output change (low to high transition) after clock (CLK) transition -
-135
80 180
180 ns
ns
tPHL3
tPLH3 Delay of power output change (high to low transition) after Latch (STB) transition
Delay of power output change (low to high transition) after Latch (STB) transition -
-115
70 165
165 ns
ns
tPHL4
tPLH4
Delay of power output change (high to low transition) to Blank or Polarity (BLK,POL)
transition
Delay of power output change (low to high transition) to Blank or Polarity (BLK,POL)
transition
-
-
100
55
160
160
ns
ns
tROUT Power Output Rise Time ( Note 7) - 50 150 ns
tFOUT Power Output Fall Time ( Note 7) - 80 200 ns
reverse
3
STV7610A
14/18 ADCS 7155031
Figure 1: AC Characteristics Waveform
F/R
OUTn
OUTn
BLK (POL=#0#)
tSFR
“1”
“0”
tPHL3
tPLH3
90%
10%
tPHL2
tPLH2
“1”
“0”
tBLK
50% 50%
“1”
“0”
90%
10%
“1”
“0”
tPHL4 tPLH4
90%
10%
tR OUT
tF OUT
90%
10%
STB 50% 50%
tSTB
tSSTB
“0”
“1”
tHSTB
tCLK
tWHCLK tWLCLK
“0”
“1”
CLK
“0”
“1”
tSDAT tHDAT
50% 50%
A INPUT
“0”
“1”
10%
90% 90%
10%
tPHL1
tPLH1
tFDAT
tRDAT
B OUTPUT
3
STV7610A
ADCS 7155031 15/18
Figure 2: Test Configuration
INPUT/OUTPUT SCHEMATICS
Figure 3: POL,BLK,F/RInput
Figure 4: CLK, STB Input
Figure 5: A1 to A6, B1 to B6
Figure 6: Power Output
VDOUTH IDOUTH
VSSP
VDOUTL IDOUTL
VSSP
VPP=VSSP
VPP=VSSP
Output sinking current as positive value, sourcing current as negative value
POL,BLK, F/R
Pins51, 50, 52
VCC
VCC
GNDLOG
GNDSUB
CLK, STB
Pins 56,57
VCC VCC
GNDLOG
GNDSUB
A1to A6,
B1 to B6
Pins 59 to 64,
49 to 44
VCC VCC
GNDLOG
GNDSUB
VCC
VPP
OUT1 to OUT 96
Pins 73 to 105,
112 to 141, 4 to 36
VSSP
3
STV7610A
16/18 ADCS 7155031
Figure 7: IC cascading mode suggestion
TESTED WAFER DISCLAIMER
All wafers are testedand guaranteed to comply with all datasheet limits up to the point of wafer sawing for
a period of ninety (90) days from the delivery date.
We remind you that it is the customer’s responsibility to test and qualify their application in which the die
is used. ST Microelectronics is ready to support the customer when qualifying the product.
STV7610A
STV7610A
time delay
data in
data out
data in
clock
Vcc
STV7610A
ADCS 7155031 17/18
PACKAGE MECHANICAL DATA
144 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
Dimensions Millimetres Inches
Min. Typ. Max. Min. Typ. Max.
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.17 0.22 0.27 0.0067 0.0087 0.011
C 0.09 0.20 0.0035 0.008
D 22.00 0.866
D1 20.00 0.787
D3 17.50 0.689
e 0.50 0.020
E 22.00 0.866
E1 20.00 0.787
E3 17.50 0.689
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
K0°(Min.), 7°(Max.)
c
B
A1 A2
A
L
K
L1
0,25 mm
.010 inch
GAGE PLANE
0.03 inch
SEATING PLANE
0,076 mm
144 109
e
37 72
1
36 73
108
D3
D1
D
E3
E1
E
STV7610A
18/18 ADCS 7155031
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no
responsibility forthe consequences ofuse of such information nor for any infringement of patents or other
rights of thirdparties which may result fromits use. No license isgranted byimplication or otherwise under
any patent or patentrights ofSTMicroelectronics. Specifications mentioned in this publication aresubject
to change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved
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