UCC15701/2
UCC25701/2
UCC35701/2
Advanced Voltage Mode Pulse Width Modulator
DESCRIPTION
The UCC35701/UCC35702 family of pulse width modulators is intended for
isolated switching power supplies using primary side control. They can be
used for both off-line applications and DC/DC converter designs such as in
a distributed power system architecture or as a telecom power source.
The devices feature low startup current, allowing for efficient off-line start-
ing, yet have sufficient output drive to switch power MOSFETs in excess of
500kHz.
Voltage feed forward compensation is operational over a 5:1 input range
and provides fast and accurate response to input voltage changes over a
4:1 range. An accurate volt-second clamp and maximum duty cycle limit
are also featured.
Fault protection is provided by pulse by pulse current limiting as well as the
ability to latch off after a programmable number of repetitive faults has oc-
curred.
Two UVLO options are offered. UCC35701 family has turn-on and turn-off
thresholds of 13V/9V and UCC35702 family has thresholds of 9.6V/8.8V.
The UCC35701/2 and the UCC25701/2 are offered in the 14 pin SOIC (D),
14 pin PDIP (N) or in 14 pin TSSOP (PW) packages. The UCC15701/2 is
offered in the 14 pin CDIP (J) package.
3VDD
12 VREF
8FB
4OUT
2ILIM
5PGND
C3
1 COUNT
CF
14 SS
CS
11 SYNC
9VSCLAMP
VREF
10 CT
CT
7RT
6VFF
13GND
VIN SUPPLY
VIN RETURN
RGND
R10
RCS
R8
R7
R6
C2
R8
RF
R5
R4
R3
R2
R1
VOUT
UCC35701
C1 C4
C6
R12 C6
C5
R11
R13
C7
R14
VOUT
R15
TYPICAL APPLICATION DIAGRAM
SLUS293C - JANUARY 2000 - REVISED JUNE 2005
FEATURES
700kHz Operation
Integrated Oscillator/ Voltage Feed
Forward Compensation
Accurate Duty Cycle Limit
Accurate Volt-second Clamp
Optocoupler Interface
Fault Counting Shutdown
Fault Latch off or Automatic Shutdown
Soft Stop Optimized for Synchronous
Rectification
1A Peak Gate Drive Output
130mA Start-up Current
750mA Operating Current
UDG-98005-1
application
INFO
available
2
UCC15701/2
UCC25701/2
UCC35701/2
ABSOLUTE MAXIMUM RATINGS
Supply voltage (Supply current limited to 20mA) ........ 15V
Supply Current................................. 20mA
Input pins ( ILIM,VFF,RT,CT,VSCLAMP,SYNC,SS, FB) . . . 6V
Output Current (OUT) DC..................... +/–180mA
Output Current (OUT) Pulse (0.5ms) .............. +/–1.2A
Storage Temperature................... –65°C to +150°C
Junction Temperature...................–55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............ +300°C
Note: All voltages are with respect to GND. Currents are posi-
tive into the specified terminal. Consult Packaging Section of
the Databook for thermal limitations and considerations of
packages.
VR E F
GND
SS
SYNC
CT
FB
VS C LAMP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ILIM
COUNT
VFF
RT
VDD
OUT
PGND
CONNECTION DIAGRAMS
DIL-14, SOIC-14, TSSOP-14 (TOP VIEW)
N or J, D, PW PACKAGE
ELECTRICAL CHARACTERISTICS:Unless otherwise specified, VDD = 11V, RT = 60.4k, CT= 330pF, CREF =C
VDD =
0.1mF, VFF = 2.0V, and no load on the outputs.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
UVLO Section
Start Threshold (UCCX5701) 12 13 14 V
(UCCX5702) 8.8 9.6 10.4 V
Stop Threshold (UCCX5701) 8 9 10 V
(UCCX5702) 8.0 8.8 9.6 V
Hysteresis (UCCX5701) 3 4 V
(UCCX5702) 0.3 0.8 V
Supply Current
Start-up Current (UCCX5701) VDD = 11V, VDD Comparator Off 130 200 mA
(UCCX5702) VDD = 8V, VDD Comparator Off 120 190 mA
IDD Active VDD Comparator On 0.75 1.5 mA
VDD Clamp Voltage (UCCX5701) IDD = 10mA 13.5 14.3 15 V
(UCCX5702) IDD = 10mA 13 13.8 15 V
VDD Clamp – Start Threshold (UCCX5701) 1.3 V
(UCCX5702) 4.2 V
Voltage Reference
VREF VDD = 10V to 13V, IVREF = 0mA to 2mA 4.9 5 5.1 V
Line Regulation VDD = 10V to 13V 20 mV
Load Regulation IVREF = 0mA to 2mA 2 mV
Short Circuit Current VREF = 0V, TJ= 25°C 20 50 mA
TA=T
JUVLO
Option Package Part Number
–55°C to +125°C 13V / 9V CDIP-14 UCC15701J
9.6V / 8.8V CDIP-14 UCC15702J
–40°C to +85°C
13V/9V SOIC-14 UCC25701D
PDIP-14 UCC25701N
TSSOP-14 UCC25701PW
9.6V / 8.8V SOIC-14 UCC25702D
PDIP-14 UCC25702N
TSSOP-14 UCC25702PW
0°C to +70°C
13V/9V SOIC-14 UCC35701D
PDIP-14 UCC35701N
TSSOP-14 UCC35701PW
9.6V / 8.8V SOIC-14 UCC35702D
PDIP-14 UCC35702N
TSSOP-14 UCC35702PW
The D and PW packages are available taped and reeled. Add
TR suffix to the device type (e.g., UCC35701DTR).
ORDERING INFORMATION
3
UCC15701/2
UCC25701/2
UCC35701/2
ELECTRICAL CHARACTERISTICS:Unless otherwise specified, VDD = 11V, RT = 60.4k, CT= 330pF, CREF =C
VDD =
0.1mF, VFF = 2.0V, and no load on the outputs.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Line Sense
Vth High Line Comparator 3.9 4 4.1 V
Vth Low Line Comparator 0.5 0.6 0.7 V
Input Bias Current –100 100 nA
Oscillator Section
Frequency VFF = 0.8V to 3.2V 90 100 110 kHz
Frequency VFF = 0.6V to 3.4V (Note 1) 90 100 110 kHz
SYNC VIH 2V
SYNC VIL 0.8 V
SYNC Input Current VSYNC = 2.0V 3 10 mA
RT Voltage VFF = 0.4V 0.5 0.6 0.7 V
VFF = 0.8V 0.75 0.8 0.85 V
VFF = 2.0V 1.95 2.0 2.05 V
VFF = 3.2V 3.15 3.2 3.25 V
VFF = 3.6V 3.3 3.4 3.5 V
CTPeak Voltage VFF = 0.8V (Note 1) 0.8 V
VFF = 3.2V (Note 1) 3.2 V
CTValley Voltage (Note 1) 0 V
Soft Start/Shutdown/Duty Cycle Control Section
ISS Charging Current 10 18 30 mA
ISS Discharging Current 300 500 750 mA
Saturation VDD = 11V, IC Off 25 100 mV
Fault Counter Section
Threshold Voltage VFF = 0.8V to 3.2V 3.8 4 4.2 V
Saturation Voltage VFF = 0.8V to 3.2V 100 mV
Count Charging Current 10 18 30 mA
Current Limit Section
Input Bias Current –100 0 100 nA
Current Limit Threshold 180 200 220 mV
Shutdown Threshold 500 600 700 mV
Pulse Width Modulator Section
FB Pin Input Impedance VFB = 3V 30 50 100 kW
Minimum Duty Cycle VFB <= 1V 0 %
Maximum Duty Cycle VFB >= 4.5V, VSCLAMP >= 2.0V 95 99 100 %
PWM Gain VFF = 0.8V 35 50 70 %/V
Volt Second Clamp Section
Maximum Duty Cycle VFF = 0.8V, VSCLAMP = 0.6V 69 74 79 %
Minimum Duty Cycle VFF = 3.2V, VSCLAMP = 0.6V 17 19 21 %
Output Section
VOH IOUT = –100mA, (VDD –V
OUT) 0.4 1 V
VOL IOUT = 100mA 0.4 1 V
Rise Time CLOAD = 1000pF 20 100 ns
Fall Time CLOAD = 1000pF 20 100 ns
Note 1: Ensured by design. Not 100% tested in production.
4
UCC15701/2
UCC25701/2
UCC35701/2
PIN DESCRIPTIONS
VDD: Power supply pin. A shunt regulator limits supply
voltage to 14V typical at 10mAshunt current.
PGND: Power Ground. Ground return for output driver
and currents.
GND: Analog Ground. Ground return for all other circuits.
This pin must be connected directly to PGND on the
board.
OUT: Gate drive output. Output resistance is 10Wmaxi-
mum.
VFF: Voltage feedforward pin. This pin connects to the
power supply input voltage through a resistive divider
and provides feedforward compensation over a 0.8V to
3.2V range. A voltage greater than 4.0V or less than
0.6V on this pin initiates a soft stop cycle.
RT: The voltage on this pin mirrors VFF over a 0.8V to
3.2V range. A resistor to ground sets the ramp capacitor
charge current. The resistor value should be between
20k and 200k.
CT: A capacitor to ground provides the oscillator/
feedforward sawtooth waveform. Charge current is 2 ·
IRT, resulting in a CT slope proportional to the input volt-
age. The ramp voltage range is GND to VRT.
Period and oscillator frequency is given by:
TVC
I
tRC
RT T
RT
DIS CH T T
=·
·+»··
205.
F
RT CT
»·
2
8FB
9VS C LAMP
10CT 3VDD
5.0V
REF
SS
2ILIM
1COUNT
14
13 GND
4OUT
5PGND
12 VREF
0.7V
13/9V (35701)
9.6/8.8V (35702)
SSDONE
7RT
6VF F
11 SYNC
4.5V
4V
VREF
0.6V
0.2V
CURRENT FAULT
CURRENT LIMIT
VREF
0.6V
4V
2*IRT
0.2V
3mA
I
25*I
RUN
I
IRT
PEAK
VALLEY
SHUTDOWN
LATC H
FAULT
LATC H
0.2V VDD
HIGH LINE
LO W LINE
PWM
SQ
RD
S
QRD
1.5R
+
R
RQ
SD
RQ
SD
SSDONE
PWM
DQ
R
DETAILED BLOCK DIAGRAM
UDG-98004
5
UCC15701/2
UCC25701/2
UCC35701/2
(Note: Refer to the Typical Application Diagram on the first
page of this datasheet for external component names.) All the
equations given below should be considered as first order ap-
proximations with final values determined empirically for a spe-
cific application.
Power Sequencing
VDD is normally connected through a high impedance
(R6) to the input line, with an additional path (R7) to a
low voltage bootstrap winding on the power transformer.
VFF is connected through a divider (R1/R2) to the input
line.
For circuit activation, all of the following conditions are
required:
1. VFF between 0.6V and 4.0V (operational input voltage
range).
2. VDD has been under the UVLO stop threshold to reset
the shutdown latch.
3. VDD is over the UVLO start threshold.
The circuit will start at this point. IVDD will increase from
the start up value of 130mA to the run value of 750mA.
The capacitor on SS is charged with a 18mA current.
When the voltage on SS is greater than 0.8V, output
pulses can begin, and supply current will increase to a
level determined by the MOSFET gate charge require-
ments to IVDD ~ 1mA + QT ·fs. When the output is ac-
tive, the bootstrap winding should be sourcing the supply
current. If VDD falls below the UVLO stop threshold, the
controller will enter a shutdown sequence and turn the
controller off, returning the start sequence to the initial
condition.
VDD Clamp
An internal shunt regulator clamps VDD so the voltage
does not exceed a nominal value of 14V. If the regulator
is active, supply current must be limited to less than
20mA.
APPLICATION INFORMATION
VSCLAMP: Voltage at this pin is compared to the CT
voltage, providing a constant volt-second limit. The com-
parator output terminates the PWM pulse when the ramp
voltage exceeds VSCLAMP. The maximum on time is
given by:
tVCT
I
ON
VS CLAMP
RT
=·
·2
The maximum duty cycle limit is given by:
Dt
T
V
V
MAX
ON VS CLAMP
RT
==
FB: Input to the PWM comparator. This pin is intended
to be driven with an optocoupler circuit. Input impedance
is 50kWTypical modulation range is 1.6V to 3.6V.
SYNC: Level sensitive oscillator sync input. A high level
forces the gate drive output low and resets the ramp ca-
pacitor. On-time starts at the negative edge the pulse.
There is a 3mA pull down current on the pin, allowing it to
be disconnected when not used.
VREF: 5.0V trimmed reference with 2% variation over
line, load and temperature. Bypass with a minimum of
0.1mF to ground.
SS: Soft Start pin. A capacitor is connected between this
pin and ground to set the start up time of the converter.
After power up (VDD>13V AND VREF>4.5V), or after a
fault condition has been cleared, the soft start capacitor
is charged to VREF by a nominal 18mA internal current
source. While the soft start capacitor is charging, and
while VSS < (0.4 VFB), the duty cycle, and therefore the
output voltage of the converter is determined by the soft
start circuitry.
At High Line or Low Line fault conditions, the soft start
capacitor is discharged with a controlled discharge cur-
rent of about 500mA. During the discharge time, the duty
cycle of the converter is gradually decreased to zero.
This soft stop feature allows the synchronous rectifiers to
gradually discharge the output LC filter. An abrupt shut
off can cause the LC filter to oscillate, producing unpre-
dictable output voltage levels.
All other fault conditions (UVLO, VREF Low, Over Cur-
rent (0.6V on ILIM) or COUNT) will cause an immediate
stop of the converter. Furthermore, both the Over Current
fault and the COUNT fault will be internally latched until
VDD drops below 9V or VFF goes below the 600mV
threshold at the input of the Low Line comparator.
After all fault conditions are cleared and the soft start ca-
pacitor is discharged below 200 mV, a soft start cycle will
be initiated to restart the converter.
ILIM: Provides a pulse by pulse current limit by terminat-
ing the PWM pulse when the input is above 200mV. An
input over 600mV initiates a latched soft stop cycle.
COUNT: Capacitor to ground integrates current pulses
generated when ILIM exceeds 200mV. A resistor to
ground sets the discharge time constant. A voltage over
4V will initiate a latched soft stop cycle.
PIN DESCRIPTIONS (cont.)
6
UCC15701/2
UCC25701/2
UCC35701/2
Output Inhibit
During normal operation, OUT is driven high at the start
of a clock period and is driven low by voltages on CT, FB
or VSCLAMP.
The following conditions cause the output to be immedi-
ately driven low until a clock period starts where none of
the conditions are true:
1. ILIM > 0.2V
2. FB or SS is less than 0.8V
Current Limiting
ILIM is monitored by two internal comparators. The cur-
rent limit comparator threshold is 0.2V. If the current limit
comparator is triggered, OUT is immediately driven low
and held low for the remainder of the clock cycle, provid-
ing pulse-by-pulse over-current control for excessive
loads. This comparator also causes CFto be charged for
the remainder of the clock cycle.
If repetitive cycles are terminated by the current limit
comparator causing COUNT to rise above 4V, the shut-
down latch is set. The COUNT integration delay feature
will be bypassed by the shutdown comparator which has
a 0.6V threshold. The shutdown comparator immediately
sets the shutdown latch. RFin parallel with CFresets the
COUNT integrator following transient faults. RFmust be
greater than (4 ·R4) ·(1–D
MAX).
Latched Shutdown
If ILIM rises above 0.6V, or COUNT rises to 4V, the shut-
down latch will be set. This will force OUT low, discharge
SS and COUNT, and reduce IDD to approximately
750mA. When, and if, VDD falls below the UVLO stop
threshold, the shutdown latch will reset and IDD will fall
to 130mA, allowing the circuit to restart. If VDD remains
above the UVLO stop threshold (within the UVLO band),
an alternate restart will occur if VFF is momentarily re-
duced below 1V. External shutdown commands from any
source may be added into either the COUNT or ILIM
pins.
Voltage Feedforward
The voltage slope on CT is proportional to line voltage
over a 4:1 range and equals 2·VFF (RT·CT). The capac-
itor charging current is set by the voltage across RT.
V(RT) tracks VFF over a range of 0.8V to 3.2V. A chang-
ing line voltage will immediately change the slope of
V(CT), changing the pulse width in a proportional manner
without using the feedback loop, providing excellent dy-
namic line regulation.
VFF is intended to operate accurately over a 4:1 range
between 0.8V and 3.2V. Voltages at VFF below 0.6V or
above 4.0V will initiate a soft stop cycle and a chip restart
when the under/over voltage condition is removed.
Volt-Second Clamp
A constant volt-second clamp is formed by comparing the
timing capacitor ramp voltage to a fixed voltage derived
from the reference. Resistors R4 and R5 set the
volt-second limit. For a volt-second product defined as
VIN tON(max), the required voltage at VSCLAMP is:
()
()
R
RR
Vt
RC
IN ON
TT
2
12+
æ
è
çö
ø
÷··
·
max .
The duty cycle limit is then:
V
V
VS CLAMP
VFF
,or V
VR
RR
VS CLAMP
IN ·+
æ
è
çö
ø
÷
2
12
.
The maximum duty cycle is realized when the
feedforward voltage is set at the low end of the operating
range (VFF = 0.8V).
The absolute maximum duty cycle is:
DVV
R
RR
MAX
VS CLAMP R EF
==·
+08 08
5
45..
Frequency Set
The frequency is set by a resistor from RT to ground and
a capacitor from CT to ground. The frequency is approxi-
mately: F
RC
TT
=·
2
()
External synchronization is via the SYNC pin. The pin
has a 1.5V threshold , making it compatible with 5V and
3.3V CMOS logic. The input is level sensitive, with a high
input forcing the oscillator ramp low and the output low.
An active pull down on the SYNC pin allows it to be un-
connected when not used.
Gate Drive Output
The UCC35701/2 is capable of a 1A peak output current.
Bypass with at least 0.1mF directly to PGND. The capac-
itor must have a low equivalent series resistance and in-
ductance. The connection from OUT to the power
MOSFET gate should have a 2Wor greater damping re-
sistor and the distance between chip and MOSFET
should be minimized. A low impedance path must be es-
tablished between the MOSFET source (or ground side
of the current sense resistor), the VDD capacitor and
PGND. PGND should then be connected by a single path
(shown as RGND) to GND.
APPLICATION INFORMATION (cont.)
7
UCC15701/2
UCC25701/2
UCC35701/2
Transitioning From UCC3570 To UCC35701
The UCC35701/2 is an advanced version of the popular,
low power UCC3570 PWM. Significant improvements
were made to the IC’s oscillator and PWM control sec-
tions to enhance overall system performance. All of the
key attributes and functional blocks of the UCC3570
were maintained in the UCC35701/2. A typical applica-
tion using UCC3570 and UCC35701/2 is shown in Fig. 6
for comparison.
The advantages of the UCC35701/2 over the UCC3570
are as follows.
Improved oscillator and PWM control section.
A precise maximum volt-second clamp circuit. The
UCC3570 has a dual time base between oscillator and
feedforward circuitry. The integated time base in
UCC35701/2 improves the duty cycle clamp accuracy,
providing better than ±5% accurate volt- second
clamp over full temperature range.
Separately programmable oscillator timing resistor
(RT) and capacitor (CT) circuits provide a higher
degree of versatility.
An independent SYNC input pin for simple external
synchronization.
A smaller value filter capacitor (0.1mF) can be used
with the enhanced reference voltage.
UCC35701/2 is pin to pin compatible to UCC3570 but is
not a direct drop-in replacement for UCC3570 sockets.
The changes required to the power supply printed circuit
board of for existing UCC3570 designs are minimal. For
conversion, only one extra resistor to set the volt-second
clamp needs to be added to the existing PC board lay-
outs. In addition, some component values will need to
be changed due to the functionality change in of four of
the IC pins.
The Pinout Changes from UCC3570 are as follows.
Pin 7 was changed from SLOPE to RT (for timing
resistor)
Pin 8 was changed from ISET to VSCLAMP (requiring
one additional resistor from pin 9 to VREF)
Pin 10 was changed from RAMP to CT (single timing
capacitor)
Pin 11 was changed from FREQ to SYNC (input only)
Additional Information
Please refer to the following two Unitrode application
topics on UCC3570 for additional information.
[1] Application Note U-150, Applying the UCC3570 Volt-
age-Mode PWM Controller to Both Off-line and DC/DC
Converter Designs by Robert A. Mammano
[2] Design Note DN-62, Switching Power Supply Topol-
ogy, Voltage Mode vs. Current Mode by Robert
Mammano
APPLICATION INFORMATION (cont.)
VS CLAMP
CT
FEEDBK
SOFT START HIGH DC LOW DC ZERO DC
SOFTST
V-S CLAMP
SOFT STOP
Figure 1. Timing diagram for PWM action with forward, soft start and volt-second clamp.
TYPICAL WAVEFORMS
UDG-98207
8
UCC15701/2
UCC25701/2
UCC35701/2
VFF
CT
SYNC
Figure 2. Timing diagram for oscillator waveforms showing feedforward action and synchronization.
TYPICAL WAVEFORMS (cont.)
10
100
1000
20 60 100 140 180 220
RT [K ]
FREQUENCY [kHz]
100pF
150pF
220pF
330pF
470pF
Figure 3. Oscillator frequency vs. RT and CT.
TYPICAL CHARACTERISTIC CURVES
0.97
0.98
0.99
1.00
1.01
1.02
1.03
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE [°C]
NORMALIZED DUTY CYCLE
VFF=0.8
VFF=3.2
Figure 5. Normalized maximum duty cycle vs.
temperature.
UDG-98208
0.98
0.99
1
1.01
1.02
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE [°C]
VFF=3.2
VFF=0.8
CT=330pF
FOSC = 100kHz
NORMALIZED FREQUENCY
Figure 4. Oscillator frequency vs. temperature.
9
UCC15701/2
UCC25701/2
UCC35701/2
6
7
10
9
11
14
1
12
8
13
3
4
2
5
VFF
SLOPE
RAMP
IS ET
FREQ
SS
COUNT
VRE F
FB
GND
PGND
OUT
VDD
ILIM
R5
C1
C2
R8
RGND
RSNS
R9
C4
R6
R7
C3
R1
R2
R3
R4
CR
CT
RT
CF
RF
CSS
UCC3570
VIN +
6
7
10
9
11
14
1
12
8
13
3
4
2
5
VFF
RT
CT
VS CLAMP
SYNC
SS
COUNT
VRE F
FB
GND
PGND
OUT
VDD
ILIM
R5
C1
C2
R8
RGND
R9
R7
C3
R1
R2
R3
R4
CT
RNEW
CF
RF
CSS
UCC35701
VIN +
R12 C6
C5
R11
R13
C7
R14
VOUT
R12 C6
C5
R11
R13
C7
R14
VOUT
VOUT
RSNS
VOUT
R6
C4
R15
R15
Figure 6. Single-ended forward circuit comparison between UCC3570 and UCC37501.
APPLICATION INFORMATION (cont.)
UDG-98210
10
UCC15701/2
UCC25701/2
UCC35701/2
DATE REVISION REASON
02/16/05 SLUS293B Add FB to abs max table. Created revision history table.
6/16/05 SLUS293C Updated block diagram and the SS pin description.
REVISION HISTORY
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC15701J OBSOLETE CDIP J 14 TBD Call TI Call TI Samples Not Available
UCC15701L OBSOLETE LCCC FK 20 TBD Call TI Call TI Samples Not Available
UCC25701D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
UCC25701DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
UCC25701DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
UCC25701DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
UCC25701N ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UCC25701NG4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UCC25701PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
UCC25701PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
UCC25701PWTR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
UCC25701PWTRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
UCC25702D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
UCC25702DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
UCC25702DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
UCC25702DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
UCC25702N ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UCC25702NG4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC25702PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
UCC25702PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
UCC25702PWTR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
UCC25702PWTRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
UCC35701D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
UCC35701DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
UCC35701DTR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
UCC35701DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
UCC35701N ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UCC35701NG4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UCC35701PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
UCC35701PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
UCC35701Q OBSOLETE UTR 20 TBD Call TI Call TI Samples Not Available
UCC35701QTR OBSOLETE UTR 20 TBD Call TI Call TI Samples Not Available
UCC35702D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
UCC35702DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
UCC35702N ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UCC35702NG4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type Request Free Samples
UCC35702PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC35702PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC15701, UCC35701 :
•Catalog: UCC35701
•Military: UCC15701
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 4
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC25701DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UCC25701PWTR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
UCC25702DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UCC25702PWTR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
UCC35701DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC25701DTR SOIC D 14 2500 333.2 345.9 28.6
UCC25701PWTR TSSOP PW 14 2000 367.0 367.0 35.0
UCC25702DTR SOIC D 14 2500 333.2 345.9 28.6
UCC25702PWTR TSSOP PW 14 2000 367.0 367.0 35.0
UCC35701DTR SOIC D 14 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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