1996 Microchip Technology Inc. DS20071H-page 1
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
-5
µ
A standby current typical at 3.0V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)
• 2-wire serial interface bus, I
2
C
compatible
• 100kHz (2.5V) and 400kHz (5.0V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 3,000V
• 10,000,000 ERASE/WRITE cycles guaranteed on
24LC01B
• 1,000,000 E/W cycles guaranteed on 24LC02B
• Data retention > 200 years
• 8 pin DIP or SOIC package
• Available for extended temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24LC01B and 24LC02B
are 1K bit and 2K bit Electrically Erasable PROMs. The
devices are organized as a single block of 128 x 8 bit or
256 x 8 bit memory with a two wire serial interface. Low
voltage design permits operation down to 2.5 volts with
a standby and active currents of only 5
µ
A and 1 mA
respectively. The 24LC01B and 24LC02B also have
page-write capability for up to 8 bytes of data. The
24LC01B and 24LC02B are available in the standard
8-pin DIP and an 8-pin surface mount SOIC package.
- Commercial (C): 0˚C to +70˚C
- Industrial (I): -40˚C to +85˚C
PACKAGE TYPES
BLOCK DIAGRAM
24LC01B/02B 24LC01B/02B
1
2
3
4
8
7
6
5
A0
A1
A2
Vss
Vcc
WP
SCL
SDA
A0
A1
A2
Vss
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA SCL
VCC
VSS
24LC01B/02B
1K/2K 2.5V I
2
C
Serial EEPROM
I
2
C is a trademark of Philips Corporation.
This document was created with FrameMaker404
24LC01B/02B
DS20071H-page 2
1996 Microchip Technology Inc.
1.0 ELECTRICAL CHARA CTERISTICS
1.1 Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature.....................................-65˚C to +150˚C
Ambient temp. with power applied................-65˚C to +125˚C
Soldering temperature of leads (10 seconds).............+300˚C
ESD protection on all pins.............................................
≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name Function
V
SS
SDA
SCL
WP
V
CC
A0, A1, A2
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5V to 5.5V Power Supply
No Internal Connection
TABLE 1-2: DC CHARACTERISTICS
FIGURE 1-1: BUS TIMING START/STOP
V
CC
= +2.5V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C
Parameter Symbol Min. Max. Units Conditions
WP, SCL and SDA pins:
High level input voltage V
IH
.7 V
CC
V
Low level input voltage V
IL
.3 V
CC
V
Hysteresis of Schmidt trigger inputs V
HYS
.05 V
CC
— V (Note)
Low level output voltage V
OL
.40 V I
OL
= 3.0 mA, V
CC
= 2.5V
Input leakage current I
LI
-10 10
µ
AV
IN
= .1V to 5.5V
Output leakage current I
LO
-10 10
µ
mA V
OUT
= .1V to 5.5V
Pin capacitance (all inputs/outputs) C
IN
,
C
OUT
—10pFV
CC
= 5.0V (Note 1)
Tamb = 25˚C, F
CLK
= 1 MHz
Operating current I
CC
Write — 3 mA V
CC
= 5.5V, SCL = 400 kHz
I
CC
Read — 1 mA
Standby current I
CCS
—30
µ
AV
CC
= 3.0V, SDA = SCL = V
CC
100
µ
AV
CC
= 5.5V, SDA = SCL = V
CC
Note:
This parameter is periodically sampled and not 100% tested.
SCL
SDA
TSU:STA THD:STA
START STOP
VHYS
TSU:STO
1996 Microchip Technology Inc. DS20071H-page 3
24LC01B/02B
TABLE 1-3: AC CHARACTERISTICS
FIGURE 1-2: BUS TIMING DATA
Parameter Symbol STANDARD
MODE Vcc = 4.5 - 5.5V
FAST MODE Units Remarks
Min. Max. Min. Max.
Clock frequency F
CLK
— 100 — 400 kHz
Clock high time T
HIGH
4000 — 600 — ns
Clock low time T
LOW
4700 — 1300 — ns
SDA and SCL rise time T
R
— 1000 — 300 ns (Note 1)
SDA and SCL fall time T
F
— 300 — 300 ns (Note 1)
START condition hold time T
HD
:
STA
4000 — 600 — ns After this period the first
clock pulse is generated
START condition setup time T
SU
:
STA
4700 — 600 — ns Only relevant for repeated
START condition
Data input hold time T
HD
:
DAT
0 — 0 — ns (Note 2)
Data input setup time T
SU
:
DAT
250 — 100 — ns
STOP condition setup time T
SU
:
STO
4000 — 600 — ns
Output valid from clock T
AA
— 3500 — 900 ns (Note 2)
Bus free time T
BUF
4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
minimum to V
IL
maximum T
OF
— 250 20 +0.1
CB 250 ns (Note 1), CB
≤
100 pF
Input filter spike suppression
(SDA and SCL pins) T
SP
— 50 — 50 ns (Note 3)
Write cycle time T
WR
— 10 — 10 ms Byte or Page mode
Endurance 24LC01B
24LC01B —10M
1M — 10M
1M — cycles 25
°
C, Vcc = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
SCL
SDA
IN
SDA
OUT
THD:STA
TSU:STA
TFTHIGH
TR
TSU:STOTSU:DATTHD:DAT
TBUFTAA
THD:STA
TAA
TSP
TLOW
24LC01B/02B
DS20071H-page 4
1996 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LC01B/02B supports a bi-directional two wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24LC01B/02B works as slave. Both master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.
3.0 BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a ST ART condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note: The 24LC01B/02B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(A) (B) (D) (D) (C) (A)
START
CONDITION ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
1996 Microchip Technology Inc. DS20071H-page 5
24LC01B/02B
3.6 Devide Address
The 24LC01B/02B are software-compatible with older
devices such as 24C01A, 24C02A, 24LC01, and
24LC02. A single 24LC02B can be used in place of two
24LC01's, for example, without any modifications to
software. The “chip select” portion of the control byte
becomes a don't care.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24LC01B/02B, followed by three
don't care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24LC01B/02B
(Figure 3-2).
The 24LC01B/02B monitors the bus for its correspond-
ing slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
FIGURE 3-2: CONTROL BYTE
ALLOCATION
Operation Control
Code Chip
Select R/W
Read
Write 1010
1010 XXX
XXX 1
0
X = Don’t care
R/W A
1 010XXX
READ/WRITE
START
SLA VE ADDRESS
4.0 WRITE OPERATION
4.1 Byte Write
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W bit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver that a byte with a word address will follow after
it has generated an acknowledge bit during the ninth
clock cycle. Therefore the next byte transmitted by the
master is the word address and will be written into the
address pointer of the 24LC01B/02B. After receiving
another acknowledge signal from the 24LC01B/02B the
master device will transmit the data word to be written
into the addressed memory location. The 24LC01B/
02B acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this time the 24LC01B/02B will not generate
acknowledge signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC01B/02B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24LC01B/02B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: PAGE WRITE
S P
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY A
C
K
A
C
K
A
C
K
CONTROL
BYTE WORD
ADDRESS DATA
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE WORD
ADDRESS (n) DATA n DATAn + 7
DATAn + 1
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
24LC01B/02B
DS20071H-page 6 1996 Microchip Technology Inc.
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately . This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
6.0 WRITE PROTECTION
The 24LC01B/02B can be used as a serial ROM when
the WP pin is connected to VCC. Programming will be
inhibited and the entire memory will be write-protected.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
7.1 Current Address Read
The 24LC01B/02B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to address
n, the next current address read operation would
access data from address n + 1. Upon receipt of the
slave address with R/W bit set to one, the 24LC01B/
02B issues an acknowledge and transmits the eight bit
data word. The master will not acknowledge the transfer
but does generate a stop condition and the 24LC01B/
02B discontinues transmission (Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC01B/02B as part of a write operation. After the
word address is sent, the master generates a start con-
dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W bit set to a one. The 24LC01B/
02B will then issue an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24LC01B/02B discontinues transmission (Figure 7-2).
7.3 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC01B/02B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LC01B/02B to transmit the next sequen-
tially addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC01B/02B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
7.4 Noise Protection
The 24LC01B/02B employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
1996 Microchip Technology Inc. DS20071H-page 7
24LC01B/02B
FIGURE 7-1: CURRENT ADDRESS READ
FIGURE 7-2: RANDOM READ
FIGURE 7-3: SEQUENTIAL READ
SP
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE DATA n
A
C
K
N
O
A
C
K
S
T
O
P
S P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE WORD
ADDRESS (n) DATA n
A
C
K
A
C
K
N
O
A
C
K
CONTROL
BYTE
A
C
K
S
T
A
R
T
P
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
DATA n
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
DATA n + 1 DATA n + 2 DATA n + X
BUS ACTIVITY
MASTER
8.0 PIN DESCRIPTIONS
8.1 SDA Serial Address/Data Input/Output
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10KΩ for 100 kHz, 1KΩ for 400
kHz).
For normal data transfer SDA is allowed to change only
during SCL low . Changes during SCL high are reserved
for indicating the START and STOP conditions.
8.2 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3 WP
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC01B/02B as
a serial ROM when WP is enabled (tied to VCC).
8.4 A0, A1, A2
These pins are not used by the 24LC01B/02B. They
may be left floating or tied to either VSS or VCC.
24LC01B/02B
DS20071H-page 8 1996 Microchip Technology Inc.
NOTES:
1996 Microchip Technology Inc. DS20071H-page 9
24LC01B/02B
NOTES:
24LC01B/02B
DS20071H-page 10 1996 Microchip Technology Inc.
NOTES:
24LC01B/02B
1996 Microchip Technology Inc. 1996 Microchip Technology Inc.DS20071H-page 11
24LC01B/02B Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body)
SM = Plastic SOIC (207 mil Body)
Temperature Blank = 0°C to +70°C
Range: I= -40°C to +85°C
Device: 24LC01B 1K I2C Serial EEPROM
24LC01BT 1K I2C Serial EEPROM (Tape and Reel)
24LC02B 2K I2C Serial EEPROM
24LC02BT 2K I2C Serial EEPROM (Tape and Reel)
24LC01B/02B – /P
DS20071H-page 12 1996 Microchip Technology Inc.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
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