Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier AD8227 Gain set with 1 external resistor Gain range: 5 to 1000 Input voltage goes below ground Inputs protected beyond supplies Very wide power supply range Single supply: 2.2 V to 36 V Dual supply: 1.5 V to 18 V Bandwidth (G = 5): 250 kHz CMRR (G = 5): 100 dB minimum (B Grade) Input noise: 24 nV/Hz Typical supply current: 350 A Specified temperature: -40C to +125C 8-lead SOIC and MSOP packages APPLICATIONS Industrial process controls Bridge amplifiers Medical instrumentation Portable data acquisition Multichannel systems PIN CONFIGURATION AD8227 -IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 -VS TOP VIEW (Not to Scale) 07759-001 FEATURES Figure 1. Table 1. Instrumentation Amplifiers by Category1 General Purpose AD8220 AD8221 AD8222 AD8224 AD8228 AD8295 1 Zero Drift AD8231 AD8290 AD8293 AD8553 AD8556 AD8557 Military Grade AD620 AD621 AD524 AD526 AD624 Low Power AD627 AD623 AD8223 AD8226 AD8227 High Speed PGA AD8250 AD8251 AD8253 See www.analog.com for the latest selection of instrumentation amplifiers. GENERAL DESCRIPTION The AD8227 is a low cost, wide supply range instrumentation amplifier that requires only one external resistor to set any gain between 5 and 1000. The AD8227 is ideal for multichannel, space-constrained applications. With its MSOP package and 125C temperature rating, the AD8227 thrives in tightly packed, zero airflow designs. The AD8227 is designed to work with a variety of signal voltages. A wide input range and rail-to-rail output allow the signal to make full use of the supply rails. Because the input range can also go below the negative supply, small signals near ground can be amplified without requiring dual supplies. The AD8227 operates on supplies ranging from 1.5 V to 18 V (2.2 V to 36 V single supply). The AD8227 is available in 8-pin MSOP and SOIC packages. It is fully specified for -40C to +125C operation. For a similar instrumentation amplifier with a gain range of 1 to 1000, see the AD8226. The robust AD8227 inputs are designed to connect to realworld sensors. In addition to its wide operating range, the AD8227 can handle voltages beyond the rails. For example, with a 5 V supply, the part is guaranteed to withstand 35 V at the input with no damage. Minimum as well as maximum input bias currents are specified to facilitate open wire detection. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved. AD8227 TABLE OF CONTENTS Features .............................................................................................. 1 Gain Selection ............................................................................. 19 Applications ....................................................................................... 1 Reference Terminal .................................................................... 20 Pin Configuration ............................................................................. 1 Input Voltage Range ................................................................... 20 General Description ......................................................................... 1 Layout .......................................................................................... 20 Revision History ............................................................................... 2 Input Bias Current Return Path ............................................... 21 Specifications..................................................................................... 3 Input Protection ......................................................................... 21 Absolute Maximum Ratings............................................................ 7 Radio Frequency Interference (RFI) ........................................ 21 Thermal Resistance ...................................................................... 7 Applications Information .............................................................. 22 ESD Caution .................................................................................. 7 Differential Drive ....................................................................... 22 Pin Configuration and Function Descriptions ............................. 8 Precision Strain Gage ................................................................. 22 Typical Performance Characteristics ............................................. 9 Driving an ADC ......................................................................... 23 Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 24 Architecture................................................................................. 19 Ordering Guide .......................................................................... 24 REVISION HISTORY 5/09--Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8227 SPECIFICATIONS +VS = +15 V, -VS = -15 V, VREF = 0 V, TA = 25C, G = 5, RL = 10 k, specifications referred to input, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO DC to 60 Hz G=5 G = 10 G = 100 G = 1000 5 kHz G=5 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=5 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average Temperature Drift Output Offset, VOSO Average Temperature Drift Offset RTI vs. Supply (PSR) G=5 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current 1 Average Temperature Drift Input Offset Current Average Temperature Drift REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error Test Conditions/ Comments VCM = -10 V to +10 V Min A Grade Typ Max Min B Grade Typ Max Unit 90 96 105 105 100 105 110 110 dB dB dB dB 80 86 86 86 80 86 86 86 dB dB dB dB Total noise: eN = (eNI2 + (eNO/G)2) 24 310 25 315 24 310 25 315 nV/Hz nV/Hz f = 0.1 Hz to 10 Hz 1.5 0.9 0.5 100 3 f = 1 kHz f = 0.1 Hz to 10 Hz Total offset voltage: VOS = VOSI + (VOSO/G) VS = 5 V to 15 V TA = -40C to +125C VS = 5 V to 15 V TA = -40C to +125C VS = 5 V to 15 V 0.2 2 1.5 0.9 0.5 100 3 200 2 1000 10 90 96 105 105 TA = +25C TA = +125C TA = -40C TA = -40C to +125C TA = +25C TA = +125C TA = -40C TA = -40C to +125C 5 5 5 0.2 2 V p-p V p-p V p-p fA/Hz pA p-p 100 1 500 5 100 105 110 110 20 15 30 70 27 25 35 5 5 5 dB dB dB dB 20 15 30 70 1.5 1.5 2 5 60 12 60 12 +VS 1 0.01 Rev. 0 | Page 3 of 24 27 25 35 1.5 1.5 2 5 -VS V V/C V V/C -VS +VS 1 0.01 nA nA nA pA/C nA nA nA pA/C k A V V/V % AD8227 Parameter DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=5 G = 10 G = 100 G = 1000 Settling Time 0.01% G=5 G = 10 G = 100 G = 1000 Slew Rate 2 GAIN 3 Gain Range Gain Error G=5 G = 10 to 1000 Gain Nonlinearity G=5 G = 10 G = 100 G = 1000 Gain vs. Temperature G=5 G>5 INPUT Impedance Differential Common Mode Operating Voltage Range 4 Overvoltage Range OUTPUT Output Swing RL = 10 k to ground RL = 100 k to ground Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current TEMPERATURE RANGE Test Conditions/ Comments Min A Grade Typ Max Min B Grade Typ Max Unit 250 200 50 5 250 200 50 5 kHz kHz kHz kHz 14 15 35 275 0.8 14 15 35 275 0.8 s s s s V/s 10 V step G = 5 to 100 G = 5 + (80 k/RG) 5 1000 5 1000 V/V 0.04 0.3 0.02 0.15 % % 10 15 15 750 10 15 50 150 ppm ppm ppm ppm 5 -100 5 -100 ppm/C ppm/C G||pF G||pF V V V V VOUT = -10 V to +10 V VOUT = -10 V to +10 V RL 2 k RL 2 k RL 2 k RL 2 k TA = -40C to +125C VS = 1.5 V to +36 V 0.8||2 0.4||2 0.8||2 0.4||2 TA = +25C TA = +125C TA = -40C TA = -40C to +125C -VS - 0.1 -VS - 0.05 -VS - 0.15 +VS - 40 +VS - 0.8 +VS - 0.6 +VS - 0.9 -VS + 40 -VS - 0.1 -VS - 0.05 -VS - 0.15 +VS - 40 +VS - 0.8 +VS - 0.6 +VS - 0.9 -VS + 40 TA = -40C to +85C TA = +85C to +125C TA = -40C to +125C -VS + 0.2 -VS + 0.2 -VS + 0.1 +VS - 0.2 +VS - 0.3 +VS - 0.1 -VS + 0.2 -VS + 0.2 -VS + 0.1 +VS - 0.2 +VS - 0.3 +VS - 0.1 V V V mA 18 425 325 525 600 +125 V A A A A C 13 Dual-supply operation TA = +25C TA = -40C TA = +85C TA = +125C 1.5 350 250 450 525 -40 1 13 18 425 325 525 600 +125 1.5 350 250 450 525 -40 The input stage uses pnp transistors, so input bias current always flows into the part. At high gains, the part is bandwidth limited rather than slew rate limited. 3 For G > 5, gain error specifications do not include the effects of External Resistor RG. 4 Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more information. 2 Rev. 0 | Page 4 of 24 AD8227 +VS = 2.7 V, -VS = 0 V, VREF = 0 V, TA = 25C, G = 5, RL = 10 k, specifications referred to input, unless otherwise noted. Table 3. Parameter COMMON-MODE REJECTION RATIO DC to 60 Hz G=5 G = 10 G = 100 G = 1000 5 kHz G=5 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=5 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average Temperature Drift Output Offset, VOSO Average Temperature Drift Offset RTI vs. Supply (PSR) G=5 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current 1 Average Temperature Drift Input Offset Current Average Temperature Drift REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error Test Conditions/ Comments VCM = 0 V to 1.7 V Min A Grade Typ Max Min B Grade Typ Max Unit 90 96 105 105 100 105 110 110 dB dB dB dB 80 86 86 86 80 86 86 86 dB dB dB dB Total noise: eN = (eNI2 + (eNO/G)2) 25 310 28 330 25 310 28 330 nV/Hz nV/Hz f = 0.1 Hz to 10 Hz 1.5 0.8 0.5 100 3 f = 1 kHz f = 0.1 Hz to 10 Hz Total offset voltage: VOS = VOSI + (VOSO/G) VS = 0 V to 1.7 V TA = -40C to +125C VS = 0 V to 1.7 V TA = -40C to +125C VS = 0 V to 1.7 V 0.2 2 1.5 0.8 0.5 100 3 200 2 1000 10 90 96 105 105 TA = +25C TA = +125C TA = -40C TA = -40C to +125C TA = +25C TA = +125C TA = -40C TA = -40C to +125C 5 5 5 0.2 2 V p-p V p-p V p-p fA/Hz pA p-p 100 1 500 5 100 105 110 110 20 15 30 70 27 25 35 5 5 5 dB dB dB dB 20 15 30 70 1.5 1.5 2 5 60 12 60 12 +VS 1 0.01 Rev. 0 | Page 5 of 24 27 25 35 1.5 1.5 2 5 -VS V V/C V V/C -VS +VS 1 0.01 nA nA nA pA/C nA nA nA pA/C k A V V/V % AD8227 Parameter DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=5 G = 10 G = 100 G = 1000 Settling Time 0.01% G=5 G = 10 G = 100 G = 1000 Slew Rate 2 GAIN 3 Gain Range Gain Error G=5 G = 10 to 1000 Gain vs. Temperature G=5 G>5 INPUT Impedance Differential Common Mode Operating Voltage Range 4 Overvoltage Range OUTPUT Output Swing RL = 2 k to 1.35 V RL = 10 k to 1.35 V Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current TEMPERATURE RANGE Test Conditions/ Comments Min A Grade Typ Max Min B Grade Typ Max Unit 250 200 50 5 250 200 50 5 kHz kHz kHz kHz 6 6 30 275 0.6 6 6 30 275 0.6 s s s s V/s 2 V step G = 5 to 10 G = 5 + (80 k/RG) 5 1000 VOUT = 0.8 V to 1.8 V VOUT = 0.2 V to 2.5 V TA = -40C to +125C 5 1000 V/V 0.04 0.3 0.04 0.3 % % 5 -100 5 -100 ppm/C ppm/C G||pF G||pF V V V V -VS = 0 V; +VS = 2.7 V to 36 V 0.8||2 0.4||2 TA = +25C TA = -40C TA = +125C TA = -40C to +125C 0.8||2 0.4||2 -0.1 -0.15 -0.05 +VS - 40 +VS - 0.7 +VS - 0.9 +VS - 0.6 -VS + 40 -0.1 -0.15 -0.05 +VS - 40 +VS - 0.7 +VS - 0.9 +VS - 0.6 -VS + 40 0.2 0.1 +VS - 0.2 +VS - 0.1 0.2 0.1 +VS - 0.2 +VS - 0.1 V V mA 36 V 400 325 500 550 +125 A A A A C TA = -40C to +125C 13 Single-supply operation +VS = 2.7 V TA = +25C TA = -40C TA = +85C TA = +125C 2.2 13 36 325 250 425 475 -40 1 400 325 500 550 +125 2.2 325 250 425 475 -40 Input stage uses pnp transistors, so input bias current always flows into the part. At high gains, the part is bandwidth limited rather than slew rate limited. 3 For G > 5, gain error specifications do not include the effects of External Resistor RG. 4 Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more information. 2 Rev. 0 | Page 6 of 24 AD8227 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage Output Short-Circuit Current Maximum Voltage at -IN or +IN Minimum Voltage at -IN or +IN REF Voltage Storage Temperature Range Operating Temperature Range Maximum Junction Temperature JA is specified for a device in free air. Rating 18 V Indefinite -VS + 40 V +VS - 40 V VS -65C to +150C -40C to +125C 140C Table 5. Package 8-Lead MSOP, 4-Layer JEDEC Board 8-Lead SOIC, 4-Layer JEDEC Board ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 24 JA 135 121 Unit C/W C/W AD8227 AD8227 -IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 -VS TOP VIEW (Not to Scale) 07759-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2, 3 4 5 6 7 8 Mnemonic -IN RG +IN -VS REF VOUT +VS Description Negative Input. Gain Setting Pins. Place a gain resistor between these two pins. Positive Input. Negative Supply. Reference. This pin must be driven by low impedance. Output. Positive Supply. Rev. 0 | Page 8 of 24 AD8227 TYPICAL PERFORMANCE CHARACTERISTICS T = 25C, VS = 15 V, RL = 10 k, unless otherwise noted. 500 MEAN: 15.9 SD: 196.50 MEAN: 0.0668 SD: 0.065827 1000 400 800 HITS HITS 300 600 200 400 100 -600 -300 0 300 OUTPUT VOS (V) 600 900 0 -0.9 Figure 3. Typical Distribution of Output Offset Voltage -0.3 0 0.3 INPUT VOS DRIFT (V) 0.6 0.9 Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100 MEAN: -0.701 SD: 0.676912 700 -0.6 07759-006 -900 07759-003 0 200 MEAN: 20.4 SD: 0.5893 1000 600 800 600 HITS HITS 500 400 300 400 200 200 -4 -2 0 2 OUTPUT VOS DRIFT (V) 4 6 0 MEAN: -5.90 SD: 15.8825 600 HITS 600 400 400 200 200 -100 -50 0 50 INPUT VOS (V) 100 150 200 24 26 MEAN: -0.027 SD: 0.079173 0 -0.9 07759-005 HITS 800 -150 20 22 POSITIVE IBIAS (nA) 1000 800 0 -200 18 Figure 7. Typical Distribution of Input Bias Current Figure 4. Typical Distribution of Output Offset Voltage Drift 1000 16 Figure 5. Typical Distribution of Input Offset Voltage -0.6 -0.3 0 IOS (nA) 0.3 0.6 Figure 8. Typical Distribution of Input Offset Current Rev. 0 | Page 9 of 24 0.9 07759-008 -6 07759-004 0 07759-007 100 AD8227 1.6 +0.02V, +1.5V VREF = 0V VREF = 0V 1.4 1.4 +2.67V, +1.2V +2.67V, +1.2V +0.02V, +1.35V 1.0 +2.7V, +1.1V VREF = 1.35V 0.8 0.6 0.4 0.2 +2.7V, 0V 0 1.2 COMMON-MODE VOLTAGE (V) +0.02V, +1.35V 1.0 0.8 0.6 0.4 0.2 0 +0.02V, -0.15V -0.2 0 0.5 1.0 1.5 2.0 OUTPUT VOLTAGE (V) 2.5 3.0 -0.4 -0.5 07759-009 -0.4 -0.5 +1.35V, -0.3V Figure 9. Input Common-Mode Voltage vs. Output Voltage, Single Supply, Vs = 2.7 V, G = 5 1.0 1.5 2.0 OUTPUT VOLTAGE (V) 2.5 3.0 5 VREF = 0V +0.02V, +4.25V COMMON-MODE VOLTAGE (V) +4.96V, +3.75V 4 +0.02V, +4V +4.96V, +3.5V VREF = 2.5V 3 2 1 +4.96V, +0.2V +0.01V, -0.05V 0 +0.02V, -0.3V -1 -0.5 0 0.5 1.0 +4.96V, +3.75V 4 +0.02V, +4V +4.96V, +3.5V VREF = 2.5V 3 2 1 0 +2.5V, -0.3V 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) +4.96V, -0.05V 4.0 4.5 5.0 5.5 -1 -0.5 Figure 10. Input Common-Mode Voltage vs. Output Voltage, Single Supply, Vs = 5 V, G = 5 +4.96V, -0.2V +0.02V, -0.25V +0.02V, -0.3V 07759-010 COMMON-MODE VOLTAGE (V) 0.5 VREF = 0V +0.02V, +4.25V 0 0.5 +2.5V, -0.3V 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) +4.96V, -0.25V 4.0 4.5 5.0 5.5 Figure 13. Input Common-Mode Voltage vs. Output Voltage, Single Supply, Vs = 5 V, G = 100 6 6 0V, +4.2V +4.96V, +3.7V 4 COMMON-MODE VOLTAGE (V) -4.98V, +3.7V 2 0 -2 -4 -4.96V, +3.75V -4.97V, -4.8V -6 -6 -4 0V, +4.2V +4.96V, +3.25V 2 0 -2 -4 0V, -5.3V 0V, -5.3V +4.96V, -4.8V -2 0 2 OUTPUT VOLTAGE (V) 4 6 -6 -6 07759-011 COMMON-MODE VOLTAGE (V) 0 +2.67V, -0.25V +1.35V, -0.3V +0.02V, -0.3V Figure 12. Input Common-Mode Voltage vs. Output Voltage, Single Supply, Vs = 2.7 V, G = 100 5 4 +2.67V, -0.25V +0.02V, -0.25V -0.2 +2.67V, -0.15V +0.02V, -0.3V +2.67V, +1.1V VREF = 1.35V 07759-013 COMMON-MODE VOLTAGE (V) 1.2 07759-012 +0.02V, +1.5V Figure 11. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, Vs = 5 V, G = 5 -4.96V, -5.1V -4 +4.96V, -5.1V -2 0 2 OUTPUT VOLTAGE (V) 4 6 Figure 14. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, Vs = 5 V, G = 100 Rev. 0 | Page 10 of 24 07759-014 1.6 AD8227 VS = 12V -5 -11.96V, -11.1V -10 -15 +11.94V, -11.1V 0V, -12.3V -14.96V, -13.8V -20 -20 -15 -10 -5 0 5 OUTPUT VOLTAGE (V) 10 15 20 0 +14.94V, +12.7V +11.94V, +10V OUTPUT VOLTAGE (V) 5 VS = 12V 0 -5 -11.96V, -11.3V -10 -15 +11.94V, -11.3V 0V, -12.3V -14.96V, -14V -20 -20 -15 -10 0V, -15.3V -5 0 5 OUTPUT VOLTAGE (V) +14.94V, -14V 10 15 20 0.3 0.2 1.75 0.1 1.50 -0.2 0.75 -0.3 0.50 -0.4 0.25 -0.5 0.3 8 2.00 0.2 1.75 0.1 1.50 0 1.25 IIN -0.1 1.00 -0.2 0.75 -0.3 0.50 -0.4 0.25 -0.5 0 -0.6 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) -0.1 1.00 12 10 OUTPUT VOLTAGE (V) VOUT 0 IIN 1.25 0.4 INPUT CURRENT (mA) OUTPUT VOLTAGE (V) 2.25 0.4 2.00 16 14 0.5 2.50 0.5 VOUT Figure 19. Input Overvoltage Performance, G = 100, Vs = 2.7 V 0.6 VS = 2.7V, G = 5 0.6 VS = 2.7V, G = 100 0 -0.6 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) 07759-017 2.75 -0.3 2.25 Figure 16. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, Vs = 15 V, G = 100 3.00 -0.2 2.50 07759-016 COMMON-MODE VOLTAGE (V) 2.75 0V, +11.2V -11.96V, +10V -0.1 -4 -6 -8 -10 -12 3.00 VS = 15V 10 0 Figure 18. Input Overvoltage Performance, G = 5, Vs = 15 V 20 0V, +14.2V 0.1 IIN -2 Figure 15. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, Vs = 15 V, G = 5 15 -14.96V, +12.7V 0.2 -0.4 -14 -16 -0.5 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) +14.94V, -13.8V 0V, -15.3V 6 4 2 INPUT CURRENT (mA) 0 0.3 8 +11.94V, +10V 0.4 07759-019 5 VOUT 0.4 VOUT -4 -6 -8 -10 -12 0.3 0.2 6 4 2 0 -2 0.5 VS = 15V, G = 100 0.1 IIN 0 -0.1 -0.2 -0.3 -0.4 -14 -16 -0.5 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) Figure 17. Input Overvoltage Performance, G = 5, Vs = 2.7 V Figure 20. Input Overvoltage Performance, G = 100, Vs = 15 V Rev. 0 | Page 11 of 24 INPUT CURRENT (mA) -11.96V, +10V OUTPUT VOLTAGE (V) 10 07759-015 COMMON-MODE VOLTAGE (V) 12 10 +14.94V, +12.7V 0V, +11.2V 07759-020 0V, +14.2V 15 -14.96V, +12.7V 0.5 VS = 15V, G = 5 INPUT CURRENT (mA) 16 14 VS = 15V 07759-018 20 AD8227 33 140 120 -0.14V 29 NEGATIVE PSRR (dB) 27 +4.23V 25 23 21 G = 1000 100 G = 100 80 60 G = 10 40 G=5 19 20 17 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 COMMON-MODE VOLTAGE (V) 4.0 4.5 0 0.1 07759-021 15 -0.5 1 Figure 21. Input Bias Current vs. Common-Mode Voltage, Vs = 5 V 10 100 1k FREQUENCY (Hz) 10k 100k 07759-024 INPUT BIAS CURRENT (nA) 31 Figure 24. Negative PSRR vs. Frequency 70 40 -15.01V 60 35 G = 1000 40 25 GAIN (dB) +14.03V 20 15 G = 100 30 20 10 G = 10 G=5 0 10 -10 5 -12 -8 -4 0 4 8 COMMON-MODE VOLTAGE (V) 12 16 -30 100 07759-022 0 -16 1k Figure 22. Input Bias Current vs. Common-Mode Voltage, Vs = 15 V 160 140 1M 10M Figure 25. Gain vs. Frequency, VS = 15 V 70 G = 1000 G = 100 60 G = 10 50 G=5 40 GAIN (dB) 100 80 60 G = 1000 G = 100 30 20 G = 10 G=5 10 0 40 -10 20 0 0.1 -20 1 10 100 1k FREQUENCY (Hz) 10k 100k -30 100 07759-023 POSITIVE PSRR (dB) 120 10k 100k FREQUENCY (Hz) 07759-025 -20 Figure 23. Positive PSRR vs. Frequency, RTI 1k 10k 100k FREQUENCY (Hz) 1M Figure 26. Gain vs. Frequency, VS = 2.7 V Rev. 0 | Page 12 of 24 10M 07759-026 INPUT BIAS CURRENT (nA) 50 30 AD8227 G = 100 30 G = 10 INPUT BIAS CURRENT (nA) 120 CMRR (dB) G=5 100 80 60 40 0 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k Figure 27. CMRR vs. Frequency, RTI 100 20 75 15 50 10 25 5 -45 -30 -15 15 30 45 60 75 TEMPERATURE (C) 90 0 105 120 135 300 140 G = 1000 200 G = 100 G = 10 GAIN ERROR (V/V) G=5 CMRR (dB) 0 Figure 30. Input Bias Current and Offset Current vs. Temperature 160 120 125 25 07759-027 20 VS = 15V VREF = 0V -IN BIAS CURRENT +IN BIAS CURRENT OFFSET CURRENT INPUT OFFSET CURRENT (pA) 140 150 35 G = 1000 07759-030 160 100 80 60 100 0 -100 40 1 10 100 1k FREQUENCY (Hz) 10k 100k -300 -40 07759-028 0 0.1 Figure 28. CMRR vs. Frequency, RTI, 1 k Source Imbalance -20 0 20 40 60 TEMPERATURE (C) 80 100 120 07759-031 -200 20 Figure 31. Gain Error vs. Temperature, G = 5 0.3 10 6 4 CMRR (V/V) 0.1 0 -0.1 2 0 -2 -4 -6 -0.2 0 10 20 30 40 50 60 70 80 WARM-UP TIME (s) 90 100 110 120 -10 -40 Figure 29. Change in Input Offset Voltage vs. Warm-Up Time -20 0 20 40 60 TEMPERATURE (C) 80 Figure 32. CMRR vs. Temperature, G = 5 Rev. 0 | Page 13 of 24 100 120 07759-032 -8 -0.3 07759-029 CHANGE IN INPUT OFFSET (V) 8 0.2 AD8227 +VS -0.4 -0.6 10 OUTPUT VOLTAGE SWING (V) -0.2 INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES 15 -40C +25C +85C +105C +125C -0.8 -VS -0.2 -0.4 -40C +25C +85C +105C +125C 5 0 -5 -10 2 4 6 8 10 12 SUPPLY VOLTAGE (VS) 14 16 18 -15 100 07759-033 +VS -0.2 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES -0.2 -40C +25C +85C +105C +125C +0.4 +0.3 +0.2 -40C +25C +85C +105C +125C -0.4 -0.6 -0.8 +0.8 +0.6 +0.4 +0.2 +0.1 4 6 8 10 12 SUPPLY VOLTAGE (VS) 14 16 18 -VS 0.01 07759-034 2 Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 k 10 Figure 37. Output Voltage Swing vs. Output Current 40 +VS G=5 -0.2 30 -0.4 -0.8 -1.0 -1.2 NONLINEARITY (10ppm/DIV) -40C +25C +85C +105C +125C -0.6 +1.2 +1.0 +0.8 +0.6 +0.4 20 10 0 -10 -20 -30 +0.2 -VS 2 4 6 8 10 12 SUPPLY VOLTAGE (VS) 14 16 18 -40 -10 07759-035 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 0.1 1 OUTPUT CURRENT (mA) -8 -6 -4 -2 0 2 4 OUTPUT VOLTAGE (V) 6 Figure 38. Gain Nonlinearity, G = 5, RL 2 k Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 k Rev. 0 | Page 14 of 24 8 10 07759-038 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +VS -VS 100k Figure 36. Output Voltage Swing vs. Load Resistance -0.1 -0.4 10k LOAD () Figure 33. Input Voltage Limit vs. Supply Voltage -0.3 1k 07759-037 -0.8 07759-036 -0.6 AD8227 40 1k G = 10 20 10 NOISE (nV/ Hz) 0 -10 100 G = 5 (67nV/ Hz) G = 10 (40nV/ Hz) G = 100 (26nV/ Hz) -20 G = 1000 (25nV/ Hz) -30 -8 -6 -4 -2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 10 07759-039 -40 -10 BANDWIDTH LIMITED 1 Figure 39. Gain Nonlinearity, G = 10, RL 2 k 10 100 1k FREQUENCY (Hz) 10k 100k 07759-042 NONLINEARITY (10ppm/DIV) 30 Figure 42. Voltage Noise Spectral Density vs. Frequency 160 G = 1000, 200nV/DIV G = 100 NONLINEARITY (40ppm/DIV) 120 80 40 0 G = 5, 1V/DIV -40 -80 -8 -6 -4 -2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 07759-040 -160 -10 07759-043 -120 Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 5, G = 1000 Figure 40. Gain Nonlinearity, G = 100, RL 2 k 1k 400 G = 1000 200 NOISE (fA/ Hz) 100 0 -100 100 -200 -400 -10 -8 -6 -4 -2 0 2 4 OUTPUT VOLTAGE (V) 6 8 10 10 1 10 100 FREQUENCY (Hz) 1k Figure 44. Current Noise Spectral Density vs. Frequency Figure 41. Gain Nonlinearity, G = 1000, RL 2 k Rev. 0 | Page 15 of 24 10k 07759-044 -300 07759-041 NONLINEARITY (100ppm/DIV) 300 AD8227 5V/DIV 13.8s TO 0.01% 16.8s TO 0.001% 1s/DIV 40s/DIV 07759-048 1.5pA/DIV 07759-045 0.002%/DIV Figure 48. Large-Signal Pulse Response and Settling Time, G = 10, 10 V Step, VS = 15 V Figure 45. 0.1 Hz to 10 Hz Current Noise 30 5V/DIV 20 35s TO 0.01% 50s TO 0.001% 15 10 5 1k 10k FREQUENCY (Hz) 100k 1M Figure 46. Large-Signal Frequency Response 07759-046 40s/DIV 0 100 07759-049 0.002%/DIV Figure 49. Large-Signal Pulse Response and Settling Time, G = 100, 10 V Step, VS = 15 V 5V/DIV 5V/DIV 275s TO 0.01% 350s TO 0.001% 13.4s TO 0.01% 16.6s TO 0.001% 0.002%/DIV 40s/DIV 07759-047 0.002%/DIV Figure 47. Large-Signal Pulse Response and Settling Time, G = 5, 10 V Step, VS = 15 V 200s/DIV 07759-050 OUTPUT VOLTAGE (V p-p) 25 Figure 50. Large-Signal Pulse Response and Settling Time, G = 1000, 10 V Step, VS = 15 V Rev. 0 | Page 16 of 24 20mV/DIV 4s/DIV Figure 52. Small-Signal Pulse Response, G = 10, RL = 10 k, CL = 100 pF 20s/DIV Figure 53. Small-Signal Pulse Response, G = 100, RL = 10 k, CL = 100 pF 07759-052 Figure 51. Small-Signal Pulse Response, G = 5, RL = 10 k, CL = 100 pF 20mV/DIV 07759-053 4s/DIV 20mV/DIV 100s/DIV 07759-054 20mV/DIV 07759-051 AD8227 Figure 54. Small-Signal Pulse Response, G = 1000, RL = 10 k, CL = 100 pF Rev. 0 | Page 17 of 24 AD8227 340 330 SUPPLY CURRENT (A) CL = 47pF NO LOAD CL = 100pF CL = 147pF 320 310 4s/DIV 290 35 25 SETTLED TO 0.001% 20 15 SETTLED TO 0.01% 10 5 4 6 8 10 12 STEP SIZE (V) 14 16 18 20 07759-056 SETTLING TIME (s) 30 2 2 4 6 8 10 12 SUPPLY VOLTAGE (VS) 14 Figure 57. Supply Current vs. Supply Voltage Figure 55. Small-Signal Pulse Response with Various Capacitive Loads, G = 5, RL = Infinity 0 0 Figure 56. Settling Time vs. Step Size, VS = 15 V, Dual Supply Rev. 0 | Page 18 of 24 16 18 07759-057 20mV/DIV 07759-055 300 AD8227 THEORY OF OPERATION +VS +VS RG NODE 3 NODE 4 -VS -VS R1 8k R3 50k R2 8k NODE 2 +IN Q1 R5 10k A1 A2 VOUT A3 NODE 1 ESD AND OVERVOLTAGE PROTECTION +VS R4 10k ESD AND OVERVOLTAGE PROTECTION Q2 +VS -VS R6 50k REF -IN -VS VBIAS RB -VS DIFFERENCE AMPLIFIER STAGE GAIN STAGE 07759-058 RB Figure 58. Simplified Schematic ARCHITECTURE GAIN SELECTION The AD8227 is based on the classic three op amp topology. This topology has two stages: a preamplifier to provide differential amplification followed by a difference amplifier that removes the common-mode voltage and provides additional amplification. Figure 58 shows a simplified schematic of the AD8227. Placing a resistor across the RG terminals sets the gain of the AD8227. The gain can be calculated by referring to Table 7 or by using the following gain equation: The first stage works as follows. To maintain a constant voltage across the bias resistor, RB, Amplifier A1 must keep Node 3 at a constant diode drop above the positive input voltage. Similarly, Amplifier A2 keeps Node 4 at a constant diode drop above the negative input voltage. Therefore, a replica of the differential input voltage is placed across the gain setting resistor, RG. The current that flows across this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. Note that, in addition to a gained differential signal, the original common-mode signal, shifted a diode drop up, is also still present. The second stage is a difference amplifier, composed of Amplifier A3 and the R3 through R6 resistors. This stage removes the common-mode signal from the amplified differential signal and gains it by 5. The transfer function of the AD8227 is VOUT = G x (VIN+ - VIN-) + VREF where: G=5+ 80 k RG RG = 80 k G -5 Table 7. Gains Achieved Using Common Resistor Values Standard Table Value of RG No resistor 100 k 49.9 k 26.7 k 20 k 16 k 10 k 5.36 k 2 k 1.78 k 1 k 845 412 162 80.6 Calculated Gain 5 5.8 6.6 8 9 10 13 19.9 45 49.9 85 99.7 199 499 998 The AD8227 defaults to G = 5 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the specifications of the AD8227 to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal. Rev. 0 | Page 19 of 24 AD8227 REFERENCE TERMINAL Common-Mode Rejection Ratio over Frequency The output voltage of the AD8227 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8227 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or -VS by more than 0.3 V. Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To keep CMRR over frequency high, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes the interaction of the source resistance with parasitic capacitance from the PCB traces. For best performance, source impedance to the REF terminal should be kept below 2 . As shown in Figure 58, the reference terminal, REF, is at one end of a 50 k resistor. Additional impedance at the REF terminal adds to this 50 k resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be calculated as follows: 6(50 k + RREF)/(60 k + RREF) Power Supplies Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR. INCORRECT A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 23 and Figure 24 for more information. CORRECT AD8227 A 0.1 F capacitor should be placed as close as possible to each supply pin. As shown in Figure 61, a 10 F tantalum capacitor can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits. AD8227 REF REF V Parasitic capacitance at the gain setting pins can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), the component should be chosen so that the parasitic capacitance is as small as possible. V + OP1177 +VS 07759-059 - 0.1F 10F Figure 59. Driving the Reference Pin +IN INPUT VOLTAGE RANGE RG Most instrumentation amplifiers have a very limited output voltage swing when the common-mode voltage is near the upper or lower limit of the part's input range. The AD8227 has very little of this limitation. See Figure 9 through Figure 16 for the input common-mode range vs. output voltage of the part. LOAD 0.1F -VS -IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF AD8227 Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground References The output voltage of the AD8227 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground. 5 -VS TOP VIEW (Not to Scale) 07759-060 +IN 4 10F 07759-061 REF -IN LAYOUT To ensure optimum performance of the AD8227 at the PCB level, care must be taken in the design of the board layout. The pins of the AD8227 are arranged in a logical manner to aid in this task. VOUT AD8227 Figure 60. Pinout Diagram Rev. 0 | Page 20 of 24 AD8227 The other AD8227 terminals should be kept within the supplies. All terminals of the AD8227 are protected against ESD. INPUT BIAS CURRENT RETURN PATH The input bias current of the AD8227 must have a return path to ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 62. INCORRECT For applications where the AD8227 encounters voltages beyond the allowed limits, external current limiting resistors and low leakage diode clamps such as the BAV199L, the FJH1100s, or the SP720 should be used. CORRECT +VS +VS RADIO FREQUENCY INTERFERENCE (RFI) AD8227 RF rectification is often a problem when amplifiers are used in applications that have strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 63. The filter limits the input signal bandwidth, according to the following relationship: AD8227 REF REF -VS -VS TRANSFORMER +VS FilterFrequency DIFF = +VS AD8227 FilterFrequency CM = AD8227 REF REF 1 2R(2C D + C C ) 1 2RC C where CD 10 CC. 10M +VS -VS -VS THERMOCOUPLE 0.1F THERMOCOUPLE +VS +VS C R REF CD 10nF R 1 fHIGH-PASS = 2RC AD8227 CC 1nF 0.1F -VS 07759-062 CAPACITIVELY COUPLED REF -IN 4.02k REF VOUT AD8227 RG R AD8227 C R -VS +IN 4.02k C C 10F CC 1nF CAPACITIVELY COUPLED 10F -VS 07759-063 TRANSFORMER Figure 63. RFI Suppression Figure 62. Creating an Input Bias Current Return Path INPUT PROTECTION The AD8227 has very robust inputs and typically does not need additional input protection. Input voltages can be up to 40 V from the opposite supply rail. For example, with a +5 V positive supply and a -8 V negative supply, the part can safely withstand voltages from -35 V to +32 V. Unlike some other instrumentation amplifiers, the part can handle large differential input voltages even when the part is in high gain. Figure 17 through Figure 20 show the behavior of the part under overvoltage conditions. CD affects the differential signal and CC affects the commonmode signal. Values of R and CC should be chosen to minimize RFI. A mismatch between R x CC at the positive input and R x CC at the negative input degrades the CMRR of the AD8227. By using a value of CD one magnitude larger than CC, the effect of the mismatch is reduced, and performance is improved. Rev. 0 | Page 21 of 24 AD8227 APPLICATIONS INFORMATION DIFFERENTIAL DRIVE Tips for Best Differential Output Performance Figure 64 shows how to configure the AD8227 for differential output. For best ac performance, an op amp with at least 2 MHz gain bandwidth and 1 V/s slew rate is recommended. Good choices for op amps are the AD8641, AD8515, or AD820. +IN Keep trace lengths from resistors to the inverting terminal of the op amp as short as possible. Excessive capacitance at this node can cause the circuit to be unstable. If capacitance cannot be avoided, use lower value resistors. +OUT -IN R R VBIAS PRECISION STRAIN GAGE + - OP AMP -OUT RECOMMENDED OP AMPS: AD8515, AD8641, AD820. RECOMMENDED R VALUES: 5k to 20k. The low offset and high CMRR over frequency of the AD8227 make it an excellent choice for bridge measurements. The bridge can be connected directly to the inputs of the amplifier (see Figure 65). 07759-064 REF 5V Figure 64. Differential Output Using an Op Amp 10F The differential output is set by the following equation: 350 0.1F 350 +IN VDIFF_OUT = VOUT+ - VOUT- = Gain x (VIN+ - VIN-) 350 The common-mode output is set by the following equation: 350 AD8227 RG -IN VCM_OUT = (VOUT+ - VOUT-)/2 = VBIAS The advantage of this circuit is that the dc differential accuracy depends on the AD8227 and not on the op amp or the resistors. This circuit takes advantage of the AD8227's precise control of its output voltage relative to the reference voltage. Op amp dc performance and resistor matching affect the dc common-mode output accuracy. However, because common-mode errors are likely to be rejected by the next device in the signal chain, these errors typically have little effect on overall system accuracy. Rev. 0 | Page 22 of 24 + - Figure 65. Precision Strain Gage 2.5V 07759-065 AD8227 AD8227 Option 2 shows a circuit for driving higher frequency signals. It uses a precision op amp (AD8616) with relatively high bandwidth and output drive. This amplifier can drive a resistor and capacitor with a much higher time constant and is, therefore, suited for higher frequency applications. DRIVING AN ADC Figure 66 shows several different methods for driving an ADC. The ADC in the ADuC7026 microcontroller was chosen for this example because it has an unbuffered charge sampling architecture that is typical of most modern ADCs. This type of architecture typically requires an RC buffer stage between the ADC and the amplifier to work correctly. Option 3 is useful for applications where the AD8227 needs to run off a large voltage supply but drives a single-supply ADC. In normal operation, the AD8227 output stays within the ADC range, and the AD8616 simply buffers it. However, in a fault condition, the output of the AD8227 may go outside the supply range of both the AD8616 and the ADC. This is not an issue in the circuit, because the 10 k resistor between the two amplifiers limits the current into the AD8616 to a safe level. Option 1 shows the minimum configuration required to drive a charge sampling ADC. The capacitor provides charge to the ADC sampling capacitor, and the resistor shields the AD8227 from the capacitance. To keep the AD8227 stable, the RC time constant of the resistor and capacitor needs to stay above 5 s. This circuit is mainly useful for lower frequency signals. 3.3V OPTION 1: DRIVING LOW FREQUENCY SIGNALS AD8227 3.3V AVDD ADC0 100 REF 3.3V 100nF ADuC7026 OPTION 2: DRIVING HIGH FREQUENCY SIGNALS 3.3V AD8227 REF AD8616 10 ADC1 10nF +15V OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES 3.3V REF AD8616 10 ADC2 10nF -15V Figure 66. Driving an ADC Rev. 0 | Page 23 of 24 AGND 07759-066 AD8227 10k AD8227 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 3.20 3.00 2.80 1 5 4.00 (0.1574) 3.80 (0.1497) 5.15 4.90 4.65 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.38 0.22 COPLANARITY 0.10 6.20 (0.2441) 5.80 (0.2284) 4 PIN 1 0.15 0.00 8 1 0.23 0.08 8 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.80 0.60 0.40 COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 67. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Figure 68. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model AD8227ARMZ 1 AD8227ARMZ-RL1 AD8227ARMZ-R71 AD8227ARZ1 AD8227ARZ-RL1 AD8227ARZ-R71 AD8227BRMZ1 AD8227BRMZ-RL1 AD8227BRMZ-R71 AD8227BRZ1 AD8227BRZ-RL1 AD8227BRZ-R71 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel Z = RoHS Compliant Part. (c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07759-0-5/09(0) Rev. 0 | Page 24 of 24 Package Option RM-8 RM-8 RM-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 Branding Y1S Y1S Y1S Y1U Y1U Y1U 012407-A 8 3.20 3.00 2.80