THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
WIDEBAND, LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIERS
–
FEATURES
DFully Differential Architecture
DBandwidth: 370 MHz
DSlew Rate: 2800 V/µs
DIMD3: –90 dBc at 30 MHz
DOIP3: 49 dBm at 30 MHz
DOutput Common-Mode Control
DWide Power Supply Voltage Range: 5 V, ±5 V,
12 V, 15 V
DInput Common-Mode Range Shifted to
Include the Negative Power Supply Rail
DPower-Down Capability (THS4500)
DEvaluation Module Available
DESCRIPTION
The THS4500 and THS4501 are high-performance fully
differential amplifiers from Texas Instruments. The
THS4500, featuring power-down capability, and the
THS4501, without power-down capability, set new
performance standards for fully differential amplifiers
with unsurpassed linearity, supporting 14-bit operation
through 40 MHz. Package options include the 8-pin
SOIC and the 8-pin MSOP with PowerPAD for a
smaller footprint, enhanced ac performance, and
improved thermal dissipation capability.
APPLICATIONS
DHigh Linearity Analog-to-Digital Converter
Preamplifier
DWireless Communication Receiver Chains
DSingle-Ended to Differential Conversion
DDifferential Line Driver
DActive Filtering of Differential Signals
1
2
3
4
8
7
6
5
VIN– VIN+
VOCM
VS+
VOUT+
PD
VS–
VOUT–
RELATED DEVICES
DEVICE(1) DESCRIPTION
THS4500/1 370 MHz, 2800 V/µs, VICR Includes VS–
THS4502/3 370 MHz, 2800 V/µs, Centered VICR
THS4120/1 3.3 V, 100 MHz, 43 V/µs, 3.7 nV√Hz
THS4130/1 ±15 V, 150 MHz, 51 V/µs, 1.3 nV√Hz
THS4140/1 ±15 V, 160 MHz, 450 V/µs, 6.5 nV√Hz
THS4150/1 ±15 V, 150 MHz, 650 V/µs, 7.6 nV√Hz
(1) Even numbered devices feature power-down capability
APPLICATION CIRCUIT DIAGRAM
f – Frequency – MHz
–80
–92
10 20 40 60
– Third-Order Intermodulation Distortion – dBc
–74
THIRD-ORDER INTERMODULA TION
DISTORTION
–62
80 100
–68
–86
–98
12
10
14
16
IMD3
Bits
VS
392 Ω
+
––
+800 Ω
VS+ VOUT
392 Ω
402 Ω
56.2 Ω
50 Ω374 Ω
VOCM
2.5 V
VS–
30 50 70 90
VS = 5 V
VS = ±5 V
–
+–
+
VOCM 12 Bit/80 MSps
IN
IN
5 V
Vref
5 V
VS
0.1 µF 10 µF
392 Ω
10 pF
1 µF
56.2 ΩADC
374 Ω
50 Ω
402 Ω
392 Ω
10 pF
24.9 Ω
24.9 Ω
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA
information current as of publication date. Products conform to specifications per
the terms of Texas Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability , standard warranty, and use in critical applications of T exas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2002, Texas Instruments Incorporated
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
2
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage, VS16.5 V
Input voltage, VI±VS
Output current, IO (2) 150 mA
Differential input voltage, VID 4 V
Continuous power dissipation See Dissipation Rating Table
Maximum junction temperature, TJ150°C
Operating free-air temperature range, TA: C suffix
I suffix 0°C to 70°C
–40°C to 85°C
Storage temperature range, Tstg –65°C to
150°C
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds 300°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) The THS450x may incorporate a PowerPAD on the underside of
the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical brief SLMA002 for more information about utilizing the
PowerPAD thermally enhanced package.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE DISSIPATION RATINGS
PACKAGE
θ
JC
θ
JA
(1) POWER RATING
PACKAGE
θJC
(°C/W)
θJA()
(°C/W) TA ≤ 25°C TA = 85°C
D (8 pin) 38.3 167 740 mW 390 mW
DGN (8 pin) 4.7 58.4 2.14 W 1.11 W
DRB (8 pin)(1) TBD TBD TBD TBD
(1) The DRB package is in the product preview stage of development
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Supplyvoltage
Dual supply ±5±7.5
V
Supply voltage Single supply 4.5 5 15 V
Operating
free air
C suffix 0 70
°C
free-air
temperature, TAI suffix –40 85 °C
PACKAGE/ORDERING INFORMATION ORDERABLE P ACKAGE AND NUMBER
TEMPERATURE PLASTIC
SMALL OUTLINE(1)
(D) LEADLESS (DRB) PACKAGE
MARKING PLASTIC MSOP
(DGN) PACKAGE
MARKING
0°Cto70°C
THS4500CD THS4500CDRB TBD THS4500CDGN BFB
0°C to 70°CTHS4501CD THS4501CDRB TBD THS4501CDGN BFD
40°Cto85°C
THS4500ID THS4500IDRB TBD THS4500IDGN BFC
–40°C to 85°CTHS4501ID THS4501IDRB TBD THS4501IDGN BFE
(1) This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., THS4501IDR).
PIN ASSIGNMENTS
THS4501
(T OP VIEW)
VIN–1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS–
VOUT–
PD
D, DRB, AND DGN
THS4500
(T OP VIEW) D, DRB, AND DGN
VIN–1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS–
VOUT–
NC
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
3
ELECTRICAL CHARACTERISTICS VS = ±5 V
Rf = Rg = 392 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4500 AND THS4501
PARAMETER
TESTCONDITIONS
TYP OVER TEMPERA TURE MIN/
PARAMETER
TEST
CONDITIONS
25°C 25°C0°C to
70°C–40°C to
85°CUNITS
MIN/
TYP/
MAX
AC PERFORMANCE G = +1, PIN= –20 dBm, Rf = 392 Ω370 MHz Typ
Small signal bandwidth
G = +2, PIN= –30 dBm, Rf = 1 kΩ175 MHz Typ
Small-signal bandwidth G = +5, PIN= –30 dBm, Rf = 2.4 kΩ70 MHz Typ
G = +10, PIN = –30 dBm, Rf = 5.1 kΩ30 MHz Typ
Gain-bandwidth product G > +10 300 MHz Typ
Bandwidth for 0.1dB flatness PIN = –20 dBm 150 MHz Typ
Large-signal bandwidth VP = 2 V 220 MHz Typ
Slew rate 4 VPP Step 2800 V/µsTyp
Rise time 2 VPP Step 0.4 ns Typ
Fall time 2 VPP Step 0.5 ns Typ
Settling time to 0.01% VO = 4 VPP 8.3 ns Typ
0.1% VO = 4 VPP 6.3 ns Typ
Harmonic distortion G = +1, VO = 2 VPP Typ
2ndharmonic
f = 8 MHz –82 dBc Typ
2n
d
harmonic f = 30 MHz –71 dBc Typ
3rdharmonic
f = 8 MHz –97 dBc Typ
3r
d
harmonic f = 30 MHz –74 dBc Typ
Third-order intermodulation
distortion VO = 2 VPP, fc = 30 MHz,
Rf = 392 Ω, 200 kHz tone spacing –90 dBc Typ
Third-order output intercept point fc = 30 MHz, Rf = 392 Ω,
Referenced to 50 Ω49 dBm Typ
Input voltage noise f > 1 MHz 7 nV/√Hz Typ
Input current noise f > 100 kHz 1.7 pA/√Hz Typ
Overdrive recovery time Overdrive = 5.5 V 60 ns Typ
DC PERFORMANCE
Open-loop voltage gain 55 52 50 50 dB Min
Input offset voltage –4–7 / –1–8 / 0 –9 / +1 mV Max
Average of fset voltage drift ±10 ±10 µV/°CTyp
Input bias current 4 4.6 5 5.2 µA Max
Average bias current drift ±10 ±10 nA/°CTyp
Input offset current 0.5 1 2 2 µA Max
Average of fset current drift ±40 ±40 nA/°CTyp
INPUT
Common-mode input range –5.7 / 2.6 –5.4 / 2.3 –5.1 / 2 –5.1 / 2 V Min
Common-mode rejection ratio 80 74 70 70 dB Min
Input impedance 107 || 1 Ω || pF Typ
OUTPUT
Differential output voltage swing RL = 1 kΩ ±8±7.6 ±7.4 ±7.4 V Min
Differential output current drive RL = 20 Ω120 110 100 100 mA Min
Output balance error PIN = –20 dBm, f = 100 kHz –58 dB Typ
Closed-loop output impedance
(single-ended) f = 1 MHz 0.1 ΩTyp
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
4
ELECTRICAL CHARACTERISTICS VS = ±5 V (continued)
Rf = Rg = 392 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4500 AND THS4501
PARAMETER
TESTCONDITIONS
TYP OVER TEMPERA TURE MIN/
PARAMETER
TEST
CONDITIONS
25°C 25°C0°C to
70°C–40°C to
85°CUNITS
MIN/
TYP/
MAX
OUTPUT COMMON-MODE VOL T AGE CONTROL
Small-signal bandwidth RL = 400 Ω180 MHz Typ
Slew rate 2 VPP step 92 V/µsTyp
Minimum gain 1 0.98 0.98 0.98 V/V Min
Maximum gain 1 1.02 1.02 1.02 V/V Max
Common-mode offset voltage –0.4 –4.6/+3.8 –6.6/+5.8 –7.6/+6.8 mV Max
Input bias current VOCM = 2.5 V 100 150 170 170 µA Max
Input voltage range ±4±3.7 ±3.4 ±3.4 V Min
Input impedance 25 || 1 kΩ || pF Typ
Maximum default voltage VOCM left floating 0 0.05 0.10 0.10 V Max
Minimum default voltage VOCM left floating 0–0.05 –0.10 –0.10 V Min
POWER SUPPL Y
Specified operating voltage ±5 7.5 7.5 7.5 V Max
Maximum quiescent current 23 28 32 34 mA Max
Minimum quiescent current 23 18 14 12 mA Min
Power supply rejection (±PSRR) 80 76 73 70 dB Min
POWER DOWN (THS4500 ONLY)
Enable voltage threshold Device enabled ON above –2.9 V –2.9 V Min
Disable voltage threshold Device disabled OFF below –4.3 V –4.3 V Max
Power-down quiescent current 800 1000 1200 1200 µA Max
Input bias current 200 240 260 260 µA Max
Input impedance 50 || 1 kΩ || pF Typ
Turnon time delay 1000 ns Typ
T urnof f time delay 800 ns Typ
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
5
ELECTRICAL CHARACTERISTICS VS = 5 V
Rf = Rg = 392 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4500 AND THS4501
PARAMETER
TYP OVER TEMPERA TURE MIN/
PARAMETER
25°C 25°C0°C to
70°C–40°C to
85°CUNITS
MIN/
TYP/
MAX
AC PERFORMANCE G = +1, PIN = –20 dBm, Rf = 392 Ω320 MHz Typ
Small signal bandwidth
G = +2, PIN = –30 dBm, Rf = 1 kΩ160 MHz Typ
Small-signal bandwidth G = +5, PIN = –30 dBm, Rf = 2.4 kΩ60 MHz Typ
G = +10, PIN = –30 dBm, Rf = 5.1 kΩ30 MHz Typ
Gain-bandwidth product G > +10 300 MHz Typ
Bandwidth for 0.1 dB flatness PIN = –20 dBm 180 MHz Typ
Large-signal bandwidth VP = 1 V 200 MHz Typ
Slew rate 2 VPP Step 1300 V/µsTyp
Rise time 2 VPP Step 0.5 ns Typ
Fall time 2 VPP Step 0.6 ns Typ
Settling time to 0.01% VO = 2 V Step 13.1 ns Typ
0.1% VO = 2 V Step 8.3 ns Typ
Harmonic distortion G = +1, VO = 2 VPP Typ
2ndharmonic
f = 8 MHz, –80 dBc Typ
2n
d
harmonic f = 30 MHz –55 dBc Typ
3rdharmonic
f = 8 MHz –76 dBc Typ
3r
d
harmonic f = 30 MHz –60 dBc Typ
Input voltage noise f > 1 MHz 7 nV/√Hz Typ
Input current noise f > 100 kHz 1.7 pA/√Hz Typ
Overdrive recovery time Overdrive = 5.5 V 60 ns Typ
DC PERFORMANCE
Open-loop voltage gain 54 51 49 49 dB Min
Input offset voltage –4–7 / –1–8 / 0 –9 / +1 mV Max
Average of fset voltage drift ±10 ±10 µV/°CTyp
Input bias current 4 4.6 5 5.2 µA Max
Average bias current drift ±10 ±10 nA/°CTyp
Input offset current 0.5 0.7 1.2 1.2 µA Max
Average of fset current drift ±20 ±20 nA/°CTyp
INPUT
Common-mode input range –0.7/2.6 –0.4 / 2.3 –0.1 / 2 –0.1 / 2 V Min
Common-mode rejection ratio 80 74 70 70 dB Min
Input Impedance 107 || 1 Ω || pF Typ
OUTPUT
Differential output voltage swing RL = 1 kΩ, Referenced to 2.5 V ±3.3 ±3±2.8 ±2.8 V Min
Output current drive RL = 20 Ω100 90 80 80 mA Min
Output balance error PIN = –20 dBm, f = 100 kHz –58 dB Typ
Closed-loop output impedance
(single-ended) f = 1 MHz 0.1 ΩTyp
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
6
ELECTRICAL CHARACTERISTICS VS = 5 V (continued)
Rf = Rg = 392 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4500 AND THS4501
PARAMETER
TYP OVER TEMPERA TURE
PARAMETER
25°C 25°C0°C to
70°C–40°C
to 85°CUNITS MIN/
MAX
OUTPUT COMMON-MODE VOL T AGE CONTROL
Small-signal bandwidth RL = 400 Ω180 MHz Typ
Slew rate 2 VPP Step 80 V/µsTyp
Minimum gain 1 0.98 0.98 0.98 V/V Min
Maximum gain 1 1.02 1.02 1.02 V/V Max
Common-mode offset voltage 0.4 –2.6/3.4 –4.2/5.4 –5.6/6.4 mV Max
Input bias current VOCM = 2.5 V 1 2 3 3 µA Max
Input voltage range 1 / 4 1.2 / 3.8 1.3 / 3.7 1.3 / 3.7 V Min
Input impedance 25 || 1 kΩ || pF Typ
Maximum default voltage VOCM left floating 2.5 2.55 2.6 2.6 V Max
Minimum default voltage VOCM left floating 2.5 2.45 2.4 2.4 V Min
POWER SUPPL Y
Specified operating voltage 5 15 15 15 V Max
Maximum quiescent current 20 25 29 31 mA Max
Minimum quiescent current 20 16 12 10 mA Min
Power supply rejection (+PSRR) 75 72 69 66 dB Min
POWER DOWN (THS4500 ONLY)
Enable voltage threshold Device enabled ON above 2.1 V 2.1 V Min
Disable voltage threshold Device disabled OFF below 0.7 V 0.7 V Max
Power-down quiescent current 600 800 1200 1200 µA Max
Input bias current 100 125 140 140 µA Max
Input impedance 50 || 1 kΩ || pF Typ
Turnon time delay 1000 ns Typ
T urnof f time delay 800 ns Typ
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
7
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small signal unity gain frequency response 1
Small signal frequency response 2
0.1 dB gain flatness frequency response 3
Large signal frequency response 4
Harmonic distortion (single-ended input to differential output) vs Frequency 5, 7, 13, 15
Harmonic distortion (differential input to differential output) vs Frequency 6, 8, 14, 16
Harmonic distortion (single-ended input to differential output) vs Output voltage swing 9, 1 1, 17, 19
Harmonic distortion (differential input to differential output) vs Output voltage swing 10, 12, 18, 20
Harmonic distortion (single-ended input to differential output) vs Load resistance 21
Harmonic distortion (dif ferential input to differential output) vs Load resistance 22
Third order intermodulation distortion (single-ended input to differential output) vs Frequency 23
Third order output intercept point vs Frequency 24
Slew rate vs Differential output voltage step 25
Settling time 26, 27
Large signal transient response 28
Small signal transient response 29
Overdrive recovery 30, 31
V oltage and current noise vs Frequency 32
Rejection ratios vs Frequency 33
Rejection ratios vs Case temperature 34
Output balance error vs Frequency 35
Open-loop gain and phase vs Frequency 36
Open-loop gain vs Case temperature 37
Input bias of fset current vs Case temperature 38
Quiescent current vs Supply voltage 39
Input of fset voltage vs Case temperature 40
Common-mode rejection ratio vs Input common-mode range 41
Output drive vs Case temperature 42
Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage 43
Small signal frequency response at VOCM 44
Output offset voltage at VOCM vs Output common-mode voltage 45
Quiescent current vs Power-down voltage 46
Turnon and turnoff delay times 47
Single-ended output impedance in power down vs Frequency 48
Power-down quiescent current vs Case temperature 49
Power-down quiescent current vs Supply voltage 50
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
8
TYPICAL CHARACTERISTICS
Table of Graphs (5 V)
FIGURE
Small signal unity gain frequency response 51
Small signal frequency response 52
0.1 dB gain flatness frequency response 53
Large signal frequency response 54
Harmonic distortion (single-ended input to differential output) vs Frequency 55, 57, 63, 65
Harmonic distortion (differential input to differential output) vs Frequency 56, 58, 64, 66
Harmonic distortion (single-ended input to differential output) vs Output voltage swing 59, 61, 67, 69
Harmonic distortion (differential input to differential output) vs Output voltage swing 60, 62, 68, 70
Harmonic distortion (single-ended input to differential output) vs Load resistance 71
Harmonic distortion (dif ferential input to differential output) vs Load resistance 72
Third-order intermodulation distortion vs Frequency 73
Third-order intercept point vs Frequency 74
Slew rate vs Differential output voltage step 75
Large-signal transient response 76
Small-signal transient response 77
V oltage and current noise vs Frequency 78
Rejection ratios vs Frequency 79
Rejection ratios vs Case temperature 80
Output balance error vs Frequency 81
Open-loop gain and phase vs Frequency 82
Open-loop gain vs Case temperature 83
Input bias of fset current vs Case temperature 84
Quiescent current vs Supply voltage 85
Input of fset voltage vs Case temperature 86
Common-mode rejection ratio vs Input common-mode range 87
Output drive vs Case temperature 88
Harmonic distortion (single-ended and differential input) vs Output common-mode voltage 89
Small signal frequency response at VOCM 90
Output offset voltage vs Output common-mode voltage 91
Quiescent current vs Power-down voltage 92
Turnon and turnoff delay times 93
Single-ended output impedance in power down vs Frequency 94
Power-down quiescent current vs Case temperature 95
Power-down quiescent current vs Supply voltage 96
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
9
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 1
–4
–3.5
–3
–2.5
–2
–1.5
–1
–0.5
0
0.5
1
0.1 1 10 100 1000
f – Frequency – MHz
Small Signal Unity Gain – dB
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = –20 dBm
VS = ±5 V
Figure 2
–2
0
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f – Frequency – MHz
Small Signal Gain – dB
SMALL SIGNAL FREQUENCY RESPONSE
Gain = 10, Rf = 5.1 kΩ
Gain = 5, Rf = 2.4 kΩ
Gain = 2, Rf = 1 kΩ
RL = 800 Ω
PIN = –30 dBm
VS = ±5 V
Figure 3
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
110 100 1000
Rf = 392 Ω
Rf = 499 Ω
Gain = 1
RL = 800 Ω
PIN = –20 dBm
VS = ±5 V
f – Frequency – MHz
0.1 dB Gain Flatness – dB
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
Figure 4
–4
–3
–2
–1
0
1
0.1 1 10 100 1000
f – Frequency – MHz
Large Signal Gain – dB
LARGE SIGNAL FREQUENCY RESPONSE
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = 10 dBm
VS = ±5 V
Figure 5
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = ±5 V
Figure 6
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = ±5 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
Figure 7 Figure 8
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
Figure 9
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 8 MHz
VS = ±5 V
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
10
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 10
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
Figure 1 1
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
Figure 12
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Differentia Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
Figure 13
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = ±5 V
Figure 14
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0.1 1 10 100
0
HD2
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = ±5 V
HD3
Figure 15
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = ±5 V
Figure 16
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0.1 1 10 100
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = ±5 V
Figure 17
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = ±5 V
Figure 18
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = ±5 V
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
11
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 19
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 30 MHz
VS = ±5 V
Figure 20
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Differentia Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = ±5 V
Figure 21
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
LOAD RESIST ANCE
RL – Load Resistance – Ω
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
Figure 22
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
LOAD RESIST ANCE
RL – Load Resistance – Ω
Differential Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
Figure 23
–100
–90
–80
–70
–60
–50
10 100
Third-Order Intermodulation Distortion – dBc
THIRD-ORDER INTERMODULA TION
DISTORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
Figure 24
30
35
40
45
50
55
0 20 40 60 80 100 120
Third-Order Output Intersept Point – dBm
f – Frequency – MHz
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
Gain = 1
Rf = 392 Ω
VO = 2 VPP
VS = ± 5 V
Figure 25
0
500
1000
1500
2000
2500
3000
VO – Differential Output Voltage Step – V
SR – Slew Rate –
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOL T AGE STEP
sµ
V/
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VS = ±5 V
0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
Figure 26
0 5 10 15 20
t – Time – ns
– Output Voltage – V
SETTLING TIME
VO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
Rising Edge
Falling Edge
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
Figure 27
–1.5
–1
–0.5
0
0.5
1
1.5
0 20 40 60 80 100 120 140
t – Time – ns
– Output Voltage – V
SETTLING TIME
VO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
Rising Edge
Falling Edge
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
12
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 28
–100 0 100 200 300 400 500
t – Time – ns
– Output Voltage – V
LARGE-SIGNAL TRANSIENT RESPONSE
VO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
–2
–1.5
–1
–0.5
0
0.5
1
1.5
2
Figure 29
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–100 0 100 200 300 400 500
t – Time – ns
– Output Voltage – V
SMALL-SIGNAL TRANSIENT RESPONSE
VO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
Figure 30
t – Time – µs
0
–1
–4
0 0.1 0.2 0.3 0.4 0.5 0.6
Single-Ended Output V oltage – V
1
2
OVERDRIVE RECOVER Y
4
0.7 0.8 0.9 1
3
–3
–5
–2
5
0
–0.5
–2
0.5
1
2
1.5
–1.5
–2.5
–1
2.5
– Input Voltage – VVI
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 4.5 V
VS = ±5 V
Figure 31
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 –3
–2
–1
0
1
2
3
t – Time – µs
Single-Ended Output V oltage – V
OVERDRIVE RECOVER Y
– Input Voltage – VVI
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 5.5 V
VS = ±5 V
Figure 32
1
10
100
0.01 0.1 1 10 100
Vn
In
f – Frequency – kHz
– Voltage Noise –
VOLT AGE AND CURRENT NOISE
vs
FREQUENCY
nV/ Hz
Vn
– Current Noise –pA/ Hz
In
1000 10 k
Figure 33
–10
0
10
20
30
40
50
60
70
80
90
0.1 1 10 100
Rejection Ratios – dB
REJECTION RA TIOS
vs
FREQUENCY
f – Frequency – MHz
PSRR+
PSRR–CMMR
RL = 800 Ω
VS = ±5 V
Figure 34
0
20
40
60
80
100
120
–40–30–20–100 102030405060708090
Rejection Ratios – dB
REJECTION RATIOS
vs
CASE TEMPERA TURE
Case Temperature – °C
PSRR+
CMMR
RL = 800 Ω
VS = ±5 V
Figure 35
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
Output Balance Error – dB
OUTPUT BALANCE ERROR
vs
FREQUENCY
f – Frequency – MHz
PIN = 10 dBm
RL = 800 Ω
Rf = 392 Ω
VS = ±5 V
Figure 36
0
10
20
30
40
50
60
0.01 0.1 1 10 100 1000
–150
–120
–90
–60
–30
0
30
Open-Loop Gain – dB
OPEN-LOOP GAIN AND FHASE
vs
FREQUENCY
f – Frequency – MHz
PIN = –30 dBm
RL = 800 Ω
VS = ±5 V
Phase –
Gain
Phase
°
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
13
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 37
58
49
50
51
52
53
54
55
56
57
–40–30–20–100 102030405060708090
Open-Loop Gain – dB
OPEN-LOOP GAIN
vs
CASE TEMPERA TURE
Case Temperature – °C
RL = 800 Ω
VS = ±5 V
Figure 38
–40–30–20–100 102030405060708090
– Input Bias Current –
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERA TURE
VS = ±5 V
– Input Offset Current –
IIB Aµ
IOS Aµ
IIB+
IOS
Case Temperature – °C
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
–0.09
–0.08
–0.07
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
0
IIB–
Figure 39
0
5
10
15
20
25
30
35
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS – Supply Voltage – ±V
Quiescent Current – mA
QUIESCENT CURRENT
vs
SUPPLY VOL TAGE
TA = 85°C
TA = 25°C
TA = –40°C
Figure 40
0
1
3
4
6
7
–40–30–20–100 102030405060708090
Case Temperature – °C
– Input Offset Voltage – mV
INPUT OFFSET VOLT AGE
vs
CASE TEMPERA TURE
VOS
VS = ±5 V
2
5
Figure 41
–6–5–4–3–2–10123456
–10
0
10
20
30
40
50
60
70
80
90
100
110
Input Common-Mode V oltage Range – V
CMRR – Common-Mode Rejection Ratio – dB
COMMON-MODE REJECTION RA TIO
vs
INPUT COMMON-MODE RANGE
VS = ±5 V
Figure 42
–150
–100
–50
0
50
100
150
200
–40–30–20–100 102030405060708090
Output Drive – mA
OUTPUT DRIVE
vs
CASE TEMPERA TURE
Case Temperature – °C
VS = ±5 V Source
Sink
Figure 43
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
–3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5
VOC – Output Common-Mode Voltage – V
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT COMMON-MODE VOL T AGE
Single-Ended and Differential
Input to Differential Output
Gain = 1, VO = 2 VPP
f= 8 MHz, Rf = 392 Ω
VS = ±5 V
HD2
-Diff
HD2-SE
HD3-Diff
HD3-SE
Figure 44
–3
–2
–1
0
1
2
3
1 10 100 1000
SMALL SIGNAL FREQUENCY RESPONSE
at VOCM
f – Frequency – MHz
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN= –20 dBm
VS = ±5 V
Small Signal Frequency Response at VOCM– dB
Figure 45
–600
–400
–200
0
200
400
600
–5–4–3–2–1012345
VOC – Output Common-Mode Voltage – V
– Output Offset Voltage – mV
OUTPUT OFFSET VOLT AGE at VOCM
vs
OUTPUT COMMON-MODE VOL T AGE
VOS
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
14
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 46
–5
0
5
10
15
20
25
30
–5–4.5 –4–3.5 –3–2.5 –2–1.5 –1–0.5 0
Power-Down Voltage – V
Quiescent Current – mA
QUIESCENT CURRENT
vs
POWER-DOWN VOL T AGE
Figure 47
–1
–2
–5
0 0.5 1 2
0
100.5101 102 103
–3
–6
–4
0
0.01
0.03
0.02
t – Time – ms
Powerdown Voltage Signal – V
TURNON AND TURNOFF DELAY TIME
Quiescent Current – mA
1.5 2.5 3
Current
Figure 48
0
100
200
300
400
500
600
700
800
0.1 1 10 100 1000
– Single-Ended Output Impedance
SINGLE-ENDED OUTPUT IMPEDANC
E
IN POWER DOWN
vs
FREQUENCY
ZOin Powerdown –
f – Frequency – MHz
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = –1 dBm
VS = ±5 V
Ω
Figure 49
–40–30–20–100 102030405060708090
Power-Down Quiescent Current –
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERA TURE
Case Temperature – °C
RL = 800 Ω
VS = ±5 V
0
100
200
300
400
500
600
700
800
900
1000
Aµ
Figure 50
0
100
200
300
400
500
600
700
800
900
1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS – Supply Voltage – ±V
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOL TAGE
RL = 800 Ω
Power-Down Quiescent Current –Aµ
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
15
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 51
–4
–3
–2
–1
0
1
0.1 1 10 100 1000
f – Frequency – MHz
Small Signal Unity Gain – dB
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = –20 dBm
VS = 5 V
Figure 52
–2
0
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f – Frequency – MHz
Small Signal Gain – dB
SMALL SIGNAL FREQUENCY RESPONSE
Gain = 10, Rf = 5.1 kΩ
Gain = 5, Rf = 2.4 kΩ
Gain = 2, Rf = 1 kΩ
RL = 800 Ω
PIN = –30 dBm
VS = 5 V
Figure 53
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.2
110 100 1000
Rf = 392 Ω
Rf = 499 Ω
f – Frequency – MHz
0.1 dB Gain Flatness – dB
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
Gain = 1
RL = 800 Ω
PIN = –20 dBm
VS = 5 V
0.1
Figure 54
0.1 1 10 100 1000
f – Frequency – MHz
Large Signal Gain – dB
LARGE SIGNAL FREQUENCY RESPONSE
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = 10 dBm
VS = 5 V
–4
–3
–2
–1
0
1
Figure 55
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = 5 V
Figure 56
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = 5 V
Figure 57
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = 5 V
Figure 58
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
Figure 59
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 8 MHz
VS = 5 V
0.5 1 1.5 2 2.5 30
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
16
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 60
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Differentia Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 8 MHz
VS = 5 V
0 0.5 1 1.5 2 2.5 3
Figure 61
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
0 0.5 1 1.5 2 2.5 3
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f = 30 MHz
VS = 5 V
Figure 62
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Differentia Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 30 MHz
VS = 5 V
0 0.5 1 1.5 2 2.5 3
Figure 63
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = 5 V
Figure 64
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0.1 1 10 100
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = 5 V
Figure 65
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = 5 V
Figure 66
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f – Frequency – MHz
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = 5 V
Figure 67
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
0 0.5 1 1.5 2 2.5 3
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f = 8 MHz
VS = 5 V
Figure 68
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Differentia Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = 5 V
0 0.5 1 1.5 2 2.5 3
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
17
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 69
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
0 0.5 1 1.5 2 2.5 3
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f = 30 MHz
VS = 5 V
Figure 70
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT VOL T AGE SWING
VO – Output Voltage Swing – V
Differentia Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 30 MHz
VS = 5 V
0 0.5 1 1.5 2 2.5 3
Figure 71
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
LOAD RESIST ANCE
RL – Load Resistance – Ω
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = 5 V
Figure 72
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
LOAD RESIST ANCE
RL – Load Resistance – Ω
Differentia Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = 5 V
Figure 73
–100
–90
–80
–70
–60
–50
10 100
Third-Order Intermodulation Distortion – dBc
THIRD-ORDER INTERMODULA TION
DISTORTION
vs
FREQUENCY
f – Frequency – MHz
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
RL = 800 Ω
VS = 5 V
Figure 74
30
35
40
45
50
55
0 20 40 60 80 100 120
Third-Order Output Intersept Point – dBm
f – Frequency – MHz
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
Gain = 1
VO = 2 VPP
Rf = 392 Ω
RL = 800 Ω
VS = 5 V
Figure 75
0
200
400
600
800
1000
1200
1400
0 0.5 1 1.5 2 2.5 3
VO – Differential Output Voltage Step – V
SR – Slew Rate –
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOL T AGE STEP
sµ
V/
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VS = 5 V
Figure 76
–2
–1.5
–1
–0.5
0
0.5
1
1.5
2
–100 0 100 200 300 400 500
t – Time – ns
– Output Voltage – V
LARGE-SIGNAL TRANSIENT RESPONSE
VO
Gain = 1
RL = 800 Ω
Rf = 392 Ω
tr/tf = 300 ps
VS = 5 V
Figure 77
–100 0 100 200 300 400 500
t – Time – ns
– Output Voltage – V
SMALL-SIGNAL TRANSIENT RESPONSE
VO
Gain = 1
RL = 800 Ω
Rf = 392 Ω
tr/tf = 300 ps
VS = 5 V
–0.4
–0.3
–0.2
–0.1
0
0.2
0.3
0.1
0.4
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
18
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 78
1
10
100
0.01 0.1 1 10 100
Vn
In
f – Frequency – kHz
– Voltage Noise –
VOLT AGE AND CURRENT NOISE
vs
FREQUENCY
nV/ Hz
Vn
– Current Noise –pA/ Hz
In
1000 10 k
Figure 79
–10
0
10
20
30
40
50
60
70
80
90
0.1 1 10 100
Rejection Ratios – dB
REJECTION RA TIOS
vs
FREQUENCY
f – Frequency – MHz
PSRR+
PSRR–CMMR
RL = 800 Ω
VS = 5 V
Figure 80
–40–30–20–100 102030405060708090
Rejection Ratios – dB
REJECTION RATIOS
vs
CASE TEMPERA TURE
Case Temperature – °C
PSRR+
PSRR–
CMMR
RL = 800 Ω
VS = 5 V
0
20
40
60
80
100
120
–70
–60
–50
–40
–30
–20
–10
0
0.1 1 10 100
Output Balance Error – dB
OUTPUT BALANCE ERROR
vs
FREQUENCY
f – Frequency – MHz
PIN = –20 dBm
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
Figure 81 Figure 82
0
10
20
30
40
50
60
0.01 0.1 1 10 100 1000
–150
–120
–90
–60
–30
0
30
Open-Loop Gain – dB
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
f – Frequency – MHz
PIN = –30 dBm
RL = 800 Ω
VS = 5 V
Phase –
Gain
Phase
°
Figure 83
–40–30–20–100 102030405060708090
Open-Loop Gain – dB
OPEN-LOOP GAIN
vs
CASE TEMPERA TURE
Case Temperature – °C
RL = 800 Ω
VS = 5 V
46
47
48
49
50
51
52
53
54
55
56
57
Figure 84
–40–30–20–100 102030405060708090
– Input Bias Current –
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERA TURE
Case Temperature – °C
VS = 5 V
– Input Offset Current –
IIB–
IIB Aµ
IOS Aµ
IIB+
IOS
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
–0.1
–0.09
–0.08
–0.07
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
0
Figure 85
0
5
10
15
20
25
30
35
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS – Supply Voltage – ±V
Quiescent Current – mA
QUIESCENT CURRENT
vs
SUPPLY VOL TAGE
TA = 85°C
TA = 25°C
TA = –40°C
Figure 86
–40–30–20–100 102030405060708090
Case Temperature – °C
– Input Offset Voltage – mV
INPUT OFFSET VOLT AGE
vs
CASE TEMPERA TURE
VOS
VS = 5 V
0
0.5
1
1.5
2
2.5
3
3.5
4
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
19
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 87
–10
0
10
20
30
40
50
60
70
80
90
100
110
–1012345
Input Common-Mode Range – V
CMRR – Common-Mode Rejection Ratio – dB
COMMON-MODE REJECTION RA TIO
vs
INPUT COMMON-MODE RANGE
VS = 5 V
Figure 88
–150
–100
–50
0
50
100
150
–40–30–20–100 102030405060708090
Output Drive – mA
OUTPUT DRIVE
vs
CASE TEMPERA TURE
Case Temperature – °C
VS = 5 V Source
Sink
Figure 89
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
Harmonic Distortion – dBc
HARMONIC DIST ORTION
vs
OUTPUT COMMON-MODE VOL T AGE
VOCM – Output Common-Mode V oltage – V
Single-Ended and
Differential Input
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 8 MHz, VS = 5 V
HD2-Diff
HD2-SE
1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
HD3-SE
and Diff
Figure 90
–3
–2
–1
0
1
2
3
4
0.1 1 10 100 1000
SMALL SIGNAL FREQUENCY RESPONSE
at VOCM
f – Frequency – MHz
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN= –20 dBm
VS = 5 V
Small Signal Frequency Response at VOCM– dB
Figure 91
–800
–600
–400
–200
0
200
400
600
800
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOC – Output Common-Mode Voltage – V
– Output Offset Voltage – mV
OUTPUT OFFSET VOLT AGE
vs
OUTPUT COMMON-MODE VOL T AGE
VOS
Figure 92
0
5
10
15
20
25
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Power-down Voltage – V
Quiescent Current – mA
QUIESCENT CURRENT
vs
POWER-DOWN VOL T AGE
VS = 5 V
Figure 93
–1
–2
–5
0 0.5 1 2
0
100.5101 102 103
–3
–6
–4
0
0.01
0.03
0.02
t – Time – ms
Power-Down V oltage Signal – V
TURNON AND TURNOFF DELAY TIME
Quiescent Current – mA
1.5 2.5 3
Current
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
20
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 94
0
100
200
300
400
500
600
700
800
900
1000
1100
0.1 1 10 100 1000
– Single-Ended Output Impedance
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER DOWN
vs
FREQUENCY
ZOin Power Down –
f – Frequency – MHz
Gain = 1
RL = 400 Ω
Rf = 499 Ω
PIN = –1 dBm
VS = 5 V
Ω
Figure 95
–40–30–20–100 102030405060708090
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERA TURE
Case Temperature – °C
RL = 800 Ω
VS = 5 V
0
100
200
300
400
500
600
700
800
Power-Down Quiescent Current –Aµ
Figure 96
0
100
200
300
400
500
600
700
800
900
1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS – Supply Voltage – V
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOL TAGE
Power-Down Quiescent Current –Aµ
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
21
APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIERS
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems, including immunity to external common-mode
noise, suppression of even-order nonlinearities, and
increased dynamic range. Fully differential amplifiers not
only serve as the primary means of providing gain to a
differential signal chain, but also provide a monolithic
solution for converting single-ended signals into
differential signals for easier, higher performance
processing. The THS4500 family of amplifiers contains
products in Texas Instruments’ expanding line of
high-performance fully differential amplifiers. Information
on fully differential amplifier fundamentals, as well as
implementation specific information, is presented in the
applications section of this data sheet to provide a better
understanding of the operation of the THS4500 family of
devices, and to simplify the design process for designs
using these amplifiers.
Applications Section
DFully Differential Amplifier Terminal Functions
DInput Common-Mode Voltage Range and the
THS4500 Family
DChoosing the Proper Value for the Feedback and
Gain Resistors
DApplication Circuits Using Fully Differential
Amplifiers
DKey Design Considerations for Interfacing to an
Analog-to-Digital Converter
DSetting the Output Common-Mode Voltage With the
VOCM Input
DSaving Power with Power-Down Functionality
DLinearity: Definitions, Terminology, Circuit
Techniques, and Design Tradeoffs
DAn Abbreviated Analysis of Noise in Fully
Differential Amplifiers
DPrinted-Circuit Board Layout Techniques for Optimal
Performance
DPower Dissipation and Thermal Considerations
DPower Supply Decoupling Techniques and
Recommendations
DEvaluation Fixtures, Spice Models, and Applications
Support
DAdditional Reference Material
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
Fully differential amplifiers are typically packaged in
eight-pin packages as shown in the diagram. The device
pins include two inputs (VIN+, VIN–), two outputs (VOUT–,
VOUT+), two power supplies (VS+, VS–), an output
common-mode control pin (VOCM), and an optional
power-down pin (PD).
VIN–1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS–
VOUT–
PD
Fully Differential Amplifier Pin Diagram
A standard configuration for the device is shown in the
figure. The functionality of a fully differential amplifier can
be imagined as two inverting amplifiers that share a
common noninverting terminal (though the voltage is not
necessarily fixed). For more information on the basic
theory of operation for fully differential amplifiers, refer to
the Texas Instruments application note titled Fully
Differential Amplifiers, literature number SLOA054.
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the two
devices. The THS4502 and THS4503 have an input
common-mode range that is centered around midrail, and
the THS4500 and THS4501 have an input common-mode
range that is shifted to include the negative power supply
rail. Selection of one or the other is determined by the
nature of the application. Specifically, the THS4500 and
THS4501 are designed for use in single-supply
applications where the input signal is ground-referenced,
as depicted in Figure 97. The THS4502 and THS4503 are
designed for use in single-supply or split-supply
applications where the input signal is centered between
the power supply voltages, as depicted in Figure 98.
Figure 97
VOCM
+VS
VS
RSRg1
Rg2
Rf1
Rf2
+
–
RT
–
+
Application Circuit for the THS4500 and THS4501,
Featuring Single-Supply Operation With a
Ground-Referenced Input Signal
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
22
Figure 98
VOCM
+VS
VS
RSRg1
Rg2
Rf1
Rf2
+
–
RT
–
+
–VS
Application Circuit for the THS4500 and THS4501,
Featuring Split-Supply Operation With an Input
Signal Referenced at the Midrail
Equations 1–5 allow for calculation of the required input
common-mode range for a given set of input conditions.
The equations allow calculation of the input common-
mode range requirements given information about the
input signal, the output voltage swing, the gain, and the
output common-mode voltage. Calculating the maximum
and minimum voltage required for VN and VP (the
amplifier’s input nodes) determines whether or not the
input common-mode range is violated or not. Four
equations are required. T wo calculate the output voltages
and two calculate the node voltages at VN and VP (note
that only one of these needs calculation, as the amplifier
forces a virtual short between the two nodes).
VOUT)+VIN)(1–β)–VIN–(1–β))2VOCMβ
2β
VOUT–+–VIN)(1–β))VIN–(1–β))2VOCMβ
2
β
(1)
(2)
VN+VIN–(1–β))VOUT)β
Where: β+RG
RF)RG
VP+VIN)(1–β))VOUT–β
(3)
(4)
(5)
NOTE:
The equations denote the device inputs as VN and
VP, and the circuit inputs as VIN+ and VIN–.
Figure 99
VOCM
Rg
Rg
Rf
Rf
+
–
–
+
Vp
Vn
VOUT–
VOUT+
VIN+
VIN–
Diagram For Input Common-Mode Range Equations
The two tables below depict the input common-mode
range requirements for two different input scenarios, an
input referenced around the negative rail and an input
referenced around midrail. The tables highlight the
differing requirements on input common-mode range, and
illustrate reasoning for choosing either the THS4500/1 or
the THS4502/3. For signals referenced around the
negative power supply , the THS4500/1 should be chosen
since its input common-mode range includes the negative
supply rail. For all other situations, the THS4502/3 offers
slightly improved distortion and noise performance for
applications with input signals centered between the
power supply rails.
Table 1. Negative-Rail Referenced
Gain
(V/V) VIN+ (V) VIN–
(V) VIN
(VPP)VOCM
(V) VOD
(VPP)VNMIN
(V) VNMAX
(V)
1–2.0 to
2.0 0 4 2.5 4 0.75 1.75
2–1.0 to
1.0 0 2 2.5 4 0.5 1.167
4–0.5 to
0.5 0 1 2.5 4 0.3 0.7
8–0.25 to
0.25 0 0.5 2.5 4 0.167 0.389
NOTE: This table assumes a negative-rail referenced, single-ended
input signal on a single 5-V supply as shown in Figure 97.
VNMIN = VPMIN and VNMAX = VPMAX.
Table 2. Midrail Referenced
Gain
(V/V) VIN+ (V) VIN–
(V) VIN
(VPP)VOCM
(V) VOD
(VPP)VNMIN
(V) VNMAX
(V)
10.5 to
4.5 2.5 4 2.5 4 2 3
21.5 to
3.5 2.5 2 2.5 4 2.16 2.83
42.0 to
3.0 2.5 1 2.5 4 2.3 2.7
82.25 to
2.75 2.5 0.5 2.5 4 2.389 2.61
NOTE: This table assumes a midrail referenced, single-ended input
signal on a single 5-V supply.
VNMIN = VPMIN and VNMAX = VPMAX.
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
23
CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values in this
section provide the optimum high frequency performance
(lowest distortion, flat frequency response). Since the
THS4500 family of amplifiers is developed with a voltage
feedback architecture, the choice of resistor values does
not have a dominant effect on bandwidth, unlike a current
feedback amplifier. However, resistor choices do have
second-order effects. For optimal performance, the
following feedback resistor values are recommended. In
higher gain configurations (gain greater than two), the
feedback resistor values have much less effect on the high
frequency performance. Example feedback and gain
resistor values are given in the section on basic design
considerations (Table 3).
Amplifier loading, noise, and the flatness of the frequency
response are three design parameters that should be
considered when selecting feedback resistors. Larger
resistor values contribute more noise and can induce
peaking in the ac response in low gain configurations, and
smaller resistor values can load the amplifier more heavily,
resulting in a reduction in distortion performance. In
addition, feedback resistor values, coupled with gain
requirements, determine the value of the gain resistors,
directly impacting the input impedance of the entire circuit.
While there are no strict rules about resistor selection,
these trends can provide qualitative design guidance.
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
Fully dif ferential amplifiers provide designers with a great
deal of flexibility in a wide variety of applications. This
section provides an overview of some common circuit
configurations and gives some design guidelines.
Designing the interface to an ADC, driving lines
differentially, and filtering with fully differential amplifiers
are a few of the circuits that are covered.
BASIC DESIGN CONSIDERATIONS
The circuits in Figures 100 through 104 are used to
highlight basic design considerations for fully differential
amplifier circuit designs.
Table 3. Resistor Values for Balanced Operation
in Various Gain Configurations
Gain ǒVOD
VIN ǓR2 & R4 (Ω)R1 (Ω)R3 (Ω) RT (Ω)
1 392 412 383 54.9
1 499 523 487 53.6
2 392 215 187 60.4
2 1.3k 665 634 52.3
5 1.3k 274 249 56.2
5 3.32k 681 649 52.3
10 1.3k 147 118 64.9
10 6.81k 698 681 52.3
NOTE: Values in the table above assume a 50 Ω source impedance.
VOCM
Vn
VS
RS
R1
RT
R2
R4
–
++
–
Vout+
Vout–
R3
VP
Figure 100
Equations for calculating fully differential amplifier resistor
values in order to obtain balanced operation in the
presence of a 50-Ω source impedance are given in
equations 6 through 9.
RT+1
1
RS–1–K
2(1)K)
R3
K+R2
R1 R2 +R4
R3 +R1 *ǒRs|| RTǓ
(6)
β1+R1
R1 )R2 β2+R3 )RT|| RS
R3 )RT|| RS)R4
VOD
VS+2ǒ1–β2
β1)β2Ǔǒ RT
RT)RSǓ
VOD
VIN +2ǒ1–β2
β1)β2Ǔ
(7)
(8)
(9)
For more detailed information about balance in fully
differential amplifiers, see Fully Differential Amplifiers,
referenced at the end of this data sheet.
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
24
INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
The THS4500 family of amplifiers are designed
specifically to interface to today’s highest-performance
analog-to-digital converters. This section highlights the
key concerns when interfacing to an ADC and provides
example ADC/fully differential amplifier interface circuits.
Key design concerns when interfacing to an
analog-to-digital converter:
DTerminate the input source properly. In high-frequency
receiver chains, the source feeding the fully
differential amplifier requires a specific load
impedance (e.g., 50 Ω).
DDesign a symmetric printed-circuit board layout.
Even-order distortion products are heavily influenced
by layout, and careful attention to a symmetric layout
will minimize these distortion products.
DMinimize inductance in power supply decoupling
traces and components. Poor power supply
decoupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power supply pins.
Thus, decoupling capacitors should be placed in a
manner that minimizes the impedance of the current
loop.
DUse separate analog and digital power supplies and
grounds. Noise (bounce) in the power supplies
(created by digital switching currents) can couple
directly into the signal path, and power supply noise
can create higher distortion products as well.
DUse care when filtering. While an RC low-pass filter
may be desirable on the output of the amplifier to filter
broadband noise, the excess loading can negatively
impact the amplifier linearity . Filtering in the feedback
path does not have this effect.
DAC-coupling allows easier circuit design. If
dc-coupling is required, be aware of the excess power
dissipation that can occur due to level-shifting the
output through the output common-mode voltage
control.
DDo not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop fully
differential amplifiers drive a specific output voltage
regardless of the load impedance present.
Terminating the output of a fully differential amplifier
with a heavy load adversely effects the amplifier’s
linearity.
DComprehend the VOCM input drive requirements.
Determine if the ADC’s voltage reference can provide
the required amount of current to move VOCM to the
desired value. A buffer may be needed.
DDecouple the VOCM pin to eliminate the antenna
effect. VOCM is a high-impedance node that can act as
an antenna. A large decoupling capacitor on this node
eliminates this problem.
DBe cognizant of the input common-mode range. If the
input signal is referenced around the negative power
supply rail (e.g., around ground on a single 5 V
supply), then the THS4500/1 accommodates the
input signal. If the input signal is referenced around
midrail, choose the THS4502/3 for the best operation.
DPackaging makes a dif ference at higher frequencies.
If possible, choose the smaller, thermally enhanced
MSOP package for the best performance. As a rule,
lower junction temperatures provide better
performance. If possible, use a thermally enhanced
package, even if the power dissipation is relatively
small compared to the maximum power dissipation
rating to achieve the best results.
DComprehend the effect of the load impedance seen by
the fully differential amplifier when performing
system-level intercept point calculations. Lighter
loads (such as those presented by an ADC) allow
smaller intercept points to support the same level of
intermodulation distortion performance.
EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at the
output of the data converter. Two representative circuits
shown below highlight single-supply operation and split
supply operation. Specific feedback resistor, gain resistor,
and feedback capacitor values are not specified, as their
values depend on the frequency of interest. Information on
calculating these values can be found in the applications
material above.
Figure 101
+
–+
–
VOCM 12 Bit/80 MSps
IN
IN
5 V
CM
5 V
–5 V
VS
10 µF 0.1 µF
10 µF 0.1 µF
THS4503
Rf
Rf
CF
CF
1 µF
Rg
Rg0.1 µF
RT
RS
ADS5410
Using the THS4503 With the ADS5410
Riso
Riso
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
25
Figure 102
+
–+
–
VOCM 14 Bit/40 MSps
IN
IN
5 V
CM
5 V
VS
10 µF 0.1 µF
THS4501
Rf
Rf
CF
CF
1 µF
Rg
Rg
RT
RS
ADS5421
0.1 µF
Using the THS4501 With the ADS5421
Riso
Riso
FULLY DIFFERENTIAL LINE DRIVERS
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers. Their
high power supply voltage rating (16.5 V absolute
maximum) allows operation on a single 12-V or a single
15-V supply. The high supply voltage, coupled with the
ability to provide differential outputs enables the ability to
drive 26 VPP into reasonably heavy loads (250 Ω or
greater). The circuit in Figure 103 illustrates the THS4500
family of devices used as high speed line drivers. For line
driver applications, close attention must be paid to thermal
design constraints due to the typically high level of power
dissipation.
Figure 103
VOCM
15 V
VS
RSRgRf
Rf
+
–
RT
–
+
Rg
CG
0.1 µF
CG
THS4500/2 VDD
CS
CS
RL
VOD = 26 VPP
Riso
Riso
Fully Differential Line Driver With High Output Swing
FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
Similar to their single-ended counterparts, fully differential
amplifiers have the ability to couple filtering functionality
with voltage gain. Numerous filter topologies can be based
on fully differential amplifiers. Several of these are outlined
in A Differential Circuit Collection, (literature number
SLOA064) referenced at the end of this data sheet. The
circuit below depicts a simple two-pole low-pass filter
applicable to many different types of systems. The first
pole is set by the resistors and capacitors in the feedback
paths, and the second pole is set by the isolation resistors
and the capacitor across the outputs of the isolation
resistors.
Figure 104
VS
RSRg1 Rf1
Rf2
+
–
RT
–
+VO
Riso
C
CF2
CF1
Rg2 Riso
A T wo-Pole, Low-Pass Filter Design Using a Fully
Differential Amplifier With Poles Located at:
P1 = (2πRfCF)–1 in Hz and P2 = (4πRisoC)–1 in Hz
Often times, filters like these are used to eliminate
broadband noise and out-of-band distortion products in
signal acquisition systems. It should be noted that the
increased load placed on the output of the amplifier by the
second low-pass filter has a detrimental effect on the
distortion performance. The preferred method of filtering
is using the feedback network, as the typically smaller
capacitances required at these points in the circuit do not
load the amplifier nearly as heavily in the pass-band.
SETTING THE OUTPUT COMMON-MODE
VOLTAGE WITH THE V OCM INPUT
The output common-mode voltage pin provides a critical
function to the fully differential amplifier; it accepts an input
voltage and reproduces that input voltage as the output
common-mode voltage. In other words, the VOCM input
provides the ability to level-shift the outputs to any voltage
inside the output voltage swing of the amplifier.
A description of the input circuitry of the VOCM pin is shown
below to facilitate an easier understanding of the VOCM
interface requirements. The VOCM pin has two 50-kΩ
resistors between the power supply rails to set the default
output common-mode voltage to midrail. A voltage
applied to the VOCM pin alters the output common-mode
voltage as long as the source has the ability to provide
enough current to overdrive the two 50-kΩ resistors. This
phenomenon is depicted in the VOCM equivalent circuit
diagram. The table contains some representative
examples to aid in determining the current drive
requirement for the VOCM voltage source. This parameter
is especially important when using the reference voltage
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
26
of an analog-to-digital converter to drive VOCM. Output
current drive capabilities differ from part to part, so a
voltage buf fer may be necessary in some applications.
Figure 105
R = 50 kΩ
R = 50 kΩ
VS+
VS–
VOCM
IIN
IIN = 2 VOCM – VS+ – VS–
R
Equivalent Input Circuit for VOCM
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal. As
shown in the equivalent circuit diagram, the VOCM input
has a high impedance associated with it, dictated by the
two 50-kΩ resistors. While the high impedance allows for
relaxed drive requirements, it also allows the pin and any
associated printed-circuit board traces to act as an
antenna. For this reason, a decoupling capacitor is
recommended on this node for the sole purpose of filtering
any high frequency noise that could couple into the signal
path through the VOCM circuitry. A 0.1-µF or 1-µF
capacitance is a reasonable value for eliminating a great
deal of broadband interference, but additional, tuned
decoupling capacitors should be considered if a specific
source of electromagnetic or radio frequency interference
is present elsewhere in the system. Information on the ac
performance (bandwidth, slew rate) of the VOCM circuitry
is included in the specification table and graph section.
Since the VOCM pin provides the ability to set an output
common-mode voltage, the ability for increased power
dissipation exists. While this does not pose a performance
problem for the amplifier, it can cause additional power
dissipation of which the system designer should be aware.
The circuit shown in Figure 106 demonstrates an
example of this phenomenon. For a device operating on
a single 5-V supply with an input signal referenced around
ground and an output common-mode voltage of 2.5 V, a
dc potential exists between the outputs and the inputs of
the device. The amplifier sources current into the
feedback network in order to provide the circuit with the
proper operating point. While there are no serious effects
on the circuit performance, the extra power dissipation
may need to be included in the system’s power budget.
Figure 106
VOCM = 2.5 V
5 V
VS
RSRg1
Rg2
Rf1
Rf2
+
–
RT
–
+RL
2.5-V DC
2.5-V DC
DC Current Path to Ground
DC Current Path to Ground
I2 = VOCM
Rf2 + Rg2
Depiction of DC Power Dissipation Caused By
Output Level-Shifting in a DC-Coupled Circuit
I1 = VOCM
Rf1+ Rg1 + RS || RT
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
The THS4500 family of fully differential amplifiers contains
devices that come with and without the power-down
option. Even-numbered devices have power-down
capability, which is described in detail here.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (i.e. an internal pullup resistor is present), putting
the amplifier in the power-on mode of operation. T o turn off
the amplifier in an effort to conserve power, the
power-down pin can be driven towards the negative rail.
The threshold voltages for power-on and power-down are
relative to the supply rails and given in the specification
tables. Above the enable threshold voltage, the device is
on. Below the disable threshold voltage, the device is off.
Behavior in between these threshold voltages is not
specified.
Note that this power-down functionality is just that; the
amplifier consumes less power in power-down mode. The
power-down mode is not intended to provide a
high-impedance output. In other words, the power-down
functionality is not intended to allow use as a 3-state bus
driver. When in power-down mode, the impedance looking
back into the output of the amplifier is dominated by the
feedback and gain setting resistors.
The time delays associated with turning the device on and
off are specified as the time it takes for the amplifier to
reach 50% of the nominal quiescent current. The time
delays are on the order of microseconds because the
amplifier moves in and out of the linear mode of operation
in these transitions.
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
27
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
The THS4500 family of devices features unprecedented
distortion performance for monolithic fully differential
amplifiers. This section focuses on the fundamentals of
distortion, circuit techniques for reducing nonlinearity,
and methods for equating distortion of fully differential
amplifiers to desired linearity specifications in RF receiver
chains.
Amplifiers are generally thought of as linear devices. In
other words, the output of an amplifier is a linearly scaled
version of the input signal applied to it. In reality , however,
amplifier transfer functions are nonlinear. Minimizing
amplifier nonlinearity is a primary design goal in many
applications.
Intercept points are specifications that have long been
used as key design criteria in the RF communications
world as a metric for the intermodulation distortion
performance of a device in the signal chain (e.g.,
amplifiers, mixers, etc.). Use of the intercept point, rather
than strictly the intermodulation distortion, allows for
simpler system-level calculations. Intercept points, like
noise figures, can be easily cascaded back and forth
through a signal chain to determine the overall receiver
chain’s intermodulation distortion performance. The
relationship between intermodulation distortion and
intercept point is depicted in Figure 107 and Figure 108.
Figure 107
IMD3 = PS – PO
PS
PO
PO
∆fc = fc – f1
∆fc = f2 – fc
PS
fc – 3∆ff1f
cf2 fc + 3∆f
Power
f – Frequency – MHz
Figure 108
IMD3
OIP3
IIP3
3X
PIN
(dBm)
1X
POUT
(dBm)
PO
PS
Due to the intercept point’s ease of use in system level
calculations for receiver chains, it has become the
specification of choice for guiding distortion-related design
decisions. Traditionally, these systems use primarily
class-A, single-ended RF amplifiers as gain blocks. These
RF amplifiers are typically designed to operate in a 50-Ω
environment, just like the rest of the receiver chain. Since
intercept points are given in dBm, this implies an
associated impedance (50 Ω).
However , with a fully dif ferential amplifier, the output does
not require termination as an RF amplifier would. Because
closed-loop amplifiers deliver signals to their outputs
regardless of the impedance present, it is important to
comprehend this when evaluating the intercept point of a
fully differential amplifier . The THS4500 series of devices
yields optimum distortion performance when loaded with
200 Ω to 1 kΩ, very similar to the input impedance of an
analog-to-digital converter over its input frequency band.
As a result, terminating the input of the ADC to 50 Ω can
actually be detrimental to system performance.
This discontinuity between open-loop, class-A amplifiers
and closed-loop, class-AB amplifiers becomes apparent
when comparing the intercept points of the two types of
devices. Equation 10 gives the definition of an intercept
point, relative to the intermodulation distortion.
OIP3+PO)ǒŤIMD3Ť
2Ǔwhere
PO+10 logǒV2
Pdiff
2RL 0.001Ǔ
(10)
(11)
NOTE: Po is the output power of a single tone, RL is the differential load
resistance, and VP(diff) is the differential peak voltage for a
single tone.
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
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28
As can be seen in the equation, when a higher impedance
is used, the same level of intermodulation distortion
performance results in a lower intercept point. Therefore,
it is important to comprehend the impedance seen by the
output of the fully differential amplifier when selecting a
minimum intercept point. The graphic below shows the
relationship between the strict definition of an intercept
point with a normalized, or equivalent, intercept point for
the THS4502.
Figure 109
40
30
20
15 0 102030405060
50
55
f – Frequency – MHz
THIRD-ORDER OUTPUT INTERCEPT POINT
vs
FREQUENCY
60
70 80 90 100
45
35
25
Normalized to 200 Ω
Gain = 1
Rf = 392 Ω
VS = ± 5 V
Tone Spacing = 200 kHz
OIP3 RL= 800 Ω
Normalized to 50 Ω
– Third-Order Output Intercept Point – dBm
OIP3
Comparing specifications between different device types
becomes easier when a common impedance level is
assumed. For this reason, the intercept points on the
THS4500 family of devices are reported normalized to a
50-Ω load impedance.
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
Noise analysis in fully differential amplifiers is analogous
to noise analysis in single-ended amplifiers. The same
concepts apply. Below, a generic circuit diagram
consisting of a voltage source, a termination resistor , two
gain setting resistors, two feedback resistors, and a fully
differential amplifier is shown, including all the relevant
noise sources. From this circuit, the noise factor (F) and
noise figure (NF) are calculated. The figures indicate the
appropriate scaling factor for each of the noise sources in
two different cases. The first case includes the termination
resistor , and the second, simplified case assumes that the
voltage source is properly terminated by the gain-setting
resistors. With these scaling factors, the amplifier’s input
noise power (NA) can be calculated by summing each
individual noise source with its scaling factor. The noise
delivered to the amplifier by the source (NI) and input noise
power are used to calculate the noise factor and noise
figure as shown in equations 23 through 27.
Figure 110. Noise Sources in a Fully
Differential Amplifier Circuit
NiNARgRf
egef
es
Rs
enNo
ini
iii
Rt
et
Ni
Si
No
So
+
–
fully-diff
amp
RgRf
ege
f
ȧ
ȡ
Ȣ
Rg
Rf)
Rg
Rg)RsRt
2ǒRs)RtǓȧ
ȣ
Ȥ
2
(eni)2
(ini)2ȧ
ȧ
ȱ
Ȳ
ȧ
ȡ
Ȣ
Rg
Rf)Rg
Rg)RsRt
2ǒRs)RtǓȧ
ȣ
Ȥ
ȧ
ȧ
ȡ
Ȣ
RfǒRg)RsRt
2ǒRs)RtǓǓ
Rf)Rg)RsRt
2ǒRs)RtǓ
ȧ
ȧ
ȣ
Ȥ
ȧ
ȧ
ȳ
ȴ
2
(iii)2ȧ
ȧ
ȱ
Ȳ
ȧ
ȧ
ȡ
Ȣ
Rg
Rf)Rg
Rg)RsRt
2ǒRs)RtǓȧ
ȧ
ȣ
Ȥ
ȧ
ȧ
ȡ
Ȣ
RfǒRg)RsRt
2ǒRs)RtǓǓ
Rf)Rg)RsRt
2ǒRs)RtǓ
ȧ
ȧ
ȣ
Ȥ
ȧ
ȧ
ȳ
ȴ
2
4kTRtȧ
ȡ
Ȣ
2RsRG
Rs)2Rg
Rt)2RsRg
Rs)2Rgȧ
ȣ
Ȥ
2
4kTRf2 ǒRg
RfǓ2
4kTRg2
ȧ
ȧ
ȡ
Ȣ
Rg
Rg)RsRt
2ǒRs)RtǓȧ
ȧ
ȣ
Ȥ
2
NA: Fully Differential Amplifier
Noise
Source Scale Factor
(12)
(13)
(14)
(15)
(16)
(17)
Figure 111. Scaling Factors for Individual Noise
Sources Assuming a Finite Value Termination
Resistor
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
29
ȧ
ȡ
Ȣ
Rg
Rf)Rg
Rg)Rs
2ȧ
ȣ
Ȥ
2
(eni)2
(ini)2ȧ
ȱ
Ȳ
ȧ
ȡ
Ȣ
Rg
Rf)Rg
Rg)Rs
2ȧ
ȣ
Ȥ
ȧ
ȡ
Ȣ
RfǒRg)Rs
2Ǔ
Rf)Rg)Rs
2ȧ
ȣ
Ȥ
ȧ
ȳ
ȴ
2
(iii)2
2 ǒRg
RfǓ2
4kTRg2
ȧ
ȡ
Ȣ
Rg
Rg)Rs
2ȧ
ȣ
Ȥ
2
NA: Fully Differential Amplifier; termination = 2Rg
Noise
Source Scale Factor
ȧ
ȱ
Ȳ
ȧ
ȡ
Ȣ
Rg
Rf)Rg
Rg)Rs
2ȧ
ȣ
Ȥ
ȧ
ȡ
Ȣ
RfǒRg)Rs
2Ǔ
Rf)Rg)Rs
2ȧ
ȣ
Ȥ
ȧ
ȳ
ȴ
2
4kTRf
Figure 112. Scaling Factors for Individual
Noise Sources Assuming No Termination
Resistance is Used (e.g., RT is open).
(18)
(19)
(20)
(21)
(22)
Ni+4kTRsȧ
ȧ
ȧ
ȧ
ȡ
Ȣ
2RtRg
Rt)2Rg
Rs)2RtRg
Rt)2Rg
ȧ
ȧ
ȧ
ȧ
ȣ
Ȥ
2
(23)
Figure 113. Input Noise With a Termination
Resistor
Ni+4kTRsǒ2Rg
Rs)2RgǓ2(24)
Figure 114. Input Noise Assuming No
Termination Resistor
Noise Factor and Noise Figure Calculations
NA+SǒNoise Source Scale FactorǓ
F+1)NA
NI
NF +10 log (F)
(25)
(26)
(27)
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier-like devices in the THS4500 family requires
careful attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
DMinimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability . To reduce
unwanted capacitance, a window around the signal
I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground
and power planes should be unbroken elsewhere on
the board.
DMinimize the distance (< 0.25”) from the power supply
pins to high frequency 0.1-µF decoupling capacitors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors. Larger
(6.8 µF or more) tantalum decoupling capacitors,
effective at lower frequency, should also be used on
the main supply pins. These may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the PC board. The
primary goal is to minimize the impedance seen in the
dif ferential-current return paths.
DCareful selection and placement of external
components preserve the high frequency
performance of the THS4500 family . Resistors should
be a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
Again, keep their leads and PC board trace length as
short as possible. Never use wirewound type resistors
in a high frequency application. Since the output pin
and inverting input pins are the most sensitive to
parasitic capacitance, always position the feedback
and series output resistors, if any, as close as possible
to the inverting input pins and output pins. Other
network components, such as input termination
resistors, should be placed close to the gain-setting
resistors. Even with a low parasitic capacitance
shunting the external resistors, excessively high
resistor values can create significant time constants
that can degrade performance. Good axial metal-film
or surface-mount resistors have approximately 0.2 pF
in shunt with the resistor. For resistor values > 2.0 kΩ,
this parasitic capacitance can add a pole and/or a zero
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
30
below 400 MHz that can effect circuit operation. Keep
resistor values as low as possible, consistent with
load driving considerations.
DConnections to other wideband devices on the board
may be made with short direct traces or through
onboard transmission lines. For short connections,
consider the trace and the input to the next device as
a lumped capacitive load. Relatively wide traces
(50 mils to 100 mils) should be used, preferably with
ground and power planes opened up around them.
Estimate the total capacitive load and determine if
isolation resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need an RS
since the THS4500 family is nominally compensated
to operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded phase
margin). If a long trace is required, and the 6-dB signal
loss intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is normally not necessary
onboard, and in fact, a higher impedance environment
improves distortion as shown in the distortion versus
load plots. With a characteristic board trace
impedance defined based on board material and trace
dimensions, a matching series resistor into the trace
from the output of the THS4500 family is used as well
as a terminating shunt resistor at the input of the
destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the input
impedance of the destination device: this total
ef fective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only.
T reat the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there is some signal
attenuation due to the voltage divider formed by the
series output into the terminating impedance.
DSocketing a high speed part like the THS4500 family
is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the THS4500 family parts
directly onto the board.
PowerPAD DESIGN CONSIDERATIONS
The THS4500 family is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die
is mounted [see Figure 115(a) and Figure 115(b)]. This
arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see
Figure 115(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good thermal
path away from the thermal pad.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in
combining the small area and ease of assembly of surface
mount with the, heretofore, awkward mechanical methods
of heatsinking.
Figure 115. Views of Thermally Enhanced
Package
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
Although there are many ways to properly heatsink the
PowerPAD package, the following steps illustrate the
recommended approach.
Figure 116. PowerPAD PCB Etch and Via
Pattern
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
Single or Dual
68 Mils x 70 Mils
(V ia diameter = 13mils)
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as shown
in Figure 116. There should be etch for the leads as
well as etch for the thermal pad.
THS4500
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31
2. Place five holes in the area of the thermal pad. These
holes should be 13 mils in diameter . Keep them small
so that solder wicking through the holes is not a
problem during reflow.
3. Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the THS4500
family IC. These additional vias may be larger than the
13-mil diameter vias directly under the thermal pad.
They can be larger because they are not in the thermal
pad area to be soldered so that wicking is not a
problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do
not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
complete connection around the entire circumference
of the plated-through hole.
6. The top-side solder mask should leave the terminals
of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should
cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8. With these preparatory steps in place, the IC is simply
placed in position and run through the solder reflow
operation as any standard surface-mount
component. This results in a part that is properly
installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer must
take care to ensure that the design does not violate the
absolute maximum junction temperature of the device.
Failure may result if the absolute maximum junction
temperature of 150°C is exceeded. For best performance,
design for a maximum junction temperature of 125°C.
Between 125°C and 150°C, damage does not occur, but
the performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
PDmax +Tmax–TA
qJA
Where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
(28)
For systems where heat dissipation is more critical, the
THS4500 family of devices is offered in an 8-pin MSOP
with PowerPAD. The thermal coefficient for the MSOP
PowerPAD package is substantially improved over the
traditional SOIC. Maximum power dissipation levels are
depicted in the graph for the two packages. The data for
the DGN package assumes a board layout that follows the
PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application notes in the
Additional Reference Material section at the end of the
data sheet.
2
1.5
1
0
–40 –20 0 20
– Maximum Power Dissipation – W
2.5
3
3.5
40 60 80
TA – Ambient Temperature – °C
PD
8-Pin DGN Package
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
ΤJ = 150°C, No Airflow
Figure 117. Maximum Power Dissipation vs
Ambient Temperature
0.5
8-Pin D Package
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
not only consider quiescent power dissipation, but also
dynamic power dissipation. Often times, this is difficult to
quantify because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
THS4500
THS4501
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32
DRIVING CAPACITIVE LOADS
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however , the
load capacitance should be isolated by two isolation
resistors in series with the output. The requisite isolation
resistor size depends on the value of the capacitance, but
10 to 25 Ω is a good place to begin the optimization
process. Larger isolation resistors decrease the amount of
peaking in the frequency response induced by the
capacitive load, but this comes at the expense of larger
voltage drop across the resistors, increasing the output
swing requirements of the system.
Figure 118
VS
RSRg
Rf
Rf
+
–
RT–
+
Riso
CL
Rg
Riso = 10 – 25 Ω
VS
–VS
Riso
Use of Isolation Resistors With a Capacitive Load.
POWER SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance (most
notably improved distortion performance). The following
guidelines ensure the highest level of performance.
1. Place decoupling capacitors as close to the power
supply inputs as possible, with the goal of minimizing
the inductance of the path from ground to the power
supply.
2. Placement priority should be as follows: smaller
capacitors should be closer to the device.
3. Use of solid power and ground planes is
recommended to reduce the inductance along power
supply return current paths.
4. Recommended values for power supply decoupling
include 10-µF and 0.1-µF capacitors for each supply.
A 1000-pF capacitor can be used across the supplies
as well for extremely high frequency return currents,
but often is not required.
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
T exas Instruments is committed to providing its customers
with the highest quality of applications support. T o support
this goal, evaluation boards have been developed for the
THS4500 family of fully differential amplifiers. Two
evaluation boards are available; a simple board for easy,
straight-forward evaluation, and a second, more complex
board designed to accommodate most fully differential
filter topologies. These evaluation boards can be obtained
by ordering through the Texas Instruments web site,
www.ti.com, or through your local Texas Instruments sales
representative. Schematics for the two evaluation boards
are shown below with their default component values.
Unpopulated footprints are shown to provide insight into
design flexibility.
Figure 119
_
+
4
5
37
26
VOCM–VS
PwrPad
VSPD
1
8
R0805 R4
C4 C0805
R5 R0805
C3
C0805
R6
R7
R0805
R0805
C5
C6
C0805
C0805
C7
C0805
J2
J3
J2
J3
R2
R0805
R3
R0805
C1
C0805C2
C0805
R1 R1206
J1
3
1
4
5
6
R11
R1206
R9
R0805
R8
R9
R0805
R0805
J2
J3
J4
T1
U1
THS450X
Simplified Schematic of the Evaluation Board. Power
Supply Decoupling, VOCM, and Power Down Circuitry
Not Shown
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the THS4500 family of devices is
available through either the Texas Instruments web site
(www.ti.com) or as one model on a disk from the Texas
Instruments Product Information Center
(1–800–548–6132). The PIC is also available for design
assistance and detailed product information at this
number. These models do a good job of predicting
small-signal ac and transient performance under a wide
variety of operating conditions. They are not intended to
model the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package types in
their small-signal ac performance. Detailed information
about what is and is not modeled is contained in the model
file itself.
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
33
ADDITIONAL REFERENCE MATERIAL
DPowerPAD Made Easy , application brief, Texas Instruments Literature Number SLMA004.
DPowerPAD Thermally Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002.
DKarki, James. Fully Differential Amplifiers. application report, Texas Instruments Literature Number SLOA054D.
DKarki, James. Fully Differential Amplifiers Applications: Line T ermination, Driving High–Speed ADCs, and Differential
Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.
DCarter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature Number
SLOA064.
DCarter , Bruce. Differential Op-Amp Single-Supply Design T echnique, application report, T exas Instruments Literature
Number SLOA072.
DKarki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog Applications
Journal, July 2001.
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
34
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN (4,80)
0.189 0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1 4
8 5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES:A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
35
MECHANICAL DATA
DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
Thermal Pad
(See Note D)
0,15 NOM
Gage Plane
4073271/B 08/01
4,98
0,25
5
3,05 4,78
2,95
8
4
3,05
2,95
1
0,38
0,15
0,05
1,07 MAX
Seating Plane
0,10
0,65 M
0,08
0°–ā6°
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments.
THS4500
THS4501
SLOS350B – APRIL 2002 – REVISED AUGUST 2002
www.ti.com
36
MECHANICAL DATA
DRB (S-PDSO-N8) PLASTIC SMALL OUTLINE
Seating Plane
4203482/B 03/02
1,00
0,80
0,05
Pin 1 Index
Area
Top and Bottom
3,25
0,00
0,08
2,75
2,75
3,25
0,20 REF.
0,25
0,37
0,65
0,45
Exposed Thermal Die Pad
(See Nore D)
1
1,85 MAX
1,59 MAX
0,10
4
85
1,95
Exposed
Metalized
Feature (4x)
8X
8X
0,65
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Small outline no-lead (SON) package configuration.
D. The package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.
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