STK17T88-RF25 - Simtek Corporation

STK17T88

This product conforms to specifications per the

terms of Simtek standard warranty. The product

has completed Simtek internal qualification testing

and has reached production status.

Jan, 2008

Document Control #ML0024 Rev 2.0

FEATURES

• nvSRAM Combined With Integrated Real-Time

Clock Functions (RTC, Watchdog Timer, Clock

Alarm, Power Monitor)

• Capacitor or Battery Backup for RTC

• 25, 45 ns Read Access & R/W Cycle Time

• Unlimited Read/Write Endurance

• Automatic Non-volatile STORE on Power Loss

• Non-Volatile STORE Under Hardware or Soft-

ware Control

• Automatic RECALL to SRAM on Power Up

• Unlimited RECALL Cycles

• 200K STORE Cycles

• 20-Year Non-volatile Data Retention

• Single 3 V +20%, -10% Power Supply

• Commercial and Industrial Temperatures

• 48-pin 300-mil SSOP Package (RoHS-

Compliant)

DESCRIPTION

The Simtek STK17T88 combines a 256Kb non-vola-

tile static RAM (nvSRAM) with a full-featured real-

time clock in a reliable, monolithic integrated circuit.

The 256Kbit nvSRAM is a fast static RAM with a

non-volatile Quantum Trap storage element

included with each memory cell.

The SRAM provides the fast access & cycle times,

ease of use and unlimited read & write endurance of

a normal SRAM. Data transfers automatically to the

non-volatile storage cells when power loss is

detected (the STORE operation). On power up, data

is automatically restored to the SRAM (the RECALL

operation). Both STORE and RECALL operations

are also available under software control.

The real time clock function provides an accurate

clock with leap year tracking and a programmable,

high accuracy oscillator. The Alarm function is pro-

grammable for one-time alarms or periodic minutes,

hours, or days alarms. There is also a programma-

ble watchdog timer for processor control.

32K x 8 AutoStore nvSRAM with Real-Time Clock

ROW DECODER INPUT BUFFERS

COLUMN DEC

COLUMN I/O

POWER

CONTROL

HSB

STORE/

RECALL

CONTROL

SOFTWARE

DETECT A13 – A0

STORE

RECALL

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VCC VCAP

RTC

MUX A14 – A0

INT

VRTCbat

VRTCcap

A11

A12

A13

A14

A0 A1 A2 A3 A4 A10

Quantum Trap

512 X 512

STATIC RAM

ARRAY

512 X 512

BLOCK DIAGRAM

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

Pin Configurations

VSS

A14

A12

DQ0

DQ1

VCC

DQ2

VCAP

A13

A11

A10

DQ7

DQ6

VSS

INT

VCC

HSB

DQ5

DQ3

DQ4

NC NC

VRTCbat VRTCcap

(TOP)

PIN DESCRIPTIONS

Pin Name I/O Description

A14-A0Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array or one of 16 bytes in the clock

DQ7-DQ0I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC

EInput Chip Enable: The active low E input selects the device

WInput Write Enable: The active low W enables data on the DQ pins to be written to the address location selected on

the falling edge of E

GInput Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high

caused the DQ pins to tri-state.

X1Output Crystal Connection, drives crystal on startup

X2Input Crystal Connection for 32.768 kHz crystal

VRTCcap Power Supply Capacitor supplied backup RTC supply voltage (Left unconnected if VRTCbat is used)

VRTCbat Power Supply Battery supplied backup RTC supply voltage (Left unconnected if VRTCcap is used)

VCC Power Supply Power: 3.0V, +20%, -10%

HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the

chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected.

(Connection Optional).

INT Output Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor.

Programmable to either active high (push/pull) or active low (open-drain)

VCAP Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile stor-

age elements.

VSS Power Supply Ground

(Blank) No Connect Unlabeled pins have no internal connections.

48 Pin SSOP

For detailed package size

specifications, see page 27.

SSOP

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.1V

Voltage on Input Relative to VSS. . . . . . . . . . –0.5V to (VCC + 0.5V)

Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)

Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . –55°C to 140°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at con-

ditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rat-

ing conditions for extended periods may affect reliability.

DC CHARACTERISTICS (VCC = 2.7V-3.6V)

Note: The HSB pin has IOUT=-10 µA for VOH of 2.4 V, this parameter is characterized but not tested.

Note: The INT pin is open-drain and does not source or sink high current when Interrupt Register bit D3 is low.

SYMBOL PARAMETER COMMERCIAL INDUSTRIAL UNITS NOTES

MIN MAX MIN MAX

ICC1Average VCC Current

tAVAV = 25ns

tAVAV = 45ns

Dependent on output loading and cycle

rate. Values obtained without output

loads.

ICC2Average VCC Current during STORE

3 3 mA

All Inputs Don’t Care, VCC = max

Average current for duration of STORE

cycle (tSTORE)

ICC3Average VCC Current at tAVAV = 200ns

3V, 25°C, Typical

10 10 mA

W ≥ (V CC

– 0.2V)

All Other Inputs Cycling at CMOS Levels

Dependent on output loading and cycle

rate. Values obtained without output

loads.

ICC4Average VCAP Current during AutoStore

Cycle 3 3 mA

All Inputs Don’t Care

Average current for duration of STORE

cycle (tSTORE)

ISB VCC Standby Current

(Standby, Stable CMOS Levels) 3 3 mA

E ≥ (VCC -0.2V)

All Others VIN≤ 0.2V or ≥ (VCC-0.2V)

Standby current level after nonvolatile

cycle complete

IILK Input Leakage Current ±1±1μAVCC = max

VIN = VSS to VCC

IOLK Off-State Output Leakage Current ±1±1μAVCC = max

VIN = VSS to VCC, E or G ≥ VIH

VIH Input Logic “1” Voltage 2.0 VCC + 0.5 2.0 VCC + 0.5 VAll Inputs

VIL Input Logic “0” Voltage VSS –0.5 0.8 VSS –0.5 0.8 VAll Inputs

VOH Output Logic “1” Voltage 2.4 2.4 V IOUT = – 2mA

VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 4mA

TAOperating Temperature 070 –40 85 °C

VCC Operating Voltage 2.7 3.6 2.7 3.6 V3.0V +20%, -10%

VCAP Storage Capacitance 17 57 17 57 μFBetween VCAP pin and VSS, 5V rated.

NVCNonvolatile STORE operations 200 200 K

DATARData Retention 20 20 Years @ 55 deg C

RF (SSOP- 48) PACKAGE TH ERMAL CHARACTERISTICS

θjc 6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].

ABSOLUTE MAXIMUM RATINGSa

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

BLOCK DIAGRAM

CAPACITANCEb (TA = 25°C, f = 1.0MHz)

Note b: These parameters are guaranteed but not tested.

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V

Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2

SYMBOL PARAMETER MAX UNITS CONDITIONS

CIN Input Capacitance 7 pF ΔV = 0 to 3V

COUT Output Capacitance 7 pF ΔV = 0 to 3V

Figure 1. AC Output Loading Figure 2. AC Output Loading for tristate specs

(THZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ)

577 Ohms

5 pF

789 Ohms

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

577 Ohms

30 pF

789 Ohms

3.0V

INCLUDING

SCOPE AND

OUTPUT

FIXTURE

AC TEST CONDITIONS

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

RTC DC CHARACTERISTICS

Symbol Parameter Commercial Industrial Units Notes

Min Max Min Max

IBAK RTC Backup

Current —300 —350 nA From either VRTCcap or

VRTCbat

VRTCbat RTC Battery Pin

Voltage 1.8 3.3 1.8 3.3 VTypical = 3.0 Volts during

normal operation

VRTCcap RTC Capacitor

Pin Voltage 1.2 2.7 1.2 2.7 VTypical = 2.4 Volts during

normal operation

tOSCS RTC Oscillator

time to start

—10 —10 sec @ MIN Temperature from

Power up or Enable

— 5 — 5 sec @ 25°C from Power up or

Enable

RTC RECOMMENDED COMPONENT CONFIGURATION

Figure 3. RTC COMPONENT CONFIGURATION

Recommended Values

Y1 = 32.768 KHz

= 10M Ohm

= 0 (install cap footprint,

but leave unloaded)

= 56 pF ± 10% (do not vary from this value)

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

SRAM READ CYCLES #1 & #2

Note c: W must be high during SRAM READ cycles.

Note d: Device is continuously selected with E and G both low

Note e: Measured ± 200mV from steady state output voltage.

Note f: HSB must remain high during READ and WRITE cycles.

SRAM READ CYCLE #1: Address Controlledc,d,f

SRAM READ CYCLE #2: E and G Controlleda,f

NO. SYMBOLS PARAMETER STK17T88-25 STK17T88-45 UNITS

#1 #2 Alt. MIN MAX MIN MAX

1 tELQV tACS Chip Enable Access Time 25 45 ns

2 tAVAVctELEHetRC Read Cycle Time 25 45 ns

3 tAVQVdtAVQVftAA Address Access Time 25 45 ns

4 tGLQV tOE Output Enable to Data Valid 12 20 ns

5 tAXQXd tAXQX tOH Output Hold after Address Change 3 3 ns

6 tELQX tLZ Address Change or Chip Enable to

Output Active 3 3 ns

7 tEHQZ tHZ Address Change or Chip Disable to

Output Inactive 10 15 ns

8 tGLQX tOLZ Output Enable to Output Active 0 0 ns

9 tGHQZetOHZ Output Disable to Output Inactive 10 15 ns

10 tELICCLctPA Chip Enable to Power Active 0 0 ns

11 tEHICCHctPS Chip Disable to Power Standby 25 45 ns

DATA VALID

tAXQX

tAVQV

DQ (DATA OUT)

ADDRESS

tAVAV

tELQ X

STAND BY

DATA VALID

tGLQV

DQ (D ATA O UT)

ADDR ESS

ICC

AC TIVE

tELI CC H

tEHI CC L

tEHQ Z

tGLQX

tEL Q V

tGH Q Z

tELEH

tEHAX

tAV Q V

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

SRAM WRITE CYCLES #1 & #2

note g: If W is low when E goes low, the outputs remain in the high-impedance state.

note h: E or W must be ≥ VIH during address transitions.

SRAM WRITE CYCLE #1: W Controlledg,h

SRAM WRITE CYCLE #2: E Controlledg,h

NO. SYMBOLS PARAMETER STK17T88-25 STK17T88-45 UNITS

#1 #2 Alt. MIN MAX MIN MAX

12 tAVAV tAVAV tWC Write Cycle Time 25 45 ns

13 tWLWH tWLEH tWP Write Pulse Width 20 30 ns

14 tELWH tELEH tCW Chip Enable to End of Write 20 30 ns

15 tDVWH tDVEH tDW Data Set-up to End of Write 10 15 ns

16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 ns

17 tAVW H tAVEH tAW Address Set-up to End of Write 20 30 ns

18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 ns

19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 ns

20 tWLQZ, tWZ Write Enable to Output Disable 10 15 ns

21 tWHQX tOW Output Active after End of Write 3 3 ns

PREVIOUS DATA

DATA OUT

ADDRESS

tAVAV

tWHDX

DATA IN

tWHAX

tWLWH

tAVWL

tAVWH

DATA VALID

tWLQZ

tDVWH

HIGH IMPEDANCE

tWHQX

tELWH

DATA IN

tAVAV

tEHDX

tWLEH

tEHAX

tAVEL

tAVEH

DATA VALID

tDVEH

HIGH IMPEDANCE

tELEH

DATA OUT

ADDRESS

DATA IN

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

AutoStore™/POWER-UP RECALL

note i: tHRECALL starts from the time VCC rises above VSWITCH

note j: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place

note k: Industrial Grade Devices require 15 ms MAX.

AutoStore™/POWER-UP RECALL

NO. SYMBOLS PARAMETER STK17T88 UNITS NOTES

Standard Alternate MIN MAX

22 tHRECALL Power-up RECALL Duration 40 ms i

23 tSTORE tHLHZ STORE Cycle Duration 12.5 ms j,k

24 VSWITCH Low Voltage Trigger Level 2.65 V

25 VCCRISE VCC Rise Time 150 μS

POWER-UP RECALL

VCC

tSTORE

tHRECALL

VSWITCH

AutoStore

POWER DOWN

AutoStoreTM

BROWN OUT

AutoStoreTM

POWER-UP

RECALL

Read & Write Inhibited

tVCCRISE

tSTORE

tHRECALL

POWER-UP

RECALL

STORE occurs only if a

SRAM write has

happened.

No STORE occurs

without at least one

SRAM write.

Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

SOFTWARE-CONTROLLED STORE/RECALL CYCLEl,m

note l: The software sequence is clocked on the falling edge of E controlled READs

note m: The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high

during all six consecutive cycles.

SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDm

NO. SYMBOLS PARAMETER STK17T88-35 STK17T88-45 UNITS NOTES

E Cont Alternate MIN MAX MIN MAX

26 tAVAV tRC STORE / RECALL Initiation Cycle Time 25 45 ns m

27 tAVEL tAS Address Set-up Time 0 0 ns

28 tELEH tCW Clock Pulse Width 20 30 ns

29 tEHAX Address Hold Time 1 1 ns

30 tRECALL RECALL Duration 100 100 μs

DQ (DATA)

tAVAV

DATA VALID

ADDRESS ADDRESS #1

HIGH IMPEDENCE

tAVEL

tEHAX

tELEH

tRECALL

tAVAV

ADDRESS #6

tSTORE

DATA VALID

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

HARDWARE STORE CYCLE

Note n: On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete

HARDWARE STORE CYCLE

SYMBOLS PARAMETER STK17T88 UNITS NOTES

Standard Alternate MIN MAX

31 tDELAY tHLQZ Hardware STORE to SRAM Disabled 1 70 μsn

32 tHLHX Hardware STORE Pulse Width 15 ns

HSB (OUT)

HSB (IN)

DQ (DATA OUT)

DELAY

SRAM Enabled

tHLHX

SRAM Enabled

STORE

Soft Sequence Commands

note o: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register

command.

note p: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.

NO. SYMBOLS PARAMETER STK17T88 UNITS NOTES

Standard MIN MAX

33 tSS Soft Sequence Processing Time 70 μso,p

Vcc

tSS

ADDRESS ADDRESS #1

Soft Sequence Command

ADDRESS #6 ADDRESS #1

Soft Sequence Command

ADDRESS #6

tSS

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

MODE SELECTION

E W G A14-A0Mode I/O Power Notes

H X X X Not Selected Output High Z Standby

L H L X Read SRAM Output Data Active

L L X X Write SRAM Input Data Active

LH L

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

Read SRAM

Output Data

Active q,r,s

0x0FC0 Nonvolatile Store Output High Z ICC2

LH L

0x0E38

0x31C7

0x03E0

0x3C1F

0x303F

0x0C63

Read SRAM

Nonvolatile Recall

Output Data

Output High Z

Active q,r,s

note q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile

cycle.

note r: While there are 15 addresses on the STK17T88, only the lower 13 are used to control software modes

note s: I/O state depends on the state of G. The I/O table shown assumes G low

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88 nvSRAM OPERATION

nvSRAM

The STK17T88 nvSRAM is made up of two func-

tional components paired in the same physical cell.

These are the SRAM memory cell and a nonvolatile

QuantumTrap cell. The SRAM memory cell operates

like a standard fast static RAM. Data in the SRAM

can be transferred to the nonvolatile cell (the

STORE operation), or from the nonvolatile cell to

SRAM (the RECALL operation). This unique archi-

tecture allows all cells to be stored and recalled in

parallel. During the STORE and RECALL operations

SRAM READ and WRITE operations are inhibited.

The STK17T88 supports unlimited read and writes

like a typical SRAM. In addition, it provides unlimited

RECALL operations from the nonvolatile cells and

up to 200K STORE operations.

SRAM READ

The STK17T88 performs a READ cycle whenever E

and G are low while W and HSB are high. The

address specified on pins A0-14 determine which of

the 32,768 data bytes will be accessed. When the

READ is initiated by an address transition, the out-

puts will be valid after a delay of tAVQV (READ cycle

#1). If the READ is initiated by E and G, the outputs

will be valid at tELQV or at tGLQV

, whichever is later

(READ cycle #2). The data outputs will repeatedly

respond to address changes within the tAVQV access

time without the need for transitions on any control

input pins, and will remain valid until another

address change or until E or G is brought high, or W

and HSB is brought low.

SRAM WRITE

A WRITE cycle is performed whenever E and W are

low and HSB is high. The address inputs must be sta-

ble prior to entering the WRITE cycle and must

remain stable until either E or W goes high at the

end of the cycle. The data on the common I/O pins

DQ0-7 will be written into memory if it is valid tDVWH

before the end of a W controlled WRITE or tDVEH

before the end of an E controlled WRITE.

It is recommended that G be kept high during the

entire WRITE cycle to avoid data bus contention on

common I/O lines. If G is left low, internal circuitry

will turn off the output buffers tWLQZ after W goes

low.

AutoStore OPERATION

The STK17T88 stores data to nvSRAM using one of

three storage operations. These three operations

are Hardware Store (activated by HSB), Software

Store (activated by an address sequence), and

AutoStore (on power down).

AutoStore operation, a unique feature of Simtek

QuanumTrap technology that is a standard feature

on the STK17T88.

During normal operation, the device will draw cur-

rent from VCC to charge a capacitor connected to

the VCAP pin. This stored charge will be used by the

chip to perform a single STORE operation. If the

voltage on the VCC pin drops below VSWITCH, the

part will automatically disconnect the VCAP pin from

VCC. A STORE operation will be initiated with power

provided by the VCAP capacitor.

Figure 5 shows the proper connection of the storage

capacitor (VCAP) for automatic store operation.

Refer to the DC CHARACTERISTICS table for the

size of the capacitor. The voltage on the VCAP pin is

driven to 5V by a charge pump internal to the chip. A

pull up should be placed on W to hold it inactive dur-

ing power up.

To reduce unneeded nonvolatile stores, AutoStore

and Hardware Store operations will be ignored

unless at least one WRITE operation has taken

place since the most recent STORE or RECALL

cycle. Software initiated STORE cycles are per-

formed regardless of whether a WRITE operation

Figure 4: AutoStore Mode

VCC

VCAP

10k Ohm

0.1µF

VCC

VCAP

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

has taken place. The HSB signal can be monitored

by the system to detect an AutoStore cycle is in

progress.

HARDWARE STORE (HSB) OPERATION

The STK17T88 provides the HSB pin for controlling

and acknowledging the STORE operations. The HSB

pin can be used to request a hardware STORE

cycle. When the HSB pin is driven low, the

STK17T88 will conditionally initiate a STORE opera-

tion after tDELAY

. An actual STORE cycle will only

begin if a WRITE to the SRAM took place since the

last STORE or RECALL cycle. The HSB pin has a

very resistive pullup and is internally driven low to

indicate a busy condition while the STORE (initiated

by any means) is in progress. This pin should be

externally pulled up if it is used to drive other inputs.

SRAM READ and WRITE operations that are in

progress when HSB is driven low by any means are

given time to complete before the STORE operation

is initiated. After HSB goes low, the STK17T88 will

continue to allow SRAM operations for tDELAY

. Dur-

ing tDELAY

, multiple SRAM READ operations may

take place. If a WRITE is in progress when HSB is

pulled low, it will be allowed a time, tDELAY

, to com-

plete. However, any SRAM WRITE cycles

requested after HSB goes low will be inhibited until

HSB returns high.

During any STORE operation, regardless of how it

was initiated, the STK17T88 will continue to drive

the HSB pin low, releasing it only when the STORE is

complete. Upon completion of the STORE opera-

tion, the STK17T88 will remain disabled until the

HSB pin returns high.

If HSB is not used, it should be left unconnected.

HARDWARE RECALL (POWER-UP)

During power up or after any low-power condition

(VCC<VSWITCH), an internal RECALL request will be

latched. When VCC once again exceeds the sense

voltage of VSWITCH, a RECALL cycle will automati-

cally be initiated and will take tHRECALL to complete.

SOFTWARE STORE

Data can be transferred from the SRAM to the non-

volatile memory by a software address sequence.

The STK17T88 software STORE cycle is initiated by

executing sequential E controlled READ cycles from

six specific address locations in exact order. During

the STORE cycle, previous data is erased and then

the new data is programmed into the nonvolatile ele-

ments. Once a STORE cycle is initiated, further

memory inputs and outputs are disabled until the

cycle is completed.

To initiate the software STORE cycle, the following

READ sequence must be performed:

Once the sixth address in the sequence has been

entered, the STORE cycle will commence and the

chip will be disabled. It is important that READ

cycles and not WRITE cycles be used in the

sequence. After the tSTORE cycle time has been ful-

filled, the SRAM will again be activated for READ

and WRITE operation.

SOFTWARE RECALL

Data can be transferred from the nonvolatile mem-

ory to the SRAM by a software address sequence. A

software RECALL cycle is initiated with a sequence

of READ operations in a manner similar to the soft-

ware STORE initiation. To initiate the RECALL

cycle, the following sequence of E controlled READ

operations must be performed:

Internally, RECALL is a two-step procedure. First,

the SRAM data is cleared, and second, the nonvola-

tile information is transferred into the SRAM cells.

After the tRECALL cycle time, the SRAM will once

again be ready for READ or WRITE operations. The

RECALL operation in no way alters the data in the

nonvolatile storage elements.

1 Read Address 0x0E38 Valid READ

2 Read Address 0x31C7 Valid READ

3 Read Address 0x03E0 Valid READ

4 Read Address 0x3C1F Valid READ

5 Read Address 0x303F Valid READ

6 Read Address 0x0FC0 Initiate STORE Cycle

1 Read Address 0x0E38 Valid READ

2 Read Address 0x31C7 Valid READ

3 Read Address 0x03E0 Valid READ

4 Read Address 0x3C1F Valid READ

5 Read Address 0x303F Valid READ

6 Read Address 0x0C63 Initiate RECALL Cycle

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

DATA PROTECTION

The STK17T88 protects data from corruption during

low-voltage conditions by inhibiting all externally

initiated STORE and WRITE operations. The low-

voltage condition is detected when VCC<VSWITCH.

If the STK17T88 is in a WRITE mode (both E and W

low) at power-up, after a RECALL, or after a

STORE, the WRITE will be inhibited until a negative

transition on E or W is detected. This protects

against inadvertent writes during power up or brown

out conditions.

NOISE CONSIDERATIONS

The STK17T88 is a high-speed memory and so

must have a high-frequency bypass capacitor of 0.1

µF connected between both VCC pins and VSS

ground plane with no plane break to chip VSS. Use

leads and traces that are as short as possible. As

with all high-speed CMOS ICs, careful routing of

power, ground, and signals will reduce circuit noise..

PREVENTING AutoStore

Because of the use of nvSRAM to store critical RTC

data, the AutoStore function can not be disabled on

the STK17T88.

BEST PRACTICES

nvSRAM products have been used effectively for

over 15 years. While ease-of-use is one of the prod-

uct’s main system values, experience gained work-

ing with hundreds of applications has resulted in the

following suggestions as best practices:

• The non-volatile cells in an nvSRAM are pro-

grammed on the test floor during final test and

quality assurance. Incoming inspection routines

at customer or contract manufacturer’s sites will

sometimes reprogram these values. Final NV pat-

terns are typically repeating patterns of AA, 55,

00, FF, A5, or 5A. End product’s firmware should

not assume an NV array is in a set programmed

state. Routines that check memory content val-

ues to determine first time system configuration,

cold or warm boot status, etc. should always pro-

gram a unique NV pattern (e.g., complex 4-byte

pattern of 46 E6 49 53 hex or more random

bytes) as part of the final system manufacturing

test to ensure these system routines work consis-

tently.

• Power up boot firmware routines should rewrite

the nvSRAM into the desired state (autostore

enabled, etc.). While the nvSRAM is shipped in a

preset state, best practice is to again rewrite the

nvSRAM into the desired state as a safeguard

against events that might flip the bit inadvertently

(program bugs, incoming inspection routines,

etc.).

• The OSCEN bit in the Calibration register at

0x7FF8 should be set to 1 to preserve battery life

when the system is in storage (see STOPPING

AND STARTING THE RTC OSCILLATOR on

page 16).

• The Vcap value specified in this datasheet

includes a minimum and a maximum value size.

Best practice is to meet this requirement and not

exceed the max Vcap value because the nvSRAM

internal algorithm calculates Vcap charge time

based on this max Vcap value. Customers that

want to use a larger Vcap value to make sure

there is extra store charge and store time should

discuss their Vcap size selection with Simtek to

understand any impact on the Vcap voltage level

at the end of a tRECALL period.

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

LOW AVERAGE ACTIVE POWER

CMOS technology provides the STK17T88 with the

benefit of power supply current that scales with

cycle time. Less current will be drawn as the mem-

ory cycle time becomes longer than 50 ns. Figure 5

shows the relationship between ICC and READ/

WRITE cycle time. Worst-case current consumption

is shown for commercial temperature range,

VCC=3.6V, and chip enable at maximum frequency.

Only standby current is drawn when the chip is dis-

abled. The overall average current drawn by the

STK17T88 depends on the following items:

1. The duty cycle of chip enable.

2. The overall cycle rate for accesses.

3. The ratio of READs to WRITEs.

4. The operating temperature.

5. The VCC level.

6. I/O loading.

Figure 5. Current vs. Cycle Time

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88 REAL TIME CLOCK OPERATION

REAL TIME CLOCK

The clock registers maintain time up to 9,999 years

in one-second increments. The user can set the time

to any calendar time and the clock automatically

keeps track of days of the week and month, leap

years, and century transitions. There are eight regis-

ters dedicated to the clock functions which are used

to set time with a write cycle and to read time during

a read cycle. These registers contain the Time of

Day in BCD format. Bits defined as “0” are currently

not used and are reserved for future use by Simtek.

READING THE CLOCK

The user should halt internal updates to the real time

clock registers before reading clock data to prevent

reading of data in transition. Stopping the internal

Write a “1” to the read bit “R” (in the Flags register at

0x7FF0) to capture the current time in holding regis-

ters. Clock updates do not restart until a “0” is written

to the read bit. The RTC registers can now be read

while the internal clock continues to run.

Within 20ms after a “0” is written to the read bit, all

real time clock registers are simultaneously updated.

SETTING THE CLOCK

Set the write bit “W” (in the Flags register at 0x7FF0)

to a “1” enable the time to be set. The correct day,

date and time can then be written into the real time

clock registers in 24-hour BCD format. The time writ-

ten is referred to as the “Base Time.” This value is

stored in non-volatile registers and used in calcula-

tion of the current time. Reset the write bit to “0” to

transfer the time to the actual clock counters, The

clock will start counting at the new base time.

BACKUP POWER

The RTC is intended to keep time even when system

power is lost. When primary power, VCC, drops

below VSWITCH, the real time clock will switch to the

backup power supply connected to either the VRTC-

cap or VRTCbat pin.

The clock oscillator uses a maximum of 300 nano-

amps at 2 volts to maximize the backup time avail-

able from the backup source.

You can power the real time clock with either a

capacitor or a battery. Factors to be considered

when choosing a backup power source include the

expected duration of power outages and the cost

and reliability trade-off of using a battery versus a

capacitor.

If you select a capacitor power source, connect the

capacitor to the VRTCcap pin and leave the VRTCbat

pin unconnected. Capacitor backup time values

based on maximum current specs are shown below.

Nominal times are approximately 3 times longer.

A capacitor has the obvious advantage of being

more reliable and not containing hazardous materi-

als. The capacitor is recharged every time the power

is turned on so that the real time clock continues to

have the same backup time over years of operation

If you select a battery power source, connect the bat-

tery to the VRTCbat pin and leave the VRTCcap pin

unconnected. A 3V lithium is recommended for this

application. The battery capacity should be chosen

for the total anticipated cumulative down-time

required over the life of the system.

The real time clock is designed with a diode inter-

nally connected to the VRTCbat pin. This prevents the

battery from ever being charged by the circuit.

ST OPPING AND STARTING THE

RTC OSCILLATOR

The OSCEN bit in Calibration register at 0x7FF8

enables RTC oscillator operation. This bit is non-vol-

atile and shipped to customers in the “enabled” state

(set to 0). OSCEN should be set to a 1 to preserve

battery life while the system is in storage. This will

turn off the oscillator circuit extending the battery life.

If the OSCEN bit goes from disabled to enabled, it

will typically take 5 seconds (10 seconds max) for

the oscillator to start.

Capacitor Value Backup Time

0.1 F 72 hours

0.47 F 14 days

1.0 F 30 days

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

The STK17T88 has the ability to detect oscillator

failure due to loss of backup power. The failure is

recorded by the OSCF (Oscillator Failed bit) of the

Flags register (at address 0x7FF0). When the

device is powered on (VCC goes above VSWITCH)

the OSCEN bit is checked for “enabled” status. If the

OSCEN bit is enabled and the oscillator is not active

within 5 ms, the OSCF bit is set. The user should

check for this condition and then write a 0 to clear

the flag. When the OSCF flag bit, the real time clock

registers are reset to the “Base Time” (see the sec-

tion SETTING THE CLOCK on page 16), the value

last written to the real time clock registers.

The value of OSCF should be reset to 0 when the

real time clock registers are written for the first time.

This will initialize the state of this bit since it may

have become set when the system was first pow-

ered on.

To reset OSCF, set the write bit “W” (in the Flags

Flags register. Write a “0” to the OSCF bit and then

reset the write bit to “0” to disable writes.

CALIBRATING THE CLOCK

The RTC is driven by a quartz controlled oscillator

with a nominal frequency of 32.768 KHz. Clock

accuracy will depend on the quality of the crystal

specified (usually 35 ppm at 25 C). This error could

equate to 1.53 minutes gain or loss per month. The

STK17T88 employs a calibration circuit that can

improve the accuracy to +1/-2 ppm at 25 C. The cal-

ibration circuit adds or subtracts counts from the

oscillator divider circuit.

The number of time pulses added or subtracted

depends upon the value loaded into the five calibra-

tion bits found in Calibration register (at 0x7FF8).

Adding counts speeds the clock up; subtracting

counts slows the clock down. The Calibration bits

occupy the five lower order bits of the register.

These bits can be set to represent any value

between 0 and 31 in binary form. Bit D5 is a Sign bit,

where a “1” indicates positive calibration and a “0”

indicates negative calibration. Calibration occurs

during a 64 minute period. The first 62 minutes in the

cycle may, once per minute, have one second either

shortened by 128 or lengthened by 256 oscillator

cycles.

If a binary “1” is loaded into the register, only the first

2 minutes of the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and

so on. Therefore each calibration step has the effect

of adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles. That is

+4.068 or -2.034 ppm of adjustment per calibration

step in the Calibration register.

The calibration register value is determined during

system test by setting the CAL bit in the Flags regis-

ter (at 0x7FF0) to 1. This causes the INT pin to tog-

gle at a nominal 512 Hz. This frequency can be

measured with a frequency counter. Any deviation

measured from the 512 Hz will indicate the degree

and direction of the required correction. For exam-

ple, a reading of 512.01024 Hz would indicate a +20

ppm error, requiring a -10 (001010) to be loaded into

the Calibration register. Note that setting or chang-

ing the calibration register does not affect the fre-

quency test output frequency.

To set or clear CAL, set the write bit “W” (in the Flags

Flags register. Write a value to CAL and then reset

the write bit to “0” to disable writes.

The default Calibration register value from the fac-

tory is 00h. The user calibration value loaded is

retained during a power loss.

ALARM

The alarm function compares a user-programmed

alarm time/date (stored in registers 0x7FF1-5) with

the real time clock time-of-day/date values. When a

match occurs, the alarm flag (AF) is set and an inter-

rupt is generated if the alarm interrupt is enabled.

The alarm flag is automatically reset when the Flags

Each of the alarm registers has a match bit as its

MSB. Setting the match bit to a 1 disables this alarm

match bit is 0, the alarm register is compared with

the equivalent real time clock register. Using the

match bits, an alarm can occur as specifically as one

particular second on one day of the month or as fre-

quently as once per minute.

Note: The product requires the match bit fo r sec-

onds (0x7FF2, bit D7) be set to 0 for proper oper-

ation of the Alarm Flag and Interrupt.

The alarm value should be initialized on power-up by

software since the alarm registers are not non-

volatile.

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

To set or clear the Alarm registers, set the write bit

“W” (in the Flags register at 0x7FF0) to a “1” to

enable writes to the Alarm registers. Write an alarm-

value to the alarm registers and then reset the write

bit to “0” to disable writes.

WATCHDOG TIMER

The watchdog timer is designed to interrupt or reset

the processor should its program get hung in a loop

and not respond in a timely manner. The software

must reload the watchdog timer before it counts

down to zero to prevent this interrupt or reset.

The watchdog timer is a free-running-down counter

that uses the 32Hz clock (31.25 ms) derived from

the crystal oscillator. The watchdog timer function

does not operate unless the oscillator is running.

The watchdog counter is loaded with a starting value

from the load register and then counts down to zero,

setting the watchdog flag (WDF) and generating an

interrupt if the watchdog interrupt is enabled. The

watchdog flag bit is reset when the Flags register is

read. The operating software would normally reload

the counter by setting the watchdog strobe bit

(WDS) to 1 within the timing interval programmed

into the load register.

To use the watchdog timer to reset the processor on

timeout, the INT is tied to processor master reset

and Interrupt register is programmed to 24h to

enable interrupts to pulse the reset pin on timeout.

To load the watchdog timer, set a new value into the

load register by writing a “0” to the watchdog write bit

(WDW) of the watchdog register (at 0x7FF7). Then

load a new value into the load register. Once the

new value is loaded, the watchdog write bit is then

set to 1 to disable watchdog writes. The watchdog

strobe bit (WDS) is set to 1 to load this value into the

watchdog timer. Note: Setting the load register to

zero will disable the watchdog timer function.

The system software should initialize the watchdog

load register on power-up to the desired value since

the register is not non-volatile.

POWER MONITOR

The STK17T88 provides a power monitor function.

The power monitor is based on an internal band-gap

reference circuit that compares the VCC voltage to

VSWITCH.

When the power supply drops below VSWITCH, the

real time clock circuit is switched to the backup sup-

ply (battery or capacitor).

When operating from the backup source, no data

may be read or written and the clock functions are

not available to the user. The clock continues to

operate in the background. Updated clock data is

available to the user tHRECALL delay after VCC has

been restored to the device.

When the power is lost, the PF flag in the Flags reg-

ister is set to indicate the power failure and an inter-

rupt is generated if the power fail interrupt is enabled

(interrupt register=20h). The INT line would normally

be tied to the processor master reset input to per-

form power-off reset.

INTERRUPTS

The STK17T88 has a Flags register, Interrupt regis-

ter, and interrupt logic that can interrupt the micro-

controller or general a power-up master reset signal.

There are three potential interrupt sources: the

watchdog timer, the power monitor, and the clock

alarm. Each can be individually enabled to drive the

INT pin by setting the appropriate bit in the Interrupt

in the Flags register that the host processor can

read to determine the interrupt source. Two bits in

the interrupt register determine the operation of the

INT pin driver.

A functional diagram of the interrupt logic is shown

below.

Figure 6. Interrupt Block Diagram

Watchdog

Timer

Power

Monitor

Clock

Alarm

PFE

VINT

AIE

P/L

H/L

Driver

INT

VCC

WIE

WDF

VSS

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

INTERRUPT REGISTER

Watchdog Interrupt Enable (WIE). When set to 1,

the watchdog timer drives the INT pin when a watch-

dog time-out occurs. When WIE is set to 0, the

watchdog time-out only sets the WDF flag bit.

Alarm Interrupt Enable (AIE). When set to 1, the INT

pin is driven when an alarm match occurs. When set

to 0, the alarm match only sets the AF flag bit.

Power Fail Interrupt Enable (PFE). When set to 1,

the INT pin is driven by a power fail signal from the

power monitor. When set to 0, only the PF flag is set.

High/Low (H/L). When set to a 1, the INT pin is

active high and the driver mode is push-pull. The

INT pin can drive high only when VCC>VSWITCH.

When set to a 0, the INT pin is active low and the

drive mode is open-drain. The active low (open

drain) output is maintained even when power is lost.

Pulse/Level (P/L). When set to a 1, the INT pin is

driven for approximately 200 ms when the interrupt

occurs. The pulse is reset when the Flags register is

read. When P/L is set to a 0, the INT pin is driven

high or low (determined by H/L) until the Flags regis-

ter is read.

The Interrupt register is loaded with the default value

00h at the factory. The user should configure the

Interrupt register to the value desired for their

desired mode of operation. Once configured, the

value is retained during power failures.

FLAGS REGISTER

The Flags register has three flag bits: WDF, AF, and

PF. These flags are set by the watchdog time-out,

alarm match, or power fail monitor respectively. The

processor can either poll this register or enable the

interrupts to be informed when a flag is set. The

flags are automatically reset once the register is

read.

The Flags register is automatically loaded with the

value 00h on power up (with the exception of the

OSCF bit).

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

*A binary value, not a BCD value.

0 - Not implemented, reserved for future use.

Default Settings of non-volatile Calibration and Interrupt registers from factory

Calibration Register=00h

Interrupt Register=00h

The User should configure to the desired value at startup or during operation and the value is then

retained during a power failure.

[ ] designates values shipped from the factory. See STOPPING AND STARTING THE RTC OSCILLA-

TOR on page 16.

RTC REGISTER MAP

D7 D6 D5 D4 D3 D2 D1 D0

0x7FFF 10s Years Years Years: 00-99

0x7FFE 000

10s

Months Months Months: 01-12

0x7FFD 00

10s Day of

Month Day of Month Day of Month: 01-

0x7FFC 0 0 0 0 0 Day of Week Day of week: 01-07

0x7FFB 0 0 10s Hours Hours Hours: 00-23

0x7FFA 0 10s Minutes Minutes Minutes: 00-59

0x7FF9 0 10s Seconds Seconds Seconds: 00-59

0x7FF8 OSCEN

[0] 0Cal

Sign Calibration [00000] Calibration values*

0x7FF7 WDS WDW WDT Watchdog*

0x7FF6 WIE[0] AIE[0] PFE

[0] 0H/L

[1] P/L [0] 0 0 Interrupts*

0x7FF5 M0

10s Alarm

Date Alarm Day Alarm, Day of

Month: 01-31

0x7FF4 M0

10s Alarm

Hours Alarm Hours Alarm, hours: 00-23

0x7FF3 M 10 Alarm Minutes Alarm Minutes Alarm, minutes: 00-

0x7FF2 M 10 Alarm Seconds Alarm Seconds Alarm, seconds:

00-59

0x7FF1 10s Centuries Centuries Centuries: 00-99

0x7FF0 WDF AF PF OSCF 0 CAL[0] W[0] R[0] Flags*

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

0x7FFF Real Time Clock – Years

D7 D6 D5 D4 D3 D2 D1 D0

10s Years Years

Contains the lower two BCD digits of the year. Lower nibble contains the value for

years; upper nibble contains the value for 10s of years. Each nibble operates from 0

to 9. The range for the register is 0-99.

0x7FFE Real Time Clock – Months

D7 D6 D5 D4 D3 D2 D1 D0

000

10s

Month Months

Contains the BCD digits of the month. Lower nibble contains the lower digit and oper-

ates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to

1. The range for the register is 1-12.

0x7FFD Real Time Clock – Date

D7 D6 D5 D4 D3 D2 D1 D0

0 0 10s Day of month Day of month

Contains the BCD digits for the date of the month. Lower nibble contains the lower digit

and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3.

The range for the register is 1-31. Leap years are automatically adjusted for.

0x7FFC Real Time Clock – Day

D7 D6 D5 D4 D3 D2 D1 D0

00000 Day of week

Lower nibble contains a value that correlates to day of the week. Day of the week is a

ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning

to the day value, as the day is not integrated with the date.

0x7FFB Real Time Clock – Hours

D7 D6 D5 D4 D3 D2 D1 D0

0 0 10s Hours Hours

Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower

digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and

operates from 0 to 2. The range for the register is 0-23.

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

0x7FFA Real Time Clock – Minutes

D7 D6 D5 D4 D3 D2 D1 D0

0 10s Minutes Minutes

Contains the BCD value of minutes. Lower nibble contains the lower digit and oper-

ates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to

5. The range for the register is 0-59.

0x7FF9 Real Time Clock – Seconds

D7 D6 D5 D4 D3 D2 D1 D0

0 10s Seconds Seconds

Contains the BCD value of seconds. Lower nibble contains the lower digit and oper-

ates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The

range for the register is 0-59.

0x7FF8 Calibration

D7 D6 D5 D4 D3 D2 D1 D0

OSCEN 0 Calibrat

ion Sign Calibration

OSCEN Oscillator Enable. When set to 1, the oscillator is disabled. When set to 0, the oscillator

is enabled. Disabling the oscillator saves battery/capacitor power during storage.

Calibration

Sign

Determines if the calibration adjustment is applied as an addition to or as a subtraction

from the time-base.

Calibration These five bits control the calibration of the clock.

0x7FF7 Watchdog Timer

D7 D6 D5 D4 D3 D2 D1 D0

WDS WDW WDT

WDS

Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit

is cleared automatically once the watchdog timer is reset. The WDS bit is write only.

Reading it always will return a 0.

WDW

Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out

value (WDT5-WDT0). This allows the user to strobe the watchdog without disturbing

the time-out value. Setting this bit to 0 allows bits 5-0 to be written.

WDT

Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value

in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range or

time-out values is 31.25 ms (a setting of 1) to 2 seconds (setting of 3Fh). Setting the

watchdog timer register to 0 disables the timer. These bits can be written only if the

WDW bit was cleared to 0 on a previous cycle.

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

0x7FF6 Interrupt

D7 D6 D5 D4 D3 D2 D1 D0

WIE AIE PFIE ABE H/L P/L 0 0

WIE

Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the

watchdog timer drives the INT pin as well as setting the WDF flag. When set to 0, the

watchdog time-out only sets the WDF flag.

AIE Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as

setting the AF flag. When set to 0, the alarm match only sets the AF flag.

PFIE Power-Fail Enable. When set to 1, a power failure drives the INT pin as well as setting

the PF flag. When set to 0, a power failure only sets the PF flag.

0 Reserved for Future Use

H/L High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin

is open drain, active low.

P/L

Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an

interrupt source for approximately 200 ms. When set to a 0, the INT pin is driven to an

active level (as set by H/L) until the Flags register is read.

0x7FF5 Alarm – Day

D7 D6 D5 D4 D3 D2 D1 D0

M 0 10s Alarm Date Alarm Date

Contains the alarm value for the date of the month and the mask bit to select or

deselect the date value.

MMatch. Setting this bit to 0 causes the date value to be used in the alarm match. Setting

this bit to 1 causes the match circuit to ignore the date value.

0x7FF4 Alarm – Hours

D7 D6 D5 D4 D3 D2 D1 D0

M 0 10s Alarm Hours Alarm Hours

Contains the alarm value for the hours and the mask bit to select or deselect the hours

value.

MMatch. Setting this bit to 0 causes the hours value to be used in the alarm match.

Setting this bit to 1 causes the match circuit to ignore the hours value.

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

0x7FF3 Alarm – Minutes

D7 D6 D5 D4 D3 D2 D1 D0

M 10s Alarm Minutes Alarm Minutes

Contains the alarm value for the minutes and the mask bit to select or deselect the

minutes value.

MMatch. Setting this bit to 0 causes the minutes value to be used in the alarm match.

Setting this bit to 1 causes the match circuit to ignore the minutes value.

0x7FF2 Alarm – Seconds

D7 D6 D5 D4 D3 D2 D1 D0

M 10s Alarm Seconds Alarm Seconds

Contains the alarm value for the seconds and the mask bit to select or deselect the

seconds’ value.

MMatch. Setting this bit to 0 causes the seconds’ value to be used in the alarm match.

Setting this bit to 1 causes the match circuit to ignore the seconds value.

0x7FF1 Real Time Clock – Centuries

D7 D6 D5 D4 D3 D2 D1 D0

10s Centuries Centuries

Contains the BCD value of Centuries. Lower nibble contains the lower digit and

operates from 0 to 9; upper nibble contains the upper centuries digit and operates from

0 to 9. The range for the register is 0-99 centuries.

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

0x7FF0 Flags

D7 D6 D5 D4 D3 D2 D1 D0

WDF AF PF OSCF 0 CAL W R

WDF

Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed

to reach 0 without being reset by the user. It is cleared to 0 when the Flags register is

read or on power-up

Alarm Flag. This read-only bit is set to 1 when the time and date match the values

stored in the alarm registers with the match bits = 0. It is cleared when the Flags

PF Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail

threshold VSWITCH. It is cleared to 0 when the Flags register is read or on power-up.

OSCF

Oscillator Fail Flag. Set to 1 on power-up only if the oscillator is enabled and not

running in the first 5ms of operation. This indicates that the RTC backup power failed

and the clock value is no longer valid. The user must reset this bit to 0 to clear this

condition.

CAL

Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When

set to 0, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on

power up.

Write Time. Setting the W bit to 1 freezes updates of the RTC registers. The user can

then write to the RTC registers, Alarm registers, Calibration register, Interrupt register

and Flags register. Setting the W bit to 0 disables writes to the registers and causes the

contents of the real time clock registers to be transferred to the timekeeping counters if

the time has changed (a new base time is loaded). The bit defaults to 0 on power up.

Read Time. Setting the R bit to 1 captures the current time in holding registers so that

clock updates are not during the reading process. Set the R bit to 0 to enable the

holding register to resume clock updates. The bit defaults to 0 on power up.

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

Commercial and Industrial Ordering Information

Packing Option

Blank=Tube

TR= Tape & Reel

Temperature Range

Blank= Commercial (0 to 70 C)

I= Industrial (-40 to +85 C)

Access Time

25 = 25ns

45 = 45ns

Lead Finish

F = 100% Sn (Matte Tin) RoHS Compliant

Package

R= Plastic 48-pin 300 mil SSOP

STK17T88 R F 45 I TR

Part Number Description

ccess Times Temperature

STK17T88-RF25 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 25 ns access time Commercial

STK17T88-RF45 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 45 ns access time Commercial

STK17T88-RF25TR 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 25 ns access time Commercial

STK17T88-RF45TR 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 45 ns access time Commercial

STK17T88-RF25I 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 25 ns access time Industrial

STK17T88-RF45I 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 45 ns access time Industrial

STK17T88-RF25ITR 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 25 ns access time Industrial

STK17T88-RF45ITR 3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300 45 ns access time Industrial

Ordering Codes

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

.045 DIA.

TOP VIEW

Pin 1 indicator

0.400

0.410 ()

10.16

10.41

0.292

0.299 ()

7.42

7.59

(11.43)

.045

.055

11.43

13.97

()

8.89

11.43

()

.035

.045

.020

(5.1)

BOTTOM VIEW

)

0.292

0.299 ()

7.42

7.59

(15.75

0.620

0.630 16.00

SEATING

PLANE

SIDE VIEW

0.095

0.110 ()

2.41

2.79

0.008

0.016 ()

0.20

0.41

(15.75

0.620

0.630 16.00)

(0.635)

0.025 (0.203

0.008

0.0135 0.343)

END VIEW PARTING

LINE

GAUGE PLANE

SEATING PLANE

DETAIL A

(0.25)

0.010

0.040 (0.61

0.024

1.02 )

SEE DETAIL

45°

(2.24

0.088

0.092 2.34 )

0.016 (0.25

0.010

0.41 )

END VIEW

DIM = INCHES MIN

MAX

DIM = mm

MIN

MAX

( )

Package Drawing

400 Pin 300 mil SSOP

48 Pin SSOP

Jan, 2008

Document Control #ML0024 Rev 2.0

STK17T88

Document Revision History

Rev Date Change

0.0 February 2003 Publish new data sheet

0.1 March 2003 Remove 525 mil SOIC, add 48 pin SSOP and 40 pin DIP packages. Modified block diagram in

AutoStore description section.

1.0 December 2004

1.1 January 2005 Changed “N” package reference to “R” package.

1.2 April 2005 Changed RTC register unused bits “X” to require zero “0” value when writing values.

1.3 October 2005

Removed plastic dip 32 pin package offering. Package type “W.”

1.4 December 2005

Discontinued 35 ns speed grade option.

Parameter Old Value New Value Notes

Vcap Min 10 μF 17 μF

tVCCRISE NA 150 μs New Spec

ICC1 Max Com. 35 mA 50 mA @ 45 ns access

ICC1 Max Com. 40 mA 55 mA @ 35 ns access

ICC1 Max Com. 50 mA 65 mA @ 25 ns access

ICC1 Max Ind. 35 mA 55 mA @ 45 ns access

ICC1 Max Ind. 45 mA 60 mA @ 35 ns access

ICC1 Max Ind. 55 mA 70 mA @ 25 ns access

ICC1 Max 1.5 mA 3.0 m Com. & Ind.

ICC1 Max 0.5 mA 3 mA Com. & Ind.

tHRECALL 5 ms 20 ms

tSTORE 10 ms 12.5 ms

tRECALL 20 μs 40 μs

tGLQV 10 μs 12 μs @ 25 ns access

Parameter Old

Value New

Value Notes

ICC3 Max Com. 5 mA 10 mA

ICC3 Max Ind. 5 mA 10 mA

ISB Max Com. 2 mA 3 mA

ISB Max Ind. 2 mA 3 mA

tRECALL 40 μa 60 μs Soft Recall

tSTORE 12.5 ms 15 ms Industrial Grade Only

Max STORE Cycles 1x1016 5x105 Contact Simtex for details

tOSCS 1 min 10 sec @ MIN Temperature

tOSCS 10 sec 5 sec @ 25C from Power UP

C1 2.2 pF 0 pF RTC Output Cap

C2 47 pF 56 pF RTC Input Cap

Parameter Old Value New Value Notes

tRECALL 60 μs 100 μs Soft Recall

tSS Undefined 70 μs New Spec

NVC 1 Million 500K Nonvolatile STORE operations

DATAR 100 Years at

Unspecified

Temperature

20 Years at Max

Temperature

Data Retention New

Specification

STK17T88

Jan, 2008

Document Control #ML0024 Rev 2.0

Rev Date Change

1.5 March 2006 Removed Leaded lead finish.

1.6 July 2006

1.7 March 2007 Iout for HSB=-10uA@2.4 Volts

tEHAX, tGHAX specification of 1 ns added

tELAX, tGLAX specification deleted

tDELAY Max specification of 70 us added

tHLBL specification deleted

tSS spec of 70 uS changed from min to max.

ABE Bit Removed From Interrupt Register

Interrupt Register Initializes to 00h

Flag Bits (WDF, AF, PF) Initialize to Zero

W-bit in Flag Register Enables Writes to RTC, Alarm, Calibration, Interrupt, and Flag Registers.

Add Tape & Reel Ordering Option

Add Product Ordering Code Listing

Add Package Drawings

Reformat Entire Document

2.0 January 2008 Page 3: added thermal characteristics.

Page 5: revised recommended value verbiage.

Page 6: in the SRAM Read Cycles #1 and #2 table, revised parameter description for tELQX and

tEHQZ and changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing

diagram and changed title to add G controlled.

Page 9: revised the notes below the Software-Controlled Store/Recall Cycle diagram.

Page 11: in the Mode Selection table, changed column to A14-A0.

Page 12: added Stefan's revised text (italics show revision): "Refer to the DC CHARACTERISTICS

table for the size of the capacitor."

Page 13: under Hardware Store (HSB) Operation, revised first paragraph to read “The HSB pin has

a very resistive pullup...”

Page 14: added best practices section.

Revised RTC register map for registers 0x1FFF8 (D7) and 0x1FFF6 (D7, D6, D5, D3, and D2).

Page 26: added access times column to the Ordering Codes.

Parameter Old

Value New Value Notes

tHRE CALL 20 ms 40 ms Power-up RECALL duration

NVC 500K 200K New Nonvolatile Store Cycle

Spec

DATAR 20 Years

@ 85 C

20 Years @

55 C

New Data Retention Spec

VSWITCH Min 2.55 V No Min. Spec

SIMTEK STK17T88 Datasheet, January 2008

This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form

or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accu-

rate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MER-

CHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a

license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.