1
®
FN3086.6
ICL7136
31/2 Digit LCD, Low Power Display, A/D
Converter with Overrange Recovery
The Intersil ICL7136 is a high performance, low power 31/2
digit, A/D converter. Included are seven segment decoders,
display drivers, a reference, and a clock. The ICL7136 is
designed to interface with a liquid crystal display (LCD) and
includes a multiplexed backplane drive.
The ICL7136 brings together a combination of high
accuracy, versatility, and true economy. It features auto-zero
to less than 10µV, zero drift of less than 1µV/oC, input bias
current of 10pA (Max), and rollover error of less than one
count. True differential inputs and reference are useful in all
systems, but give the designer an uncommon advantage
when measuring load cells, strain gauges and other bridge
type transducers. Finally, the true economy of single power
supply operation, enables a high performance panel meter
to be built with the addition of only 10 passive components
and a display.
The ICL7136 is an improved version of the ICL7126,
eliminating the overrange hangover and hysteresis effects,
and should be used in its place in all applications. It can also
be used as a plug-in replacement for the ICL7106 in a wide
variety of applications, changing only the passive
components.
Features
• First Reading Overrange Recovery in One Conversion
Period
• Guaranteed Zero Reading for 0V Input on All Scales
• True Polarity at Zero for Precise Null Detection
• 1pA Typical Input Current
• True Differential Input and Reference, Direct Display Drive
- LCD ICL7136
• Low Noise - Less Than 15µVP-P
• On Chip Clock and Reference
• No Additional Active Circuits Required
• Low Power - Less Than 1mW
• Surface Mount Package Available
• Drop-In Replacement for ICL7126, No Changes Needed
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
ICL7136CPL 0 to 70 40 Ld PDIP E40.6
ICL7136CPLZ
(Note 1)
0 to 70 40 Ld PDIP
(Pb-free) (Note 2)
E40.6
ICL7136CM44 0 to 70 44 Ld MQFP Q44.10x10
ICL7136CM44Z
(Note 1)
0 to 70 44 Ld MQFP
(Pb-free)
Q44.10x10
ICL7136CM44ZT
(Note 1)
44 Ld MQFP Tape and Reel
(Pb-free)
Q44.10x10
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
2. Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Data Sheet July 21, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN3086.6
July 21, 2005
Pinouts
(PDIP)
TOP VIEW
(MQFP)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
(1000) AB4
(MINUS) POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF+
CREF-
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2 (10’s)
C3
A3
G3
BP/GND
(1’s)
(10’s)
(100’s)
(100’s)
OSC 2
NC
OSC 3
TEST
NC
NC 1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
OSC 1
V+
D1
C1
B1
A1 F1 G1 E1 D2 C2
28
27
26
25
24
23
2221201918
B2 A2 F2 E2 D3
B3
F3
E3
AB4
POL
BP/GND
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
IN HI
IN LO
A-Z
BUFF
INT
V-
NC
G2
C3
A3
G3
REF HI
REF LO
CREF+
CREF-
COMMON
ICL7136
3FN3086.6
July 21, 2005
Absolute Maximum Ratings Thermal Information
Supply Voltage
ICL7136, V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . V+ to V-
Reference Input Voltage (Either Input). . . . . . . . . . . . . . . . . V+ to V-
Clock Input
ICL7136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Thermal Resistance (Typical, Note 2) θJA (°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . .-65oC to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(MQFP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications (Note 3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
SYSTEM PERFORMANCE
Zero Input Reading VIN = 0V, Full Scale = 200mV -000.0 ±000.0 +000.0 Digital
Reading
Ratiometric Reading VlN = VREF, VREF = 100mV 999 999/
1000
1000 Digital
Reading
Rollover Error -VIN = +VlN ≅ 200mV Difference in Reading for Equal Positive
and Negative Inputs Near Full Scale
-±0.2 ±1 Counts
Linearity Full Scale = 200mV or Full Scale = 2V Maximum
Deviation from Best Straight Line Fit (Note 5)
-±0.2 ±1 Counts
Common Mode Rejection Ratio VCM = ±1V, VIN = 0V, Full Scale = 200mV (Note 5) - 50 - µV/V
Noise VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not
Exceeded 95% of Time) (Note 5)
-15-µV
Leakage Current Input VlN = 0V (Note 5) - 1 10 pA
Zero Reading Drift VlN = 0V, 0°C To 70°C (Note 5) - 0.2 1 µV/°C
Scale Factor Temperature Coefficient VIN = 199mV, 0°C To 70°C, (Ext. Ref. 0ppm/×°C) (Note 5) - 1 5 ppm/°C
COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply (With Respect
to + Supply)
2.4 3.0 3.2 V
Temperature Coefficient of Analog
Common
25kΩ Between Common and Positive Supply (With Respect
to + Supply) (Note 5)
- 150 - ppm/°C
SUPPLY CURRENT
V+ Supply Current VIN = 0 (Does Not Include Common Current) 16kHz
Oscillator (Note 6)
- 70 100 µA
DISPLAY DRIVER
Peak-To-Peak Segment Drive Voltage and
Peak-To-Peak Backplane Drive Voltage
V+ to V- = 9V (Note 4) 4 5.5 6 V
NOTES:
3. Unless otherwise noted, specifications apply to the ICL7136 at TA = 25°C, fCLOCK = 48kHz. ICL7136 is tested in the circuit of Figure 1.
4. Back plane drive is in phase with segment drive for “off“ segment, 180 degrees out of phase for “on“ segment. Frequency is 20 times conversion rate.
Average DC component is less than 50mV.
5. Not tested, guaranteed by design.
6. 48kHz oscillator increases current by 20µA (Typ).
ICL7136
4FN3086.6
July 21, 2005
Typical Applications and Test Circuits
FIGURE 1. ICL7136 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF+
CREF-
COM
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
DISPLAY
DISPLAY
C1C2C3
C4
R3
R1
R4C5
+-
IN
R5
R2
ICL7136
C1= 0.1µF
C2= 0.47µF
C3= 0.047µF
C4= 50pF
C5= 0.01µF
R1= 240kΩ
R2= 180kΩ
R3= 180kΩ
R4= 10kΩ
R5= 1MΩ
9V
+
-
ICL7136
5FN3086.6
July 21, 2005
Typical Integrator Amplifier Output Waveform (INT Pin)
Design Information Summary Sheet
• OSCILLATOR FREQUENCY
fOSC = 0.45/RC
COSC > 50pF; ROSC > 50kΩ
fOSC (Typ) = 48kHz
• OSCILLATOR PERIOD
tOSC = RC/0.45
• INTEGRATION CLOCK FREQUENCY
fCLOCK = fOSC/4
• INTEGRATION PERIOD
tINT = 1000 x (4/fOSC)
• 60/50Hz REJECTION CRITERION
tINT/t60Hz or tlNT/t50Hz = Integer
• OPTIMUM INTEGRATION CURRENT
IINT = 1µA
• FULL SCALE ANALOG INPUT VOLTAGE
VlNFS (Typ) = 200mV or 2V
• INTEGRATE RESISTOR
• INTEGRATE CAPACITOR
• INTEGRATOR OUTPUT VOLTAGE SWING
•V
INT MAXIMUM SWING:
(V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V
• DISPLAY COUNT
• CONVERSION CYCLE
tCYC = tCL0CK x 4000
tCYC = tOSC x 16,000
when fOSC = 48kHz; tCYC = 333ms
• COMMON MODE INPUT VOLTAGE
(V- + 1V) < VlN < (V+ - 0.5V)
• AUTO-ZERO CAPACITOR
0.01µF < CAZ < 1µF
• REFERENCE CAPACITOR
0.1µF < CREF < 1µF
•V
COM
Biased between V+ and V-.
•V
COM ≅ V+ - 2.8V
Regulation lost when V+ to V- < ≅6.8V.
If VCOM is externally pulled down to (V + to V -)/2,
the VCOM circuit will turn off.
• POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
Digital supply is generated internally
VTEST ≅ V+ - 4.5V
•DISPLAY:LCD
Type: Direct drive with digital logic supply amplitude.
RINT
VINFS
IINT
-----------------
=
CINT
tINT
()IINT
()
VINT
--------------------------------
=
VINT
tINT
()IINT
()
CINT
--------------------------------
=
COUNT 1000 VIN
VREF
---------------
×=
AUTO ZERO PHASE
(COUNTS)
2999 - 1000
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
DE-INTEGRATE PHASE
0 - 1999 COUNTS
TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC
ICL7136
6FN3086.6
July 21, 2005
Detailed Description
Analog Section
Figure 2 shows the Analog Section for the ICL7136. Each
measurement cycle is divided into four phases. They are (1)
auto-zero (A-Z), (2) signal integrate (INT) and (3) de-
integrate (DE), (4) zero integrate (ZI).
Auto-Zero Phase
During auto-zero three things happen. First, input high and low
are disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor CAZ to compensate
for offset voltages in the buffer amplifier, integrator, and
comparator. Since the comparator is included in the loop, the A-
Z accuracy is limited only by the noise of the system. In any
case, the offset referred to the input is less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
Pin Descriptions
PIN NUMBER
NAME FUNCTION DESCRIPTION40 PIN DIP
44 PIN
FLATPACK
1 8 V+ Supply Power Supply.
2 9 D1 Output Driver Pin for Segment “D” of the display units digit.
3 10 C1 Output Driver Pin for Segment “C” of the display units digit.
4 11 B1 Output Driver Pin for Segment “B” of the display units digit.
5 12 A1 Output Driver Pin for Segment “A” of the display units digit.
6 13 F1 Output Driver Pin for Segment “F” of the display units digit.
7 14 G1 Output Driver Pin for Segment “G” of the display units digit.
8 15 E1 Output Driver Pin for Segment “E” of the display units digit.
9 16 D2 Output Driver Pin for Segment “D” of the display tens digit.
10 17 C2 Output Driver Pin for Segment “C” of the display tens digit.
11 18 B2 Output Driver Pin for Segment “B” of the display tens digit.
12 19 A2 Output Driver Pin for Segment “A” of the display tens digit.
13 20 F2 Output Driver Pin for Segment “F” of the display tens digit.
14 21 E2 Output Driver Pin for Segment “E” of the display tens digit.
15 22 D3 Output Driver pin for segment “D” of the display hundreds digit.
16 23 B3 Output Driver pin for segment “B” of the display hundreds digit.
17 24 F3 Output Driver pin for segment “F” of the display hundreds digit.
18 25 E3 Output Driver pin for segment “E” of the display hundreds digit.
19 26 AB4 Output Driver pin for both “A” and “B” segments of the display thousands digit.
20 27 POL Output Driver pin for the negative sign of the display.
21 28 BP/GND Output Driver pin for the LCD backplane/Power Supply Ground.
22 29 G3 Output Driver pin for segment “G” of the display hundreds digit.
23 30 A3 Output Driver pin for segment “A” of the display hundreds digit.
24 31 C3 Output Driver pin for segment “C” of the display hundreds digit.
25 32 G2 Output Driver pin for segment “G” of the display tens digit.
26 34 V-Supply Negative power supply.
27 35 INT Output Integrator amplifier output. To be connected to integrating capacitor.
28 36 BUFF Output Input buffer amplifier output. To be connected to integrating resistor.
29 37 A-Z Input Integrator amplifier input. To be connected to auto-zero capacitor.
30
31
38
39
IN LO
IN HI
Input Differential inputs. To be connected to input voltage to be measured. LO and HI
designators are for reference and do not imply that LO should be connected to lower
potential, e.g., for negative inputs IN LO has a higher potential than IN HI.
32 40 COMMON Supply/
Output
Internal voltage reference output.
33
34
41
42
CREF-
CREF+
Connection pins for reference capacitor.
35
36
43
44
REF LO
REF HI
Input Input pins for reference voltage to the device. REF HI should be positive reference to
REF LO.
37 3 TEST Input Display test. Turns on all segments when tied to V+.
38
39
40
4
6
7
OSC3
OSC2
OSC1
Output
Output
Input
Device clock generator circuit connection pins.
ICL7136
7FN3086.6
July 21, 2005
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range: up to 1V from either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog
COMMON to establish the correct common mode voltage. At
the end of this phase, the polarity of the integrated signal is
determined.
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
.
Zero Integrator Phase
The final phase is zero integrator. First, input low is shorted to
analog COMMON. Second, the reference capacitor is charged
to the reference voltage. Finally, a feedback loop is closed
around the system to IN HI to cause the integrator output to
return to zero. Under normal conditions, this phase lasts for
between 11 to 140 clock pulses, but after a “heavy” overrange
conversion, it is extended to 740 clock pulses.
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
0.5V below the positive supply to 1V above the negative supply.
In this range, the system has a CMRR of 86dB typical.
However, care must be exercised to assure the integrator
output does not saturate. A worst case condition would be a
large positive common mode voltage with a near full scale
negative differential input voltage. The negative input signal
drives the integrator positive when most of its swing has been
used up by the positive common mode voltage. For these
critical applications the integrator output swing can be reduced
to less than the recommended 2V full scale swing with little loss
of accuracy. The integrator output can swing to within 0.3V of
either supply without loss of linearity.
Differential Reference
The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray
capacity on its nodes. If there is a large common mode
voltage, the reference capacitor can gain charge (increase
voltage) when called up to de-integrate a positive signal but
lose charge (decrease voltage) when called up to de-
integrate a negative input signal. This difference in reference
for positive or negative input voltage will give a roll-over
error. However, by selecting the reference capacitor such
that it is large enough in comparison to the stray
capacitance, this error can be held to less than 0.5 count
worst case. (See Component Value Selection.)
DISPLAY READING = 1000 VIN
VREF
---------------
DE-DE+
CINT
CAZ
RINT
BUFFER A-Z INT
-
+
A-Z
COMPARATOR
IN HI
COMMON
IN LO
31
32
30
DE- DE+
INT
A-Z
34
CREF+
36
REF HI
CREF
REF LO
35
A-Z, A-Z,
33
CREF-
28 29 27
TO
DIGITAL
SECTION
A-Z AND DE(±)
INTEGRATOR
INT
STRAY STRAY
V+
10µA
V-
N
INPUT
HIGH
2.8V
6.2V
V+
1
INPUT
LOW
-
+
-
+
-
+
ZI ZI
AND ZI
ZI
26
FIGURE 2. ANALOG SECTION OF ICL7136
ICL7136
8FN3086.6
July 21, 2005
Analog COMMON
This pin is included primarily to set the common mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 2.8V
more negative than the positive supply. This is selected to
give a minimum end-of-life battery voltage of about 6.8V.
However, analog COMMON has some of the attributes of a
reference voltage. When the total supply voltage is large
enough to cause the zener to regulate (>7V), the COMMON
voltage will have a low voltage coefficient (0.001%/V), low
output impedance (≅15Ω), and a temperature coefficient
typically less than 150ppm/oC.
The limitations of the on chip reference should also be
recognized, however. Due to their higher thermal resistance,
plastic parts are poorer in this respect than ceramic. The
combination of reference Temperature Coefficient (TC), internal
chip dissipation, and package thermal resistance can increase
noise near full scale from 25µV to 80µVP-P. Also the linearity in
going from a high dissipation count such as 1000 (20 segments
on) to a low dissipation count such as 1111 (8 segments on) can
suffer by a count or more. Devices with a positive TC reference
may require several counts to pull out of an over range
condition. This is because over-range is a low dissipation
mode, with the three least significant digits blanked. Similarly,
units with a negative TC may cycle between over range and a
non-over range count as the die alternately heats and cools. All
these problems are of course eliminated if an external
reference is used.
The ICL7136, with its negligible dissipation, suffers from
none of these problems. In either case, an external
reference can easily be added, as shown in Figure 3.
Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If
reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.
Within the lC, analog COMMON is tied to an N-Channel FET
that can sink approximately 3mA of current to hold the
voltage 2.8V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
10µA of source current, so COMMON may easily be tied to a
more negative voltage thus overriding the internal reference.
TEST
The TEST pin serves two functions. On the ICL7136 it is
coupled to the internally generated digital supply through a
500Ω resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other presentation the user may want to include on
the LCD display. Figures 4 and 5 show such an application.
No more than a 1mA load should be applied.
The second function is a “lamp test”. When TEST is pulled
high (to V+) all segments will be turned on and the display
should read “-1888”. The TEST pin will sink about 5mA
under these conditions.
CAUTION: On the ICL7136, in the lamp test mode, the segments have a
constant DC voltage (no square-wave) and may burn the LCD
display if left in this mode for several minutes.
ICL7136
V
REF LO
REF HI
V+
V-
6.8V
ZENER
IZ
FIGURE 3A.
ICL7136
V
REF HI
REF LO
COMMON
V+
ICL8069
1.2V
REFERENCE
6.8kΩ
20kΩ
FIGURE 3B.
FIGURE 3. USING AN EXTERNAL REFERENCE
ICL7136
V+
BP
TEST
21
37 TO LCD
BACKPLANE
TO LCD
DECIMAL
POINT
1MΩ
FIGURE 4. SIMPLE INVERTER FOR FIXED DECIMAL POINT
ICL7136
9FN3086.6
July 21, 2005
Digital Section
Figures 6 shows the digital section for the ICL7136. In the
ICL7136, an internal digital ground is generated from a 6V
Zener diode and a large P-Channel source follower. This
supply is made stiff to absorb the relatively large capacitive
currents when the back plane (BP) voltage is switched. The
BP frequency is the clock frequency divided by 800. For
three readings/second this is a 60Hz square wave with a
nominal amplitude of 5V. The segments are driven at the
same frequency and amplitude and are in phase with BP
when OFF, but out of phase when ON. In all cases negligible
DC voltage exists across the segments.
The polarity indication is “on” for negative analog inputs. If IN
LO and IN HI are reversed, this indication can be reversed
also, if desired.
ICL7136
V+
BP
TEST
DECIMAL
POINT
SELECT
CD4030
GND
V+
TO LCD
DECIMAL
POINTS
FIGURE 5. EXCLUSIVE “OR” GATE FOR DECIMAL POINT DRIVE
FIGURE 6. ICL7136 DIGITAL SECTION
7
SEGMENT
DECODE
LCD PHASE DRIVER
LATCH
7
SEGMENT
DECODE ÷200
LOGIC CONTROL
INTERNAL VTH = 1V
7
SEGMENT
DECODE
1000’s 100’s 10’s 1’s
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
DIGITAL
GROUND
÷4
CLOCK
40 39 38
OSC 1 OSC 2 OSC 3
BACKPLANE
21
V+
TEST
V-
500Ω
37
26
6.2V
COUNTER COUNTER COUNTER COUNTER
1
†
† THREE INVERTERS
ONLY ONE INVERTER SHOWN
FOR CLARITY
SEGMENT
OUTPUT
0.5mA
2mA
INTERNAL DIGITAL GROUND
TYPICAL SEGMENT OUTPUT
V+
c
a
b
c
d
f
g
e
a
b
a
b
c
d
f
g
e
a
b
c
d
f
g
e
ICL7136
10 FN3086.6
July 21, 2005
System Timing
Figure 7 shows the clocking arrangement used in the
ICL7136. Two basic clocking arrangements can be used:
1. Figure 9A, an external oscillator connected to DIP pin 40.
2. Figure 9B, an R-C oscillator using all three pins.
The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate
(1000 counts), reference de-integrate (0 to 2000 counts) and
auto-zero (1000 to 3000 counts). For signals less than full
scale, auto-zero gets the unused portion of reference de-
integrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of 48kHz
would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 331/3kHz, etc., should be selected. For 50Hz
rejection, Oscillator frequencies of 200kHz, 100kHz,
662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that
40kHz (2.5 readings/sec.) will reject both 50Hz and 60Hz
(also 400Hz and 440Hz).
Component Value Selection
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100µA of quiescent current. They can
supply 1µA of drive current with negligible nonlinearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full scale, 1.8MΩ is near optimum and
similarly a 180kΩ for a 200mV scale.
Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance buildup will
not saturate the integrator swing (approximately 0.3V from
either supply). In the ICL7136, when the analog COMMON
is used as a reference, a nominal +2V full-scale integrator
swing is fine. For three readings/second (48kHz clock)
nominal values for ClNT are 0.047µF and 0.5µF,
respectively. Of course, if different oscillator frequencies are
used, these values should be changed in inverse proportion
to maintain the same output swing.
An additional requirement of the integrating capacitor is that
it must have a low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for this
application, polypropylene capacitors give undetectable
errors at reasonable cost.
Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence on
the noise of the system. For 200mV full scale where noise is
very important, a 0.47µF capacitor is recommended. On the
2V scale, a 0.047µF capacitor increases the speed of
recovery from overload and is adequate for noise on this
scale.
Reference Capacitor
A 0.1µF capacitor gives good results in most applications.
However, where a large common mode voltage exists (i.e.,
the REF LO pin is not at analog COMMON) and a 200mV
scale is used, a larger value is required to prevent roll-over
error. Generally 1µF will hold the roll-over error to 0.5 count
in this instance.
Oscillator Components
For all ranges of frequency a 180kΩ resistor is
recommended and the capacitor is selected from the
equation:
CLOCK
INTERNAL TO PART
40 39 38
³4
TEST
CLOCK
INTERNAL TO PART
40 39 38
³4
RC
FIGURE 7B. RC OSCILLATOR
FIGURE 7. CLOCK CIRCUITS
FIGURE 7A. EXTERNAL OSCILLATOR
f0.45
RC
-------------For 48kHz Clock (3 Readings/s.),=
C50pF.=
ICL7136
11 FN3086.6
July 21, 2005
Reference Voltage
The analog input required to generate full scale output (2000
counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale,
VREF should equal 100mV and 1V, respectively. However, in
many applications where the A/D is connected to a
transducer, there will exist a scale factor other than unity
between the input voltage and the digital reading. For
instance, in a weighing system, the designer might like to
have a full scale reading when the voltage from the
transducer is 0.662V. Instead of dividing the input down to
200mV, the designer should use the input voltage directly
and select VREF = 0.341V. Suitable values for integrating
resistor and capacitor would be 330kΩ and 0.047µF. This
makes the system slightly quieter and also avoids a divider
network on the input. Another advantage of this system
occurs when a digital reading of zero is desired for VIN ≠ 0.
Temperature and weighing systems with a variable fare are
examples. This offset reading can be conveniently
generated by connecting the voltage transducer between
IN HI and COMMON and the variable (or fixed) offset
voltage between COMMON and IN LO.
Typical Applications
The ICL7136 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility
of these A/D converters.
The following application notes contain very useful
information on understanding and applying this part and are
available from Intersil.
Application Notes
NOTE # DESCRIPTION
AN016 “Selecting A/D Converters”
AN017 “The Integrating A/D Converter”
AN018 “Do’s and Don’ts of Applying A/D Converters”
AN023 “Low Cost Digital Panel Meter Designs”
AN032 “Understanding the Auto-Zero and Common Mode
Performance of the ICL7136/7/9 Family”
AN046 “Building a Battery-Operated Auto Ranging DVM with
the ICL7106”
AN052 “Tips for Using Single Chip 31/2 Digit A/D Converters”
FIGURE 8. ICL7136 USING THE INTERNAL REFERENCE FIGURE 9. RECOMMENDED COMPONENT VALUES FOR 2V
FULL SCALE
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP
50pF
TO PIN 1
SET VREF
= 100mV
0.1µF
0.01µF
1MΩ
180kΩ
20kΩ240kΩ
IN
+
-
9V
180kΩ
0.047µF
0.47µF
TO BACKPLANE
TO DISPLAY
Values shown are for 200mV full scale, 3 readings/sec., floating
supply voltage (9V battery).
+
-28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP/GND
50pF
TO PIN 1
SET VREF
= 100mV
0.1µF
0.01µF
1MΩ
180kΩ
250kΩ240kΩ
IN
+
-
1.8M
0.047µF
0.01µF
TO DISPLAY
V+
V-
ICL7136
12 FN3086.6
July 21, 2005
FIGURE 10. ICL7136 USED AS A DIGITAL CENTIGRADE
THERMOMETER FIGURE 11. CIRCUIT FOR DEVELOPING UNDERRANGE AND
OVERRANGE SIGNAL FROM ICL7136 OUTPUTS
FIGURE 12. AC TO DC CONVERTER WITH ICL7136
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP
50pF
TO PIN 1
0.1µF
0.01µF
†
100kΩ1MΩ
9V
390kΩ
†
0.47µF
TO BACKPLANE
TO DISPLAY
A silicon diode-connected transistor has a temperature coefficient
of about -2mV/oC. Calibration is achieved by placing the sensing
transistor in ice water and adjusting the zeroing potentiometer for a
000.0 reading. The sensor should then be placed in boiling water
and the scale-f act or p ote nt iome ter adju s te d f or a 1 00. 0 re ad in g.
† Value depends on clock frequency.
SCALE
FACTOR
ADJUST
200kΩ470kΩ
22kΩ
SILICON NPN
MPS 3704 OR
SIMILAR
ZERO
ADJUST
+
-13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
O /RANGE
U /RANGE
CD4023 OR
74C10 CD4077
TO LOGIC
VCC
V+
TO
LOGIC
V-
GND
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
CREF
CREF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP
50pF
TO PIN 1
0.1µF
180kΩ
20kΩ220kΩ
180kΩ
0.047µF
0.47µF
TO BACKPLANE
TO DISPLAY
Test is used as a common-mode reference level to ensure compatibility with most op amps.
10µF
9V
10µF
470kΩ
1µF
4.3kΩ
100pF
(FOR OPTIMUM
BANDWIDTH)
1µF
10kΩ10kΩ
1N914
1µF
0.22µF
5µFCA3140
2.2MΩ
+
-
100kΩ
AC IN
SCALE FACTOR ADJUST
(VREF = 100mV FOR AC TO RMS)
+
-
ICL7136
13 FN3086.6
July 21, 2005
Die Characteristics
DIE DIMENSIONS:
127 mils x 149 mils
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
PASSIVATION:
Type: PSG Nitride
Thickness: 15kÅ ±3kÅ
Metallization Mask Layout
ICL7136
A2
(12)
(37) TEST
(39) OSC 2
(40) OSC 1
(2) D1
(4) B1
(27)
INT
(28)
BUFF
(33)
CREF-
A1
(5)
F1
(6)
G1
(7)
E1
(8)
D2
(9)
C2
(10)
B2
(11)
F2
(13)
E2
(14)
B3 (16)
D3 (15)
F3 (17)
E3 (18)
AB4 (19)
POL (20)
BP/GND (21)
G3 (22)
A3 (23)
C3 (24)
G2 (25)
V- (26)
(29)
A/Z
(30)
IN LO
(31)
IN HI
(32)
COMM
(34)
CREF+
(35)
REF
(36)
REF
LO HI
(38) OSC 3
(1) V+
(3) C1
ICL7136
14 FN3086.6
July 21, 2005
ICL7136
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E40.6 (JEDEC MS-011-AC ISSUE B)
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.250 -6.35 4
A1 0.015 -0.39 -4
A2 0.125 0.195 3.18 4.95 -
B0.014 0.022 0.356 0.558 -
B1 0.030 0.070 0.77 1.77 8
C0.008 0.015 0.204 0.381 -
D1.980 2.095 50.3 53.2 5
D1 0.005 -0.13 -5
E0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC -
eA0.600 BSC 15.24 BSC 6
eB-0.700 -17.78 7
L0.115 0.200 2.93 5.08 4
N40 409
Rev. 0 12/93
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3086.6
July 21, 2005
ICL7136
Metric Plastic Quad Flatpack Packages (MQFP)
D
D1
EE1
-A-
PIN 1
A2 A1
A
12o-16o
12o-16o
0o-7o
0.40
0.016 MIN
L
0o MIN
PLANE
b
0.005/0.009
0.13/0.23
WITH PLATING
BASE METAL
SEATING
0.005/0.007
0.13/0.17
b1
-B-
e
0.008
0.20 A-B SD SCM
0.076
0.003
-C-
-D-
-H-
Q44.10x10 (JEDEC MS-022AB ISSUE B)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.096 -2.45 -
A1 0.004 0.010 0.10 0.25 -
A2 0.077 0.083 1.95 2.10 -
b0.012 0.018 0.30 0.45 6
b1 0.012 0.016 0.30 0.40 -
D0.515 0.524 13.08 13.32 3
D1 0.389 0.399 9.88 10.12 4, 5
E0.516 0.523 13.10 13.30 3
E1 0.390 0.398 9.90 10.10 4, 5
L0.029 0.040 0.73 1.03 -
N44 447
e 0.032 BSC 0.80 BSC -
Rev. 2 4/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane .
4. Dimensions D1 and E1 to be determined at datum plane
.
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
-C-
-H-
