LMP7312
LMP7312 Precision SPI-Programmable AFE with Differential/Single-Ended
Input/Output
Literature Number: SNOSB32A
LMP7312
June 18, 2010
Precision SPI-Programmable AFE with Differential/Single-
Ended Input/Output
General Description
The LMP7312 is a digitally programmable variable gain am-
plifier/attenuator. Its wide input voltage range and superior
precision make it a prime choice for applications requiring
high accuracy such as data acquisition systems for IO mod-
ules in programmable logic control (PLC). The LMP7312
provides a differential output to maximize dynamic range and
signal to noise ratio, thereby reducing the overall system er-
ror. It can also be configured to handle single ended input data
converters by means of the VOCM pin (see application section
for details). The inputs of LMP7312 can be configured in at-
tenuation mode to handle large input signals of up to +/- 15V,
as well as in amplification mode to handle current loops of
0-20mA and 4-20mA.The LMP7312 is equipped with a null
switch to evaluate the offset of the internal amplifier. A guar-
anteed 0.035% maximum gain error (for all gains) and a
maximum gain drift of 5ppm over the extended industrial tem-
perature range (-40° to 125°C) make the LMP7312 very
attractive for high precision systems even under harsh con-
ditions. A low input offset voltage of 100µV and low voltage
noise of 3µVpp give the LMP7312 a superior performance.
The LMP7312 is fully specified from -40° to 125°C and is
available in SOIC-14 package.
Features
Typical Values, TA = 25°C, V+=5V, V-=0V.
■Gain bandwidth 1 MHz
■Input voltage range (G= 0.096 V/V) -15V to +15V
■Core op-amp input offset voltage 100 µV (max)
■Supply current 2 mA (max)
■Gain (Attenuation Mode) 0.096 V/V, 0.192 V/V
0.384 V/V, 0.768 V/V
■Gain (AmplificationMode) 1 V/V, 2 V/V
■Gain Error 0.035% (max)
■Core op-amp PSRR 90 dB (min)
■CMRR 80 dB (min)
■Adjustable output common mode 1V to 4V
■Temperature range −40 to 125°C
■Package 14-Pin SOIC
Applications
■Signal conditioning AFE
±10V; ±5V; 0-5V; 0-10V; 0-20mA; 4-20mA
■Data Acquisition systems
■Motor control
■Instrument and process control
■Remote sensing
■Programmable automation control
Typical Application
30075513
LMP™ is a trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation 300755 www.national.com
LMP7312 Precision SPI-Programmable AFE with Differential/Single-Ended Input/Output
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Rating (Note 2)
Human Body Model 2000V
Machine Body Model 150V
Charge device Model 1000V
Analog Supply Voltage (VS = V+ - V-)6V
DigitaI Supply Voltage (VDIO=VIO-V-)6V
Attenuation pins -VIN, +VIN referred to V-±17.5V
Amplification pins -IN, +IN referred to V-±10V
Voltage at all other pins referred to V-6V
Storage Temperature Range -65°C to 150°C
For soldering specification:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
Junction Temperature 150°C
Operating Ratings (Note 1)
Analog Supply Voltage (VS = V+ – V-), V-
=0V 4.5V to 5.5V
Digital Supply Voltage (VDIO = VIO– V-),
V-=0V 2.7V to 5.5V
Attenuation pins -VIN, +VIN referred to V--15V to 15V
Amplification pins -IN, +IN referred to V--2.35V to 7.35V
Temperature Range (Note 3) −40°C to 125°C
Package Thermal Resistance (Note 3)
SOIC-14 145°C/W
5V Electrical Characteristics (Note 4)
Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 5V, VIO = 5V, V− = 0V, G = 0.192 V/V,
VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. Differential output configuration. SE = Single Ended Output,
DE = Differential Output. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)Units
VOS Core op-amp Input
Offset Voltage
Nulling Switch Mode, DE, VOCM = 1V;
Nulling switch Mode, SE, -VOUT/VR = 1V
–100
–250
100
250
µV
Nulling Switch Mode, DE, VOCM = 4V;
Nulling Switch Mode, SE, -VOUT/VR = 4V
–100
–250
100
250
TCVOS Core op-amp Input
Offset Voltage
(Note 7)
Nulling Switch Mode, DE, VOCM = 1V;
Nulling Switch Mode, SE, -VOUT/VR = 1V
-3 ±1.5 3
µV/°C
Nulling Switch Mode, DE, VOCM = 4V;
Nulling Switch Mode, SE, -VOUT/VR = 4V
-3 ±1.5 3
Av Gain Error All gains, RL = 10 kΩ, CL = 50pF, SE / DE –0.035
–0.045
0.035
0.045 %
Gain Drift SE / DE -5 ±1 5 ppm/°C
enCore op-amp Voltage
Noise Density
RTI, Nulling Switch Mode, f = 10 kHz 7.25 nV/
Core op-amp Peak to
Peak Voltage Noise
RTI, Nulling Switch Mode, f= 0.1Hz to 10Hz 3 µVPP
IVA Analog Supply Current +VIN = −VIN = VOCM 2mA
IVIO Digital Supply Current Without any load connected to SDO pin 120 μA
RIN_CM CM Input Resistance G= 0.192 V/V 62.08 kΩ
G= 1 V/V 40
RIN_DIFF Differential Input
Resistance
G= 0.192 V/V 248.3 kΩ
G= 1 V/V 160
CMRR DC Common Mode
Rejection Ratio
G= 0.096V/V, -15V < VCM_ATT < 15V, SE / DE
80
77
dB
G= 0.192V/V, -11.4V < VCM_ATT < 15V, SE / DE
G= 0.384V/V, -6V < VCM_ATT < 11V, SE / DE
G= 0.768V/V, -3V < VCM_ATT < 8V, SE / DE
G= 1V/V, -2.3V < VCM_AMP < 7.3V, SE / DE
G= 2V/V, -1.15V < VCM_AMP < 6.15V, SE / DE.
PSRR Core op-amp DC
Power Supply
Rejection Ratio
Nulling Switch Mode, 4.5V <V+ <5.5V 90 dB
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LMP7312
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)Units
VOCM_OS VOCM Output Offset
(Note 8)
VOCM = 2.5 V -20 20 mV
VOUT Positive Output
Voltage Swing
RL = 10 kΩ, CL = 50 pF,
+VIN= 15V, -VIN= -15V
V+−0.2
V
Negative Output
Voltage Swing
RL = 10 kΩ, CL = 50 pF,
+VIN= -15V, -VIN= 15V
V−+0.2
IOUT
Short circuit current +VIN= -VIN = 2.5V, +VOUT, -VOUT/VR connected
individually to either V+ or V-
10
mA
Current limitation Internal current limiter 55
GBW Bandwidth
Attenuation Mode, G = 0.096 V/V, RL =10 kΩ,
CL = 50 pF
1.2
MHz
Attenuation Mode, G = 0.192 V/V, RL = 10 kΩ,
CL = 50 pF
1.0
Attenuation Mode, G = 0.384 V/V, RL = 10 kΩ,
CL = 50 pF
560
kHz
Attenuation Mode, G = 0.768 V/V, RL = 10 kΩ,
CL = 50 pF
310
Amplification Mode, G = 1 V/V, RL = 10 kΩ,
CL = 50 pF
530
kHz
Amplification Mode, G = 2 V/V, RL = 10 kΩ,
CL = 50 pF
280
SR Slew Rate RL = 10 kΩ, CL = 50 pF
(Note 9)
1.4 V/μsec
THD+N Total Harmonic
Distorsion + Noise
Vout = 4.096 Vpp, f = 1KHz,
RL = 10 kΩ
0.0026 %
Electrical Characteristics (Serial Interface) (Note 4)
Unless otherwise specified. All limits guaranteed for TA = 25°C, V+ = 5V, V− = 0V, 2.7V < VIO < 5.5V
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)Units
VIL Input Logic Low Threshold 0.8 V
VIH Input Logic High Threshold (SDO pin) 2 V
VOL Output logic Low Threshold (SDO pin) ISDO= 100µA 0.2 V
ISDO= 2mA 0.4
VOH Output logic High Threshold ISDO= 100µA VIO-0.2 V
ISDO= 2mA VIO-0.6
t1High Period, SCK (Note 10) 100 ns
t2Low Period, SCK (Note 10) 100 ns
t3Set Up Time, CS to SCK (Note 10) 50 ns
t4Set Up Time, SDI to SCK (Note 10) 30 ns
t5Hold Time, SCK to SDI (Note 10) 10 ns
t6Prop. Delay, SCK to SDO (Note 10) 60 ns
t7Hold Time, SCK Transition to CS Rising
Edge
(Note 10) 50 ns
t8CS Inactive (Note 10) 100 ns
t9Hold Time, SCK Transition to CS Falling
Edge
(Note 10) 10 ns
tR/tFSignal Rise and Fall Times (Note 10) 1.5 5 ns
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LMP7312
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but for which specific performance is not guaranteed. For guaranteed specifications and the test conditions, see Electrical Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22–A115–A (ESD MM std. of JEDEC). Field-
Induced Charge-Device Model, applicable std. JESD22–C101–C (ESD FICDM std. of JEDEC).
Note 3: The maximum power dissipation is a function of TJ(max), θJA. The maximum allowable power dissipation at any ambient temperature is: PD(max) = (TJ
(max) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >
TA.
Note 5: Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend
on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 6: All limits are guaranteed by testing, design, or statistical analysis.
Note 7: Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
Note 8: VOCM_OS is the difference between the Output Common mode voltage (+VOUT+(-VOUT/VR))/2 and the Voltage on the VOCM pin.
Note 9: The number specified is the average of rising and falling slew rates and is measured at 90% to 10%.
Note 10: Load for these tests is shown in the Test Circuit Diagram.
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LMP7312
Test Circuit Diagram
30075510
Timing Diagram
30075509
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LMP7312
Connection Diagram
14-Pin SOIC
30075502
Top View
Pin Descriptions
Pin Name Description
1 SDI SPI data IN
2 +IN Non-inverting input of Amplification pair
3 -IN Inverting input of Amplification pair
4 +VIN Non-inverting input of Attenuation pair
5 -VIN Inverting input of Attenuation pair
6 CS SPI chip select
7 SDO SPI data OUT
8 VIO SPI supply voltage
9 V+Positive supply voltage
10 +VOUT Non-inverting output
11 -VOUT/VRInverting output in differential output mode, reference input in single-ended operation mode
12 VOCM Output common mode voltage in DE
13 V−Negative supply voltage, reference for both Analog and Digital supplies
14 SCK SPI Clock
Ordering Information
Package Part Number Package Marking Transport Media NSC Drawing
14-Pin SOIC LMP7312MA LMP7312MA 95 Units/Rail M14A
LMP7312MAX 2.5k units Tape and Reel
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LMP7312
Typical Performance Characteristics
Unless otherwise specified, TA = 25°C, V+ = 5V, VIO = 5V, V− = 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL = 10kΩ,
CL =50pF, Differential output configuration.
Offset Voltage distribution (PMOS)
30075546
Offset Voltage distribution (NMOS)
30075547
TCVOS distribution (PMOS)
30075548
TCVOS distribution (NMOS)
30075549
Noise vs. Frequency (Core op-amp)
30075519
0.1Hz to 10Hz Noise (Core op-amp)
30075520
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LMP7312
Gain vs. Frequency (Attenuation Mode)
30075521
Gain vs. Frequency (Amplification Mode)
30075522
CMRR vs. Frequency (Attenuation Mode)
30075536
CMRR vs. Frequency (Amplification Mode)
30075537
PSRR (Core op-amp)
30075523
Vos vs. Input Common Mode Voltage
30075545
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LMP7312
Small signal step (Attenuation Mode)
30075524
Small signal step (Amplification Mode)
30075525
Large signal step (Attenuation Mode)
30075526
Large signal step (Amplification Mode)
30075527
Settling time – Rise (Attenuation Mode)
30075528
Settling time – Rise (Amplification Mode)
30075529
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LMP7312
Settling time – Fall (Attenuation Mode)
30075530
Settling time – Fall (Amplification Mode)
30075531
Gain change (Attenuation Mode)
30075532
Gain change (Amplification Mode)
30075533
THD + N (Attenuation Mode)
30075534
THD + N (Amplification Mode)
30075535
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LMP7312
IVA vs. VA
30075551
IVIO vs. VIO Voltage
30075550
Short Circuit Current +VOUT vs. Temperature
30075541
Short Circuit Current -VOUT vs. Temperature
30075540
Output voltage swing +VOUT vs. Output current
30075543
Output voltage swing -VOUT vs. Output current
30075542
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LMP7312
SDO sink current vs. SDO Voltage
30075539
SDO source current vs. SDO Voltage
30075538
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LMP7312
Application Section
GENERAL DESCRIPTION
The LMP7312 is a single supply programmable gain differ-
ence amplifier with two input pairs: Attenuation pair (-VIN,
+VIN) and Amplification pair (-IN, +IN). The output can be
configured in both single-ended and differential modes with
the output common mode voltage set by the user. The input
selection, the gains and the mode of operation of the
LMP7312 are controlled through a 4- wire SPI interface (SCK,
CS, SDI, SDO). These features combined make the
LMP7312 a very easy interface between the analog high volt-
age industrial buses and the low voltage digital converters.
OUTPUT MODE CONFIGURATION
The LMP7312 is able to work in both single ended and differ-
ential output mode. The selection of the mode is made
through the VOCM (output common mode voltage) pin.
Differential Output
This mode of operation is enabled when the output common
mode voltage pin (VOCM) is connected to a voltage higher than
1V, for instance the common mode voltage supplied by an
ADC, (Figure 1) or a voltage reference. If the VOCM pin is
floating an internal voltage divider biases it at the half supply
voltage. In this configuration the output signals are set on the
VOCM voltage level.
Single-Ended Output
This mode of operation is enabled when the VOCM pin is tied
to a voltage less than 0.5 V, for example to ground. In this
mode of operation the LMP7312 behaves as a difference am-
plifier, where the +VOUT pin is the single-ended output while
the –VOUT /VR is the reference voltage.
1. In the case of bipolar input signal the non inverting output
will be connected to an external reference through a
buffer (Figure 2).
2. In the case of unipolar input signal the non inverting
output will be connected to ground (Figure 3).
In both cases the inverting output pin is configured as an input
pin.
30075503
FIGURE 1. Differential ADC Interfacing with VCM provided by the ADC
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LMP7312
30075504
FIGURE 2. Bipolar Input Signal to Single-Ended ADC Interface
30075505
FIGURE 3. Unipolar Input Signal to Single-Ended ADC Interface
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LMP7312
INPUT VOLTAGE RANGE
The LMP7312 has an internal OpAmp with rail-to-rail input
voltage range capability. The requirement to stay within the
V- and V+ rail at the OpAmp input translates in an Input Volt-
age Range specification as explained in this application sec-
tion.
Differential Output
Considering a single positive supply (V- = GND, V+ = VS) the
Input Common mode voltage, VCM_ATT = (+VIN + (-VIN))/2 for
the Attenuation inputs and VCM_AMP = (+IIN + (-IIN))/2 for the
Amplification inputs, has to stay between the MIN and MAX
values determined by these formulas:
CMMAX = VS + 1/KV*(VS - VOCM)
CMMIN = -1/KV*VOCM
KV is a function of the Gain according to the table below:
Gain 0.096 V/
V
0.192 V/
V
0.384 V/
V
0.768 V/
V
1 V/V 2 V/V
KV0.12 0.218 0.414 0.806 1.065 2.096
Regardless to the values derived by the formula, the voltage
on each input pin must never exceed the specified Absolute
Maximum Ratings.
Below are some typical values:
Differential Input, Differential Output, VS= 5V, VOCM = 2.5V
VCM_ATT VCM_AMP
Gain Min Max Min Max
0.096 V/V -15 V*+15 V*
0.192 V/V -11.5 V +15 V
0.384 V/V -6 V +11 V
0.768 V/V -3.1 V +8.1 V
1 V/V -2.3 V +7.3 V
2 V/V -1.2 V +6.2 V
* Limited by the operating ratings on input pins
In the case of a single ended input referred to ground (-VIN =
GND, -IN = GND) the table below summarizes the voltage
range allowed on the +VIN and +IIN inputs.
Single Ended Input, Differential Output, VS= 5V, VOCM =
2.5V, -VIN = GND, -IIN = GND
+VIN +IN
Gain Min Max Min Max
0.096 V/V -15 V*+15 V*
0.192 V/V -15 V*+15 V*
0.384 V/V -12 V** +12 V**
0.768 V/V -6 V** +6 V**
1 V/V -4.6 V** +4.6 V**
2 V/V -2.3 V** +2.3 V**
* Limited by the operating ratings on input pins
** Limited by the output voltage swing (0.2V to VS-0.2V on both + VOUT and
-VOUT)
Single Ended Output
In this mode the LMP7312 behaves as a Difference Amplifier,
with -VOUT/VR being the reference output voltage when a zero
volt differential input signal is applied. The voltages at the
OpAmp inputs are determined by +VIN and -VOUT/VR voltages.
The voltage range of +VIN and +IIN inputs is as follows:
VMAX = VS + 1/ KV * (VS – (-VOUT/VR))
VMIN = -1/KV * (-VOUT/VR)
Regardless of the values derived by the formula, the voltage
on each input pin must never exceed the specified Absolute
Maximum Ratings.
Below are some typical values:
Differential Input, Single Ended Output, VS = 5V, VOCM =
GND, and -VOUT/VR = 2.5V
+VIN +IIN
Gain Min Max Min Max
0.096 V/V -15 V*+15 V*
0.192 V/V -11.5 V*+15 V
0.384 V/V -6 V +11 V
0.768 V/V -3.1 V +8.1 V
1 V/V -2.3 V +7.3 V
2 V/V -1.2 V +6.2 V
* Limited by the operating ratings on input pins
In the case of a single ended input referred to ground (-VIN =
GND, -IN = GND) this table summarize the voltage ranges
allowed on the +VIN and +IIN inputs.
Single Ended Input, Single Ended Output, VS = 5V, VOCM
= GND, -VOUT/VR = 2.5V, -VIN = GND, -IIN = GND
+VIN +IIN
Gain Min Max Min Max
0.096 V/V -15 V*+15 V*
0.192 V/V -11.5 V +12 V**
0.384 V/V -6 V** +6 V**
0.768 V/V -3 V** +3 V**
1 V/V -2.3 V** +2.3 V**
2 V/V -1.1 V** +1.1 V**
* Limited by the operating ratings on input pins
** Limited by the output voltage swing (0.2V to VS-0.2V on +VOUT )
SERIAL INTERFACE CONTROL OPERATION
The serial interface control of the LMP7312 can be supplied
with a voltage between 2.7V and 5.5V through the VIO pin for
compatibility with different logic families present in the market.
The LMP7312 Attenuation, Amplification, Null switch and HiZ
modes are controlled by a register. Data to be written into the
control register is first loaded into the LMP7312 via the serial
interface. The serial interface employs a 5-bit shift register.
Data is loaded through the serial data input, SDI. Data pass-
ing through the shift register is obtained through the serial
data output, SDO. The serial clock, SCK controls the serial
loading process. All five data bits are required to correctly
program the device. The falling edge of CS enables the shift
register to receive data. The SCK signal must be high during
the falling edge of CS. Each data bit is clocked into the shift
register on the rising edge of SCK. Data is transferred from
the shift register to the holding register on the rising edge of
CS. Operation is shown in the timing diagram .
SPI Registers
MSB LSB
Gain_1 Gain_0 EN_CL Null_SW Hi_Z
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LMP7312
Gain_0, Gain_1 bit: Gain Values
Different gains are available in Attenuation Mode or Amplifi-
cation Mode according to the following Gain Table.
Gain_1 Gain_0 EN_CL Gain Value (V/V)
000 0.096
010 0.192
100 0.384
110 0.768
101 1
111 2
EN_CL bit: Enable Amplification Mode
This register selects which input pair is processed.
EN_CL Mode Description
0 Attenuation
Mode
±VIN inputs are processed
through the 104.16k input
resistors
1 Amplification
Mode
±IN inputs are processed
through the 40k input
resistors
NULL_SW bit: Input Offset Nulling Switch Mode
This register selects a mode in which the amplifier is not pro-
cessing any input but it is configured in unity gain to allow
system level amplifier offset calibration. The Nulling Switch
mode is available in both single ended and fully differential
output mode. The LMP7312 in Nulling Switch and fully differ-
ential mode has he following configuration.
NULL_SW Mode Description
0 Normal
Operation
Mode
±VIN and ±IN inputs are
processed depending on
EN_CL register setting.
1 Nulling Switch
Mode
Enables to evaluate the offset
of the internal amplifier for
system level calibration
30075507
FIGURE 4. LMP7312 in Nulling Switch Mode
In this condition at the Output pins is possible to measure the
input voltage offset of the op-amp:
Output Mode +VOUT −VOUT/VR
Differential VCM_out+VOS/2 VCM_out -VOS/2
Single-Ended VR+VOS VR
Hi_Z bit: High Impedance
In this mode both outputs +VOUT and -VOUT/VR of the
LMP7312 are in tri-state Figure 5.
HI_Z Mode Description
0 Normal
Operation Mode
The LMP7312 is configured
according to value of the
other 4 bits of the register.
1 High Impedance
Mode
The LMP7312 output is in
high impedance
30075560
FIGURE 5. LMP7312 in High Impedance Mode
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LMP7312
In each case the SPI registers require 5 bits. The table below is a summary of all allowed configurations.
MSB LSB
Gain_1 Gain_0 EN_CL Null_SW Hi_Z Gain Value
(V/V)
Mode of Operation
0 0 0 0 0 0.096 Attenuation Mode
0 1 0 0 0 0.192 Attenuation Mode
1 0 0 0 0 0.384 Attenuation Mode
1 1 0 0 0 0.768 Attenuation Mode
1 0 1 0 0 1 Amplification Mode
1 1 1 0 0 2 Amplification Mode
xxxx1 –High Impedance Output
x x x 1 0 1 Null Switch Mode
Daisy Chain
The LMP7312 supports daisy chaining of the serial data
stream between multiple chips. To use this feature serial data
is clocked into the first chip SDI pin, and the next chip SDI pin
is connected to the SDO pin of the first chip. Both chips may
share a chip select signal, or the second chip can be enabled
separately. When the chip select pin goes low on both chips
and 5 bits have been clocked into the first chip the next 5 clock
cycle begins moving new configuration data into the second
chip. With a full 10 clock cycles both chips have valid data and
the chip select pin of both chips should be brought high to
prevent the data from overshooting.
30075511
FIGURE 6. Daisy chain
Shared 4-wire SPI with ADC
The LMP7312 is a good choice when interfacing to differential
analog to digital converters ADC141S626 and ADC161S626
of PowerWise® Family. Its SPI interface has been designed
to enable sharing CSB with the ADC. LMP7312 register ac-
cess happens only when CSB is asserted low while SCK is
high. However, the ADC starts conversion under any of the
following conditions: (1) CSB goes low while SCK is high, (2)
CSB goes low while SCK is low, (3) CSB and SCK both going
low. Therefore, if a system uses timing condition #2 above,
LMP7312 and ADC1x1S626 can share CSB and SCK as
shown in Figure 7. The only side-effect would be that writing
to LMP7312 triggers an ADC conversion, but then the result
can be ignored. At other times, the LMP7312 is not affected
by the CSB assertions used to initiate normal ADC conver-
sions.
30075512
FIGURE 7. 4-wire SPI with ADC interface
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LMP7312
LMP7312 IN 4-20mA CURRENT LOOP APPLICATION
The 4-20mA current loop shown in Figure 8 is a common
method of transmitting sensor information in many industrial
process-monitoring applications. Transmitting sensor infor-
mation via a current loop is particularly useful when the infor-
mation has to be sent to a remote location over long distances
(1000 feet, or more). The loop’s operation is straightforward:
a sensor’s output voltage is first converted to a proportional
current, with 4mA normally representing the sensor’s zero-
level output, and 20mA representing the sensor’s full-scale
output. Then, a receiver at the remote end converts the 4-20-
mA current back into a voltage which in turn can be further
processed by a computer or display module. A typical 4-20mA
current-loop circuit is made up of four individual elements: a
sensor/transducer; a voltage-to-current converter (commonly
referred to as a transmitter and/or signal conditioner); a loop
power supply; and a receiver/monitor. In loop powered appli-
cations, all four elements are connected in a closed, series
circuit, loop configuration (Figure 8). Sensors provide an out-
put voltage whose value represents the physical parameter
being measured. The transmitter amplifies and conditions the
sensor’s output, and then converts this voltage to a propor-
tional 4-20mA dc-current that circulates within the closed
series-loop. The loop power-supply generally provides all op-
erating power to the transmitter and receiver, and any other
loop components that require a well-regulated dc voltage. In
loop-powered applications, the power supply’s internal ele-
ments also furnish a path for closing the series loop. The
receiver/monitor, normally a subsection of a panel meter or
data acquisition system, converts the 4-20mA current back
into a voltage which can be further processed and/or dis-
played. The high DC performance of the LMP7312 makes this
difference amplifier an ideal choice for use in current loop AFE
receiver. The LMP7312 has a low input offset voltage and low
input offset voltage drift when configured in amplification
mode. In the circuit shown in Figure 8 the LMP7312 is in am-
plification mode with a gain of 2V/V and differential output in
order to well match the input stage of the ADC141S626 (SAR
ADC with differential input). The shunt resistor is 100ohm in
order to have a max voltage drop of 2V when 20mA flows in
the loop. The first order filter between the LMP7312 and the
ADC141S626 reduces the noise bandwidth and allows han-
dling input signal up to 2kHz. That frequency has been cal-
culated taking in account the roll off of the filter and ensuring
a gain error less than 1LSB of the ADC141S626. In order to
utilize the maximum number of bits of the ADC141S626 in this
configuration, a 4.1V reference voltage is used. With this sys-
tem, the current of the 4-20mA loop is accurately gained to
the full scale of the ADC and then digitized for further pro-
cessing.
30075561
FIGURE 8. LMP7312 in 4-20mA Current Loop application
LAYOUT CONSIDERATIONS
Power supply bypassing
In order to preserve the gain accuracy of the LMP7312, power
supply stability requires particular attention. The LMP7312
guarantees minimum PSRR of 90dB (or 31.62 µV/V). How-
ever, the dynamic range, the gain accuracy and the inherent
low-noise of the amplifier can be compromised by introducing
and amplifying power supply noise. To decouple the
LMP7312 from supply line AC noise, a 0.1 µF ceramic ca-
pacitor should be located on the supply line, close to the
LMP7312. Adding a 10 µF tantalum capacitor in parallel with
the 0.1 µF ceramic capacitor will reduce the noise introduced
to the LMP7312 even further by providing an AC path to
ground for most frequency ranges.
APPENDIX
Offset Voltage and Offset Voltage Drift calculation
Listed in the table below are the calculated values for Offset
Voltage and Offset Voltage Drift based on the max specifica-
tions of these parameters for the core op-amp (for all gain
configurations).
www.national.com 18
LMP7312
Parameter Unit Value
Gain V/V 0.096 0.192 0.384 0.768 1 2
Total Offset Input Referred (MAX) µV ±1141 ±620 ±360 ±230 ±200 ±150
Total Offset Output Referred (MAX) µV ±109 ±119 ±138 ±176 ±200 ±300
TCVOS Input Referred @ 25°C (MAX) µV/°C ±32.3 ±18.6 ±10.8 ±6.9 ±6 ±4.5
TCVOS Output Referred @ 25°C (MAX) µV/°C ±3.3 ±3.6 ±4.1 ±5.3 ±6 ±9
Noise calculation
Listed in the table below are the calculated values for Voltage
Noise based on the spectral density of the core op-amp at
10kHz (for all gain configurations).
Parameter Unit Value
Gain V/V 0.096 0.192 0.384 0.768 1 2
Total Noise Referred to Input nV/ 211 150 112 89 53 46
Total Noise Referred to Output nV/ 20 29 43 68 53 92
Input resistance calculation
The common mode input resistance is the resistance seen
from node “A” when ΔV1 = ΔV2 = 0 and a common mode
voltage ΔVCM is applied to both inputs of the LMP7312. The
differential input resistance is the resistance seen from the
nodes “B” and “C” when ΔVCM=0 and a differential voltage
ΔV1 = ΔV2 = V/2 is applied to the inputs of the LMP7312.
30075508
FIGURE 9. Circuit for Input Resistance calculation
Mode of Operation Unit Gains
Attenuation Mode 0.096 0.192 0.384 0.768
Common Mode Resistance kΩ57.08 62.08 72.08 92.08
Differential Resistance kΩ228.30 248.30 288.30 368.30
Amplification Mode 1 2
Common Mode Resistance kΩ40.0 60.0
Differential Resistance kΩ160.0 240.0
19 www.national.com
LMP7312
Physical Dimensions inches (millimeters) unless otherwise noted
14-Pin SOIC
NS Package Number M14A
www.national.com 20
LMP7312
Notes
21 www.national.com
LMP7312
Notes
LMP7312 Precision SPI-Programmable AFE with Differential/Single-Ended Input/Output
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