DGK-8DGN-8 D-8
1
2
3
4
8
7
6
5
VIN− VIN+
VOCM
VS+
VOUT+
PD
VS−
VOUT
APPLICATION CIRCUIT DIAGRAM
f − Frequency − MHz
−80
−92
10 20 40 60
− Third-Order Intermodulation Distortion − dBc
−74
THIRD-ORDER INTERMODULATION
DISTORTION
−62
80 100
−68
−86
−98
12
10
14
16
IMD3
Bits
VS
392
+
+800
VS+ VOUT
392
402
56.2
50 374
VOCM
2.5 V
VS−
30 50 70 90
VS = 5 V
VS = ±5 V
+
+
VOCM 12 Bit/80 MSps
IN
IN
5 V
Vref
5 V
VS
0.1 µF10 µF
392
10 pF
1 µF
56.2 ADC
374
50
402
392
10 pF
24.9
24.9
THS4500
THS4501
www.ti.com
SLOS350F APRIL 2002REVISED OCTOBER 2011
WIDEBAND, LOW-DISTORTION, FULLY DIFFERENTIAL AMPLIFIERS
Check for Samples: THS4500,THS4501
1FEATURES APPLICATIONS
23Fully Differential Architecture High Linearity Analog-to-Digital Converter
Preamplifier
Bandwidth: 370 MHz Wireless Communication Receiver Chains
Slew Rate: 2800 V/μsSingle-Ended to Differential Conversion
IMD3:90 dBc at 30 MHz Differential Line Driver
OIP3: 49 dBm at 30 MHz Active Filtering of Differential Signals
Output Common-Mode Control
Wide Power-Supply Voltage Range: 5 V, ±5 V,
12 V, 15 V
Input Common-Mode Range Shifted to Include
Negative Power-Supply Rail
Power-Down Capability (THS4500)
Evaluation Module Available
DESCRIPTION RELATED DEVICES
DEVICE(1) DESCRIPTION
The THS4500 and THS4501 are high-performance
fully differential amplifiers from Texas Instruments. THS4500/1 370 MHz, 2800 V/μs, VICR Includes VS
The THS4500, featuring power-down capability, and THS4502/3 370 MHz, 2800 V/μs, Centered VICR
the THS4501, without power-down capability, set new THS4120/1 3.3 V, 100 MHz, 43 V/μs, 3.7 nV/Hz
performance standards for fully differential amplifiers THS4130/1 ±15 V, 150 MHz, 51 V/μs, 1.3 nV/Hz
with unsurpassed linearity, supporting 14-bit THS4140/1 ±15 V, 160 MHz, 450 V/μs, 6.5 nV/Hz
operation through 40 MHz. Package options include
the SOIC-8 and the MSOP-8 with PowerPADfor a THS4150/1 ±15 V, 150 MHz, 650 V/μs, 7.6 nV/Hz
smaller footprint, enhanced ac performance, and
improved thermal dissipation capability. (1) Even-numbered devices feature power-down capability.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments, Incorporated.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©20022011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. UNIT
Supply voltage, VS16.5 V
Input voltage, VI±VS
Output current, IO(2) 150 mA
Differential input voltage, VID 4 V
Continuous power dissipation See Dissipation Rating Table
Maximum junction temperature, TJ(3) +150°C
Maximum junction temperature, continuous operation, long-term reliability, TJ+125°C
C suffix 0°C to +70°C
Operating free-air temperature range, TA(4) I suffix 40°C to +85°C
Storage temperature range, Tstg 65°C to +150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds +300°C
HBM 4000 V
ESD rating: CDM 1000 V
MM 100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The THS4500/1 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
DISSIPATION RATINGS TABLE POWER RATING(2)
θJC θJA (1)
PACKAGE (°C/W) (°C/W) TA+25°C TA= +85°C
D (8-pin) 38.3 97.5 1.02 W 410 mW
DGN (8-pin) 4.7 58.4 1.71 W 685 mW
DGK (8-pin) 54.2 260 385 mW 154 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and
long-term reliability.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Dual supply ±5±7.5
Supply voltage V
Single supply 4.5 5 15
C suffix 0 +70
Operating free- air temperature, TA°C
I suffix 40 +85
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(TOPVIEW)
THS4501 D,DGN,DGK
(TOPVIEW)
THS4500 D,DGN,DGK
VIN-1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS-
VOUT-
PD
VIN-1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS-
VOUT-
NC
THS4500
THS4501
www.ti.com
SLOS350F APRIL 2002REVISED OCTOBER 2011
PACKAGE/ORDERING INFORMATION(1)
ORDERABLE PACKAGE AND NUMBER
PLASTIC MSOP(2)
TEMPERATURE PLASTIC MSOP(2)
PLASTIC SMALL PowerPAD
OUTLINE (D) DGN SYMBOL DGK SYMBOL
THS4500CD THS4500CDGN BFB THS4500CDGK ATVB
0°C to +70°CTHS4501CD THS4501CDGN BFD THS4501CDGK ATW
THS4500ID THS4500IDGN BFC THS4500IDGK ASV
40°C to +85°CTHS4501ID THS4501IDGN BFE THS4501IDGK ASW
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) All packages are available taped and reeled. The R suffix standard quantity is 2500. The T suffix standard quantity is 250 (for example,
THS4501DT).
PIN ASSIGNMENTS
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VS=±5 V
RF= RG= 392 , RL= 800 , G = +1, and single-ended input, unless otherwise noted.THS4500 AND THS4501
TYP OVER TEMPERATURE MIN/
PARAMETER TEST CONDITIONS TYP/
0°C to 40°C to
+25°C +25°C UNITS MAX
+70°C +85°C
AC PERFORMANCE
G = +1, PIN =20 dBm, RF= 392 370 MHz Typ
G = +2, PIN =30 dBm, RF= 1 k175 MHz Typ
Small-signal bandwidth G = +5, PIN =30 dBm, RF= 2.4 k70 MHz Typ
G = +10, PIN =30 dBm, RF= 5.1 k30 MHz Typ
Gain-bandwidth product G >+10 300 MHz Typ
Bandwidth for 0.1-dB flatness PIN =20 dBm 150 MHz Typ
Large-signal bandwidth VP= 2 V 220 MHz Typ
Slew rate 4 VPP Step 2800 V/μs Typ
Rise time 2 VPP Step 0.4 ns Typ
Fall time 2 VPP Step 0.5 ns Typ
Settling time to 0.01% VO= 4 VPP 8.3 ns Typ
0.1% VO= 4 VPP 6.3 ns Typ
Harmonic distortion G = +1, VO= 2 VPP Typ
f = 8 MHz 82 dBc Typ
2nd harmonic f = 30 MHz 71 dBc Typ
f = 8 MHz 97 dBc Typ
3rd harmonic f = 30 MHz 74 dBc Typ
Third-order intermodulation VO= 2 VPP, fC= 30 MHz, RF= 392 ,90 dBc Typ
distortion 200 kHz tone spacing
fC= 30 MHz, RF= 392 ,
Third-order output intercept point 49 dBm Typ
Referenced to 50
Input voltage noise f >1 MHz 7 nV/Hz Typ
Input current noise f >100 kHz 1.7 pA/Hz Typ
Overdrive recovery time Overdrive = 5.5 V 60 ns Typ
DC PERFORMANCE
Open-loop voltage gain 55 52 50 50 dB Min
Input offset voltage 47/18/0 9/+1 mV Max
Average offset voltage drift ±10 ±10 μV/°C Typ
Input bias current 4 4.6 5 5.2 μA Max
Average bias current drift ±10 ±10 nA/°C Typ
Input offset current 0.5 1 2 2 μA Max
Average offset current drift ±40 ±40 nA/°C Typ
INPUT
Common-mode input range 5.7/2.6 5.4/2.3 5.1/2 5.1/2 V Min
Common-mode rejection ratio 80 74 70 70 dB Min
Input impedance 107|| 1 || pF Typ
OUTPUT
Differential output voltage swing RL= 1 k ±8±7.6 ±7.4 ±7.4 V Min
Differential output current drive RL= 20 120 110 100 100 mA Min
Output balance error PIN =20 dBm, f = 100 kHz 58 dB Typ
Closed-loop output impedance f = 1 MHz 0.1 Typ
(single-ended)
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THS4500
THS4501
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SLOS350F APRIL 2002REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS: VS=±5 V (continued)
RF= RG= 392 , RL= 800 , G = +1, and single-ended input, unless otherwise noted.THS4500 AND THS4501
TYP OVER TEMPERATURE MIN/
PARAMETER TEST CONDITIONS TYP/
0°C to 40°C to
+25°C +25°C UNITS MAX
+70°C +85°C
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth RL= 400 180 MHz Typ
Slew rate 2 VPP Step 92 V/μs Typ
Minimum gain 1 0.98 0.98 0.98 V/V Min
Maximum gain 1 1.02 1.02 1.02 V/V Max
Common-mode offset voltage 0.4 4.6/+3.8 6.6/+5.8 7.6/+6.8 mV Max
Input bias current VOCM = 2.5 V 100 150 170 170 μA Max
Input voltage range ±4±3.7 ±3.4 ±3.4 V Min
Input impedance 25 || 1 k|| pF Typ
Maximum default voltage VOCM left floating 0 0.05 0.10 0.10 V Max
Minimum default voltage VOCM left floating 0 0.05 0.10 0.10 V Min
POWER SUPPLY
Specified operating voltage ±5 7.5 7.5 7.5 V Max
Maximum quiescent current 23 28 32 34 mA Max
Minimum quiescent current 23 18 14 12 mA Min
Power-supply rejection (±PSRR) 80 76 73 70 dB Min
POWER-DOWN (THS4500 ONLY)
Enable voltage threshold Device enabled ON above 2.9 V 2.9 V Min
Disable voltage threshold Device disabled OFF below 4.3 V 4.3 V Max
Power-down quiescent current 800 1000 1200 1200 μA Max
Input bias current 200 240 260 260 μA Max
Input impedance 50 || 1 k|| pF Typ
Turn-on time delay 1000 ns Typ
Turn-off time delay 800 ns Typ
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VS= 5 V
RF= RG= 392 , RL= 800 , G = +1, and single-ended input, unless otherwise noted.
THS4500 AND THS4501
TYP OVER TEMPERATURE MIN/T
PARAMETER TEST CONDITIONS YP/M
0°C to 40°C to
+25°C +25°C UNITS AX
+70°C +85°C
AC PERFORMANCE
G = +1, PIN =20 dBm, RF= 392 320 MHz Typ
G = +2, PIN =30 dBm, RF= 1 k160 MHz Typ
Small-signal bandwidth G = +5, PIN =30 dBm, RF= 2.4 k60 MHz Typ
G = +10, PIN =30 dBm, RF= 5.1 k30 MHz Typ
Gain-bandwidth product G >+10 300 MHz Typ
Bandwidth for 0.1-dB flatness PIN =20 dBm 180 MHz Typ
Large-signal bandwidth VP= 1 V 200 MHz Typ
Slew rate 2 VPP Step 1300 V/μs Typ
Rise time 2 VPP Step 0.5 ns Typ
Fall time 2 VPP Step 0.6 ns Typ
Settling time to 0.01% VO= 2 V Step 13.1 ns Typ
0.1% VO= 2 V Step 8.3 ns Typ
Harmonic distortion G = +1, VO= 2 VPP Typ
f = 8 MHz, 80 dBc Typ
2nd harmonic f = 30 MHz 55 dBc Typ
f = 8 MHz 76 dBc Typ
3rd harmonic f = 30 MHz 60 dBc Typ
Input voltage noise f >1 MHz 7 nV/Hz Typ
Input current noise f >100 kHz 1.7 pA/Hz Typ
Overdrive recovery time Overdrive = 5.5 V 60 ns Typ
DC PERFORMANCE
Open-loop voltage gain 54 51 49 49 dB Min
Input offset voltage 47/18/0 9/+1 mV Max
Average offset voltage drift ±10 ±10 μV/°C Typ
Input bias current 4 4.6 5 5.2 μA Max
Average bias current drift ±10 ±10 nA/°C Typ
Input offset current 0.5 0.7 1.2 1.2 μA Max
Average offset current drift ±20 ±20 nA/°C Typ
INPUT
Common-mode input range 0.7/2.6 0.4/2.3 0.1/2 0.1/2 V Min
Common-mode rejection ratio 80 74 70 70 dB Min
Input Impedance 107|| 1 || pF Typ
OUTPUT
Differential output voltage swing RL= 1 k, Referenced to 2.5 V ±3.3 ±3±2.8 ±2.8 V Min
Output current drive RL= 20 100 90 80 80 mA Min
Output balance error PIN =20 dBm, f = 100 kHz 58 dB Typ
Closed-loop output impedance f = 1 MHz 0.1 Typ
(single-ended)
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THS4500
THS4501
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SLOS350F APRIL 2002REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS: VS= 5 V (continued)
RF= RG= 392 , RL= 800 , G = +1, and single-ended input, unless otherwise noted.
THS4500 AND THS4501
TYP OVER TEMPERATURE MIN/T
PARAMETER TEST CONDITIONS YP/M
0°C to 40°C to
+25°C +25°C UNITS AX
+70°C +85°C
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth RL= 400 180 MHz Typ
Slew rate 2 VPP Step 80 V/μs Typ
Minimum gain 1 0.98 0.98 0.98 V/V Min
Maximum gain 1 1.02 1.02 1.02 V/V Max
Common-mode offset voltage 0.4 2.6/3.4 4.2/5.4 5.6/6.4 mV Max
Input bias current VOCM = 2.5 V 1 2 3 3 μA Max
Input voltage range 1/4 1.2/3.8 1.3/3.7 1.3/3.7 V Min
Input impedance 25 || 1 k|| pF Typ
Maximum default voltage VOCM left floating 2.5 2.55 2.6 2.6 V Max
Minimum default voltage VOCM left floating 2.5 2.45 2.4 2.4 V Min
POWER SUPPLY
Specified operating voltage 5 15 15 15 V Max
Maximum quiescent current 20 25 29 31 mA Max
Minimum quiescent current 20 16 12 10 mA Min
Power-supply rejection (+PSRR) 75 72 69 66 dB Min
POWER -DOWN (THS4500 ONLY)
Enable voltage threshold Device enabled ON above 2.1 V 2.1 V Min
Disable voltage threshold Device disabled OFF below 0.7 V 0.7 V Max
Power-down quiescent current 600 800 1200 1200 μA Max
Input bias current 100 125 140 140 μA Max
Input impedance 50 || 1 k|| pF Typ
Turn-on time delay 1000 ns Typ
Turn-off time delay 800 ns Typ
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small-signal unity-gain frequency response 1
Small-signal frequency response 2
0.1-dB gain flatness frequency response 3
Large-signal frequency response 4
Harmonic distortion (single-ended input to differential output) vs Frequency 5, 7, 13, 15
Harmonic distortion (differential input to differential output) vs Frequency 6, 8, 14, 16
Harmonic distortion (single-ended input to differential output) vs Output voltage swing 9, 11, 17, 19
Harmonic distortion (differential input to differential output) vs Output voltage swing 10, 12, 18, 20
Harmonic distortion (single-ended input to differential output) vs Load resistance 21
Harmonic distortion (differential input to differential output) vs Load resistance 22
Third-order intermodulation distortion vs Frequency 23
(single-ended input to differential output)
Third-order output intercept point vs Frequency 24
Slew rate vs Differential output voltage step 25
Settling time 26, 27
Large-signal transient response 28
Small-signal transient response 29
Overdrive recovery 30, 31
Voltage and current noise vs Frequency 32
Rejection ratios vs Frequency 33
Rejection ratios vs Case temperature 34
Output balance error vs Frequency 35
Open-loop gain and phase vs Frequency 36
Open-loop gain vs Case temperature 37
Input bias offset current vs Case temperature 38
Quiescent current vs Supply voltage 39
Input offset voltage vs Case temperature 40
Common-mode rejection ratio vs Input common-mode range 41
Output drive vs Case temperature 42
Harmonic distortion vs Output common-mode voltage 43
(single-ended and differential input to differential output)
Small-signal frequency response at VOCM 44
Output offset voltage at VOCM vs Output common-mode voltage 45
Quiescent current vs Power-down voltage 46
Turn-on and turn-off delay times 47
Single-ended output impedance in power-down vs Frequency 48
vs Case temperature 49
Power-down quiescent current vs Supply voltage 50
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Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
www.ti.com
SLOS350F APRIL 2002REVISED OCTOBER 2011
Table of Graphs (5 V)
FIGURE
Small-signal unity-gain frequency response 51
Small-signal frequency response 52
0.1-dB gain flatness frequency response 53
Large-signal frequency response 54
Harmonic distortion (single-ended input to differential output) vs Frequency 55, 57, 63, 65
Harmonic distortion (differential input to differential output) vs Frequency 56, 58, 64, 66
Harmonic distortion (single-ended input to differential output) vs Output voltage swing 59, 61, 67, 69
Harmonic distortion (differential input to differential output) vs Output voltage swing 60, 62, 68, 70
Harmonic distortion (single-ended input to differential output) vs Load resistance 71
Harmonic distortion (differential input to differential output) vs Load resistance 72
Third-order intermodulation distortion vs Frequency 73
Third-order intercept point vs Frequency 74
Slew rate vs Differential output voltage step 75
Large-signal transient response 76
Small-signal transient response 77
Voltage and current noise vs Frequency 78
Rejection ratios vs Frequency 79
Rejection ratios vs Case temperature 80
Output balance error vs Frequency 81
Open-loop gain and phase vs Frequency 82
Open-loop gain vs Case temperature 83
Input bias offset current vs Case temperature 84
Quiescent current vs Supply voltage 85
Input offset voltage vs Case temperature 86
Common-mode rejection ratio vs Input common-mode range 87
Output drive vs Case temperature 88
Harmonic distortion (single-ended and differential input) vs Output common-mode voltage 89
Small-signal frequency response at VOCM 90
Output offset voltage vs Output common-mode voltage 91
Quiescent current vs Power-down voltage 92
Turn-on and turn-off delay times 93
Single-ended output impedance in power-down vs Frequency 94
vs Case temperature 95
Power-down quiescent current vs Supply voltage 96
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Product Folder Link(s): THS4500 THS4501
−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Unity Gain − dB
Gain = 1
RL = 800
Rf = 392
PIN = −20 dBm
VS = ±5 V
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
110 100 1000
Rf = 392
Rf = 499
Gain = 1
RL = 800
PIN = −20 dBm
VS = ±5 V
f − Frequency − MHz
0.1 dB Gain Flatness − dB
−2
0
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Gain − dB
Gain = 10, Rf = 5.1 k
Gain = 5, Rf = 2.4 k
Gain = 2, Rf = 1 k
RL = 800
PIN = −30 dBm
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
VO = 1 VPP
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
VO = 1 VPP
VS = ±5 V
−4
−3
−2
−1
0
1
0.1 1 10 100 1000
f − Frequency − MHz
Large Signal Gain − dB
Gain = 1
RL = 800
Rf = 392
PIN = 10 dBm
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
f= 8 MHz
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
VO = 2 VPP
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
VO = 2 VPP
VS = ±5 V
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS: ±5 V
SMALL-SIGNAL UNITY-GAIN SMALL-SIGNAL FREQUENCY 0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE RESPONSE FREQUENCY RESPONSE
Figure 1. Figure 2. Figure 3.
HARMONIC DISTORTION HARMONIC DISTORTION
LARGE-SIGNAL FREQUENCY vs vs
RESPONSE FREQUENCY FREQUENCY
Figure 4. Figure 5. Figure 6.
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY OUTPUT VOLTAGE SWING
Figure 7. Figure 8. Figure 9.
10 Submit Documentation Feedback Copyright ©20022011, Texas Instruments Incorporated
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−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 1
RL = 800
Rf = 499
f= 8 MHz
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
f= 30 MHz
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Differentia Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
f= 30 MHz
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
VO = 1 VPP
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0.1 1 10 100
0
HD2
Harmonic Distortion − dBc
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
VO = 1 VPP
VS = ±5 V
HD3
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0.1 1 10 100
0
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
VO = 2 VPP
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
f= 8 MHz
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
f= 8 MHz
VS = ±5 V
THS4500
THS4501
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SLOS350F APRIL 2002REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 10. Figure 11. Figure 12.
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 13. Figure 14. Figure 15.
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 16. Figure 17. Figure 18.
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 11
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−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
f= 30 MHz
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Differentia Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
f= 8 MHz
VS = ±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion − dBc
RL − Load Resistance −
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392
f= 30 MHz
VS = ±5 V
30
35
40
45
50
55
0 20 40 60 80 100 120
Third-OrderOutputInterceptPoint dBm-
f Frequency MHz- -
Gain = 1
RF= 392 W
VO= 2 VPP
VS=±5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion − dBc
RL − Load Resistance −
Differential Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392
f= 30 MHz
VS = ±5 V
−100
−90
−80
−70
−60
−50
10 100
Third-Order Intermodulation Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
VO = 2 VPP
VS = ±5 V
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
0 2 4 6 8 10 12 14
t Time ns- -
VOOutputVoltage V- -
Gain = 1
RL= 800 W
RF= 499 W
f= 1MHz
VS=±5 V
Rising Edge
Falling Edge
0 5 10 15 20
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800
Rf = 499
f= 1 MHz
VS = ±5 V
Rising Edge
Falling Edge
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
0
500
1000
1500
2000
2500
3000
VO − Differential Output Voltage Step − V
SR − Slew Rate − sµ
V/
Gain = 1
RL = 800
Rf = 392
VS = ±5 V
0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
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TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING LOAD RESISTANCE
Figure 19. Figure 20. Figure 21.
THIRD-ORDER INTERMODULATION THIRD-ORDER OUTPUT INTERCEPT
HARMONIC DISTORTION DISTORTION POINT
vs vs vs
LOAD RESISTANCE FREQUENCY FREQUENCY
Figure 22. Figure 23. Figure 24.
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE
STEP SETTLING TIME SETTLING TIME
Figure 25. Figure 26. Figure 27.
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−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800
Rf = 499
tr/tf = 300 ps
VS = ±5 V
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800
Rf = 499
tr/tf = 300 ps
VS = ±5 V
t − Time − µs
0
−1
−4
0 0.1 0.2 0.3 0.4 0.5 0.6
Single-Ended Output Voltage − V
1
2
4
0.7 0.8 0.9 1
3
−3
−5
−2
5
0
−0.5
−2
0.5
1
2
1.5
−1.5
−2.5
−1
2.5
− Input Voltage − VVI
Gain = 4
RL = 800
Rf = 499
Overdrive = 4.5 V
VS = ±5 V
−10
0
10
20
30
40
50
60
70
80
90
0.1 1 10 100
Rejection Ratios − dB
f − Frequency − MHz
PSRR+
PSRR− CMMR
RL = 800
VS = ±5 V
−150
−100
−50
0
50
100
150
200
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Output Drive − mA
Case Temperature − °C
VS = ±5 V Source
Sink
1
10
100
0.01 0.1 1 10 100
Vn
In
f − Frequency − kHz
− Voltage Noise − nV/ Hz
Vn
− Current Noise − pA/ Hz
In
1000 10 k
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
Output Balance Error − dB
f − Frequency − MHz
PIN = 10 dBm
RL = 800
Rf = 392
VS = ±5 V
0
20
40
60
80
100
120
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Rejection Ratios − dB
Case Temperature − °C
PSRR+
CMMR
RL = 800
VS = ±5 V
0
10
20
30
40
50
60
0.01 0.1 1 10 100 1000
−150
−120
−90
−60
−30
0
30
Open-Loop Gain − dB
f − Frequency − MHz
PIN = −30 dBm
RL = 800
VS = ±5 V
Phase −
Gain
Phase
°
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SLOS350F APRIL 2002REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS: ±5 V (continued)
LARGE-SIGNAL TRANSIENT SMALL-SIGNAL TRANSIENT
RESPONSE RESPONSE OVERDRIVE RECOVERY
Figure 28. Figure 29. Figure 30.
VOLTAGE AND CURRENT NOISE REJECTION RATIOS
vs vs
OVERDRIVE RECOVERY FREQUENCY FREQUENCY
Figure 31. Figure 32. Figure 33.
REJECTION RATIOS OUTPUT BALANCE ERROR OPEN-LOOP GAIN AND PHASE
vs vs vs
CASE TEMPERATURE FREQUENCY FREQUENCY
Figure 34. Figure 35. Figure 36.
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 13
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−40−30−20−100 10 20 30 40 50 60 70 80 90
− Input Bias Current −
VS = ±5 V
− Input Offset Current −
IIB Aµ
IOS Aµ
IIB+
IOS
Case Temperature − °C
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
−0.09
−0.08
−0.07
−0.06
−0.05
−0.04
−0.03
−0.02
−0.01
0
IIB−
58
49
50
51
52
53
54
55
56
57
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Open-Loop Gain − dB
Case Temperature − °C
RL = 800
VS = ±5 V
0
5
10
15
20
25
30
35
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS − Supply Voltage − ±V
Quiescent Current − mA
TA = 85°C
TA = 25°C
TA = −40°C
0
1
3
4
6
7
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
− Input Offset Voltage − mV
VOS
VS = ±5 V
2
5
−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6
−10
0
10
20
30
40
50
60
70
80
90
100
110
Input Common-Mode Voltage Range − V
CMRR − Common-Mode Rejection Ratio − dB
VS = ±5 V
−150
−100
−50
0
50
100
150
200
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Output Drive − mA
Case Temperature − °C
VS = ±5 V Source
Sink
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
−3.5 −2.5 −1.5 −0.5 0.5 1.5 2.5 3.5
VOC − Output Common-Mode Voltage − V
Harmonic Distortion − dBc
Single-Ended and Differential
Input to Differential Output
Gain = 1, VO = 2 VPP
f= 8 MHz, Rf = 392
VS = ±5 V
HD2
-Diff
HD2-SE
HD3-Diff
HD3-SE
−600
−400
−200
0
200
400
600
−5 −4 −3 −2 −1 0 1 2 3 4 5
VOC − Output Common-Mode Voltage − V
− Output Offset Voltage − mV
VOS
−3
−2
−1
0
1
2
3
1 10 100 1000
f − Frequency − MHz
Gain = 1
RL = 800
Rf = 392
PIN= −20 dBm
VS = ±5 V
Small Signal Frequency Response at VOCM− dB
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
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TYPICAL CHARACTERISTICS: ±5 V (continued)
INPUT BIAS AND OFFSET
OPEN-LOOP GAIN CURRENT QUIESCENT CURRENT
vs vs vs
CASE TEMPERATURE CASE TEMPERATURE SUPPLY VOLTAGE
Figure 37. Figure 38. Figure 39.
INPUT OFFSET VOLTAGE COMMON-MODE REJECTION RATIO OUTPUT DRIVE
vs vs vs
CASE TEMPERATURE INPUT COMMON-MODE RANGE CASE TEMPERATURE
Figure 40. Figure 41. Figure 42.
OUTPUT OFFSET VOLTAGE AT
HARMONIC DISTORTION VOCM
vs vs
OUTPUT COMMON-MODE SMALL-SIGNAL FREQUENCY OUTPUT COMMON-MODE
VOLTAGE RESPONSE AT VOCM VOLTAGE
Figure 43. Figure 44. Figure 45.
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0
100
200
300
400
500
600
700
800
0.1 1 10 100 1000
− Single-Ended Output ImpedanceZOin Powerdown −
f − Frequency − MHz
Gain = 1
RL = 800
Rf = 392
PIN = −1 dBm
VS = ±5 V
−5
0
5
10
15
20
25
30
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0
Power-Down Voltage − V
Quiescent Current − mA
−1
−2
−5
0 0.5 1 2
0
100.5101 102 103
−3
−6
−4
0
0.01
0.03
0.02
t − Time − ms
Powerdown Voltage Signal − V
Quiescent Current − mA
1.5 2.5 3
Current
0
100
200
300
400
500
600
700
800
900
1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS − Supply Voltage − ±V
RL = 800
Power-Down Quiescent Current − Aµ
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Power-Down Quiescent Current −
Case Temperature − °C
RL = 800
VS = ±5 V
0
100
200
300
400
500
600
700
800
900
1000
Aµ
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SLOS350F APRIL 2002REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS: ±5 V (continued) SINGLE-ENDED OUTPUT
QUIESCENT CURRENT IMPEDANCE IN POWER-DOWN
vs TURN-ON AND TURN-OFF DELAY vs
POWER-DOWN VOLTAGE TIME FREQUENCY
Figure 46. Figure 47. Figure 48.
POWER-DOWN QUIESCENT CURRENT POWER-DOWN QUIESCENT CURRENT
vs vs
CASE TEMPERATURE SUPPLY VOLTAGE
Figure 49. Figure 50.
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−4
−3
−2
−1
0
1
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Unity Gain − dB
Gain = 1
RL = 800
Rf = 392
PIN = −20 dBm
VS = 5 V
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.2
110 100 1000
Rf = 392
Rf = 499
f − Frequency − MHz
0.1 dB Gain Flatness − dB
Gain = 1
RL = 800
PIN = −20 dBm
VS = 5 V
0.1
−2
0
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Gain − dB
Gain = 10, Rf = 5.1 k
Gain = 5, Rf = 2.4 k
Gain = 2, Rf = 1 k
RL = 800
PIN = −30 dBm
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
VO = 1 VPP
VS = 5 V
0.1 1 10 100 1000
f − Frequency − MHz
Large Signal Gain − dB
Gain = 1
RL = 800
Rf = 392
PIN = 10 dBm
VS = 5 V
−4
−3
−2
−1
0
1
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
VO = 1 VPP
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 1
RL = 800
Rf = 499
VO = 2 VPP
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
VO = 2 VPP
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
f= 8 MHz
VS = 5 V
0.5 1 1.5 2 2.5 30
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SLOS350F APRIL 2002REVISED OCTOBER 2011
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TYPICAL CHARACTERISTICS: 5 V
SMALL-SIGNAL UNITY-GAIN SMALL-SIGNAL FREQUENCY 0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE RESPONSE FREQUENCY RESPONSE
Figure 51. Figure 52. Figure 53.
HARMONIC DISTORTION HARMONIC DISTORTION
LARGE-SIGNAL FREQUENCY vs vs
RESPONSE FREQUENCY FREQUENCY
Figure 54. Figure 55. Figure 56.
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY OUTPUT VOLTAGE SWING
Figure 57. Figure 58. Figure 59.
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−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Differentia Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
f= 8 MHz
VS = 5 V
0 0.5 1 1.5 2 2.5 3
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
0 0.5 1 1.5 2 2.5 3
Single-Ended Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
f = 30 MHz
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
Differentia Input to
Differential Output
Gain = 1
RL = 800
Rf = 392
f= 30 MHz
VS = 5 V
0 0.5 1 1.5 2 2.5 3
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
VO = 1 VPP
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
VO = 2 VPP
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0.1 1 10 100
0
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
VO = 1 VPP
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
VO = 2 VPP
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
0 0.5 1 1.5 2 2.5 3
Single-Ended Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
f = 8 MHz
VS = 5 V
100
90
80
70
60
50
40
30
20
10
0
HD2
HD3
HarmonicDistortion dBc-
VO- -OutputVoltageSwing V
Differential Inputto
Differential Output
Gain = 2
RL= 800 W
RF= 1 kW
f= 8MHz
VS= 5 V
0 0.5 1 1.5 2 2.5 3
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SLOS350F APRIL 2002REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 60. Figure 61. Figure 62.
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 63. Figure 64. Figure 65.
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 66. Figure 67. Figure 68.
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−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion − dBc
RL − Load Resistance −
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392
f= 30 MHz
VS = 5 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
HD2
HD3
Harmonic Distortion − dBc
VO − Output Voltage Swing − V
0 0.5 1 1.5 2 2.5 3
Single-Ended Input to
Differential Output
Gain = 2
RL = 800
Rf = 1 k
f = 30 MHz
VS = 5 V
100
90
80
70
60
50
40
30
20
10
0
HD2
HD3
HarmonicDistortion dBc-
VOOutputVoltageSwing V- -
Differential Inputto
Differential Output
Gain = 2
RL= 800 W
RF= 1 kW
f= 30MHz
VS= 5 V
0 0.5 1 1.5 2 2.5 3
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 400 800 1200 1600
HD2
HD3
HarmonicDistortion -dBc
RLLoadResistance- - W
Differential Inputto
Differential Output
Gain = 1
VO= 2 VPP
RF= 392 W
f= 30MHz
VS= 5 V
30
35
40
45
50
55
0 20 40 60 80 100 120
Third-OrderOutputInterceptPoint dBm-
f Frequency MHz- -
Gain = 1
VO= 2 VPP
RF= 392 W
RL= 800 W
VS= 5 V
−100
−90
−80
−70
−60
−50
10 100
Third-Order Intermodulation Distortion − dBc
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392
RL = 800
VS = 5 V
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800
Rf = 392
tr/tf = 300 ps
VS = 5 V
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − VVO
Gain = 1
RL = 800
Rf = 392
tr/tf = 300 ps
VS = 5 V
−0.4
−0.3
−0.2
−0.1
0
0.2
0.3
0.1
0.4
0
200
400
600
800
1000
1200
1400
0 0.5 1 1.5 2 2.5 3
VO − Differential Output Voltage Step − V
SR − Slew Rate − sµ
V/
Gain = 1
RL = 800
Rf = 392
VS = 5 V
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING LOAD RESISTANCE
Figure 69. Figure 70. Figure 71.
THIRD-ORDER INTERMODULATION THIRD-ORDER OUTPUT INTERCEPT
HARMONIC DISTORTION DISTORTION POINT
vs vs vs
LOAD RESISTANCE FREQUENCY FREQUENCY
Figure 72. Figure 73. Figure 74.
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE LARGE-SIGNAL TRANSIENT SMALL-SIGNAL TRANSIENT
STEP RESPONSE RESPONSE
Figure 75. Figure 76. Figure 77.
18 Submit Documentation Feedback Copyright ©20022011, Texas Instruments Incorporated
Product Folder Link(s): THS4500 THS4501
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Rejection Ratios − dB
Case Temperature − °C
PSRR+
PSRR−
CMMR
RL = 800
VS = 5 V
0
20
40
60
80
100
120
−10
0
10
20
30
40
50
60
70
80
90
0.1 1 10 100
Rejection Ratios − dB
f − Frequency − MHz
PSRR+
PSRR− CMMR
RL = 800
VS = 5 V
1
10
100
0.01 0.1 1 10 100
Vn
In
f − Frequency − kHz
− Voltage Noise − nV/ Hz
Vn
− Current Noise − pA/ Hz
In
1000 10 k
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
Output Balance Error − dB
f − Frequency − MHz
PIN = −20 dBm
RL = 800
Rf = 499
VS = 5 V
−40−30−20−100 10 20 30 40 50 60 70 80 90
Open-Loop Gain − dB
Case Temperature − °C
RL = 800
VS = 5 V
46
47
48
49
50
51
52
53
54
55
56
57
0
10
20
30
40
50
60
0.01 0.1 1 10 100 1000
−150
−120
−90
−60
−30
0
30
Open-Loop Gain − dB
f − Frequency − MHz
PIN = −30 dBm
RL = 800
VS = 5 V
Phase −
Gain
Phase
°
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
− Input Bias Current −
Case Temperature − °C
VS = 5 V
− Input Offset Current −
IIB−
IIB Aµ
IOS Aµ
IIB+
IOS
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
−0.1
−0.09
−0.08
−0.07
−0.06
−0.05
−0.04
−0.03
−0.02
−0.01
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
− Input Offset Voltage − mV
VOS
VS = 5 V
0
0.5
1
1.5
2
2.5
3
3.5
4
0
5
10
15
20
25
30
35
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS − Supply Voltage − ±V
Quiescent Current − mA
TA = 85°C
TA = 25°C
TA = −40°C
THS4500
THS4501
www.ti.com
SLOS350F APRIL 2002REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS: 5 V (continued)
REJECTION RATIOS REJECTION RATIOS
VOLTAGE AND CURRENT NOISE
vs vs vs
FREQUENCY FREQUENCY CASE TEMPERATURE
Figure 78. Figure 79. Figure 80.
OUTPUT BALANCE ERROR OPEN-LOOP GAIN AND PHASE OPEN-LOOP GAIN
vs vs vs
FREQUENCY FREQUENCY CASE TEMPERATURE
Figure 81. Figure 82. Figure 83.
INPUT BIAS AND OFFSET QUIESCENT CURRENT INPUT OFFSET VOLTAGE
CURRENT
vs vs vs
CASE TEMPERATURE SUPPLY VOLTAGE CASE TEMPERATURE
Figure 84. Figure 85. Figure 86.
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 19
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−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Harmonic Distortion − dBc
VOCM − Output Common-Mode Voltage − V
Single-Ended and
Differential Input
Gain = 1
VO = 2 VPP
Rf = 392
f= 8 MHz, VS = 5 V
HD2-Diff
HD2-SE
1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
HD3-SE
and Diff
−10
0
10
20
30
40
50
60
70
80
90
100
110
−1 0 1 2 3 4 5
Input Common-Mode Range − V
CMRR − Common-Mode Rejection Ratio − dB
VS = 5 V
−150
−100
−50
0
50
100
150
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Output Drive − mA
Case Temperature − °C
VS = 5 V Source
Sink
0
5
10
15
20
25
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Power-down Voltage − V
Quiescent Current − mA
VS = 5 V
−800
−600
−400
−200
0
200
400
600
800
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOC − Output Common-Mode Voltage − V
− Output Offset Voltage − mV
VOS
−3
−2
−1
0
1
2
3
4
0.1 1 10 100 1000
f − Frequency − MHz
Gain = 1
RL = 800
Rf = 392
PIN= −20 dBm
VS = 5 V
Small Signal Frequency Response at VOCM− dB
0
100
200
300
400
500
600
700
800
900
1000
1100
0.1 1 10 100 1000
− Single-Ended Output ImpedanceZOin Power Down −
f − Frequency − MHz
Gain = 1
RL = 400
Rf = 499
PIN = −1 dBm
VS = 5 V
−1
−2
−5
0 0.5 1 2
0
100.5101 102 103
−3
−6
−4
0
0.01
0.03
0.02
t − Time − ms
Power-Down Voltage Signal − V
Quiescent Current − mA
1.5 2.5 3
Current
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
RL = 800
VS = 5 V
0
100
200
300
400
500
600
700
800
Power-Down Quiescent Current − Aµ
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS: 5 V (continued) HARMONIC DISTORTION
OUTPUT DRIVE
COMMON-MODE REJECTION RATIO vs
vs vs OUTPUT COMMON-MODE
INPUT COMMON-MODE RANGE CASE TEMPERATURE VOLTAGE
Figure 87. Figure 88. Figure 89.
OUTPUT OFFSET VOLTAGE QUIESCENT CURRENT
vs
SMALL-SIGNAL FREQUENCY OUTPUT COMMON-MODE vs
RESPONSE AT VOCM VOLTAGE POWER-DOWN VOLTAGE
Figure 90. Figure 91. Figure 92.
SINGLE-ENDED OUTPUT POWER-DOWN QUIESCENT
IMPEDANCE IN POWER-DOWN CURRENT
TURN-ON AND TURN-OFF DELAY vs vs
TIME FREQUENCY CASE TEMPERATURE
Figure 93. Figure 94. Figure 95.
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0
100
200
300
400
500
600
700
800
900
1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS − Supply Voltage − V
Power-Down Quiescent Current − Aµ
THS4500
THS4501
www.ti.com
SLOS350F APRIL 2002REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS: 5 V (continued)
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
Figure 96.
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): THS4500 THS4501
VIN-
1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS-
VOUT-
PD
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
FULLY DIFFERENTIAL AMPLIFIERS Fully differential amplifiers are typically packaged in
Differential signaling offers a number of performance eight-pin packages, as shown in Figure 97. The
advantages in high-speed analog signal processing device pins include two inputs (VIN+, VIN), two
systems, including immunity to external outputs (VOUT, VOUT+), two power supplies (VS+, VS),
common-mode noise, suppression of even-order an output common-mode control pin (VOCM), and an
nonlinearities, and increased dynamic range. Fully optional power-down pin (PD).
differential amplifiers not only serve as the primary
means of providing gain to a differential signal chain,
but also provide a monolithic solution for converting
single-ended signals into differential signals for
easier, higher performance processing. The THS4500
family of amplifiers contains products in Texas
Instruments' expanding line of high-performance, fully
differential amplifiers. Information on fully differential
amplifier fundamentals, as well as implementation
specific information, is presented in the Applications
Section of this data sheet to provide a better
understanding of the operation of the THS4500 family
of devices, and to simplify the design process for Figure 97. Fully Differential Amplifier Pin Diagram
designs using these amplifiers.
A standard configuration for the device is shown in
APPLICATIONS SECTION Figure 97. The functionality of a fully differential
Fully Differential Amplifier Terminal Functions amplifier can be imagined as two inverting amplifiers
Input Common-Mode Voltage Range and the that share a common noninverting terminal (though
THS4500 Family the voltage is not necessarily fixed). For more
information on the basic theory of operation for fully
Choosing the Proper Value for the Feedback and differential amplifiers, refer to the Texas Instruments
Gain Resistors application note Fully Differential Amplifiers, literature
Application Circuits Using Fully Differential number SLOA054 , available for download
Amplifiers at www.ti.com.
Key Design Considerations for Interfacing to an
Analog-to-Digital Converter INPUT COMMON-MODE VOLTAGE RANGE
Setting the Output Common-Mode Voltage With AND THE THS4500 FAMILY
the VOCM Input The key difference between the THS4500/1 and the
Saving Power with Power-Down Functionality THS4502/3is the input common-mode range for the
Linearity: Definitions, Terminology, Circuit four devices. The THS4502 and THS4503 have an
Techniques, and Design Tradeoffs input common-mode range that is centered around
An Abbreviated Analysis of Noise in Fully midrail, and the THS4500 and THS4501 have an
Differential Amplifiers input common-mode range that is shifted to include
Printed-Circuit Board Layout Techniques for the negative power-supply rail. Selection of one or
Optimal Performance the other amplifier is determined by the nature of the
application. Specifically, the THS4500 and THS4501
Power Dissipation and Thermal Considerations are designed for use in single-supply applications
Power Supply Decoupling Techniques and where the input signal is ground-referenced, as
Recommendations depicted in Figure 98. The THS4502 and THS4503
Evaluation Fixtures, Spice Models, and are designed for use in single-supply or split-supply
Applications Support applications where the input signal is centered
Additional Reference Material between the power-supply voltages, as depicted in
Figure 99.
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Product Folder Link(s): THS4500 THS4501
VOUT)+VIN)(1–β)–VIN–(1–β))2VOCMβ
2β
VOUT– +–VIN)(1–β))VIN–(1–β))2VOCMβ
2β
VN+VIN–(1–β))VOUT)β
VOCM
+VS
VS
RSRG1
RG2
RF1
RF2
+
RT
+
-
-
β+RG
RF)RG
VP+VIN)(1–β))VOUT–β
VOCM
RG
RG
RF
RF
+
+
VP
VN
VOUT-
VOUT+
VIN+
VIN-
-
-
VOCM
+VS
VS
RSRG1
RG2
RF1
RF2
+
RT
+
-VS
-
-
THS4500
THS4501
www.ti.com
SLOS350F APRIL 2002REVISED OCTOBER 2011
(1)
(2)
(3)
Where:
(4)
Figure 98. Application Circuit for the THS4500
and THS4501, Featuring Single-Supply Operation NOTE: The equations denote the device inputs as VNand VP, and
the circuit inputs as VIN+ and VIN. (5)
With a Ground-Reference Input Signal
Figure 100. Diagram For Input Common-Mode
Figure 99. Application Circuit for the THS4500 Range Equations
and THS4501, Featuring Split-Supply Operation
With an Input Signal Referenced at the Midrail Table 1 and Table 2 depict the input common-mode
range requirements for two different input scenarios,
Equation 1 through Equation 5 are used to calculate an input referenced around the negative rail and an
the required input common-mode range for a given input referenced around midrail. The tables highlight
set of input conditions. the differing requirements on input common-mode
range, and illustrate the reasoning to choose either
The equations allow calculation of the input the THS4500/1 or the THS4502/3. For signals
common-mode range requirements, given information referenced around the negative power supply, the
about the input signal, the output voltage swing, the THS4500/1 should be chosen because its input
gain, and the output common-mode voltage. common-mode range includes the negative supply
Calculating the maximum and minimum voltage rail. For all other situations, the THS4502/3 offers
required for VNand VP(the amplifier input nodes) slightly improved distortion and noise performance for
determines whether or not the input common-mode applications with input signals centered between the
range is violated or not. Four equations are required: power-supply rails.
two calculate the output voltages and two calculate
the node voltages at VNand VP(note that only one of
these nodes needs calculation, because the amplifier
forces a virtual short between the two nodes).
Table 1. Negative-Rail Referenced
Gain VIN+ VINVIN VOCM VOD VNMIN VNMAX
(V/V) (V) (V) (VPP) (V) (VPP) (V) (V)
12.0 to 2.0 0 4 2.5 4 0.75 1.75
21.0 to 1.0 0 2 2.5 4 0.5 1.167
40.5 to 0.5 0 1 2.5 4 0.3 0.7
80.25 to 0.25 0 0.5 2.5 4 0.167 0.389
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): THS4500 THS4501
Gain ǒVOD
VIN Ǔ
RSR3
R1
R4
+
RT
+
V
PVOCM
-
-
VS
Vout+
Vout-
V
n
R2
RT+1
1
RS1– K
2(1)K)
R3
K+R2
R1 R2 +R4
R3 +R1 *ǒRs|| RTǓ
β1+R1
R1 )R2 β2+R3 )RT|| RS
R3 )RT|| RS)R4
VOD
VS+2ǒ1–β2
β1)β2Ǔǒ RT
RT)RSǓ
VOD
VIN +2ǒ1–β2
β1)β2Ǔ
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
Table 2. Midrail Referenced
Gain VIN+ VINVIN VOCM VOD VNMIN VNMAX
(V/V) (V) (V) (VPP) (V) (VPP) (V) (V)
1 0.5 to 4.5 2.5 4 2.5 4 2 3
2 1.5 to 3.5 2.5 2 2.5 4 2.16 2.83
4 2.0 to 3.0 2.5 1 2.5 4 2.3 2.7
8 2.25 to 2.75 2.5 0.5 2.5 4 2.389 2.61
Table 3. Resistor Values for Balanced Operation
CHOOSING THE PROPER VALUE FOR THE in Various Gain Configurations
FEEDBACK AND GAIN RESISTORS
The selection of feedback and gain resistors impacts R2 and R4 R1 () R3 () RT()
circuit performance in a number of ways. The values ()
presented in this section provide the optimum
high-frequency performance (lowest distortion, flat 1 392 412 383 54.9
frequency response). Since the THS4500 family of 1 499 523 487 53.6
amplifiers is developed with a voltage feedback 2 392 215 187 60.4
architecture, the choice of resistor values does not 2 1.3 k 665 634 52.3
have a dominant effect on bandwidth, unlike a
current-feedback amplifier. However, resistor choices 5 1.3 k 274 249 56.2
do have second-order effects. For optimal 5 3.32 k 681 649 52.3
performance, the following feedback resistor values 10 1.3 k 147 118 64.9
are recommended. In higher gain configurations (gain 10 6.81 k 698 681 52.3
greater than two), the feedback resistor values have
much less effect on the high-frequency performance.
Example feedback and gain resistor values are given
in the section on basic design considerations
(Table 3).
Amplifier loading, noise, and the flatness of the
frequency response are three design parameters that
should be considered when selecting feedback
resistors. Larger resistor values contribute more noise
and can induce peaking in the ac response in low
gain configurations; smaller resistor values can load
the amplifier more heavily, resulting in a reduction in
distortion performance. In addition, feedback resistor Figure 101. Diagram for Design Calculations
values, coupled with gain requirements, determine
the value of the gain resistors and directly impact the Equations for calculating fully differential amplifier
input impedance of the entire circuit. While there are resistor values in order to obtain balanced operation
no strict rules about resistor selection, these trends in the presence of a 50-source impedance are
can provide qualitative design guidance. given in Equation 6 through Equation 9.
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
Fully differential amplifiers provide designers with a (6)
great deal of flexibility in a wide variety of
applications. This section provides an overview of
some common circuit configurations and gives some (7)
design guidelines. Designing the interface to an
analog-to-digital converter (ADC), driving lines
differentially, and filtering with fully differential (8)
amplifiers are a few of the circuits that are covered.
(9)
BASIC DESIGN CONSIDERATIONS
The circuits in Figure 98 through Figure 101 are used
to highlight basic design considerations for fully
differential amplifier circuit designs.
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SLOS350F APRIL 2002REVISED OCTOBER 2011
For more detailed information about balance in fully voltage regardless of the load impedance present.
differential amplifiers, see the application report, Fully Terminating the output of a fully differential
Differential Amplifiers (SLOA054), referenced at the amplifier with a heavy load adversely affects the
end of this data sheet. amplifier linearity.
Comprehend the VOCM input drive requirements.
INTERFACING TO AN ANALOG-TO-DIGITAL Determine if the ADC voltage reference can
CONVERTER provide the required amount of current to move
VOCM to the desired value. A buffer may be
The THS4500 family of amplifiers are designed needed.
specifically to interface to today's Decouple the VOCM pin to eliminate the antenna
highest-performance ADCs. This section highlights effect. VOCM is a high-impedance node that can
the key concerns when interfacing to an ADC and act as an antenna. A large decoupling capacitor
provides example interface circuits. on this node eliminates this problem.
There are several key design concerns when Know the input common-mode range. If the input
interfacing to an analog-to-digital converter: signal is referenced around the negative
Terminate the input source properly. In power-supply rail (for example, around ground on
high-frequency receiver chains, the source that a single 5 V supply), then the THS4500/1
feeds the fully differential amplifier requires a accommodates the input signal. If the input signal
specific load impedance (that is, 50 ). is referenced around midrail, choose the
Design a symmetric printed circuit board (PCB) THS4502/3 for the best operation.
layout. Even-order distortion products are heavily Packaging makes a difference at higher
influenced by layout, and careful attention to a frequencies. If possible, choose the smaller,
symmetric layout minimizes these distortion thermally-enhanced MSOP package for the best
products. performance. As a rule, lower junction
Minimize inductance in power-supply decoupling temperatures provide better performance. If
traces and components. Poor power-supply possible, use a thermally-enhanced package,
decoupling can have a dramatic effect on circuit even if the power dissipation is relatively small
performance. Since the outputs are differential, compared to the maximum power dissipation
differential currents exist in the power-supply pins. rating to achieve the best results.
Thus, decoupling capacitors should be placed in a Understand the effect of the load impedance seen
manner that minimizes the impedance of the by the fully differential amplifier when performing
current loop. system-level intercept point calculations. Lighter
Use separate analog and digital power supplies loads (such as those presented by an ADC) allow
and grounds. Noise (bounce) in the power smaller intercept points to support the same level
supplies (created by digital switching currents) can of intermodulation distortion performance.
couple directly into the signal path, and
power-supply noise can create higher distortion EXAMPLE ANALOG-TO-DIGITAL
products as well. CONVERTER DRIVER CIRCUITS
Use care when filtering. While an RC low-pass The THS4500 family of devices is designed to drive
filter may be desirable on the output of the high-performance ADCs with extremely high linearity,
amplifier to filter broadband noise, the excess allowing for the maximum effective number of bits at
loading can negatively impact the amplifier the output of the data converter. Two representative
linearity. Filtering in the feedback path does not circuits shown below highlight single-supply operation
have this effect. and split supply operation, respectively. Specific
AC-coupling allows easier circuit design. If feedback resistor, gain resistor, and feedback
dc-coupling is required, be aware of the excess capacitor values are not shown, as these values
power dissipation that can occur due to depend on the frequency of interest. Information on
level-shifting the output through the output calculating these values can be found in the
common-mode voltage control. applications material above.
Do not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-
termination for proper operation, but closed-loop
fully differential amplifiers drive a specific output
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): THS4500 THS4501
VOCM
15V
VS
RSRGRF
RF
+
RT
+
RG
CG
0.1 mF
CG
THS4500/2 VDD
CS
CS
RL
VOD =26VPP
RISO
RISO
-
-
+
+
VOCM 12-Bit/80MSPS
IN
IN
5 V
CM
5 V
5 V
VS
10 mF 0.1 mF
10 mF 0.1 mF
THS4503
RF
RF
CF
CF
1mF
RG
RG0.1 mF
RT
RS
ADS5410
RISO
RISO
-
-
+
+
VOCM 14-Bit/40MSPS
IN
IN
5 V
CM
5 V
VS
10 mF 0.1 mF
THS4501
RF
RF
CF
CF
1mF
RG
RG
RT
RS
ADS5421
0.1 mF
RISO
RISO
-
-
VS
RSRG1 RF1
R
F2
+
RT
+
VO
RISO
C
CF2
CF1
RG2 RISO
-
-
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
Figure 104. Fully Differential Line Driver With
High Output Swing
Figure 102. Using the THS4503 With the ADS5410 FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
Similar to single-ended counterparts, fully differential
amplifiers have the ability to couple filtering
functionality with voltage gain. Numerous filter
topologies can be based on fully differential
amplifiers. Several of these are outlined in the
application report A Differential Circuit Collection
(literature number SLOA064), referenced at the end
of this data sheet. The circuit below depicts a simple,
two-pole, low-pass filter applicable to many different
types of systems. The first pole is set by the resistors
and capacitors in the feedback paths, and the second
pole is set by the isolation resistors and the capacitor
across the outputs of the isolation resistors.
Figure 103. Using the THS4501 With the ADS5421
FULLY DIFFERENTIAL LINE DRIVERS
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers.
The high power-supply voltage rating (16.5 V
absolute maximum) allows operation on a single 12-V
or a single 15-V supply. The high supply voltage,
coupled with the ability to provide differential outputs,
enables the ability to drive 26 VPP into reasonably
heavy loads (250 or greater). The circuit in Figure 105. A Two-Pole, Low-Pass Filter Design
Figure 104 illustrates the THS4500 family of devices Using a Fully Differential Amplifier With Poles
used as high-speed line drivers. For line driver Located at: P1 = (2πRFCF)1in Hz and
applications, close attention must be paid to thermal P2 = (4πRISOC)1in Hz
design constraints because of the typically high level
of power dissipation. Often, filters like these are used to eliminate
broadband noise and out-of-band distortion products
in signal acquisition systems. It should be noted that
the increased load placed on the output of the
amplifier by the second low-pass filter has a
26 Submit Documentation Feedback Copyright ©20022011, Texas Instruments Incorporated
Product Folder Link(s): THS4500 THS4501
R =50kW
R =50kW
VS+
VS-
VOCM
IIN
IIN =
2 VOCM V-S+ -VS-
R
VOCM =2.5V
5V
VS
RSRG1
RG2
RF1
RF2
+
RT
+RL
2.5-VDC
2.5-VDC
DCCurrentPathtoGround
DCCurrentPathtoGround
I2=VOCM
RF2 +RG2
I1=VOCM
RF1+RG1+RS||RT
-
-
THS4500
THS4501
www.ti.com
SLOS350F APRIL 2002REVISED OCTOBER 2011
detrimental effect on the distortion performance. The capacitance is a reasonable value for eliminating a
preferred method of filtering is to use the feedback great deal of broadband interference, but additional,
network, as the typically smaller capacitances tuned decoupling capacitors should be considered if a
required at these points in the circuit do not load the specific source of electromagnetic or radio frequency
amplifier nearly as heavily in the passband. interference is present elsewhere in the system.
Information on the ac performance (bandwidth, slew
rate) of the VOCM circuitry is included in the Electrical
SETTING THE OUTPUT COMMON-MODE Characteristics and Typical Characterisitcs sections.
VOLTAGE WITH THE VOCM INPUT Since the VOCM pin provides the ability to set an
The output common-mode voltage pin provides a output common-mode voltage, the ability for
critical function to the fully differential amplifier; it increased power dissipation exists. While this
accepts an input voltage and reproduces that input possibility does not pose a performance problem for
voltage as the output common-mode voltage. In other the amplifier, it can cause additional power
words, the VOCM input provides the ability to level-shift dissipation of which the system designer should be
the outputs to any voltage inside the output voltage aware. The circuit shown in Figure 107 demonstrates
swing of the amplifier. an example of this phenomenon. For a device
A description of the input circuitry of the VOCM pin is operating on a single 5-V supply with an input signal
shown in Figure 106 to facilitate an easier referenced around ground and an output
understanding of the VOCM interface requirements. common-mode voltage of 2.5 V, a dc potential exists
The VOCM pin has two 50-kresistors between the between the outputs and the inputs of the device. The
power supply rails to set the default output amplifier sources current into the feedback network in
common-mode voltage to midrail. A voltage applied to order to provide the circuit with the proper operating
the VOCM pin alters the output common-mode voltage point. While there are no serious effects on the circuit
as long as the source has the ability to provide performance, the extra power dissipation may need to
enough current to overdrive the two 50-kresistors. be included in the system power budget.
This phenomenon is depicted in the VOCM equivalent
circuit diagram. Current drive is especially important
when using the reference voltage of an
analog-to-digital converter to drive VOCM. Output
current drive capabilities differ from part to part, so a
voltage buffer may be necessary in some
applications.
Figure 106. Equivalent Input Circuit for VOCM Figure 107. Depiction of DC Power Dissipation
Caused By Output Level-Shifting in a DC-Coupled
Circuit
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal.
As shown in Figure 106, the VOCM input has a high
impedance associated with it, dictated by the two
50-kresistors. While the high impedance allows for
relaxed drive requirements, it also allows the pin and
any associated PCB traces to act as an antenna. For
this reason, a decoupling capacitor is recommended
on this node for the sole purpose of filtering any
high-frequency noise that could couple into the signal
path through the VOCM circuitry. A 0.1-μF or 1-μF
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): THS4500 THS4501
IMD3 = PS − PO
PS
PO
PO
fc = fc − f1
fc = f2 − fc
PS
fc − 3f f1 fcf2 fc + 3f
Power
f − Frequency − MHz
IMD3
OIP3
IIP3
3X
PIN
(dBm)
1X
POUT
(dBm)
PO
PS
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
SAVING POWER WITH POWER-DOWN etc.). Use of the intercept point, rather than strictly the
FUNCTIONALITY intermodulation distortion, allows for simpler
system-level calculations. Intercept points, like noise
The THS4500 family of fully differential amplifiers figures, can be easily cascaded back and forth
contains devices that come with and without the through a signal chain to determine the overall
power-down option. Even-numbered devices have receiver chain intermodulation distortion performance.
power-down capability, which is described in detail The relationship between intermodulation distortion
here. and intercept point is depicted in Figure 108 and
Figure 109.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (that is, an internal pull-up resistor is present),
putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and given in the specification tables. Above the
enable threshold voltage, the device is on. Below the
disable threshold voltage, the device is off. Behavior
between these threshold voltages is not specified.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain Figure 108. 2-Tone and 3rd-Order
setting resistors. Intermodulation Products
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
The THS4500 family of devices features
unprecedented distortion performance for monolithic
fully differential amplifiers. This section focuses on
the fundamentals of distortion, circuit techniques for
reducing nonlinearity, and methods for equating
distortion of fully differential amplifiers to desired
linearity specifications in RF receiver chains.
Amplifiers are generally thought of as linear devices.
In other words, the output of an amplifier is a linearly
scaled version of the input signal applied to it. In
reality, however, amplifier transfer functions are
nonlinear. Minimizing amplifier nonlinearity is a
primary design goal in many applications. Figure 109. Graphical Representation of 2-Tone
and 3rd-Order Intercept Point
Intercept points are specifications that have long
been used as key design criteria in the RF Due to the intercept point ease-of-use in system level
communications world as a metric for the calculations for receiver chains, it has become the
intermodulation distortion performance of a device in specification of choice for guiding distortion-related
the signal chain (for example, amplifiers, mixers,
28 Submit Documentation Feedback Copyright ©20022011, Texas Instruments Incorporated
Product Folder Link(s): THS4500 THS4501
40
30
20
15 0 10 20 30 40 50 60
50
55
f − Frequency − MHz
60
70 80 90 100
45
35
25
Normalized to 200
Gain = 1
Rf = 392
VS = ± 5 V
Tone Spacing = 200 kHz
OIP3 RL= 800
Normalized to 50
− Third-Order Output Intercept Point − dBm
OIP3
OIP3+PO)ǒŤIMD3Ť
2Ǔwhere
PO+10 logǒV2
Pdiff
2RL 0.001Ǔ
NOTE: Po is the output power of a single tone, RL is the
differential load resistance, and VP(diff) is the differential
peak voltage for a single tone.
THS4500
THS4501
www.ti.com
SLOS350F APRIL 2002REVISED OCTOBER 2011
design decisions. Traditionally, these systems use
primarily class-A, single-ended RF amplifiers as gain
blocks. These RF amplifiers are typically designed to
operate in a 50-environment, just like the rest of
the receiver chain. Since intercept points are given in
dBm, this implies an associated impedance (50 ).
However, with a fully differential amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to the outputs regardless of the impedance present, it
is important to comprehend this feature when
evaluating the intercept point of a fully differential
amplifier. The THS4500 series of devices yields
optimum distortion performance when loaded with
200 to 1 k, very similar to the input impedance of Figure 110. Equivalent 3rd-Order Intercept Point
an analog-to-digital converter over its input frequency for the THS4500
band. As a result, terminating the input of the ADC to
50 can actually be detrimental to system Comparing specifications between different device
performance. types becomes easier when a common impedance
This discontinuity between open-loop, class-A level is assumed. For this reason, the intercept points
amplifiers and closed-loop, class-AB amplifiers on the THS4500 family of devices are reported
becomes apparent when comparing the intercept normalized to a 50-load impedance.
points of the two types of devices. Equation 10 gives
the definition of an intercept point, relative to the AN ANALYSIS OF NOISE IN FULLY
intermodulation distortion. DIFFERENTIAL AMPLIFIERS
Noise analysis in fully differential amplifiers is
(10) analogous to noise analysis in single-ended
amplifiers; the same concepts apply. Figure 111
shows a generic circuit diagram consisting of a
voltage source, a termination resistor, two gain
setting resistors, two feedback resistors, and a fully
differential amplifier is shown, including all the
relevant noise sources. From this circuit, the noise
factor (F) and noise figure (NF) are calculated. The
(11) figures indicate the appropriate scaling factor for each
As can be seen in the equations, when a higher of the noise sources in two different cases. The first
impedance is used, the same level of intermodulation case includes the termination resistor, and the
distortion performance results in a lower intercept second, simplified case assumes that the voltage
point. Therefore, it is important to understand the source is properly terminated by the gain-setting
impedance seen by the output of the fully differential resistors. With these scaling factors, the amplifier
amplifier when selecting a minimum intercept point. input noise power (NA) can be calculated by summing
Figure 110 shows the relationship between the strict each individual noise source with its scaling factor.
definition of an intercept point with a normalized, or The noise delivered to the amplifier by the source (NI)
equivalent, intercept point for the THS4500. and input noise power are used to calculate the noise
factor and noise figure as shown in Equation 23
through Equation 27.
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): THS4500 THS4501
ȧ
ȡ
Ȣ
Rg
Rf)Rg
Rg)Rs
2ȧ
ȣ
Ȥ
2
(eni)2
NA: Fully Differential Amplifier; termination = 2Rg
Noise
Source Scale Factor
(ini)2Rg2
(iii)2Rg2
NiNARgRf
egef
es
Rs
enNo
ini
iii
Rt
et
Ni
Si
No
So
+
fully-diff
amp
RgRf
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2 ǒRg
RfǓ2
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Rg
Rg)Rs
2ȧ
ȣ
Ȥ
2
Ni+4kTRsȧ
ȧ
ȧ
ȧ
ȡ
Ȣ
2RtRg
Rt)2Rg
Rs)2RtRg
Rt)2Rg
ȧ
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Ȣ
Rg
Rf)
Rg
Rg)RsRt
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ȣ
Ȥ
2
(eni)2
NA: Fully Differential Amplifier
Noise
Source Scale Factor
(ini)2Rg2
(iii)2Rg2
2
N =4kTR
i S
2RG
R +2R
S G
N = (NoiseSource ScaleFactor)S ´
A
4kTRtȧ
ȡ
Ȣ
2RsRG
Rs)2Rg
Rt)2RsRg
Rs)2Rg
ȧ
ȣ
Ȥ
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F=1+
NA
NI
4kTRf2 ǒRg
RfǓ2
NF +10 log (F)
4kTRg2
ȧ
ȧ
ȡ
Ȣ
Rg
Rg)RsRt
2ǒRs)RtǓȧ
ȧ
ȣ
Ȥ
2
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
Scaling Factors for Individual Noise Sources
Asseming No Termination Resistance is Used
(that is, RTis Open)
(18)
(19)
(20)
(21)
Figure 111. Noise Sources in a Fully Differential
Amplifier Circuit
Scaling Factors for Individual Noise Sources (22)
Assuming a Finite Value Termination Resistor Input Noise With a Termination Resistor
(23)
(12) Input Noise Assuming No Termination Resistor
(13)
(14)
(24)
Noise Factor and Noise Figure Calculations (25)
(15)
(26)
(16) (27)
(17)
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THS4501
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SLOS350F APRIL 2002REVISED OCTOBER 2011
PRINTED CIRCUIT BOARD LAYOUT capacitance can add a pole and/or a zero below
TECHNIQUES FOR OPTIMAL 400 MHz that can affect circuit operation. Keep
PERFORMANCE resistor values as low as possible, consistent with
load driving considerations.
Achieving optimum performance with high frequency Connections to other wideband devices on the
amplifier-like devices in the THS4500 family requires board may be made with short direct traces or
careful attention to PCB layout parasitic and external through onboard transmission lines. For short
component types. connections, consider the trace and the input to
Recommendations that optimize performance include: the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils, or 1.27
Minimize parasitic capacitance to any ac ground mm to 2.54 mm) should be used, preferably with
for all of the signal I/O pins. Parasitic capacitance ground and power planes opened up around
on the output and input pins can cause instability. them. Estimate the total capacitive load and
To reduce unwanted capacitance, a window determine if isolation resistors on the outputs are
around the signal I/O pins should be opened in all necessary. Low parasitic capacitive loads (less
of the ground and power planes around those than 4 pF) may not need an RSsince the
pins. Otherwise, ground and power planes should THS4500 family is nominally compensated to
be unbroken elsewhere on the board. operate with a 2-pF parasitic load. Higher parasitic
Minimize the distance (<0.25, 6.35 mm) from the capacitive loads without an RSare allowed as the
power-supply pins to high frequency 0.1-μFsignal gain increases (increasing the unloaded
decoupling capacitors. At the device pins, the phase margin). If a long trace is required, and the
ground and power-plane layout should not be in 6-dB signal loss intrinsic to a doubly-terminated
close proximity to the signal I/O pins. Avoid transmission line is acceptable, implement a
narrow power and ground traces to minimize matched impedance transmission line using
inductance between the pins and the decoupling microstrip or stripline techniques (consult an ECL
capacitors. The power supply connections should design handbook for microstrip and stripline layout
always be decoupled with these capacitors. techniques).
Larger (6.8 μF or more) tantalum decoupling A 50-environment is normally not necessary
capacitors, effective at lower frequency, should onboard, and in fact, a higher impedance
also be used on the main supply pins. These may environment improves distortion as shown in the
be placed somewhat farther from the device and distortion versus load plots. With a characteristic
may be shared among several devices in the board trace impedance defined based onboard
same area of the PCB. The primary goal is to material and trace dimensions, a matching series
minimize the impedance seen in the resistor into the trace from the output of the
differential-current return paths. THS4500 family is used as well as a terminating
Careful selection and placement of external shunt resistor at the input of the destination
components preserve the high-frequency device.
performance of the THS4500 family. Resistors Remember also that the terminating impedance is
should be a very low reactance type. the parallel combination of the shunt resistor and
Surface-mount resistors work best and allow a the input impedance of the destination device: this
tighter overall layout. Metal-film and carbon total effective impedance should be set to match
composition, axially-leaded resistors can also the trace impedance. If the 6-dB attenuation of a
provide good high frequency performance. Again, doubly-terminated transmission line is
keep the leads and PCB trace length as short as unacceptable, a long trace can be
possible. Never use wirewound type resistors in a series-terminated at the source end only. Treat
high-frequency application. Since the output pin the trace as a capacitive load in this case. This
and inverting input pins are the most sensitive to configuration does not preserve signal integrity as
parasitic capacitance, always position the well as a doubly-terminated line. If the input
feedback and series output resistors, if any, as impedance of the destination device is low, there
close as possible to the inverting input pins and is some signal attenuation due to the voltage
output pins. Other network components, such as divider formed by the series output into the
input termination resistors, should be placed close terminating impedance.
to the gain-setting resistors. Even with a low
parasitic capacitance shunting the external Socketing a high-speed part such as the THS4500
resistors, excessively high resistor values can family is not recommended. The additional lead
create significant time constants that can degrade length and pin-to-pin capacitance introduced by
performance. Good axial metal-film or the socket can create an extremely troublesome
surface-mount resistors have approximately parasitic network that can make it almost
0.2 pF in shunt with the resistor. For resistor impossible to achieve a smooth, stable frequency
values greater than 2.0 k, this parasitic response. Best results are obtained by soldering
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): THS4500 THS4501
0.060
0.040
0.075 0.025
0.205
0.010
vias
Pin 1
Top View
0.017
0.035
0.094
0.030
0.013
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
the THS4500 family parts directly onto the board.
PowerPAD DESIGN CONSIDERATIONS
The THS4500 family is available in a
thermally-enhanced PowerPAD set of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 112(a) and Figure 112(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 112(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad.
The PowerPAD package allows for both assembly Figure 113. PowerPAD PCB Etch and Via Pattern
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad PowerPAD PCB LAYOUT CONSIDERATIONS
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this 1. Prepare the PCB with a top side etch pattern as
copper area, heat can be conducted away from the shown in Figure 113. There should be etch for
package into either a ground plane or other heat the leads as well as etch for the thermal pad.
dissipating device. 2. Place five holes in the area of the thermal pad.
These holes should be 13 mils (0.33 mm) in
The PowerPAD package represents a breakthrough diameter. Keep them small so that solder wicking
in combining the small area and ease of assembly of through the holes is not a problem during reflow.
surface mount with the, heretofore, awkward
mechanical methods of heatsinking. 3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. These holes help dissipate the heat
generated by the THS4500 family IC. These
additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad.
They can be larger because they are not in the
thermal pad area to be soldered so that wicking
is not a problem.
4. Connect all holes to the internal ground plane.
Figure 112. Views of PowerPAD, 5. When connecting these holes to the ground
Thermally-Enhanced Package plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
Although there are many ways to properly heatsink useful for slowing the heat transfer during
the PowerPAD package, the following steps illustrate soldering operations. This transfer slowing makes
the recommended approach. the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
complete connection around the entire
circumference of the plated-through hole.
32 Submit Documentation Feedback Copyright ©20022011, Texas Instruments Incorporated
Product Folder Link(s): THS4500 THS4501
2
1.5
1
0
−40 −20 0 20
− Maximum Power Dissipation − W
2.5
3
3.5
40 60 80
TA − Ambient Temperature − °C
PD
8-Pin DGN Package
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
ΤJ = 150°C, No Airflow
0.5
8-Pin D Package
P =
Dmax
T T-
MAX A
qJA
THS4500
THS4501
www.ti.com
SLOS350F APRIL 2002REVISED OCTOBER 2011
6. The top-side solder mask should leave the Maximum power dissipation levels are depicted in
terminals of the package and the thermal pad Figure 114 for the two packages. The data for the
area with its five holes exposed. The bottom-side DGN package assumes a board layout that follows
solder mask should cover the five holes of the the PowerPAD layout guidelines referenced above
thermal pad area. This configuration prevents and detailed in the PowerPAD application notes in
solder from being pulled away from the thermal the Additional Reference Material section at the end
pad area during the reflow process. of the data sheet.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This process results
in a part that is properly installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer
must take care to ensure that the design does not
violate the absolute maximum junction temperature of
the device. Failure may result if the absolute
maximum junction temperature of +150°C is
exceeded. For best performance, design for a
maximum junction temperature of +125°C. Between Figure 114. Maximum Power Dissipation vs
+125°C and +150°C, damage does not occur, but the Ambient Temperature
performance of the amplifier begins to degrade. When determining whether or not the device satisfies
The thermal characteristics of the device are dictated the maximum power dissipation requirement, it is
by the package and the PCB. Maximum power important to not only consider quiescent power
dissipation for a given package can be calculated dissipation, but also dynamic power dissipation. Often
using the following formula. times, this consideration is difficult to quantify
because the signal pattern is inconsistent; an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
Where:
PDmax is the maximum power dissipation in the DRIVING CAPACITIVE LOADS
amplifier (W). High-speed amplifiers are typically not well-suited for
TMAX is the absolute maximum junction driving large capacitive loads. If necessary, however,
temperature (°C). the load capacitance should be isolated by two
TAis the ambient temperature (°C). isolation resistors in series with the output. The
θJA =θJC +θCA requisite isolation resistor size depends on the value
of the capacitance, but 10 to 25 is a good place
θJC is the thermal coefficient from the silicon to begin the optimization process. Larger isolation
junctions to the case (°C/W). resistors decrease the amount of peaking in the
θCA is the thermal coefficient from the case to frequency response induced by the capacitive load,
ambient air (°C/W). (28) but this decreased peaking comes at the expense ofa
For systems where heat dissipation is more critical, larger voltage drop across the resistors, increasing
the THS4500 family of devices is offered in an the output swing requirements of the system.
MSOP-8 package with PowerPAD. The thermal
coefficient for the MSOP PowerPAD package is
substantially improved over the traditional SOIC.
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): THS4500 THS4501
VS
RSRG
RF
RF
+
RT+
RISO
CL
RG
Riso=10 25- W
VS
-VS
RISO
-
-
_
+
4
5
3
7
26
VOCM S
PwrPad
VS
PD
1
8
R0805
R4
C4 C0805
R5 R0805
C3
C0805
R6
R7
R0805
R0805
C5
C6
C0805
C0805
C7
C0805
J2
J3
J2
J3
R2
R0805
R3
R0805
C1
C0805
C2
C0805
R1
R1206
J1
3
1
4
5
6
R11
R1206
R9
R0805
R8
R9
R0805
R0805
J2
J3
J4
T1
U1
THS450X
-V
THS4500
THS4501
SLOS350F APRIL 2002REVISED OCTOBER 2011
www.ti.com
THS4501 product folder on the Texas Instruments
web site, www.ti.com, or through your local Texas
Instruments sales representative. A schematic for the
evaluation board is shown in Figure 116 with the
default component values. Unpopulated footprints are
shown to provide insight into design flexibility.
Figure 115. Use of Isolation Resistors With a
Capacitive Load
POWER-SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
Power-supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of
performance. Figure 116. Simplified Schematic of the
Evaluation Board
1. Place decoupling capacitors as close to the
power-supply inputs as possible, with the goal of
minimizing the inductance of the path from Computer simulation of circuit performance using
ground to the power supply. SPICE is often useful when analyzing the
performance of analog circuits and systems. This
2. Placement priority should be as follows: smaller practice is particularly true for video and RF amplifier
capacitors should be closer to the device. circuits where parasitic capacitance and inductance
3. Use of solid power and ground planes is can have a major effect on circuit performance. A
recommended to reduce the inductance along SPICE model for the THS4500 family of devices is
power-supply return current paths. available through either the Texas Instruments web
4. Recommended values for power-supply site (www.ti.com) or as one model on a disk from the
decoupling include 10-μF and 0.1-μF capacitors Texas Instruments Product Information Center
for each supply. A 1000-pF capacitor can be (1-800-548-6132). The PIC is also available for
used across the supplies as well for extremely design assistance and detailed product information at
high frequency return currents, but often is not this number. These models do a good job of
required. predicting small-signal ac and transient performance
under a wide variety of operating conditions. They are
EVALUATION FIXTURES, SPICE MODELS, not intended to model the distortion characteristics of
AND APPLICATIONS SUPPORT the amplifier, nor do they attempt to distinguish
between the package types in their small-signal ac
Texas Instruments is committed to providing its performance. Detailed information about what is and
customers with the highest quality of applications is not modeled is contained in the model file itself.
support. To support this goal, an evaluation board
has been developed for the THS4500 family of fully
differential amplifiers. The evaluation board can be
obtained by ordering through the THS4500 or
34 Submit Documentation Feedback Copyright ©20022011, Texas Instruments Incorporated
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THS4501
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SLOS350F APRIL 2002REVISED OCTOBER 2011
ADDITIONAL REFERENCE MATERIAL
PowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004.
PowerPAD Thermally-Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002.
Karki, James. Fully Differential Amplifiers. application report, Texas Instruments Literature Number
SLOA054D.
Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, and
Differential Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.
Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature
Number SLOA064.
Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments
Literature Number SLOA072.
Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog
Applications Journal, July 2001.
REVISION HISTORY
Changes from Revision D (January 2004) to Revision E Page
Updated document format .................................................................................................................................................... 1
Added footnote 1 to Package/Ordering Information table .................................................................................................... 3
Changed x-axis of Figure 27 ............................................................................................................................................... 12
Updated crossreferences for Figure 97 in first two paragraphs of the Fully Differential Amplifier Terminal Functions
section ................................................................................................................................................................................. 22
Added available for download at www.ti.com and end of second paragraph of the Fully Differential Amplifier
Terminal Functions section ................................................................................................................................................. 22
Changed allow for calculation of to are used to calculate in second paragraph of Input Common-Mode Voltage
Range and the THS4500 Family section ............................................................................................................................ 22
Clarified last sentence of third paragraph of Input Common-Mode Voltage Range and the THS4500 Family section ..... 22
Changed two to four in first sentence of Input Common-Mode Voltage Range and the THS4500 Family section ........... 22
Corrected title of Basic Design Considerations section ...................................................................................................... 24
Clarified cross-references of the circuits mentioned in the first sentence of the Basic Design Considerations section .... 24
Deleted figure from Basic Design Considerations section .................................................................................................. 24
Corrected cross-references in first sentence of Basic Design Considerations section ...................................................... 24
Clarified the Interfacing to an Analog-to-Digital Converter section ..................................................................................... 25
Removed cross-reference to nonexistant tble in second paragraph of Setting the Output Common-Mode Voltage
with the V OCM Input section ................................................................................................................................................ 27
Added caption titles to figures in the Linearity: Definitions, Terminology, Circuit Techniques, and Design Treadeoffs
section ................................................................................................................................................................................. 28
Changed THS4502 to THS4500 in seventh paragraph of Linearity: Definitions, Terminology, Circuit Techniques, and
Design Treadeoffs section .................................................................................................................................................. 28
Corrected spelling in title of An Analysis of Noise in Fully Differential Amplifiers section .................................................. 29
Added 6.35 mm to second bullet of Printed Circuit Board Layout Techniques for Optimal Performance list .................... 31
Added 1.27 mm to 2.54 mm to fourth bullet of Printed Circuit Board Layout Techniques for Optimal Performance list ... 31
Added 0.33 mm to second list item in the PowerPAD PCB Layout Considerations section .............................................. 32
Changed title of Figure 116 ................................................................................................................................................ 34
Changes from Revision E (MAy 2008) to Revision F Page
Added Figure 101 to the Basic Design Considerations section ......................................................................................... 24
Copyright ©20022011, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): THS4500 THS4501
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4500CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500CDGKR ACTIVE VSSOP DGK 8 TBD Call TI Call TI
THS4500CDGKRG4 ACTIVE VSSOP DGK 8 TBD Call TI Call TI
THS4500CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4500IDR ACTIVE SOIC D 8 TBD Call TI Call TI
THS4500IDRG4 ACTIVE SOIC D 8 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4501CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4501IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4500CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4500IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4501IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4500CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4500IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4501IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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