A6277 8-Bit Serial Input Constant-Current Latched LED Driver Features and Benefits Description Up to 150 mA constant-current outputs Undervoltage lockout Low-power CMOS logic and latches High data input rate Similar to Toshiba TD62715FN High/low output current function Digital dimming control The A6277 is specifically designed for LED display applications. Each BiCMOS device includes an 8-bit CMOS shift register, accompanying data latches, and eight NPN constant-current sink drivers. Two package styles and two operating temperature ranges are available. Packages 20-pin DIP (A package) 20-pin SOICW (LW package) The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V logic supply, typical serial data-input rates are up to 20 MHz. The LED drive current is determined by the user selection of a single resistor. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. For inter-digit blanking, all output drivers can be disabled with an ENABLE input high. In addition, a HIGH/LOW function enables full selected current with the application of a logic low, or 50% selected current with the application of a logic high. Two package styles are provided, a through-hole DIP (suffix A), and a surface-mount SOIC (LW). The copper leadframe and low logic-power dissipation allow the DIP to sink 122 mA through all outputs continuously over the operating temperature range (1.0 V drop, 85C). Both packages are lead (Pb) free, with 100% matte-tin leadframe plating. Not to scale Functional Block Diagram 26185.202F A6277 8-Bit Serial Input Constant-Current Latched LED Driver Selection Guide Part Number Packing Package A6277EA-T* 20-pin DIP 18 per tube A6277ELWTR-T 20-pin SOICW 1000 per reel *Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change November 2, 2009. Deadline for receipt of LAST TIME BUY orders is April 30, 2010. Absolute Maximum Ratings* Characteristic Symbol Notes Rating Units Supply Voltage VDD 7.0 V Output Voltage Range VO -0.5 to 24 V Input Voltage Voltage VI -0.4 to VDD + 0.4 V Output Current IO 150 mA Operating Ambient Temperature TA -40 to 85 C Maximum Junction Temperature TJ(max) 150 C Tstg -55 to 150 C Storage Temperature Range E * Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol RJA Package Thermal Resistance Test Conditions* Value Units Package A, on 1-layer PCB 60 C/W Package LW, 1-layer PCB 90 C/W ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS *Additional thermal information available on the Allegro website. 2.5 SUFFIX 'A', R QJA = 60oC/W 2.0 1.5 1.0 0.5 SUFFIX 'LW', R QJA = 90oC/W 0 25 50 75 100 125 AMBIENT TEMPERATURE IN oC 150 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A6277 8-Bit Serial Input Constant-Current Latched LED Driver ELECTRICAL CHARACTERISTICS at TA = +25oC, VH/L = VDD = 5 V (unless otherwise noted). Limits Characteristic Symbol Supply Voltage Range VDD Under-Voltage Lockout VDD(UV) Output Current (any single output) IO Output Current Matching $IO (difference between any two outputs at same VCE) Test Conditions Min. Typ. Max. Unit Operating 4.5 5.0 5.5 V VDD = 0 to 5 V 3.4 - 4.0 V VCE = 1.0 V, REXT = 160 7 100 120 140 mA VCE = 0.4 V, REXT = 470 7 34 42 48 mA REXT = 160 7 - p1.5 p6.0 % REXT = 470 7 - p1.5 p6.0 % - 1.0 5.0 MA 0.4 V b VCE(A) = VCE(B) b 1.0 V: Output Leakage Current ICEX Logic Input Voltage VIH 0.7VDD - - V VIL - - 0.3VDD V SERIAL DATA OUT Voltage (SDO1 & SDO2) Input Resistance Supply Current VOH = 20 V VOL IOL = 1.0 mA - - 0.4 V VOH IOH = -1.0 mA 4.6 - - V ENABLE input, pull up 150 300 600 k7 LATCH & HIGH/LOW inputs, pull down 100 270 400 k7 REXT = open, VOE = 5 V - 0.8 1.6 mA REXT = 470 7, VOE = 5 V 3.5 6.5 9.5 mA REXT = 160 7, VOE = 5 V 14 17 22 mA REXT = 470 7, VOE = 0 V 5.0 10 15 mA REXT = 160 7, VOE = 0 V 20 27 40 mA RI IDD(OFF) IDD(ON) Typical Data is at VDD = 5 V and is for design information only. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A6277 8-Bit Serial Input Constant-Current Latched LED Driver SWITCHING CHARACTERISTICS at TA = 25oC, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V, REXT = 470 7, IO = 40 mA, VL = 3 V, RL = 65 7, CL = 10.5 pF. Limits Characteristic Propagation Delay Time Propagation Delay Time Symbol tpHL tpLH Test Conditions Min. Typ. Max. Unit CLOCK-OUTn - 350 1000 ns LATCH-OUTn - 350 1000 ns ENABLE-OUTn - 350 1000 ns CLOCK-SERIAL DATA OUT1 - 40 - ns CLOCK-OUTn - 300 1000 ns LATCH-OUTn - 400 1000 ns ENABLE-OUTn - 380 1000 ns CLOCK-SERIAL DATA OUT2 - 40 - ns Output Fall Time tf 90% to 10% voltage 150 250 1000 ns Output Rise Time tr 10% to 90% voltage 150 250 600 ns Min. Typ. Max. Unit RECOMMENDED OPERATING CONDITIONS Characteristic Symbol Supply Voltage VDD 4.5 5.0 5.5 V Output Voltage VO - 1.0 4.0 V Output Current IO Continuous, any one output - - 150 mA IOH SERIAL DATA OUT - - -1.0 mA IOL SERIAL DATA OUT - - 1.0 mA VIH 0.7VDD - - V VIL - - 0.3VDD V - - 10 MHz Logic Input Voltage Clock Frequency fCK Conditions Cascade operation Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A6277 8-Bit Serial Input Constant-Current Latched LED Driver TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) C 50% CLOCK A SERIAL DATA IN B DATA 50% tp SERIAL DATA OUT.1 DATA 50% tp SERIAL DATA OUT.2 D E LATCH ENABLE OUTPUT ENABLE DATA 50% 50% LOW = ALL OUTPUTS ENABLED tp HIGH = OUTPUT OFF DATA 50% OUT N LOW = OUTPUT ON Dwg. WP-029-3 HIGH = ALL OUTPUTS DISABLED (BLANKED) OUTPUT ENABLE 50% t pLH F tf 90% OUT N t pHL DATA tr 50% 10% Dwg. WP-030-1A A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) .......................................... 60 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .............................................. 20 ns C. Clock Pulse Width, tw(CK) ............................................... 50 ns D. Time Between Clock Activation and Latch Enable, tsu(L) ............................................ 100 ns E. Latch Enable Pulse Width, tw(L) ................................... 100 ns F. Output Enable Pulse Width, tw(OE) ................................ 4.5 Ms NOTE - Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable. -- Max. Clock Transition Time, tr or tf .............................. 10 Ms Information present at any register is transferred to the respective latch when the LATCH ENABLE is high (serial-toparallel conversion). The latches will continue to accept new data as long as the LATCH ENABLE is held high. Applications where the latches are bypassed (LATCH ENABLE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A6277 8-Bit Serial Input Constant-Current Latched LED Driver ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE Package A Package LW VCE = 1 V VCE = 1 V 140 ALLOWABLE OUTPUT CURRENT IN mA/BIT ALLOWABLE OUTPUT CURRENT IN mA/BIT 140 VCE = 2 V 120 VCE = 3 V 100 VCE = 4 V 80 60 40 TA = +25oC VDD = 5 V RQJA = 55oC/W 20 0 VCE = 2 V 120 VCE = 3 V 100 80 VCE = 4 V 60 40 TA = +25oC VDD = 5 V RQJA = 70oC/W 20 0 0 20 40 60 80 100 0 20 DUTY CYCLE IN PER CENT 40 60 80 DUTY CYCLE IN PER CENT Dwg. GP-062-17 Dwg. GP-062-16 VCE = 1 V 140 140 ALLOWABLE OUTPUT CURRENT IN mA/BIT ALLOWABLE OUTPUT CURRENT IN mA/BIT 100 VCE = 2 V 120 VCE = 3 V 100 80 VCE = 4 V 60 40 TA = +50oC VDD = 5 V RQJA = 55oC/W 20 0 VCE = 1 V 120 VCE = 2 V 100 VCE = 3 V 80 VCE = 4 V 60 40 TA = +50oC VDD = 5 V RQJA = 70oC/W 20 0 0 20 40 60 80 100 DUTY CYCLE IN PER CENT 0 20 40 60 80 100 DUTY CYCLE IN PER CENT Dwg. GP-062-15 Dwg. GP-062-14 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A6277 8-Bit Serial Input Constant-Current Latched LED Driver ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.) Package A Package LW VCE = 0.7 V 140 ALLOWABLE OUTPUT CURRENT IN mA/BIT 120 VCE = 1 V 100 VCE = 2 V VCE = 3 V 80 VCE = 4 V 60 40 TA = +85oC VDD = 5 V RQJA = 55oC/W 20 VCE = 0.7 V 120 VCE = 1 V 100 VCE = 2 V 80 VCE = 3 V 60 VCE = 4 V 40 TA = +85oC VDD = 5 V RQJA = 70oC/W 20 0 0 0 20 40 60 80 0 100 20 40 60 80 100 DUTY CYCLE IN PER CENT DUTY CYCLE IN PER CENT Dwg. GP-062-12 Dwg. GP-062-13 TYPICAL CHARACTERISTICS 60 OUTPUT CURRENT IN mA/BIT ALLOWABLE OUTPUT CURRENT IN mA/BIT 140 40 TA = +25oC REXT = 470 7 20 0 0 0.5 1.0 1.5 2.0 VCE IN VOLTS Dwg. GP-063-1 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A6277 8-Bit Serial Input Constant-Current Latched LED Driver VDD VDD IN IN Dwg. EP-010-12 Dwg. EP-010-11 OUTPUT ENABLE (active low) LATCH ENABLE and HIGH/LOW VDD VDD OUT IN Dwg. EP-063-6 Dwg. EP-010-13 CLOCK and SERIAL DATA IN SERIAL DATA OUT TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN Serial Latch Data Enable Output Input Latch Contents I1 I2 I3 ... IN-1 IN Output Enable Input Output Contents I1 I2 I3 ... IN-1 IN H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X L R1 R2 R3 ... RN-1 RN PN H P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN X X H H H H ... H X X ... P1 P2 P3 ... L = Low Logic (Voltage) Level X PN-1 PN H = High Logic (Voltage) Level X X ... X = Irrelevant X P = Present State H R = Previous State Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A6277 8-Bit Serial Input Constant-Current Latched LED Driver Applications Information The load current per bit (IO) is set by the external resistor (REXT) as shown in the figure below. 140 VCE = 0.7 V 0.7 V per diode) for a group of drivers. If the available voltage source will cause unacceptable dissipation and series resistors or diode(s) are undesirable, a regulator such as the Sanken Series SAI or Series SI can be used to provide supply voltages as low as 3.3 V. OUTPUT CURRENT IN mA/BIT 120 For reference, typical LED forward voltages are: White 3.5 - 4.0 V Blue 3.0 - 4.0 V Green 1.8 - 2.2 V Yellow 2.0 - 2.1 V Amber 1.9 - 2.65 V Red 1.6 - 2.25 V Infrared 1.2 - 1.5 V 100 80 60 40 20 0 100 200 300 500 700 2k 1k CURRENT-CONTROL RESISTANCE, R EXT 3k 5k IN OHMS Dwg. GP-061-1 Package Power Dissipation (PD). The maximum allowable package power dissipation is determined as PD(max) = (150 - TA)/RQJA. The actual package power dissipation is PD(act) = dc(VCE * IO * 8) + (VDD * IDD). When the load supply voltage is greater than 3 V to 5 V, considering the package power dissipating limits of these devices, or if PD(act) > PD(max), an external voltage reducer (VDROP) should be used. Load Supply Voltage (VLED). These devices are designed to operate with driver voltage drops (VCE) of 0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to 4.0 V. If higher voltages are dropped across the driver, package power dissipation will be increased significantly. To minimize package power dissipation, it is recommended to use the lowest possible load supply voltage or to set any series dropping voltage (VDROP) as VDROP = VLED - VF - VCE with VDROP = Io * RDROP for a single driver, or a Zener diode (VZ), or a series string of diodes (approximately Pattern Layout. This device has separate logic-ground and power-ground terminals. If ground pattern layout contains large common-mode resistance, and the voltage between the system ground and the LATCH ENABLE or CLOCK terminals exceeds 2.5 V (because of switching noise), these devices may not operate correctly. VLED V DROP VF V CE Dwg. EP-064 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A6277 8-Bit Serial Input Constant-Current Latched LED Driver Pin-out Diagram (A and LW packages) LOGIC GROUND 1 SERIAL DATA IN 2 VDD IO REGULATOR CLOCK 3 CK LATCH ENABLE 4 L HIGH/LOW (CURRENT) 5 POWER GROUND 6 FF OE SUB REGISTER LATCHES 20 LOGIC SUPPLY 19 REXT 18 SERIAL DATA OUT 1 17 SERIAL DATA OUT 2 16 OUTPUT ENABLE 15 POWER GROUND 14 OUT 7 SUB OUT 0 7 OUT 1 8 13 OUT 6 OUT 2 9 12 OUT 5 OUT 3 10 11 OUT 4 TERMINAL DESCRIPTION Terminal No. Terminal Name Function 1 LOGIC GROUND Reference terminal for control logic. 2 SERIAL DATA IN Serial-data input to the shift-register. 3 CLOCK 4 LATCH ENABLE 5 HIGH/LOW (CURRENT) 6 POWER GROUND 7-14 OUT0-7 15 POWER GROUND Ground. 16 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). 17 SERIAL OUT2 CMOS serial-data output (on clock falling edge). 18 SERIAL OUT1 CMOS serial-data output (on clock rising edge) to the following shift-registers. 19 REXT 20 LOGIC SUPPLY Clock input terminal for data shift on rising edge. Data strobe input terminal; serial data is latched with high-level input. Logic low for 100% of programmed current level; logic high for 50% of programmed current level. Ground. The eight current-sinking output terminals. An external resistor at this terminal establishes the output current for all sink drivers. (VDD) The logic supply voltage. Typically 5 V. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A6277 8-Bit Serial Input Constant-Current Latched LED Driver Package A,20-pin DIP +0.76 26.16 -1.27 20 +0.10 0.38 -0.05 +0.76 6.35 -0.25 +0.38 10.92 -0.25 7.62 A 1 2 5.33 MAX SEATING PLANE C +0.51 3.30 -0.38 2.54 +0.25 1.52 -0.38 For Reference Only Dimensions in millimeters (reference JEDEC MS-001 AD) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 0.46 0.12 Package LW, 20-pin SOICW 12.800.20 4 4 20 20 +0.07 0.27 -0.06 7.500.10 10.300.33 9.50 A 1 2.25 +0.44 0.84 -0.43 2 1 2 0.65 0.25 20X SEATING PLANE 0.10 C 0.41 0.10 1.27 C SEATING PLANE GAUGE PLANE 1.27 B PCB Layout Reference View 2.65 MAX 0.20 0.10 For Reference Only Dimensions in millimeters (Reference JEDEC MS-013 AC) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P1030X265-20M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Copyright (c)2001-2009, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11