74VCX16244MTDX - Fairchild Semiconductor

October 1996

Revised June 2005

74VCX16244 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

74VCX16244

Low Voltage 16-Bit Buffer/Line Driver with

3.6V Tolerant Inputs and Outputs

General Descript ion

The VCX 16244 contains sixt een non-i nverting b uffers with

3-STATE outputs to be employed as a memory and

address driver, clock driver, or bus oriented transmitter/

receiver. The device is nibble (4-bit) controlled. Each nibble

has separate 3- S TATE control inpu ts which can be sh ort ed

together for full 16-bit operation.

The 74VCX16244 is designed for low voltage (1.2V to

3.6V) VCC applications with I/O capability up to 3.6V.

The 74VCX16244 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

■1.2V to 3.6V VCC supply oper atio n

■3.6V tol erant inpu ts and outputs

■tPD

2.5 ns max for 3.0V to 3.6V VCC

■Power-off high impedance inputs and outputs

■Supports live insertion and withdrawal (Note 1)

■Static Drive (IOH/IOL)

24 mA @ 3.0V VCC

■Latch-up per for man c e exce eds 300 mA

■ESD performa nce :

Human body model

2000V

Machine model

200V

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to VCC through a pull-up resistor; the minimum

value of th e resistor is determin ed by the curr ent-so urcing capab ility of the

driver.

Ordering Code:

Note 2: Ordering Code “G” indicates Tray .

Note 3: Devices also available in Tape and Reel. Specify by ap pending the suffix lette r “X” to the or dering co de.

Order Number Package Number Package Description

74VCX16244G

(Note 2)( Note 3) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74VCX16244MTD

(Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

■Uses proprietary noise /E MI reduct ion c ircui tr y

www.fairchildsemi.com 2

74VCX16244

Logic Symbol

Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA

(Top Thru View)

Pin Descriptions

FBGA Pin Assignments

Truth Tables

HIGH Voltag e Level

LOW Voltage Le ve l

Immaterial (HIGH or LOW, inputs may not float)

High Impedance

Pin Names Description

OEnOutput Enable Input (Active LOW)

I0–I15 Inputs

O0–O15 Outputs

NC No Connect

123456

AO0NC OE1OE2NC I0

BO2O1NC NC I1I2

CO4O3VCC VCC I3I4

DO6O5GND GND I5I6

EO8O7GND GND I7I8

FO10 O9GND GND I9I10

GO12 O11 VCC VCC I11 I12

HO14 O13 NC NC I13 I14

JO15 NC OE4OE3NC I15

Inputs Outputs

OE1I0–I3O0–O3

LL L

LH H

HX Z

Inputs Outputs

OE3I8-I11 O8–O11

LL L

LH H

HX Z

Inputs Outputs

OE2I4-I7O4-O7

LL L

LH H

HX Z

Inputs Outputs

OE4I12-I15 O12-O15

LL L

LH H

HX Z

3 www.fairchildsemi.com

74VCX16244

Functional Description

The 74VCX16244 contains sixteen non-inverting buffers

with 3-STATE outputs. The device is nibble (4 bits) con-

trolled wi th ea ch nibb l e fun ction i ng ide nti ca lly, but inde pe n-

dent of each other. The control pins may be shorted

together to obtain full 16-bit operation.The 3-STATE out-

puts are controlled by an Output Enable (OEn) input. When

OEn is LOW, the outputs are in the 2-state mode. When

OEn is HIGH, the standard outp uts are in the high imped-

ance mode but this does not interfere with entering new

data into the inputs.

Logic Diagram

www.fairchildsemi.com 4

74VCX16244

Absolute Maximum Ratings(Note 4) Recommended Operating

Conditions (Note 6)

Note 4: The Absolute Maximum Ratings are those values beyond which

the saf ety of the device cannot be guarante ed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the Absolute Maximum Rat-

ings. The “Recommended Operating Conditions” tab le wil l defi ne the c ondi-

tio ns f or act ual devi c e opera tion.

Note 5: IO Absolute Maximum Rating must be observed.

Note 6: Floa ti ng or unus ed inputs mus t be held HIG H or LOW.

DC Electrical Characteristics

Supply Voltage (VCC)



0.5V to



4.6V

DC Input Voltage (VI)



0.5V to



4.6V

Output Voltage (VO)

Outputs 3-STATED



0.5V to



4.6V

Outputs Active (Note 5)



0.5V to VCC



0.5V

DC Input Diode Current (IIK) VI





50 mA

DC Output Diode Current (IOK)





50 mA

VCC



50 mA

DC Output Source/Sink Current

(IOH/IOL)

50 mA

DC VCC or GND Current per

Supply Pin (ICC or GND)

100 mA

Storage Temperature Range (TSTG)



C to



150

Power Supply

Operating 1.2V to 3.6V

Input Voltage



0.3V to



3.6V

Output Voltage (VO)

Output in Active States 0.0V to VCC

Output in 3-State 0.0V to 3.6V

Output Current in IOH/IOL

VCC

3.0V to 3.6V

24 mA

VCC

2.3V to 2.7V

18 mA

VCC

1.65V to 2.3V

6 mA

VCC

1.4V to 1.6V

2 mA

VCC

1.2V

100

Free Air Operating Temperature (TA)



C to



Minimum Input Edge Rate (

VIN

0.8V to 2.0V, VCC

3.0V 10 ns/V

Symbol Parameter Conditions VCC Min Max Units

(V)

VIH HIGH Level Input V oltage 2.7 - 3.6 2.0

2.3 - 2.7 1.6

1.65 - 2.3 0.65

VCC

1.4 - 1.6 0.65

VCC

1.2 0.65 x VCC

VIL LOW Level Input Voltage 2.7 - 3.6 0.8

2.3 - 2.7 0.7

1.65 - 2.3 0.35

VCC

1.4 - 1.6 0.35

VCC

1.2 0.05 x VCC

VOH HIGH Level Output Voltage IOH



100

A 2.7 - 3.6 VCC - 0.2

IOH



12 mA 2.7 2.2

IOH



18 mA 3.0 2.4

IOH



24 mA 3.0 2.2

IOH



100

A 2.3 - 2.7 VCC - 0.2

IOH



6 mA 2.3 2.0

IOH



12 mA 2.3 1.8

IOH



18 mA 2.3 1.7

IOH



100

A 1.65 - 2.3 VCC - 0.2

IOH



6 mA 1.65 1.25

IOH



100

A 1.4 - 1.6 VCC - 0.2

IOH



2 mA 1.4 1.05

IOH



100

A1.2V

CC - 0.2

5 www.fairchildsemi.com

74VCX16244

DC Electrical Characteristics (Continued)

Note 7: Outputs disabled or 3-STATE only.

AC Electrical Characteristics (Note 8)

Note 8: For CL

50PF, add approximately 300 ps to th e AC max im um specif ic ation.

Note 9: Skew is def ined as t he abso lute valu e of the difference between the actual propagation delay for a ny t w o separat e outputs of the same d evi ce. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HI GH (t OSLH).

Symbol Parameter Conditions VCC Min Max Units

(V)

VOL LOW Level Output Voltage IOL

100

A 2.7 - 3.6 0.2

IOL

12 mA 2.7 0.4

IOL

18 mA 3.0 0.4

IOL

24 mA 3.0 0.55

IOL

100

A 2.3 - 2.7 0.2

IOL

12 mA 2.3 0.4

IOL

18 mA 2.3 0.6

IOL

100

A 1.65 - 2.3 0.2

IOL

6 mA 1.65 0.3

IOL

100

A 1.4 - 1.6 0.2

IOL

2 mA 1.4 0.35

IOL

100

A 1.2 0.05

IIInput Leakage Current 0

3.6V 1.2 - 3.6

5.0

IOZ 3-STATE Output Leakage 0

3.6V 1.2 - 3.6

10.0

VIH or VIL

IOFFI Power-OFF Leakage Current 0

(VI, VO)

3.6V 0 10.0

ICC Quiescent Supply Current VI

VCC or GND 1.2 - 3.6 20.0

VCC

(VI, VO)

3.6V (Note 7) 1.2 - 3.6

20.0

ICC Increase in ICC per Input VIH

VCC



0.6V 2.7 - 3.6 750

Symbol Parameter Conditions VCC TA



C to



CUnits Figure

(V) Min Max Number

tPHL Propagation Delay CL

30 pF, RL

500

3.3

0.3 0.8 2.5

Figures

1, 2

tPLH 2.5

0.2 1.0 3.0

1.8

0.15 1.5 6.0

15 pF, RL

1.5

0.1 1.0 12.0 Figures

5, 6

1.2 1.5 30.0

tPZL Output Enable Time CL

30 pF, RL

500

3.3

0.3 0.8 3.5

Figures

1, 3, 4

tPZH 2.5

0.2 1.0 4.1

1.8

0.15 1.5 8.2

15 pF, RL

1.5

0.1 1.0 16.4 Figures

5, 7, 8

1.2 1.5 41.0

tPLZ Output Disable Time CL

30 pF, RL

500

3.3

0.3 0.8 3.5

Figures

1, 3, 4

tPHZ 2.5

0.2 1.0 3.8

1.8

0.15 1.5 6.8

15 pF, RL

1.5

0.1 1.0 13.6 Figures

5, 7, 8

1.2 1.5 34.0

tOSHL Output to Output Skew CL

30 pF, RL

500

3.3

0.3 0.5

tOSLH (Note 9) 2.5

0.2 0.5

1.8

0.15 0.75

15 pF, RL

1.5

0.1 1.5

1.2 1.5

www.fairchildsemi.com 6

74VCX16244

Dynamic Switching Characteristics

Capacitance

Symbol Parameter Conditions VCC TA



CUnits

(V) Typical

VOLP Quiet Output Dynamic Peak VOL CL

30 pF, VIH

VCC, VIL

0V 1.8 0.25 V2.5 0.6

3.3 0.8

VOLV Quiet Output Dynamic Valley VOL CL

30 pF, VIH

VCC, VIL

0V 1.8



0.25 V2.5



0.6

3.3



0.8

VOHV Quiet Output Dynamic Valley VOH CL

30 pF, VIH

VCC, VIL

0V 1.8 1.5 V2.5 1.9

3.3 2.2

Symbol Parameter Conditions TA



CUnits

Typical

CIN Input Capacitance VCC

1.8, 2.5V or 3.3V, VI

0V or VCC 6.0 pF

COUT Output Capacitance VI

0V or VCC, VCC

1.8V, 2.5V or 3.3V 7.0 pF

CPD Power Dissipation Capacitance VI

0V or VCC, f

10 MHz, VCC

1.8V, 2.5V or 3.3V 20.0 pF

7 www.fairchildsemi.com

74VCX16244

AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V)

FIGURE 1. AC Test Circuit

FIGURE 2. Waveform for Inverting and Non-Inverting Functions

FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic

FIGURE 4. 3 - STATE Output Low Enable and Disable Times for Low Voltage Logic

TEST SWITCH

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC

3.3

0.3V;

VCC x 2 at VCC

2.5

0.2V; 1.8V

0.15V

tPZH, tPHZ GND

Symbol VCC

3.3V

0.3V 2.5V

0.2V 1.8V

0.15V

Vmi 1.5V VCC/2 VCC/2

Vmo 1.5V VCC/2 VCC/2

VXVOL



0.3V VOL



0.15V VOL



0.15V

VYVOH



0.3V VOH



0.15V VOH



0.15V

www.fairchildsemi.com 8

74VCX16244

AC Loading and Waveforms (VCC 1.5 r 0.1V to 1.2V)

FIGURE 5. AC Test Circuit

FIGURE 6. Waveform for Inverting and Non-Inverting Functions

FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic

FIGURE 8. 3-STATE Output Low Enabl e and Disable Times for Low Vo ltage Logic

TEST SWITCH

tPLH, tPHL Open

tPZL, tPLZ VCC x 2 at VCC

1.5

0.1V

tPZH, tPHZ GND

Symbol VCC

1.5V

0.1V

Vmi VCC/2

Vmo VCC/2

VXVOL



0.1V

VYVOH



0.1V

9 www.fairchildsemi.com

74VCX16244

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA54 A

www.fairchildsemi.com 10

74VCX16244 Low Voltage 16-Bit Buffer/L ine Driver with 3.6V Tolerant Inputs and Output s

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.