Data Sheet, Rev 1.1, Sept. 2010 TLE7181EM H-Bridge and Dual Half Bridge Driver IC Automotive Power H-Bridge and Dual Half Bridge Driver IC TLE7181EM Table of Contents Table of Contents 1 Overview 3 2 Block Diagram 4 3 3.1 3.2 Pin Configuration 5 Pin Assignment 5 Pin Definitions and Functions 5 4 4.1 4.2 4.3 4.4 General Product Characteristics 7 Absolute Maximum Ratings 7 Functional Range 8 Thermal Resistance 9 Default State of Inputs 9 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.1.9 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 5.3 5.3.1 Description and Electrical Characteristics 10 MOSFET Driver 10 Driving MOSFET Output Stages 10 MOSFET Output Stages 10 Dead Time 11 Bootstrap Principle 11 100% D.C. charge pumps 12 Reverse polarity protection of motor bridge 12 Sleep mode 12 Wake up 12 Electrical Characteristics 13 Protection and Diagnostic Functions 17 State diagram of different operation modes 17 Short Circuit Protection 18 SCDL Pin Open Detection 18 Vs and VDH Over Voltage Warning 18 VS Under Voltage Shutdown 18 VREG Under Voltage Warning 18 Over Temperature Warning 19 Over Current Warning 19 Passive Gxx Clamping 19 ERR Pin 19 Electrical Characteristics 21 Shunt Signal Conditioning 23 Electrical Characteristics 23 6 6.1 6.2 Application Information 25 Layout Guide Lines 26 Further Application Information 26 7 Package Outlines 27 8 Revision History 28 Data Sheet 2 Rev 1.1, 2010-09-30 TLE7181EM H-Bridge and Dual Half Bridge Driver IC 1 Overview Features * * * * * * * * * * * * * * * * * PWM/DIR-interface drives 4 N-Channel Power MOSFETs Unlimited D.C. switch on time of Low and Highside MOSFETs 0 ...95% at 20kHz & 100% Duty cycle of High Side MOSFETs 0 ... 100 % Duty cycle of Low Side MOSFETs Additional output to drive a reverse polarity protection N-MOSFET Current sense OPAMP Low quiescent current mode Internal shoot through protection PG-SSOP-24 Adjustable dead time 1 bit diagnosis / ERR Over current warning based on current sense OPAMP with fixed warning level Analog adjustable Short Circuit Protection levels via SCDL pin with open pin detection Over temperature warning Over voltage warning Under voltage warning and shutdown Green Product (RoHS compliant) AEC Qualified Description The TLE7181EM is a H-bridge driver IC dedicated to control 4 N-channel MOSFETs typically forming the converter for a high current DC motor drives in the automotive sector. It incorporates several protection features such as over current and short circuit detection as well as under-, over voltage and over temperature diagnosis. Typical applications are fans, pumps and electric power steering. The TLE7181EM is designed for a 12V power net. Table 1 Product Summary Specified operating voltage VSOP 7.0 V ... 34 V Junction temperature Tj -40 C .. 150C Maximum output source resistance RSou 13.5 Maximum output sink resistance RSink 9 IQVS 8 A 1) maximum quiescent current 1) typical value at Tj=25CC Type Package Marking TLE7181EM PG-SSOP-24 TLE7181EM Data Sheet 3 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Block Diagram 2 Block Diagram VS VREG Charge pump HS2 Charge pump HS1 VREG RPP RPP VDH BH1 Floating HS driver Short circuit detection GH1 SH1 ____ ERR SCDL Diagnostic logic Under voltage Over voltage Over current Overtemperature Short circuit Reset ENA DRV DIS L E V E L Floating LS driver Short circuit detection S H I F T E R GL1 BH2 Floating HS driver Short circuit detection GH2 SH2 DT PWM Input control dead time Floating LS driver Short circuit detection GL2 SL DIR ISO ISP ISN Shunt signal conditioning Over current detection GND Figure 1 Data Sheet Block diagram TLE7181EM 4 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Pin Configuration 3 Pin Configuration 3.1 Pin Assignment BH2 GH2 SH2 GL2 VDH RPP Vs VREG ENA ISN ISP ISO 1 2 3 4 5 6 7 8 9 10 11 12 Figure 2 Pin Configuration 3.2 Pin Definitions and Functions # of Pins 24 23 22 21 20 19 18 17 16 15 14 13 BH1 GH1 SH1 GL1 SL GND SCDL ___ ERR DIR PWM DRVDIS DT Symbol Function 1 BH2 Pin for + terminal of the bootstrap capacitor of phase 2 2 GH2 Output pin for gate of high side MOSFET 2 3 SH2 Pin for source connection of high side MOSFET 2 4 GL2 Output pin for gate of low side MOSFET 2 5 VDH Voltage input common drain high side for short circuit detection 6 RPP charge pump output for reverse polarity protection of the motor bridge 7 VS Pin for supply voltage 8 VREG Output of supply for driver output stage - connect to a capacitor 9 ENA Input pin for reset of ERR registers, active switch off of external MOSFETs and low quiescent current mode, set HIGH to enable operation 10 ISN Input for OPAMP + terminal 11 ISP Input for OPAMP - terminal 12 ISO Output of OPAMP 13 DT Input for adjustable dead time function, connect to GND via resistor 14 DRVDIS Disable DIR/PWM interface & all output stages switched off 15 PWM control input for PWM frequency and duty cycle 16 DIR control input for spinning direction of the motor Data Sheet 5 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Pin Configuration # of Pins Symbol Function 17 ERR Push pull output stage 18 SCDL Input pin for adjustable Short Circuit Detection function 19 GND Ground pin 20 SL Pin for common source of lowside MOSFETs 21 GL1 Output pin for gate of low side MOSFET 1 22 SH1 Pin for source connection of high side MOSFET 1 23 GH1 Output pin for gate of high side MOSFET 1 24 BH1 Pin for + terminal of the bootstrap capacitor of phase 1 Tab Tab should be connected to GND Data Sheet 6 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) 40 C Tj 150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Max. Unit Conditions Voltages 4.1.1 Supply voltage at VS VVS -0.3 45 V - 4.1.2 Supply voltage at VS VVSRP -4.0 45 V RVS10 4.1.3 Voltage range at VDH VVDH -0.3 55 V - 4.1.4 Voltage range at RPP -0.3 55 V - 4.1.5 maximum current at RPP -25 25 mA - 4.1.6 Voltage range at ENA VRPP IRPP VENA VSCDL VDPI -0.3 45 V - -0.3 6 V - -0.3 6 V - VDPO VOPI VVREG VBH VGH VGHP VSH VSHP VGL VGLP -0.3 6 V - -5.0 5.0 V - -0.3 15 V - -0.3 55 V - -0.3 55 V - -7.0 55 V tP<1s; f=50kHz -2.0 45 V - -7.0 45 V tP<1s; f=50kHz -0.3 18 V - -7.0 18 V tP<0.5s; f=50kHz VSL VSLP -1.0 5.0 V - -7.0 5.0 V tP<0.5s; f=50kHz; 4.1.7 Voltage range at SCDL 4.1.8 Voltage range at PWM, DIR, DT, DRVDIS 4.1.9 Voltage range at ERR, ISO 4.1.10 Voltage range at ISP, ISN 4.1.11 Voltage range at VREG 4.1.12 Voltage range at BHx 4.1.13 Voltage range at GHx 4.1.14 Voltage range at GHx 4.1.15 Voltage range at SHx 4.1.16 Voltage range at SHx 4.1.17 Voltage range at GLx 4.1.18 Voltage range at GLx 4.1.19 Voltage range at SL 4.1.20 Voltage range at SL CBS330nF 4.1.21 Voltage difference Gxx-Sxx 4.1.22 Voltage difference BHx-SHx VGS VBS -0.3 15 V - -0.3 15 V - Temperatures 4.1.23 Junction temperature Tj -40 150 C - 4.1.24 Storage temperature Tstg -55 150 C - 4.1.25 Lead soldering temperature (1/16'' from body) Tsol - 260 C - 4.1.26 Peak reflow soldering temperature2) Tref - 260 C - Ptot - 2 W - Power Dissipation 4.1.27 Power Dissipation (DC) Data Sheet 7 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM General Product Characteristics Absolute Maximum Ratings (cont'd)1) 40 C Tj 150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Max. Unit Conditions ESD Susceptibility 4.1.28 ESD Resistivity3) VESD - 2 kV 4.1.29 CDM VCDM - 1 kV 1) Not subject to production test, specified by design. 2) Reflow profile IPC/JEDEC J-STD-020C 3) ESD susceptibility HBM according to EIA/JESD 22-A 114B Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Pos. 4.2.1 Functional Range Parameter Symbol Specified supply voltage range 1) Limit Values Unit Conditions Min. Max. VVS1 7.0 34 V - VVS2 5.5 45 V VVS<7V reduced functionality 4.2.2 supply voltage range 4.2.3 Quiescent current at VS IQVS1 - 8 A VVS,VVDH=12V; ENA=Low; Tj=25C 4.2.4 Quiescent current at VS IQVS2 - 10 A VVS,VVDH<15V; ENA=Low; Tj85C 4.2.5 Quiescent current at VDH IQVDH1 - 8 A VVS,VVDH=12V; ENA=Low; Tj=25C 4.2.6 Quiescent current at VDH IQVDH2 - 10 A VVS,VVDH<15V; ENA=Low; Tj85C 4.2.7 Supply current at Vs (device enabled)2) IVs(1) - 22 mA no switching 4.2.8 Supply current at Vs (device enabled) IVs(2) - 45 mA 4xQGSxfPWM20mA ; VVS=7.0..34V 4.2.9 D.C. switch on time of output stages DDC - s - 4.2.10 Duty cycle Highside output stage3) DHS 0 95 % fPWM=20kHz; continuous operation; CBS 330nF 4.2.11 Duty cycle Lowside output stage 0 100 % - DLS 1) operation above 34V limited by max. allowed power dissipation and max. ratings 2) Current can be higher, if driver output stages are unsupplied 3) max. limit of D.C. will increase, if fPWM or external gate charge of the MOSFETs is reduced Data Sheet 8 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM General Product Characteristics The PWM frequency is limited by thermal constraints and the maximum duty cycle (minimum charging time of bootstrap capacitor). Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. 4.3.1 4.3.2 Parameter Junction to Case Symbol 1) Junction to Ambient 1) RthJC RthJA Limit Values Unit Conditions Min. Typ. Max. - - 5 K/W - - 35 - K/W 2) 1) Not subject to production test, specified by design. 2) Exposed Heatslug Package use this sentence: Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m Cu, 2 x 35m Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 4.4 Default State of Inputs Table 2 Default State of Inputs (if left open) Characteristic State Remark Default state of PWM and DIR Low Low side MOSFETs off and Highside MOSFETs on Default state of DT OPEN maximum deadtime Default state of ENA Low Output stages disabled device in sleep mode Default state of SCDL OPEN Short circuit detection deactivation & warning Default state of DRVDIS High All output stages off & no error will be reported Data Sheet 9 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Description and Electrical Characteristics 5 Description and Electrical Characteristics 5.1 MOSFET Driver 5.1.1 Driving MOSFET Output Stages The TLE7181EM incorporates 2 high side and low side output stages for 4 external MOSFETs. The 4 MOSFET output stages will be driven by the PWM/DIR interface. With the PWM/DIR interface only 2 inputs pins are necessary to drive a typical H-bridge topology for a DC-brush motor. The rotation direction of the motor can be chosen with the input pin DIR. The speed of the motor can is controlled by applying a PWM-signal at pin PWM. The DRVDIS pin allows to switch off all 4 MOSFETs. Table 3 provides an overview of the different states with this interface. Table 3 PWM/DIR interface normal operation DRVDIS DIR PWM Highside switch1 Lowside switch1 Highside switch2 Lowside switch2 0 0 0 ON OFF ON OFF 0 0 1 ON OFF OFF ON 0 1 0 ON OFF ON OFF 0 1 1 OFF ON ON OFF 1 x x OFF OFF OFF OFF 5.1.2 MOSFET Output Stages The six push-pull MOSFET driver stages of the TLE7181EM are realized as separate floating blocks. This means that the output stage is follows the individual MOSFET source voltages and so ensuring stable MOSFET driving even in harsh electrical environment. All 4 output stages have the same output power and thanks to the used bootstrap principle they can be switched all up to high frequencies. Each output stage has its own short circuit detection block. For more details about short circuit detection see Chapter 5.2.2. Data Sheet 10 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Description and Electrical Characteristics VS VREG ENA VDH BHx RPP Voltage regulator Charge pump ____ ERR + V RE G Error logic Reset Power On Reset GHx VSCP V DH blanking S CD S CD SHx Level shifter Floating HS driver 2x S CD VREG loc k / unlock short circuit filter Short Circuit Detection Level + DRVDIS PWM DIR Input Logic GLx - ON / OFF VSCP Dead Time SL Level shifter ON / OFF Floating LS driver 2x DT GND SCDL Figure 3 Block Diagram of Driver Stages including Short Circuit Detection 5.1.3 Dead Time In bridge applications it has to be assured that the external high side and low side MOSFETs are not "on" at the same time, connecting directly the battery voltage to GND. The dead time generated in the TLE7181EM can be programmed by applying an resistor between the DT pin and GND. Higher external resistor values lead to higher dead time. A minimum dead time applied, if the DT pin is connected to GND. The typical dead time can be calculated with the following formula: t deadtime [ s ] = 0.081 0.02 + 2.4 4+ Rdt [ k ] If an exact dead time of the bridge is needed, the use of the C PWM generation unit is recommended. 5.1.4 Bootstrap Principle The TLE7181EM provides a bootstrap based supply for its high side output stages. The bootstrap capacitors are charged by switching on the external low side MOSFETs, connecting the bootstrap capacitor to GND. Under this condition the bootstrap capacitor will be charged from the VREG capacitor via the integrated bootstrap diode. If the low side MOSFET is switched off and the high side MOSFET is switched on, the bootstrap capacitor will float together with the SHx voltage to the supply voltage of the bridge. Under this condition the supply current of the high side output stage will discharge the bootstrap capacitor. This current is specified. The size of the capacitor together with this current will determine how long the high side MOSFET can be kept on without recharging the bootstrap capacitor. Data Sheet 11 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Description and Electrical Characteristics 5.1.5 100% D.C. charge pumps 100% D.C. charge pumps are implemented for each high side output stage. Therefore the high side output stages can be switch on for an unlimited time. These integrated charge pumps can handle leakage currents which will be caused by external MOSFETs and the TLE7181EM itself. They are not strong enough to drive a 99% duty cycle for a longer time. the charge pumps are running when the driver is not in sleep mode and assure that the bootstrap capacitors are charged as long as the user does not apply critical duty cycle for a longer time. 5.1.6 Reverse polarity protection of motor bridge The TLE7181EM provides an additional RPP pin to protect motor bridge for reverse polarity. This RPP pin can drive an additional external N-channel power MOSFET designed in between battery and the motor bridge. The RPP pin is internally supplied by the two integrated 100% D.C. charge pumps. They are especially designed to handle additional current which is needed to drive a the gate charge of the reverse polarity MOSFET. The guarantied output current of the charge pumps is specified. 5.1.7 Sleep mode If ENA pin is set to low, the ERR flag will be set to low and the output stages will be switched off. After ENA pin is kept low for tLQM the sleep mode of the Driver IC will be activated. In Sleep mode the complete chip is deactivated. This means the internal supply structure of the TLE7181EM will be switched off. This mode is designed for lowest current consumption from the power net of the car. The passive clamping is active. For details see the description of passive clamping, see Chapter 5.2.9. The TLE7181EM will wake up, if ENA is set to high.The ENA pin is 45V compatible, so ENA can be directly be connected to the ignition key signal KL15. 5.1.8 Wake up A special start up procedure is implemented into the TLE7181EM to guarantee charged bootstrap capacitors. This start up procedure is automatically performed before normal H-bridge motor control with PWM/DIR is possible. If the ENA pin is set to high, the VREG voltage starts to increase. As soon as the under voltage threshold VREG_UV is reached, both low side output stages will be switched on for a short period of time for fast charging of the bootstrap capacitors. When the bootstrap capacitor voltage is high enough the auto start up procedure is completed and the low side MOSFETs will be driven accoring the input pattern. During wake up procedure the ERR signal is set to low. It will be set to high, if no error occurs at the TLE7181EM and auto start procedure is completed. To assure that the driver is finally in the normal operation mode, it is recommended to set the DRVDIS pin to high for minimum 1us. After that procedure the output stages can be driven by PWM/DIR interface. Data Sheet 12 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Description and Electrical Characteristics 5.1.9 Electrical Characteristics Electrical Characteristics MOSFET Drivers VS = 7.0 to 34V, Tj = -40 to +150C all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions Control inputs 5.1.1 Low level input voltage of PWM; DIR VI_LL - - 1.0 V - 5.1.2 High level input voltage of PWM; DIR VI_HL 2.0 - - V - 5.1.3 Input hysteresis of PWM; DIR 100 200 - mV - 5.1.4 PWM; DIR pull-down resistors to GND dVI RIL 20 - 50 k - 5.1.5 VE_LL High level input voltage of ENA VE_HL Input hysteresis of ENA dVE ENA pull-down resistor to GND RIL Low level input voltage of DRVDIS VD_LL High level input voltage of DRVDIS VD_HL Input hysteresis of DRVDIS dVD DRVDIS pull-up resistor to internal RDH - - 0.75 V - 2.1 - - V - 50 200 - mV - 70 125 200 k - - - 1.0 V - 2.0 - - V - 100 200 - mV - 30 50 80 k - RSou RSink VGxx1 2 - 13.5 2 - 9.0 - 11 15 V VGxx2 - 11 13.5 V ILoad=-20mA ILoad=20mA 13.5VVVS34V; ILoad=0mA 13.5VVVS34V; CLoad=20nF; 5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 5.1.11 5.1.12 Low level input voltage of ENA supply MOSFET driver output 5.1.13 Output source resistance 5.1.14 Output sink resistance 5.1.15 High level output voltage Gxx vs. Sxx 5.1.16 High level output voltage Gxx vs. Sxx D.C.=50%; fPWM=20kHz 5.1.17 High level output voltage GHx vs. SHx1) VGHx3 - VVS-1.5 - V 7.0V<VVS<13.5V; CLoad=20nF; D.C.=50%; 5.1.18 High level output voltage GLx vs. GND1) VGLx3 - VVS-0.5 - V fPWM=20kHz 7.0V<VVS<13.5V; CLoad=20nF; fPWM=20kHz & D.C.=50%; or D.C=100% Data Sheet 13 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Description and Electrical Characteristics Electrical Characteristics MOSFET Drivers VS = 7.0 to 34V, Tj = -40 to +150C all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol 5.1.19 High level output voltage GHx vs. SHx1)2) VGHx4 Limit Values Min. Typ. Max. 5.0 +Vdiode - - Unit Conditions V VVS=7.0V; CLoad=20nF; D.C.=95%; fPWM=20kHz; passive freewheeling 5.1.20 High level output voltage GHx vs. SHx1) VGHx5 5.0 - - V VVS=7.0V; CLoad=20nF; D.C.=95%; 5.1.21 High level output voltage GLx vs. SLx1) VGLx5 6.0 - - V fPWM=20kHz VVS=7.0V; CLoad=20nF; V fPWM=20kHz 7.0VVVS13.5V; CLoad=20nF; D.C.=95%; 5.1.22 High level output voltage GHx vs. SHx1) VGHx5 10 - - D.C.=100% 5.1.23 High level output voltage GLx vs. SLx1) VGLx5 6.5 - - V VVS=7.0V; CLoad=20nF; D.C.=100% 5.1.24 Rise time 5.1.25 Fall time trise tfall - 250 - ns - 200 - ns CLoad=11nF; RLoad=1; VVS=7V; 20-80% 5.1.26 High level output voltage (in passive clamping)1) VGxxUV - - 1.2 V Sleep mode or VS_UVLO 5.1.27 Pull-down resistor at BHx to GND RBHUVx - - 85 k Sleep mode or VS_UVLO 5.1.28 Pull-down resistor at VREG to GND RVRUV - - 30 k Sleep mode or VS_UVLO 5.1.29 Bias current into BHx - - 150 A VCBS>5V; IBHx no switching 5.1.30 Bias current out of SHx ISHx - 40 - A VSHx=VSL; ENA=HIGH; affected highside output stage static on; VCBS>5V 5.1.31 Bias current out of SL ISL - - 1.4 mA 0VSHxVVS+1V; ENA=HIGH; no switching; VCBS>5V Data Sheet 14 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Description and Electrical Characteristics Electrical Characteristics MOSFET Drivers VS = 7.0 to 34V, Tj = -40 to +150C all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions Dead time & input propagation delay times 5.1.32 Programmable internal dead time tDT 0.08 0.25 0.82 1.0 2.0 0.13 0.42 1,21 1.88 3.62 0.20 0.57 1.65 2.7 5.6 s RDT=0k RDT=10k RDT=47k RDT=100k RDT=1000k 5.1.33 Max. internal dead time tDT_MAX 2.3 4.0 6.4 s DT pin open 5.1.34 Dead time deviation between channels dtDT1 -20 - 20 % - -15 - 15 % RDT47k Dead time deviation between channels LSoff -> HS on dtDTH1 -14 - 14 % - -12 - 12 % RDT47k Dead time deviation between channels HSoff -> LS on dtDTL1 -14 - 14 % - -12 - 12 % 5.1.37 Input propagation time (low on) 0 100 200 ns 5.1.38 Input propagation time (low off) 0 100 200 ns 5.1.39 Input propagation time (high on) 0 100 200 ns 5.1.40 Input propagation time (high off) 0 100 200 ns 5.1.41 Absolute input propagation time difference between above propagation times tP(ILN) tP(ILF) tP(IHN) tP(IHF) tP(diff) RDT47k CLoad=10nF; RLoad=1 - 50 100 ns 5.1.35 5.1.36 VREG 5.1.42 VREG output voltage VVREG 11 12.5 14 V VVS13.5V; ILoad=-35mA 5.1.43 VREG over current limitation 100 - 500 mA -3) 5.1.44 Voltage drop between Vs and VREG IVREGOCL VVsVREG - - 0.5 V VVS7V; ILoad=-35mA; Ron operation 100% D.C. charge pump 5.1.45 Charge pump frequency1) fCP - 21 - MHz - Motor bridge reverse polarity protection output 5.1.46 High level output voltage RPP vs. VS VRPP1 - 11 15 V ILoad=0A 5.1.47 High level output voltage RPP vs. VS VRPP2 - 11 12.5 V ILoad-30A 5.1.48 D.C. output current at RPP IRPP1 - -110 -150 A VRPP10V; 5.1.49 Rise time1) - 1 2 ms 5.1.50 Rise time1) tRPPrise tRPPrise - 10 20 s CLOAD=10nF CLOAD=100pF Lowside on Data Sheet 15 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Description and Electrical Characteristics Electrical Characteristics MOSFET Drivers VS = 7.0 to 34V, Tj = -40 to +150C all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions ENA and Low quiescent current mode 5.1.51 ENA propagation time to output stages switched off tPENA_H-L - 2.0 3.0 s - 5.1.52 Low time of ENA signal without clearing error register tRST0 - - 1.2 s - 5.1.53 High time of ENA signal after ENA tRST1 rising edge for error logic active 4 5.75 7 s - 5.1.54 go to sleep time tsleep 310 415 540 s - 5.1.55 wake up time twake - 50 100 s CREG=2.2F; CBS=330nF 1) Not subject to production test, specified by design. 2) Vdiode is the bulk diode of the external low side MOSFET 3) normally no error flag; Error flag might by triggered by under voltage VREG caused by very high load current Data Sheet 16 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM 5.2 Protection and Diagnostic Functions 5.2.1 State diagram of different operation modes Error conditions TLE7181EM and used abbreviations: Warnings: Over Current Detection (OCD) VS/VDH Over Voltage Detection (OVD) SCDL Pin Open Detection (SCDLPOD) Over Temperature Detection (OTD) Sleep Mode Errors: VREG Under Voltage Error (VREG_UV) VS Under Voltage Lockout ( VS_UVLO) Short circuit detection (SCD) - low quiescent current - all supplies switched off * VS_UVLO: leads from every mode into the Sleep Mode ** ENA = low: leads from every mode into the Go to Sleep Mode ENA = High Wake-up Mode *) VS_UVLO - error is reported - auto start mode with Lowside switched-on phases Wake-up time expired **) ENA=low Non Latched Error Mode: VREG_UV/SCDLPOD VREG_UV/SCDL pin open *) VS_UVLO **) ENA=low No VREG_UV/ SCDL pin open - error is reported - MOSFets switched-off VREG_UV Normal Mode without Error Conditions Warning Mode: OCD/OVD/OTD Warning detection *) VS_UVLO No warning - no error is reported - driver stages are active *) VS_UVLO - error is reported - driver stages are active **) ENA=low Short circuit detection ENA=low No SCD "&" ENA reset Latched Error Mode : SCD Short circuit detection *) VS_UVLO - latched error is reported - MOSFets switched-off - VREG and VDD on ENA = high "&" go to sleep time not expired VS_UVLO Error Mode Go-to-Sleep Mode - MOSFets switched-off - error is reported ENA = Low "&" go to sleep time expired Figure 4 Data Sheet **) ENA=low *) VS_UVLO - error is reported - MOSFets switched-off - VREG and charge pump off State diagramTLE7181EM 17 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM 5.2.2 Short Circuit Protection The TLE7181EM provides a short circuit protection for the external MOSFETs by monitoring the drain-source voltage of the external MOSFETs. This monitoring of the short circuit detection for a certain external MOSFET is active as soon as the corresponding driver output stage is set to "on" and the dead time and the blanking time are expired. The blanking time starts when the dead time has expired and assures that the switch on process of the MOSFET is not taken into account. It is recommended to keep the switching times of the MOSFETs below the blanking time. The short circuit detection level is adjustable in an analog way by the voltage setting at the SCDL pin. There is a 1:1 translation between the voltage applied to the SCDL pin and the drain-source voltage limit. E.g. to trigger the SCD circuit at 1 V drain-source voltage, the SCDL pin must be set to 1 V. The drain-source voltage limit can be chosen between 0.2 ... 2 V. If after the expiration of the blanking time the drain source voltage of the observed MOSFET is still higher then the SCDL level, the SCD filter time tSCP starts to run. A capacitor is charged with a current. If the capacitor voltage reaches a specific level (filter time tSCP), the error signal is set and the IC goes into SCDL Error Mode. If the SCD condition is removed before the SC is detected, the capacitor is discharged with the same current. The discharging of the capacitor happens as well when the MOSFET is switched off. It has to be considered that the high side and the low side output of one phase are working with the same capacitor. 5.2.3 SCDL Pin Open Detection An integrated structure at the SCDL pin assures that in case of an open pin the SCDL voltage is pulled to a medium voltage level. The external MOSFETs are actively switched off and an ERR flag is set. This error is self-clearing. 5.2.4 Vs and VDH Over Voltage Warning The TLE7181EM has an integrated over voltage warning to minimize risk of destruction of the IC at high supply voltages caused by violation of the maximum ratings. For the over voltage warning the voltage is observed at the pin VS and VDH. If the voltage level has reached, the fixed over voltage threshold VOVW for the filter time tOV, a warning at ERR pin is set and TLE7181EM will go in normal operation with warning. The over voltage warning is self clearing. If the voltage at pin VS and VDH returns into the specified voltage range, the Error register will be cleared and TLE7181EM returns to normal operation mode. It is the decision of the user, if and how to react on the over voltage warning. 5.2.5 VS Under Voltage Shutdown The TLE7181EM has an integrated VS Under Voltage Shutdown, to assure that the behavior of the complete IC is predictable in all supply voltage ranges. As soon as the under voltage threshold VUVVR is reached for a specified filter time the TLE7181EM is in VS_UVLO error mode. The error signal will be set and output stages, voltage regulator and charge pump will be switched off so the IC will go into sleep mode. An enable is necessary to restart the TLE7181EM. 5.2.6 VREG Under Voltage Warning The TLE7181EM has an integrated under voltage warning detection at VREG. If the supply voltage at VREG reaches the VREG under voltage threshold VUVVR, a warning at ERR pin is set and the TLE7181EM will go into VREG error mode. In case of VREG error mode all output stages will actively switched off to prevent low gate source voltages at the power MOSFETs causing high RDSon. If supply voltage at the VREG pin recovers; the error flag will be cleared and the TLE7181EM will return in normal operation mode. Data Sheet 18 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM 5.2.7 Over Temperature Warning The TLE7181EM provides an integrated digital over temperature warning to minimize risk of destruction of the IC at high temperature. The temperature will be detected by a embedded sensor. During over temperature warning the ERR signal is set and the TLE7181EM is in normal operation mode with warning. The over temperature warning is self clearing. So if temperature is below Tj(PW) -dTj(OW), the warning will be cleared and TLE7181EM returns to normal operation mode. It is the decision of the user to react on the over temperature warning. 5.2.8 Over Current Warning The TLE7181EM offers an integrated over current detection. The output signal of the current sense OpAmp will be monitored. If the output signal reaches the specified voltage threshold VOCTH for a certain time, over current will be detected. After the comparator the filter time tOC is implemented to avoid false triggering caused by overswing of the current sense signal. The ERR pin will be set to low and the TLE7181EM will go into normal operation mode with warning. The error signal disappears as soon as the current decreases below the over current threshold VOCTH. The error signal disappears as well when the current commutates from the low side MOSFET to the associated high side MOSFET and is no longer flowing over the shunt resistor. It is the decision of the user to react on the over current signal by modifying input patterns. 5.2.9 Passive Gxx Clamping If VS Under Voltage shutdown is detected or the device is in Sleep Mode, a passive clamping is active as long as the voltage at VS or VDH is higher than 3V. Even below 3V it is assured that the MOSFET driver stage will not switch on the MOSFET actively. The passive clamping means that the BHx and the VREG pin are pulled to GND with specified pull down resistors. Together with the intrinsic diode of the push stage of the output stages which connect the gate output to BHx respectively VREG, this assures that the gate of the external MOSFETs are not floating undefined. 5.2.10 ERR Pin The TLE7181EM has a status pin to provide diagnostic feedback to the C. The logical output of this pin is a push pull output stage with an integrated pull-down resistor to GND (see Figure 5). Reset of error registers and Disable The TLE7181EM can be reset by the enable pin ENA. If the ENA pin is pulled to low for a specified minimum time, the error registers are cleared. ERR output is still set to low. After the next rising edge at ENA pin ERR pin will be set to high and no error condition is applied. Data Sheet 19 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM C TLE718xEM Internal 5V internal Error Logic ERR Interface_ C GND Figure 5 Structure of ERR output Table 4 Overview of error condition GND ERR Driver conditions Driver action Restart High no errors Fully functional - Low Over temperature Warning only Self clearing Low Over voltage VS/VDH Warning only Self clearing Low Over current OPAMP Warning only Self clearing Low Under voltage error VREG All MOSFETs actively switched off Self clearing Low Under voltage shutdown based MOSFET, charge pump, on VS Vreg switched off Self clearing restart when enable high1) Low SCDL open pin All MOSFETs actively switched off Self clearing Low Short circuit detection All MOSFETs actively switched off Reset at ENA needed Low Go to sleep mode All MOSFETs actively switched off immediate restart when ENA goes high Low Wake up mode start up - 1) When SC detected, reset with ENA necessary Table 5 Prioritization of Errors Priority Errors and Warnings 0 Under voltage lockout at Vs (VS_UVLO) 1 Short circuit detection error (SCD) SCDL pin open warning (SCDLPOD) 2 Under voltage detection VREG (UV_VREG) Over voltage detection warning (OVD) Over temperature warning (OTD) Over current warning (OCD) Data Sheet 20 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM 5.2.11 Electrical Characteristics Electrical Characteristics - Protection and diagnostic functions VS = 7.0 to 34V, Tj = -40 to +150C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions Short circuit protection 5.2.1 Short circuit protection detection level input range VSCDL 0.2 - 2.0 V programmed by SCDL pin 5.2.2 Short circuit protection detection accuracy ASCP1 -50 - +50 % 0.2V VSCDL0.3V 5.2.3 Short circuit protection detection accuracy ASCP2 -30 - +30 % 0.3V VSCDL1.2V 5.2.4 Short circuit protection detection accuracy ASCP3 -10 - +10 % 1.2V VSCDL2.0V 5.2.5 Filter time of short circuit protection tSCP(off) 2.5 3.5 4.5 s - 5.2.6 Filter time and blanking time of short circuit protection 4 6 8 s - 5.2.7 Internal pull-up resistor SCDL to 3V RSCDL 180 300 475 k - 5.2.8 SCDL open pin detection level 2.1 - 3.2 V - 5.2.9 Filter time of SCDL open pin detection VSCPOP tSCPOP 1.5 2.5 3.5 s - 5.2.10 SCDL open pin detection level hysteresis1) VSCOPH - 0.3 - V - VOVW 34.5 36.5 38.5 V VVS and/or VVDH increasing tSCPBT Over- and under voltage monitoring 5.2.11 Over voltage warning at Vs and/or VDH 5.2.12 Over voltage warning hysteresis for VOVWhys Vs and/or VDH 2.1 3.1 4.1 V - 5.2.13 Over voltage warning filter time for tOV Vs and/or VDH 13 19 25 s - 5.2.14 VUVVR Under voltage shutdown filter time tUVLO 4.5 5.0 5.5 V VVS decreasing - 20 - s - VUVVR Under voltage diagnosis filter time tUVVR 5.5 6.0 6.5 V VVS decreasing 10 - 30 s - - 0.5 - V - 5.2.15 Under voltage shutdown at Vs for VS1) 5.2.16 5.2.17 Under voltage warning at VREG for VREG 5.2.18 Under voltage hysteresis at VREG VUWRhys Temperature monitoring 5.2.19 Over temperature warning Tj(PW) 160 170 180 C - 5.2.20 Hysteresis for over temperature warning dTj(OW) 10 - 20 C - VOCTH 4.5 - 4.99 V - Over current detection 5.2.21 Over current detection level Data Sheet 21 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Electrical Characteristics - Protection and diagnostic functions (cont'd) VS = 7.0 to 34V, Tj = -40 to +150C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter 5.2.22 Filter time for over current detection tOC ERR pin 5.2.23 5.2.24 Symbol Limit Values Unit Conditions Min. Typ. Max. 2.3 - 4.3 s - 4.6 - - V - - 3 s VVS=7V; CLOAD=1nF; 60 100 170 k - 2) VERR Rise time ERR (20 - 80% of internal tf(ERR) ERR output voltage 5V) 5.2.25 Internal pull-down resistor ERR to GND Rf(ERR) 1) Not subject to production test, specified by design. 2) ERR pin and Reset & Enable functional between VVS=6 ... 7V, but characteristics might be out of specified range Data Sheet 22 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM 5.3 Shunt Signal Conditioning The TLE7181EM incorporates a fast and precise operational amplifier for conditioning and amplification of the current sense shunt signal. The gain of the OpAmp is adjustable by external resistors within a range higher than 5. The usage of higher gains in the application might be limited by required settling time and band width. It is recommended to apply a small offset to the OpAmp, to avoid operation in the lower rail at low currents. The output of the OpAmp ISO is not short-circuit proof. V DD RREF1 TLE718xEM R S1 ISP R shunt + ISO ISN R S2 external + RREF2 - ERR RFB Figure 6 VOCTH RFB=(R REF1 ||R REF2 ) Shunt Signal Conditioning Block Diagram and Over Current Limitation Over current warning see Chapter 5.2.8. 5.3.1 Electrical Characteristics Electrical Characteristics - Current sense signal conditioning VS = 7.0 to 36V, Tj = -40 to +150C, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Unit Conditions Min. Typ. Max. 5.3.1 Series resistors 100 500 5.3.2 Feedback resistor Limited by the output voltage dynamic range RS Rfb 1000 - 2000 7500 - - 5.3.3 Resistor ratio (gain ratio) 5.3.4 Steady state differential input voltage range across VIN Rfb/RS VIN(ss) 5 - - - - -400 - 400 mV - 5.3.5 Input differential voltage (ISP - ISN) VIDR -800 - 800 mV - 5.3.6 Input voltage (Both Inputs - GND) (ISP - GND) or (ISN -GND) -800 - 2000 mV - 5.3.7 Input offset voltage of the I-DC link VIO OpAmp, including temperature drift - - +/-2 mV 5.3.8 Input bias current (ISN,ISP to GND) IIB -300 - - A 5.3.9 Low level output voltage of ISO -0.1 - 0.2 V RS=500; VCM=0V; VISO=1.65V; VCM=0V; VISO=open IOH=3mA Data Sheet VLL VOL Limit Values 23 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Electrical Characteristics - Current sense signal conditioning (cont'd) VS = 7.0 to 36V, Tj = -40 to +150C, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Min. Typ. Max. 5.3.10 High level output voltage of ISO VOH 4.75 - 5.2 5.3.11 Output short circuit current - Differential input resistance1) ISCOP RI CCM CMRR 5 5.3.12 100 - - - 80 100 1) Limit Values Unit Conditions V IOH=-3mA - mA - - k - 10 pF 10kHz - dB - - dB VIN=360mV* 5.3.13 Common mode input capacitance 5.3.14 Common mode rejection ratio at DC CMRR = 20*Log((Vout_diff/Vin_diff) * (Vin_CM/Vout_CM)) 5.3.15 Common mode suppression2) with CMS CMS = 20*Log(Vout_CM/Vin_CM) Freq =100kHz Freq = 1MHz Freq = 10MHz - dV/dt - 10 - V/s Gain 5; RL=1.0k; CL=500pF sin(2**freq*t); Rs=500; Rfb=7500 62 43 23 5.3.16 Slew rate 5.3.17 Large signal open loop voltage gain AOL (DC) 80 100 - dB - 5.3.18 Unity gain bandwidth1) GBW FM 10 20 - MHz RL=1k; CL=100pF - 50 - Gain 5; RL=1k; CL=100pF - 12 - dB RL=1k; CL=100pF 0.7 1.3 - MHz Gain=15; RL=1k; CL=500pF; Rs=500 Gain=15; RL=1k; CL=500pF; 0.3<VISO< 4.8V; Rs=500 1) 5.3.19 Phase margin 5.3.20 Gain margin 1) 5.3.21 Bandwidth AM BWG 5.3.22 Output settle time to 98% tset1 - 1 1.8 s 5.3.23 Output settle time to 98%1) tset2 - 4.6 - s Gain=75; RL=1k; CL=500pF; 0.3<VISO< 4.8V; Rs=500 1) Not subjected to production test; specified by design 2) Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. Data Sheet 24 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Application Information 6 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. This is the description how the IC is used in its environment... L 2,2H VBAT RVS RG CVS2 10nF CVS1 2,2F CREG2 10nF PGND VS VREG GND CREG1 2,2F RRPS 4.7k PGND RPP VDH BH1 ____ ERR CBS1 330nF THS1 GH1 CC1 + CSNH1 RGH1 CB1 R SNH1 SH1 BH2 ENA DRVDIS CBS2 330nF PGND GH2 RGH2 PWM CSNH2 CC2 + CB2 R SNH2 SH2 DIR DT THS2 TLE 7181EM PGND RDT M TLS 1 C SNL1 C e.g.: XC878 GL1 RGL1 RSNL1 TLS 2 VDD C SNL2 GL2 RGL2 RSC1 SCDL R SNL2 SL Vref RSC2 RREF1 ISO RISO ISP CISO 100pF ISN GND GND R CIS REF2 50pF GND RS2 Shunt GND RS1 RFB RFB =(RREF1||RREF2) GND Figure 7 GND PGND Application Diagram 1: DC-Brush motor controlled by TLE7181EM Note: This are very simplified examples of an application circuit. The function must be verified in the real application. Data Sheet 25 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Application Information 6.1 Layout Guide Lines Please refer also to the simplified application example. * * * * * * * * * Two separated bulk capacitors CB should be used - one per half bridge Two separated ceramic capacitors CC should be used - one per half bridge Each of the two bulk capacitors CB and each of the two ceramic capacitors CC should be assigned to one of the half bridges and should be placed very close to it The components within one half bridge should be placed close to each other: high side MOSFET, low side MOSFET, bulk capacitor CB and ceramic capacitor CC (CB and CC are in parallel) and the shunt resistor form a loop that should be as small and tight as possible. The traces should be short and wide The connection between the source of the high side MOSFET and the drain of the low side MOSFET should be as low inductive and as low resistive as possible. VDH is the sense pin used for short circuit detection; VDH should be routed (via Rvdh) to the common point of the drains of the high side MOSFETs to sense the voltage present on drain high side SL is the sense pin used for short circuit detection; SL should be routed o the common point of the source of the low side MOSFETs to sense the voltage present on source low side Additional R-C snubber circuits (R and C in series) can be placed to attenuate/suppress oscillations during switching of the MOSFETs, there may be one or two snubber circuits per half bridge, R (several Ohm) and C (several nF) must be low inductive in terms of routing and packaging (ceramic capacitors) if available the exposed pad on the backside of the package should be connected to GND 6.2 * Further Application Information For further information you may contact http://www.infineon.com/ Data Sheet 26 Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Package Outlines 0.2 M 0.64 0.25 6 0.2 D 0.2 M D Bottom View A 24 13 1 3.9 0.11) 0.08 C Seating Plane C A-B D 24x 0.19 +0.06 0.1 C D 12 B 8.65 0.1 Index Marking 1 12 24 13 2.65 0.25 0.25 0.05 2) 2x 8 MAX. C 0.65 0.35 x 45 1.7 MAX. Stand Off (1.47) Package Outlines 0.1+0 -0.1 7 6.4 0.25 0.1 C A-B 2x 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.13 max. PG-SSOP-24-4-PO V01 Figure 8 PG-SSOP-24-4 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 27 Dimensions in mm Rev 1.1, 2010-09-30 H-Bridge and Dual Half Bridge Driver IC TLE7181EM Revision History 8 Revision History Revision Date Changes 1.1 2010-09-30 Datasheet Max rating of current at RPP pin increased 1.0 2010-09-29 Datasheet Thermal resistance of package adjusted Output rise time adjusted Pull up and pull down resistor values adapted Dead time values centered Go to sleep time modified Filter time of short circuit detection adjusted SCDL pin open detection description improved Overview of error condition table improved Filter time and blanking time of short circuit detection adjusted SCDL open pin detection level added Filter time of SCDL open pin detection adjusted Over voltage warning at Vs and/or VDH centered Over voltage warning hysteresis for Vs and/or VDH centered Over voltage warning filter time for Vs and/or VDH centered ERR output voltage added OpAmp bandwidth adjusted 0.8 2010-08-31 Preliminary Datasheet 0.7 2009-11-19 Target data sheet 0.6 2008-30-10 Target data sheet Data Sheet 28 Rev 1.1, 2010-09-30 Edition 2010-09-30 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2010 Infineon Technologies AG All Rights Reserved. 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