LP3883
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LP3883 3A Fast-Response Ultra Low Dropout Linear Regulators
Check for Samples: LP3883
1FEATURES DESCRIPTION
The LP3883 is a high-current, fast-response regulator
2 Ultra Low Dropout Voltage (210 mV @ 3A typ) which can maintain output voltage regulation with
Low Ground Pin Current minimum input to output voltage drop. Fabricated on
Load Regulation of 0.04%/A a CMOS process, the device operates from two input
voltages: Vbias provides voltage to drive the gate of
60 nA Typical Quiescent Current in Shutdown the N-MOS power transistor, while Vin is the input
1.5% Output Accuracy (25°C) voltage which supplies power to the load. The use of
TO-220, DDPAK/TO-263 Packages an external bias rail allows the part to operate from
ultra low Vin voltages. Unlike bipolar regulators, the
Over Temperature/over Current Protection CMOS architecture consumes extremely low
40°C to +125°C Junction Temperature Range quiescent current at any output load current. The use
of an N-MOS power transistor results in wide
APPLICATIONS bandwidth, yet minimum external capacitance is
required to maintain loop stability.
DSP Power Supplies
Server Core and I/O Supplies The fast transient response of these devices makes
them suitable for use in powering DSP,
Linear Power Supplies for PC Add-in-Cards Microcontroller Core voltages and Switch Mode
Set-Top Box Power Supplies Power Supply post regulators. The parts are available
Microprocessor Power Supplies in TO-220 and DDPAK/TO-263 packages.
High Efficiency Linear Power Supplies Dropout Voltage: 210 mV (typ) @ 3A load current.
SMPS Post-Regulators Ground Pin Current: 3 mA (typ) at full load.
Shutdown Current: 60 nA (typ) when S/D pin is low.
Precision Output Voltage: 1.5% room temperature
accuracy.
Typical Application Circuit
At least 4.7 µF of input and output capacitance is required for stability.
Connection Diagram
Figure 1. TO-220, Top View Figure 2. DDPAK/TO-263, Top View
See NDH0005D Package See KTT0005B Package
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LP3883
SNVS223F NOVEMBER 2002REVISED APRIL 2013
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Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Storage Temperature Range 65°C to +150°C
Lead Temp. (Soldering, 5 seconds) 260°C
ESD Rating Human Body Model(3) 2 kV
Machine Model(4) 200V
Power Dissipation(5) Internally Limited
VIN Supply Voltage (Survival) 0.3V to +6V
VBIAS Supply Voltage (Survival) 0.3V to +7V
Shutdown Input Voltage (Survival) 0.3V to +7V
IOUT (Survival) Internally Limited
Output Voltage (Survival) 0.3V to +6V
Junction Temperature 40°C to +150°C
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical
Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.
(4) The machine model is a 220 pF capacitor discharged directly into each pin. The machine model ESD rating of pin 5 is 100V.
(5) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values.
θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be
assumed. θJ-A for DDPAK/TO-263 devices is approximately 40°C/W if soldered down to a copper plane which is at least 1.5 square
inches in area. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.
OPERATING RATINGS
VIN Supply Voltage (VOUT + VDO) to 5.5V
Shutdown Input Voltage 0 to +6V
IOUT 3A
Operating Junction Temperature Range 40°C to +125°C
VBIAS Supply Voltage 4.5V to 6V
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ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL= 10 mA, CIN = COUT = 4.7 µF, VS/D = VBIAS.
Symbol Parameter Conditions Typical(1) MIN(2) MAX(2) Units
VOOutput Voltage Tolerance 10 mA < IL< 3A 1.198 1.234
VO(NOM) + 1V VIN 5.5V 1.216
4.5V VBIAS 6V 1.186 1.246
1.478 1.522
1.5 V
1.455 1.545
1.773 1.827
1.8 1.746 1.854
ΔVO/ΔVIN Output Voltage Line Regulation(3) VO(NOM) + 1V VIN 5.5V 0.01 %/V
ΔVO/ΔILOutput Voltage Load Regulation(4) 10 mA < IL< 3A 0.04 %/A
0.06
VDO Dropout Voltage(5) IL= 3A 270
210 mV
420
IQ(VIN) Quiescent Current Drawn from VIN 10 mA < IL< 3A 7
3 mA
Supply 8
VS/D 0.3V 1
0.03 µA
30
IQ(VBIAS) Quiescent Current Drawn from 10 mA < IL< 3A 2
1 mA
VBIAS Supply 3
VS/D 0.3V 1
0.03 µA
30
ISC Short-Circuit Current VOUT = 0V 6 A
Shutdown Input
VSDT Output Turn-off Threshold Output = ON 0.7 1.3 V
Output = OFF 0.7 0.3
Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 µs
Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15
IS/D S/D Input Current VS/D =1.3V 1 µA
VS/D 0.3V 1
AC Parameters
PSRR (VIN) Ripple Rejection for VIN Input VIN = VOUT +1V, f = 120 Hz 80
Voltage VIN = VOUT + 1V, f = 1 kHz 65 dB
PSRR (VBIAS) Ripple Rejection for VBIAS Voltage VBIAS = VOUT + 3V, f = 120 Hz 70
VBIAS = VOUT + 3V, f = 1 kHz 65
Output Noise Density f = 120 Hz µV/rootH
1z
enOutput Noise Voltage BW = 10 Hz 100 kHz 150 µV (rms)
VOUT = 1.8V BW = 300 Hz 300 kHz 90
(1) Typical numbers represent the most likely parametric norm for 25°C operation.
(2) Limits are ensured through testing, statistical correlation, or design.
(3) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(4) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load
to full load.
(5) Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value.
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TA= 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
Dropout IGND
vs vs
ILVSD
Figure 3. Figure 4.
VOUT
vs
Temperature DC Load Regulation
Figure 5. Figure 6.
Line Regulation Line Regulation
vs vs
VIN VBIAS
Figure 7. Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
IBIAS IBIAS
vs vs
ILVBIAS
Figure 9. Figure 10.
IGND
vs
VSD Noise Measurement
Figure 11. Figure 12.
VOUTStartup Waveform VOUTStartup Waveform
Figure 13. Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
Line Regulation
vs
VOUTStartup Waveform VBIAS
Figure 15. Figure 16.
Line Regulation
vs
VBIAS VIN PSRR
Figure 17. Figure 18.
VIN PSRR VBIAS PSRR
Figure 19. Figure 20.
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VOUT
100mV/DIV
ILOAD
3A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
3A/DIV
TIME (50Ps/DIV)
MAGNITUDE
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
3A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
3A/DIV
VOUT
100mV/DIV
ILOAD
3A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
3A/DIV
TIME (50Ps/DIV)
MAGNITUDE
LP3883
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SNVS223F NOVEMBER 2002REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
Load Transient Response Load Transient Response
(Both Oscon 10µF/3A) (Both Oscon 100µF/3A)
Figure 21. Figure 22.
Load Transient Response Load Transient Response
(Both POSCAP 100µF/3A) (SANYO 150µF/3A)
Figure 23. Figure 24.
Load Transient Response Load Transient Response
(Tantalum 10µF/3A) (Tantalum 100µF/3A)
Figure 25. Figure 26.
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VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
LP3883
SNVS223F NOVEMBER 2002REVISED APRIL 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA= 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
Load Transient Response Load Transient Response
(Both Oscon 10µF/1A) (Both Oscon 100µF/1A)
Figure 27. Figure 28.
Load Transient Response Load Transient Response
(Both POSCAP 100µF/1A) (SANYO 150µF/1A)
Figure 29. Figure 30.
Load Transient Response Load Transient Response
(Tantalum 10µF/1A) (Tantalum 100µF/1A)
Figure 31. Figure 32.
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LOAD CURRENT (A)
STABLE REGION COUT = 4.7PF
COUT = 100PF
0 1 2
COUT ESR (:)
3
.001
.01
0.1
1.0
10
LP3883
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SNVS223F NOVEMBER 2002REVISED APRIL 2013
APPLICATION HINTS
EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit.
OUTPUT CAPACITOR
At least 4.7µF of output capacitance is required for stability (the amount of capacitance can be increased without
limit). The output capacitor must be located less than 1 cm from the output pin of the IC and returned to a clean
analog ground. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" range
as shown in the graph below over the full operating temperature range for stable operation.
Figure 33. Minimum ESR vs Output Load Current
Tantalum capacitors are recommended for the output as their ESR is ideally suited to the part's requirements
and the ESR is very stable over temperature. Aluminum electrolytics are not recommended because their ESR
increases very rapidly at temperatures below 10C. Aluminum caps can only be used in applications where lower
temperature operation is not required.
A second problem with Al caps is that many have ESR's which are only specified at low frequencies. The typical
loop bandwidth of a linear regulator is a few hundred kHz to several MHz. If an Al cap is used for the output cap,
it must be one whose ESR is specified at a frequency of 100 kHz or more.
Because the ESR of ceramic capacitors is only a few milli Ohms, they are not suitable for use as output
capacitors on LP388X devices. The regulator output can tolerate ceramic capacitance totaling up to 15% of the
amount of Tantalum capacitance connected from the output to ground.
OUTPUT "BYPASS" CAPACITORS
Many designers place small value "bypass" capacitors at various circuit points to reduce noise. Ceramic
capacitors in the value range of about 1000pF to 0.1µF placed directly on the output of a PNP or P-FET LDO
regulator can cause a loss of phase margin which can result in oscillations, even when a Tantalum output
capacitor is in parallel with it. This is not unique to Texas Instruments LDO regulators, it is true of any P-type
LDO regulator.
The reason for this is that PNP or P-FET regulators have a higher output impedance (compared to an NPN
regulator), which results in a pole-zero pair being formed by every different capacitor connected to the output.
The zero frequency is approximately:
Fz= 1 / (2 X πX ESR X C)
where
ESR is the equivalent series resistance of the capacitor
C is the value of capacitance (1)
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The pole frequency is:
Fp= 1 / (2 X πX RLX C)
where
RLis the load resistance connected to the regulator output (2)
To understand why a small capacitor can reduce phase margin: assume a typical LDO with a bandwidth of
1MHz, which is delivering 0.5A of current from a 2.5V output (which means RLis 5 Ohms). We then place a .047
µF capacitor on the output. This creates a pole whose frequency is:
Fp= 1 / (2 X πX 5 X .047 X 10E-6) = 677 kHz (3)
This pole would add close to 60 degrees of phase lag at the crossover (unity gain) frequency of 1 MHz, which
would almost certainly make this regulator oscillate. Depending on the load current, output voltage, and
bandwidth, there are usually values of small capacitors which can seriously reduce phase margin. If the
capacitors are ceramic, they tend to oscillate more easily because they have very little internal inductance to
damp it out. If bypass capacitors are used, it is best to place them near the load and use trace inductance to
"decouple" them from the regulator output.
INPUT CAPACITOR
The input capacitor must be at least 4.7 µF, but can be increased without limit. It's purpose is to provide a low
source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very
good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be
used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application
where temperatures go below about 10°C.
BIAS CAPACITOR
The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended).
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage
must be in the range of 4.5 - 6V to assure proper operation of the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage
is below approximately 4V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a
pull-up resistor (10 kto 100 k) for a proper operation. If this pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin
if not used.
POWER DISSIPATION/HEATSINKING
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible conditions, the junction temperature must be within the range specified under
operating conditions. The total power dissipation of the device is given by:
PD= (VINVOUT)IOUT+ (VIN)IGND
where
IGND is the operating ground current of the device (4)
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the
application, and the maximum allowable junction temperature (TJmax):
TRmax = TJmaxTAmax (5)
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
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θJA = TRmax / PD(6)
These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount
of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is 60 °C/W
for TO-220 package and 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can
dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat
sink is required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a
PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for TO263
package.
The heatsink to be used in the application should have a heatsink to ambient thermal resistance,
θHA θJA θCH θJC. (7)
In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal
resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO220 package. The value for
θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value
is unknown, 2°C/W can be assumed.
HEATSINKING DDPAK/TO-263 PACKAGE
The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are
soldered to the copper plane for heat sinking. The graph below shows a curve for the θJA of DDPAK/TO-263
package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the
copper area for heat sinking.
Figure 34. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 package
As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement.
The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W.
Figure 35 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient
temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.
Figure 35. Maximum power dissipation vs ambient temperature for DDPAK/TO-263 package
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REVISION HISTORY
Changes from Revision E (April 2013) to Revision F Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP3883ES-1.2 NRND DDPAK/
TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3883ES
-1.2
LP3883ES-1.2/NOPB ACTIVE DDPAK/
TO-263 KTT 5 45 Pb-Free (RoHS
Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3883ES
-1.2
LP3883ES-1.5/NOPB ACTIVE DDPAK/
TO-263 KTT 5 45 Pb-Free (RoHS
Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3883ES
-1.5
LP3883ESX-1.2 NRND DDPAK/
TO-263 KTT 5 500 TBD Call TI Call TI -40 to 125 LP3883ES
-1.2
LP3883ESX-1.2/NOPB ACTIVE DDPAK/
TO-263 KTT 5 500 Pb-Free (RoHS
Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3883ES
-1.2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2017
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP3883ESX-1.2 DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
LP3883ESX-1.2/NOPB DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP3883ESX-1.2 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
LP3883ESX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
MECHANICAL DATA
KTT0005B
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BOTTOM SIDE OF PACKAGE
TS5B (Rev D)
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consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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