Features
•Incorporates the ARM7TDMI® ARM® Thumb® Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
•Internal High-speed Flash
– 512 Kbytes, Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes Dual
Plane (SAM7SE512)
– 256 Kbytes (SAM7SE256) Organized in One Bank of 1024 Pages of 256 Bytes
Single Plane (SAM7SE256)
– 32 Kbytes (SAM7SE32) Organized in One Bank of 256 Pages of 128 Bytes Single
Plane (SAM7SE32)
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Pr ogramming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms
– 10,000 Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,
Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
•32 Kbytes (SAM7SE512/256) or 8 Kbytes (SAM7SE32) of Internal
High-speed SRAM, Singl e-cycle Access at Maximum Speed
•One External Bus Interface (EBI)
– Suppor ts SDRAM, Static Memory, Glueless Connection to CompactFlash® and
ECC-enabled NAND Flash
•Memory Controller (MC)
– Embedded Flash Controller
– Memory Protectio n Unit
– Abort Status and Misalignment Detection
•Reset Controller (RSTC)
– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout
Detector
– Pr ovides Extern al Reset Signal Shaping and Reset Source Status
•Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL
•Power Management Controller (PMC)
– P o wer Op timization Cap abilities, Inc ludi ng Slow Clock Mode (Down to 500 Hz) and
Idle Mode
– Three Programmable External Clock Signals
•Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
•Debug Unit (DBGU)
– Two-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
– Mode for General Purpose Two-wire UART Serial Communication
•Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
•Windowed Watchdog (WDT)
– 12-bit key-protected Programmable Counter
AT91SAM
ARM-based
Flash MCU
SAM7SE512
SAM7SE256
SAM7SE32
6222H–ATARM–25-Jan-12
2 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
– Pro vides Reset or Interrupt Signals to the System
– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
•Real-time Timer (RTT)
– 32-bit Free-running Counter with Alarm
– Runs Off the Internal RC Oscillator
•Three Parallel Input/Output Controllers (PIO)
– Eighty-eight Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individ ually Programmable Open-drain, Pull -up Resistor and Synchronous Output
– Schmitt Trigger on All inputs
•Eleven Peripheral DMA Controller (PDC) Channels
•One USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, Eight Endpoints, 2688-byte Configurable Integrated FIFOs
•One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continu ous Data Stream Capabilities with 32-bit Data Transfer
•Two Universal Synchronous/Asynchr ono us Receiver Transmitters (USAR T)
– Individual Baud Rate Generator, IrDA® Infrared Modulatio n/ D emo dul atio n
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Line Support on USART1
•One Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
•One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
•One Four-channel 16-bit PWM Controller (PWMC)
•One Two-wire Interface (TWI)
– Master, Multi-Master and Slave Mode Suppor t, All Two-wire Atmel EEPROMs Supported
– General Call Supported in Slave Mode
•One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
•SAM-BA®
– Default Boot program
– Interface with SAM-BA Graphic User Interface
•IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
•Four High-current Drive I/O lines, Up to 16 mA Each
•Power Supplies
– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components
– 1.8V or 3,3V VDDIO I/O Li nes Power Supply, Independent 3.3V VDDFL ASH Flash Power Supply
– 1.8V VDDCORE Core P ower Supply with Brownout Detector
•Fully Static Operation:
– Up to 55 MHz at 1.8V and 85⋅C Worst Case Conditions
– Up to 48 MHz at 1.65V and 85⋅C Worst Case Conditions
•Available in a 128-lead LQFP Green Package, or a 144-ball LFBGA RoHS-compliant Package
3
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
1. Description Atmel's SAM7SE Series i s a member of its Smart ARM Microcontroller family based on the 32-
bit ARM7™ RISC processor and high-speed Flash memory.
• SAM7SE512 features a 512-Kbyte high-speed Flash and a 32 Kbyte SRAM.
• SAM7SE256 features a 256-Kbyte high-speed Flash and a 32 Kbyte SRAM.
• SAM7SE32 features a 32-Kbyte high-speed Flash and an 8 Kbyte SRAM.
It also embeds a large set of peripherals, including a USB 2.0 device, an External Bus Interface
(EBI), and a complete set of system functions minimizing the number of external components.
The EBI incorporates controllers for synchronous DRAM (SDRAM) and Static memories and
features specific circuitry facilitating the interface for NAND Flash, SmartMedia and
CompactFlash.
The device is an ideal migration path fo r 8/16 -b it micr ocont roller user s look ing for additi onal pe r-
formance, extended memory and higher levels of system integration.
The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via
a parallel interface on a production programmer prior to moun ting. Built- in lock bits and a secu-
rity bit protect the firmware from accidental overwrite and preserve its confidentiality.
The SAM7SE Series system controller includes a reset controller capable of managing the
power-on sequence of the microcontroller and the complete system. Correct device operation
can be monitored by a built-in brownout detector and a watchdog runn ing off an integrated RC
oscillator.
By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of
peripheral functions, including USART, SPI, External Bus Interface, Timer Counter, RTT and
Analog-to-Digital Converters on a monolithic chip, the SAM7SE512/256/32 is a powerful device
that provides a flexible, cost-effective solution to many embedded control applications.
1.1 Configuration Summary of the SAM7SE512, SAM7SE256 and SAM7SE32
The SAM7SE512, SAM7SE256 and SAM7SE32 differ in memory sizes and organization. Table
1-1 below summarizes th e configurations for the three devices.
Table 1-1. Configuration Summary
Device Flash Size Flash Organization RAM Size
SAM7SE512 512K bytes dual plane 32K bytes
SAM7SE256 256K bytes single plane 32K bytes
SAM7SE32 32K bytes single plane 8K bytes
4 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
2. Block Diagram
Figure 2-1. SAM7SE512/256/32 Block Dia gram Signal Description
Reset
Controller
PMC
APB
ICE
JTAG
SCAN ARM7TDMI
Processor
System Controller
AIC
DBGU PDC
PDC
PLL
OSC
RCOSC
BOD
POR
PIO
PIT
WDT
RTT
PIOA
PIOB
PIOC
PIO
PIO PIO
USART0
USART1
SPI
Timer Counter
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
TC0
TC1
TC2
ADC
ADVREF TWI
SSC
PWMC
USB Device
FIFO
Static Memory
Controller
ECC
Controller
SDRAM
Controller
EBI
CompactFlash
NAND Flash
SRAM
32 Kbytes (SE512/256)
or
8 Kbytes (SE32)
Flash
512 Kbytes (SE512)
256 Kbytes (SE256)
32 Kbytes (SE32)
1.8V
Voltage
Regulator
Memory Controller
Embedded
Flash
Controller Address
Decoder
Abort
Status Misalignment
Detection
Memory Protection
Unit
Peripheral DMA
Controller
11 Channels
Peripheral Bridge
Fast Flash
Programming
Interface
SAM-BA
Transciever
PDC
ROM
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
ADTRG
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
TCLK0
TCLK1
TCLK2
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1
RI1
NRST
VDDCORE
VDDCORE
VDDFLASH
XIN
XOUT
PLLRC
PCK0-PCK2
DRXD
DTXD
IRQ0-IRQ1
FIQ
TST
TDI
TDO
TMS
TCK
JTAGSEL VDDIN
GND
VDDOUT
VDDCORE
VDDIO
VDDFLASH
ERASE
PGMRDY
PGMNVALID
PGMNOE
PGMCK
PGMM0-PGMM3
PGMD0-PGMD15
PGMNCMD
PGMEN0-PGMEN1
D[31:0]
A0/NBS0
A1/NBS2
A[15:2], A[20:18]
A21/NANDALE
A22/REG/NANDCLE
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NCS2/CFCS1
NCS3/NANDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NBS3/CFIOW
SDCKE
RAS
CAS
SDWE
SDA10
CFRNW
NCS4/CFCS0
NCS5/CFCE1
NCS6/CFCE2
NCS7
NANDOE
NANDWE
NWAIT
SDCK
DDM
DDP
PWM0
PWM1
PWM2
PWM3
TF
TK
TD
RD
RK
RF
TWD
TWCK
5
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
3. Signal Description
Table 3-1. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDIN Voltage Regulator and ADC P ower
Supply Input Power 3V to 3.6V
VDDOUT Voltage Regulator Output Pow er 1.85V
VDDFLASH Flash and USB Power Supply Power 3V to 3.6V
VDDIO I/O Lines Power Supply Power 3V to 3.6V or 1.65V to 1.95V
VDDCORE Core Power Supply Power 1.65V to 1.95V
VDDPLL PLL Power 1.65V to 1.95V
GND Ground Ground
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input
XOUT Main Oscillator Ou tput Output
PLLRC PLL Filter Input
PCK0 - PCK2 Programmable Clock Output Output
ICE and JTAG
TCK Test Clock Input No pull-up resistor
TDI Test Data In Input No pull-up resistor
TDO Test Data Out Output
TMS Test Mode Select Input No pull-up resistor.
JTAGSEL JTAG Selection Input Pull-down resistor (1)
Flash Memory
ERASE Flash and NVM Configuration Bits
Erase Command Input High Pull-down resistor (1)
Reset/Test
NRST M icrocontroller Reset I/O Low Open drain with pull-up resistor (1)
TST Test Mode Select Input High Pull-down resistor (1)
Debug Uni t
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
AIC
IRQ0 - IRQ1 External Interrupt Inputs Input
FIQ Fast Interrupt Input Input
6 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
PIO
PA0 - PA31 Parallel IO Controller A I/O Pulled-up input at reset
PB0 - PB31 Parallel IO Controller B I/O Pulled-up input at reset
PC0 - PC23 Parallel IO Controller C I/O Pulled-up input at reset
USB Device Port
DDM USB Device Port Data - Analog
DDP USB De vice Port Data + Analog
USART
SCK0 - SCK1 Serial Clock I/O
TXD0 - TXD1 Tra n s mi t Da t a I/O
RXD0 - RXD1 Receive Data Input
RTS0 - RTS1 Request To Send Output
CTS0 - CTS1 Clear To Send Input
DCD1 Data Carrier Detect Input
DTR1 Data Term inal Ready Output
DSR1 Data Set Ready Input
RI1 Ring Indicator Input
Synchronous Serial Controller
TD Transmit Data Output
RD Receive Data Input
TK Transmit Clock I/O
RK Receive Clock I/O
TF Transmit Frame Sync I/O
RF Receive Frame Sync I/O
Timer/Counter
TCLK0 - TCLK2 External Clock Inputs Input
TIOA0 - TIOA2 Timer Counter I/O Line A I/O
TIOB0 - TIOB2 Timer Counter I/O Line B I/O
PWM Controller
PWM0 - PWM3 PWM Channels Output
Serial Peripheral Interface
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
SPCK SPI Serial Clock I/O
NPCS0 SPI Peripheral Chip Select 0 I/O Low
NPCS1-NPCS3 SPI Peripheral Chip Select 1 to 3 Output Low
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
7
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Two-Wire Interface
TWD Two-wire Serial Data I/O
TWCK Two-wire Serial Clock I/O
Analog-to-Digital Converter
AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset
AD4-AD7 Analog Inputs Analog Analog Inputs
ADTRG ADC Trigger Input
ADVREF ADC Reference Analog
Fast Flash Programming Interface
PGMEN0-PGMEN2 Programming Enabling Input
PGMM0-PGMM3 Programming Mode Input
PGMD0-PGMD15 Progra mming Data I/O
PGMRDY Pr ogramming Ready Output High
PGMNVALID Data Direction Output Low
PGMNOE Programming Read Input Low
PGMCK Programming Clock Input
PGMNCMD Programming Command Input Low
External Bus Interface
D[31:0] Data Bus I/O
A[22:0] Address Bus Output
NWAIT External Wait Signal Input Low
Static Memory Controller
NCS[7:0] Chip Select Lines Output Low
NWR[1:0] Write Signals Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NUB NUB: Upper Byte Select Output Low
NLB NLB: Lower Byte Select Output Low
EBI for CompactFlash Support
CFCE[2:1] CompactFlash Chip Enable Output Low
CFOE CompactFlash Output Enable Output Low
CFWE CompactFlash Write Enable Output Low
CFIOR CompactFlash I/O Read Signal Output Low
CFIOW CompactFlash I/O Write Signal Output Low
CFRNW CompactFlash Read Not Write Signal Output
CFCS[1:0] CompactFlash Chip Select Lines Output Low
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
8 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Note: 1. Refer to Section 6. ”I/O Lines Considerations” .
EBI for NAND Flash Support
NANDCS NAND Flash Chip Select Line Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
NANDCLE NAND Flash Command Line Enable Output Low
NANDALE NAND Flash Address Line Enable Output Low
SDRAM Controller
SDCK SDRAM Clock Output Tied low after reset
SDCKE SDRAM Clock Enable Output High
SDCS SDRAM Controller Chip Select Line Output Low
BA[1:0] Bank Select Output
SDWE SDRAM Write Enable Output Low
RAS - CAS Row and Column Signal Output Low
NBS[3:0] Byte Mask Signals Output Low
SDA10 SDRAM Address 10 Line Output
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
9
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
4. Package The SAM7SE512/256/32 is available in:
• 20 x 14 mm 128-lead LQFP package with a 0.5 mm lead pitch.
• 10x 10 x 1.4 mm 144-ba ll LFBGA package with a 0.8 mm lead pitch
4.1 128-lead LQFP Package Outline
Figure 4-1 shows the orientation of the 128 -lead LQFP package and a detailed mechanical
description is given in the Mechanical Characteristics section of the full datasheet.
Figure 4-1. 128-lead LQFP Package Outline (Top View)
65
103
102
64
39
38
1
128
10 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
4.2 128-lead LQFP Pinout
Table 4-1. Pinout in 128-lead LQFP Package
1 ADVREF 33 PB31 65 TDI 97 SDCK
2 GND 34 PB30 66 TDO 98 PC8
3 AD7 35 PB29 67 PB2 99 PC7
4 AD6 36 PB28 68 PB1 100 PC6
5 AD5 37 PB27 69 PB0 101 PC5
6 AD4 38 PB26 70 GND 102 PC4
7 VDDOUT 39 PB25 71 VDDIO 103 PC3
8 VDDIN 40 PB24 72 VDDCORE 104 PC2
9 PA20/PGMD8/AD3 41 PB23 73 NRST 105 PC1
10 PA19/PGMD7/AD2 42 PB22 74 TST 106 PC0
11 PA18/PGMD6/AD1 43 PB21 75 ERASE 107 PA31
12 PA17/PGMD5/AD0 44 PB20 76 TCK 108 PA30
13 PA16/PGMD4 45 GND 77 TMS 109 PA29
14 PA15/PGMD3 46 VDDIO 78 JTAGSEL 110 PA28
15 PA14/PGMD2 47 VDDCORE 79 PC23 111 PA27/PGMD15
16 PA13/PGMD1 48 PB19 80 PC22 112 PA26/PGMD14
17 PA12/PGMD0 49 PB18 81 PC21 113 PA25/PGMD13
18 PA11/PGMM3 50 PB17 82 PC20 114 PA24/PGMD12
19 PA10/PGMM2 51 PB16 83 PC19 115 PA23/PGMD11
20 PA9/PGMM1 52 PB15 84 PC18 116 PA22/PGMD10
21 VDDIO 53 PB14 85 PC17 117 PA21/PGMD9
22 GND 54 PB13 86 PC16 118 VDDCORE
23 VDDCORE 55 PB12 87 PC15 119 GND
24 PA8/PGMM0 56 PB11 88 PC14 120 VDDIO
25 PA7/PGMNVALID 57 PB10 89 PC13 121 DM
26 PA6/PGMNOE 58 PB9 90 PC12 122 DP
27 PA5/PGMRDY 59 PB8 91 PC11 123 VDDFLASH
28 PA4/PGMNCMD 60 PB7 92 PC10 124 GND
29 PA3 61 PB6 93 PC9 125 XIN/PGMCK
30 PA2/PGMEN2 62 PB5 94 GND 126 XOUT
31 PA1/PGMEN1 63 PB4 95 VDDIO 127 PLLRC
32 PA0/PGMEN0 64 PB3 96 VDDCORE 128 VDDPLL
11
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
4.3 144-ball LFBGA Package Outline
Figure 4-2 shows the orientation of the 14 4-ball LFBGA package and a detaile d mechanical
description is given in the Mechanical Characteristics section.
Figure 4-2. 144-ball LFBGA Packa ge Outline (Top View)
ABCDEFGHJKLM
12
11
10
9
8
7
6
5
4
3
2
1
Ball A1
12 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
4.4 144-ball LFBGA Pinout
Table 4-2. SAM7SE512/256/32 Pinout for 144-ball LFBGA Package
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 PB7 D1 VDDCORE G1 PC18 K1 PC11
A2 PB8 D2 VDDCORE G2 PC16 K2 PC6
A3 PB9 D3 PB2 G3 PC17 K3 PC2
A4 PB12 D4 TDO G4 PC9 K4 PC0
A5 PB13 D5 TDI G5 VDDIO K5 PA27/PGMD15
A6 PB16 D6 PB17 G6 GND K6 PA26/PGMD14
A7 PB22 D7 PB26 G7 GND K7 GND
A8 PB23 D8 PA14/PGMD2 G8 GND K8 VDDCORE
A9 PB25 D9 PA12/PGMD0 G9 GND K9 VDDFLASH
A10 PB29 D10 PA11/PGMM3 G10 AD4 K10 VDDIO
A11 PB30 D11 PA8/PGMM0 G11 VDDIN K11 VDDIO
A12 PB31 D12 PA7/PGMNVALID G12 VDDOUT K12 PA18/PGMD6/AD1
B1 PB6 E1 PC22 H1 PC15 L1 SDCK
B2 PB3 E2 PC23 H2 PC14 L2 PC7
B3 PB4 E3 NRST H3 PC13 L3 PC4
B4 PB10 E4 TCK H4 VDDCORE L4 PC1
B5 PB14 E5 ERASE H5 VDDCORE L5 PA29
B6 PB18 E6 TEST H6 GND L6 PA24/PGMD12
B7 PB20 E7 VDDCORE H7 GND L7 PA21/PGMD9
B8 PB24 E8 VDDCORE H8 GND L8 ADVREF
B9 PB28 E9 GND H9 GND L9 VDDFLASH
B10 PA4/PGMNCMD E10 PA9/PGMM1 H10 PA19/PGMD7/AD2 L10 VDDFLASH
B11 PA0/PGMEN0 E11 PA10/PGMM2 H11 PA20/PGMD8/AD3 L11 PA17/PGMD5/AD0
B12 PA1/PGMEN1 E12 PA13/PGMD1 H12 VDDIO L12 GND
C1 PB0 F1 PC21 J1 PC12 M1 PC8
C2 PB1 F2 PC20 J2 PC10 M2 PC5
C3 PB5 F3 PC19 J3 PA30 M3 PC3
C4 PB11 F4 JTAGSEL J4 PA28 M4 PA31
C5 PB15 F5 TMS J5 PA23/PGMD11 M5 PA25/PGMD13
C6 PB19 F6 VDDIO J6 PA22/PGMD10 M6 DM
C7 PB21 F7 GND J7 AD6 M7 DP
C8 PB27 F8 GND J8 AD7 M8 GND
C9 PA6/PGMNOE F9 GND J9 VDDCORE M9 XIN/PGMCK
C10 PA5/PGMRDY F10 AD5 J10 VDDCORE M10 XOUT
C11 PA2/PGMEN2 F11 PA15/PGMD3 J11 VDDCORE M11 PLLRC
C12 PA3 F12 PA16/PGMD4 J12 VDDIO M12 VDDPLL
13
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
5. Power Considerations
5.1 Power Supplies
The SAM7SE512/256/32 has six types of power supply pins and integrates a voltage regulator,
allowing the device to be su pplied with only one voltage. The six power supply pin types are:
• VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V,
3.3V nominal.
• VDDOUT pin. It is the output of the 1.8V voltage regulator.
• VDDIO pin. It powers the I/O lines; two voltage ranges are supported:
– from 3.0V to 3.6 V, 3.3V nominal
– or from 1.65V to 1.95V, 1.8V nominal.
• VDDFLASH pin. I t powers the USB transceivers and a part of the Flash. It is required for the
Flash to operate correctly; voltage r anges from 3.0V to 3.6V, 3.3V nominal.
• VDDCORE pins. They power the logic of the device; v oltage ranges from 1.65V to 1.95V,
1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE
is required for the device, including its embedded Flash, to operate correctly.
• VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the
VDDOUT pin.
In order to de crease current consum ption, if the voltage regula tor and the ADC are not u sed,
VDDIN, ADVREF, AD4, AD5, AD6 and AD7 should be connected to GND. In this case VDDOUT
should be left unconnected.
No separate ground pins are provided for the different power supplies. Only GND pins are pro-
vided and should be connected as shortly as possible to the system ground plane.
5.2 Power Consumption
The SAM7SE512/256/32 has a static current of less than 60 µA on VDDCORE at 25°C, includ-
ing the RC oscillator, the voltage regulator and the power-on reset when the brownout detector
is deactivated. Activating the brownout detector adds 20 µA static current.
The dynamic power consumption on VDDCORE is less than 80 mA at full speed when running
out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not
exceed 10 mA.
5.3 Voltage Regulator
The SAM7SE512/256/32 embeds a voltage regulator that is managed by the System Controller.
In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100
mA of output curre nt.
The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 20 µA
static current and draws 1 mA of output current.
Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscil-
lations. The best way to achieve this is to use two capacitors in parallel:
• One external 470 pF (or 1 nF) NPO capacitor should be connected betw een VDDOUT and
GND as close to the chip as possible.
14 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and
GND.
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
and reduce sour ce voltage drop. The input decoupling capacitor sho uld be placed close to the
chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4. 7 µF X7R.
5.4 Typical Powering Schematics
The SAM7SE512/256/32 supports a 3.3V single supply mode. The internal regulator input con-
nected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. F igure 5-1 shows
the power schematics to be used for USB bus-powered systems.
Figure 5-1. 3.3V System Single Power Supply Schematic
Power Source
ranges
from 4.5V (USB)
to 18V
3.3V
VDDIN
Voltage
Regulator
VDDOUT
VDDIO
DC/DC Converter
VDDCORE
VDDFLASH
VDDPLL
15
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
6. I/O Lines Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs. TMS, TDI and TCK do not integrate a pull-up
resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asser ted at a high level. The
JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ.
To eliminate any risk of spuriously entering the JTAG boundary scan mode due to noise on
JTAGSEL, it should be tied externally to GND if boundary scan is not used, or put in place an
external low value resistor (such as 1 kΩ) .
6.2 Test Pin The TST pin is used for manufacturing test or fast programming mode of the
SAM7SE512/256/32 when asserted high. The TST pin integrates a permanent pull-down resis-
tor of about 15 kΩ to GND.
To eliminate any risk of entering the test mode due to noise on the TST pin, it should be tied to
GND if the FFPI is not used, or put in place an external low value resistor (such as 1 kΩ) .
To enter fast programming mod e, the TST pin and the PA0 and PA1 pins should be tied high
and PA2 tied low.
Driving the TST pin at a h igh level wh ile PA0 or PA1 is driven at 0 leads to unp redictable resu lts.
6.3 Reset Pin The NRST pin is bidirectional with an open-drain out put buffer. It is handled by the on-chip reset
controller and can be dr iven low to provide a r eset signal to th e external compon ents or asse rted
low externally to reset th e microcontr oller. There is no constraint on the le ngth of the re set pulse,
and the reset cont roller can gu arant ee a minimum p u lse length . This allows conn ection of a sim-
ple push-button on the NRST pin as system user reset, and the use of the NRST signal to reset
all the components of the system.
An external power-on reset can drive this pin during the start-up instead of using the internal
power-on reset circuit.
The NRST pin integrat es a permanent pull-up of about 100 kΩ resistor to VDDIO.
This pin has Schmitt trigger input.
6.4 ERASE Pin The ERASE pin is used to re-ini tialize t he Flash con tent and some of its NVM bits . It int egrates a
permanent pull-down resistor of about 15 kΩ to GND.
To eliminate any risk of erasing the Flash due to noise on the ERASE pin, it should be tied exter-
nally to GND, which prevents erasing the Flash from the application, or put in place an external
low value resistor (s uc h as 1 kΩ) .
This pin is debounced by the RC oscillator to improve the glitch tolerance. When the pin is tied to
high during less than 100 ms, ERASE pin is not taken into account. The pin must be tied high
during more than 220 ms to perform the re-initialization of the Flash.
16 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
6.5 SDCK Pin The SDCK pin is dedicated to the SDRAM Clock and is an out put-only witho ut pull-up. Maximum
Output Frequency of this pad is 48 MHz at 3.0V and 25 MHz at 1.65V with a maximum load of
30 pF.
6.6 PIO Controller lines
All the I/O lines PA0 to PA31, PB0 to PB31, PC0 to PC23 inte grate a programmable pull-up
resistor. Programming of this pull-up resistor is performed independently for each I/O line
through the PI O controllers.
Typical pull-up value is 100 kΩ.
All the I/O lines have schmitt trigger inputs.
6.7 I/O Lines Current Drawing
The PIO lines PA0 to PA3 are high-d rive current capable . Each of these I/ O lines can drive up to
16 mA permanently.
The remaining I/O lines can draw only 8 mA.
However, the total current drawn by all the I/O lines cannot exceed 300 mA.
17
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
7. Processor and Architecture
7.1 ARM7TDMI Processor
• RISC processor based on ARMv4T Von Neumann architecture
– Runs at up to 55 MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V)
• Two instruction sets
–ARM
® high-performance 32-bit instruction set
–Thumb
® high code density 16-bit instruction set
• Three-stage pipeline architecture
– Instruction Fetch (F)
– Instruction Deco de (D)
– Execute (E)
7.2 Debug and Test Features
• EmbeddedICE™ (Integrated embedded in-circuit emulator)
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
• Debug Unit
–Two-pin UART
– Deb ug communication channel interrupt handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on all digital pins
7.3 Memory Controller
• Programmable Bus Arbiter
– Handles requests from the ARM7TDMI and the Peripheral DMA Controller
• Address decoder provides selection signals for
– Four internal 1 Mbyte memory areas
– One 256-Mbyte embedded peripheral area
– Eight external 256-Mbyte memory areas
• Abort Status Registers
– Source, Type and all para meters of the access leading to an abort are saved
– Facilitates debug by detection of bad pointers
• Misalignment Detector
– Alignment checking of all data accesses
– Abort generation in case of misalignment
• Remap Command
– Remaps the SRAM in place of the embedded non-volatile memory
– Allows handling of dynamic exception vectors
• 16-area Memory Protection Unit (Internal Memory and peripheral prot ection only)
18 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
– Individually programmable size between 1K Byte and 1M Byte
– Individually programmable pro tection against write and/or user access
– Peripheral protection against write and/or user access
• Embedded Flash Controller
– Embedded Flash interface, up to three pr ogrammable wait states
– Prefetch buffer, buffering and anticipating the 16-bit requ ests, reducing the required
wait states
– Key-protected program, erase and lock/unlock sequencer
– Single command for erasing, programming and locking operations
– Interrupt generation in case of forbidden operation
7.4 External Bus Interface
• Integrates Three External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
– ECC Controller
• Additional Logic for NAND Flash and CompactFlash® Support
– NAND Flash support: 8-bit as we ll as 16-bit de vices are supported
– CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True
IDE) are supported but the signals _IOIS16 ( I/O and True IDE modes) and -ATA SEL
(True IDE mode) are not handled.
• Optimized External Bus:
– 16- or 32-bit Data Bus (32-bit Data Bus for SDRAM only)
– Up to 23-bit Address Bus, Up to 8-Mbytes Addressable
– Up to 8 Chip Selects, each reserved to one of the eight Memory Areas
– Optimized pin multiplexing to reduce latencies on External Memories
• Configurable Chip Select Assignment:
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2, Optional CompactFlash Support
– Static Memory Controller on NCS3, NCS5 - NCS6, Optional NAND Flash Support
– Static Memory Controller on NCS4, Optional CompactFlash Support
– Static Memory Controller on NCS7
7.5 Static Memory Controller
• External memory mapping, 512-Mbyte address space
• 8-, or 16-bit Data Bus
• Up to 8 Chip Select Lines
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Two different Read Protocols for each Memor y Bank
19
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• Multiple device adaptability
– Compliant with LCD Module
– Compliant with PSRAM in synchronous operations
– Programmable Setup Time Read/Write
– Programmable Hold Time Read/Write
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
7.6 SDRAM Contr oller
• Numerous configurations suppor ted
– 2K, 4K, 8K Row Address Memory P arts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32- bit Data Path
• Programming facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
• Energy-saving capabilities
– Self-refresh, and Low-power Modes supported
• Error detecti on
– Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• Latency is set to two cl ocks (CAS Latency of 1, 3 Not Supported)
• Auto Precharge Command not used
• Mobile SDRAM supported (except for low-power extended mode and deep power-down
mode)
7.7 Err or Corrected Code Controller
• Tracking the accesses to a NAND F lash de vice by triggering on the correspon ding chip select
• Single bit error correction and 2-bit Rando m detection.
• Automatic Hamming Code Calculation while writing
– ECC value available in a register
• Automatic Hamming Code Calculation while reading
– Error Report, including error flag, correctable error flag and word address being
detected erroneous
– Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte
pages
20 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
7.8 Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Eleven channels
– Two for each USART
– Two for the Debug Unit
– Two for the Serial Synchronous Controller
– Two for the Serial Peripheral Interface
– One for the Analog-to-digital Converter
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interr upt latency requirements
• P eripheral DM A Controller (PDC) priority is as f ollows (from the highest priority to the low est):
Receive DBGU
Receive USART0
Receive USART1
Receive SSC
Receive ADC
Receive SPI
Transmit DBGU
Transmit USART0
Transmit USART1
Transmit SSC
Transmit SPI
21
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
8. Memories • 512 Kbytes of Flash Memory (SAM7SE512)
– dual plane
– two contiguo us ba n ks of 10 2 4 pa ge s of 256 bytes
– Fast access time, 30 MHz single-cycle access in Worst Case conditions
– Page programming tim e: 6 ms, including page au to -e rase
– Page programming without auto-erase: 3 ms
– Full chip erase time: 15 ms
– 10,000 write cycles, 10-year data retention capability
– 32 lock bits, each protecting 32 lock regions of 64 pa ge s
– Protection Mode to secure contents of the Flash
• 256 Kbytes of Flash Memory (SAM7SE256)
– single plane
– one bank of 1024 pages of 25 6 bytes
– Fast access time, 30 MHz single-cycle access in Worst Case conditions
– Page programming tim e: 6 ms, including page au to -e rase
– Page programming without auto-erase: 3 ms
– Full chip erase time: 15 ms
– 10,000 cycles, 10-year data retention capability
– 16 lock bits, each protecting 16 lock regions of 64 pa ge s
– Protection Mode to secure contents of the Flash
• 32 Kbytes of Flash Memory (SAM 7SE32 )
– single plane
– one bank of 256 pages of 128 bytes
– Fast access time, 30 MHz single-cycle access in Worst Case conditions
– Page programming tim e: 6 ms, including page au to -e rase
– Page programming without auto-erase: 3 ms
– Full chip erase time: 15 ms
– 10,000 cycles, 10-year data retention capability
– 8 lock bits, each protecting 8 lock regions of 32 pages
– Protection Mode to secure contents of the Flash
• 32 Kbytes of Fast SRAM (SAM7SE512/256)
– Single-cycle access at full speed
• 8 Kbytes of Fast SRAM (SAM7SE32)
– Single-cycle access at full speed
22 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 8-1. SAM7SE Memory Mapping
Internal Peripherals
0x1000 0000
0x0000 0000
0x0FFF FFFF
0x2000 0000
0x1FFF FFFF
0x3000 0000
0x2FFF FFFF
0x4000 0000
0x3FFF FFFF
0x6FFF FFFF
0x6000 0000
0x5FFF FFFF
0x5000 0000
0x4FFF FFFF
0x7000 0000
0x7FFF FFFF
0x8000 0000
0x8FFF FFFF
0x9000 0000
0xF000 0000
0xEFFF FFFF
0xFFFF FFFF
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
6 x 256 MBytes
1,536 MBytes
0x000F FFFF
0x0010 0000
0x001F FFFF
0x0020 0000
0x002F FFFF
0x0030 0000
0x003F FFFF
0x0040 0000
0x0000 0000
1 MBytes
1 MBytes
1 MBytes
1 MBytes
252 MBytes
0xFFFA 0000
0xFFFA 3FFF
0xFFFA 4000
0xF000 0000
0xFFFB 8000
0xFFFC 0000
0xFFFC 3FFF
0xFFFC 4000
0xFFFC 7FFF
0xFFFD 4000
0xFFFD 7FFF
0xFFFD 3FFF
0xFFFD FFFF
0xFFFE 0000
0xFFFE 3FFF
0xFFFF EFFF
0xFFFF F000
0xFFFF FFFF
0xFFFE 4000
0xFFFB 4000
0xFFFB 7FFF
0xFFF9 FFFF
0xFFFC FFFF
0xFFFD 8000
0xFFFD BFFF
0xFFFC BFFF
0xFFFC C000
0xFFFB FFFF
0xFFFB C000
0xFFFB BFFF
0xFFFA FFFF
0xFFFB 0000
0xFFFB 3FFF
0xFFFD 0000
0xFFFD C000
0xFFFC 8000
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
0x0FFF FFFF
512 Bytes/128 registers
512 Bytes/128 registers
512 Bytes/128 registers
256 Bytes/64 registers
16 Bytes/4 registers
16 Bytes/4 registers
16 Bytes/4 registers
16 Bytes/4 registers
256 Bytes/64 registers
4 Bytes/1 register
512 Bytes/128 registers
512 Bytes/128 registers
0xFFFF F000
0xFFFF F200
0xFFFF F1FF
0xFFFF F3FF
0xFFFF F9FF
0xFFFF FBFF
0xFFFF FCFF
0xFFFF FEFF
0xFFFF FFFF
0xFFFF F400
0xFFFF FA00
0xFFFF FC00
0xFFFF FD0F
0xFFFF FC2F
0xFFFF FC3F
0xFFFF FD4F
0xFFFF FC6F
0xFFFF F5FF
0xFFFF F600
0xFFFF F7FF
0xFFFF F800
0xFFFF FD00
0xFFFF FF00
0xFFFF FD20
0xFFFF FD30
0xFFFF FD40
0xFFFF FD60
0xFFFF FD70
Internal Memories
EBI
Chip Select 0
SMC
EBI
Chip Select 1/
SMC or SDRAMC
EBI
Chip Select 2
SMC
EBI
Chip Select 3
SMC/NANDFlash/
SmartMedia
EBI
Chip Select 4
SMC
Compact Flash
EBI
Chip Select 5
SMC
Compact Flash
EBI
Chip Select 6
EBI
Chip Select 7
Undefined
(Abort)
(1) Can be ROM, Flash or SRAM
depending on GPNVM2 and REMAP
Flash before Remap
SRAM after Remap
Internal Flash
Internal SRAM
Internal ROM
Reserved
Boot Memory (1)
Address Memory Space Internal Memory Mapping
Note:
TC0, TC1, TC2
USART0
USART1
PWMC
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ReservedReserved
ReservedReserved
ReservedReserved
Reserved
ReservedReserved
TWI
SSC
SPI
SYSC
UDP
ADC
AIC
DBGU
PIOA
Reserved
PMC
MC
WDT
PIT
RTT
RSTC
VREG
PIOB
PIOC
Peripheral Mapping
System Controller Mapping
23
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
A first level of ad dress decod ing is perf or med by the Memor y Cont ro ller, i. e., b y the imp l ement a-
tion of the Advanced System Bus (ASB) with additional features.
Decoding splits the 4G byte s of address space int o 16 areas of 2 56M bytes. Th e areas 1 to 8 are
directed to the EBI that associates these areas to the external chip selects NC0 to NCS7. The
area 0 is reserved for the addressing of the internal memories, and a second level of decoding
provides 1M byte of internal memory area. The area 15 is reserved for the peripherals and pro-
vides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
8.1 Embedded Memories
8.1.1 Internal Memories
8.1.1.1 Internal SRAM
The SAM7SE512/256 embeds a high-speed 32-Kbyte SRAM bank. The SAM7SE32 embeds a
high-speed 8-Kbyte SRAM bank. After reset and until the Remap Command is performed, the
SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes avail-
able at address 0x0.
8.1.1.2 Internal ROMThe SAM7SE512/256 /3 2 e mbeds a n I nter na l ROM. At a ny t ime , th e ROM is m app ed at addr ess
0x30 0000. The ROM contains the FFPI and the SAM-BA boot program.
8.1.1.3 Internal Flash • The SAM7SE512 features two banks of 256 Kbytes of Flash.
• The SAM7SE256 features one bank of 256 Kbytes of Flash.
• The SAM7SE32 features one bank of 32 Kbytes of Flash.
At any time, the Flash is mapped to address 0x0010 0000.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from th e
Flash.
This GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Se t General-purpose NVM Bit” of the EFC User Interface.
Setting the GPNVM bit 2 selects the boot from the Flash, clearing it selects the boot from the
ROM. Asserting ERASE clears the GPNVM bit 2 and thus selects the boot from the ROM by
default.
24 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 8-2. Internal Memory Mapping with GPNVM Bit 2 = 0 (default)
Figure 8-3. Internal Memory Mapping with GPNVM Bit 2 = 1
8.1.2 Embedded Fl ash
8.1.2.1 Flash Overview
The Flash of the SAM7SE512 is organized in two banks (dual plane) of 1024 pages of 256
bytes. It reads as 131,072 32-bit words.
The Flash of th e SAM7SE256 is organized in 1024 pages (sing le plan e) of 25 6 byte s. It r eads as
65,536 32-bit words.
The Flash of the SAM7SE32 is organized in 256 pages (sin gle plane) of 128 bytes. It reads as
8192 32-bit words.
The Flash of the SAM7SE32 contains a 128-byte write buffer, accessible through a 32-bit
interface.
The Flash of the SAM7SE512/256 contains a 256-byte write buffer, accessible through a 32-bit
interface.
256M Bytes
ROM Before Remap
SRAM After Remap
Undefined Areas
(Abort)
0x000F FFFF
0x001F FFFF
0x002F FFFF
0x0FFF FFFF
1 M Bytes
1 M Bytes
1 M Bytes
252 M Bytes
Internal FLASH
Internal SRAM
0x0000 0000
0x0010 0000
0x0020 0000
0x0030 0000 Internal ROM
0x003F FFFF
0x0040 0000
1 M Bytes
256M Bytes
Flash Before Remap
SRAM After Remap
Undefined Areas
(Abort)
0x000F FFFF
0x001F FFFF
0x002F FFFF
0x0FFF FFFF
1 M Bytes
1 M Bytes
1 M Bytes
252 M Bytes
Internal FLASH
Internal SRAM
0x0000 0000
0x0010 0000
0x0020 0000
0x0030 0000 Internal ROM
0x003F FFFF
0x0040 0000
1 M Bytes
25
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The Flash benefits from the integration of a power reset cell and from the brownout detector.
This prevents code corruption during power supply changes, even in the worst conditions.
8.1.2.2 Embedded Flash Controller
The Embedded Flash Contro ller (EFC) man ages accesses perform ed by the m asters of t he sys-
tem. It enables reading the Flash and writing the write buffer. It also contains a User Interface,
mapped within the Memory Controller on the APB. The User Interface allows:
• programming of the access parameters of the Flash (number of wait states, timings, etc.)
• starting commands such as full erase, page erase, page program, NVM bit set, NVM bit
clear, etc.
• getting the end status of the last command
• getting error status
• programming interrupts on the end of the last commands or on errors
The Embedde d F las h Co ntroller also prov ide s a d ual 32 -b it Pre fe tc h Bu ffe r th a t op tim ize s 16 -b it
access to the Flash. This is particularly efficient when the processor is running in Thumb mode.
• Two EFCs (EFC0 and EFC1) are embedded in the SAM7SE5 12 to contro l each plane of 256
KBytes. Dual plane organization allows concurrent Read and Program.
• One EFC (EFC0) is embedded in the SAM7SE25 6 to control the single plane 256 KBytes.
• One EFC (EFC0) is embedded in the SAM7SE32 to control the single plane 32 KBytes.
8.1.2.3 Lock Regions
The SAM7SE512 Embedded Flash Controller manages 32 lock bits to protect 32 regions of the
flash against inadvertent flash erasing or programming commands. The SAM7SE512 contains
32 lock regions and each lock region contains 64 pages of 25 6 bytes. Each lock region has a
size of 16 Kbytes.
The SAM7SE256 Embedded Flash Controller manages 16 lock bits to protect 16 regions of the
flash against inadvertent flash erasing or programming commands. The SAM7SE256 contains
16 lock regions and each lock region contains 64 pages of 25 6 bytes. Each lock region has a
size of 16 Kbytes.
The SAM7SE32 Embedded Flash Controller manages 8 lock bits to protect 8 regions of the
flash against inadvertent flash erasing or programming commands. The SAM7SE32 contains 8
lock regions and each lock regio n contains 32 pages of 1 28 bytes. Each lock region has a size of
4 Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the EFC
trigs an interrupt.
The 32 (SAM7SE512), 16 (SAM7SE256) or 8 (SAM7SE32) NVM bits are software programma-
ble through the EFC User Interface. The command “Set Lock Bit” enables the protection. The
command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.1.2.4 Security Bit Feature
The SAM7SE512/256/32 features a security bit, based on a specific NVM-bit. When the security
is enabled, any access to the Flash, either through the ICE interface or through th e Fast Flash
Programming Interface, is forbidden.
26 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The security bit can only be enable d through the Command “Set Secu rity Bit” of the EFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1 and
after a full flash erase is performed. When the se curity bit is deactivated, all accesses to the
flash are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during nor mal
operation. However, it is safer to connect it directly to GND for the final application.
8.1.2.5 Non-volatile Brownout Detector Control
Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD),
so that even after a power loss, the brownout detector operations remain in their state.
These two GPNVM bits can be cleared or set respectively through the comm ands “Clear Gen-
eral-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.
• GPNVM bit 0 is used as a bro wnout de tector enab le bit. Set ting the GPNVM b it 0 enab les the
BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM bit 0 and thus
disabl es the brownout detector by default.
• GPNVM bit 1 is used as a brownout reset enab le signal for the reset controller. Setting the
GPNVM bit 1 enab les th e bro wnout reset when a bro wnout is detected, Clearing the GPNVM
bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.
8.1.2.6 Calibration Bits
Sixteen NVM bits are used to calibrate the brownout detector and the voltage regulator. These
bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on
the calibration bits.
8.1.3 F ast Flash Programming Interface
The Fast Flash Programm ing Interface allows progr amming the device through either a serial
JTAG interface or through a multiplexed fully-handshaked parallel port. It allo ws gang- program-
ming with mar ke t-standard indu s tr ial pr og ra m m er s.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered
when the TST pin and the PA0 and PA1 pins are all tied high and PA2 tied to low.
• The Flash of the SAM7SE512 is organized in 2048 pages of 256 bytes (dual plane). It reads
as 131,072 32-bit words.
• The Flash of the SAM7SE256 is organ ized in 1024 pages of 256 b ytes (single plane ). It reads
as 65,536 32-bit words.
• The Flash of the SAM7SE32 is organized in 256 pages of 128 bytes (single plane). It reads
as 32,768 32-bit words.
• The Flash of the SAM7SE512/25 6 contains a 256-byte write buffer, accessible through a 32-
bit interface.
• The Flash of the SAM7SE32 contains a 128-byt e write buffer, accessible through a 32-bit
interface.
27
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
8.1.4 SAM-BA® BootThe SAM-BA Boo t is a defau lt Boot Program which pro vides an easy wa y to pr ogram in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device
Port.
• Communication via the DBGU supports a wide range of crystals from 3 to 20 MHz via
software auto-detection.
• Communication via the USB Device Port is limited to an 18.432 MHz crystal.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM an d is mapped in Flash at addre ss 0x0 when GPNVM bit 2 is set to
0.
8.2 External Memories
The external memories are accessed through the Exte rn a l Bus Int er fa ce.
Refer to the mem ory ma p in Figure 8-1 on page 22.
28 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
9. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power,
time, debug and reset.
The System Controller peripherals are all mapped to the highest 4 Kbytes of address space,
between addresses 0xFFFF F000 and 0xFFFF FFFF.
Figure 9-1 on page 29 shows the System Controller Block Diagram.
Figure 8-1 on p ag e 22 shows the mapping of the User Interface of the System Controller periph-
erals. Note that the Memo ry Controller configuration user interface is also mapped within this
address space.
29
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 9-1. System Controller Block Diagram
NRST
SLCK
Advanced
Interrupt
Controller
Real-Time
Timer
Periodic
Interval
Timer
Reset
Controller
PA0-PA31
periph_nreset
System Controller
Watchdog
Timer
wdt_fault
WDRPROC
PIO
Controller
POR
BOD
RCOSC
gpnvm[0]
cal
en
Power
Management
Controller
OSC
PLL
XIN
XOUT
PLLRC
MAINCK
PLLCK
pit_irq
MCK
proc_nreset
wdt_irq
periph_irq{2-3]periph_nreset
periph_clk[2..18]
PCK
MCK
pmc_irq
UDPCK
nirq
nfiq
rtt_irq
Embedded
Peripherals
periph_clk[2-3]
pck[0-3]
in
out
enable
ARM7TDMI
SLCK
SLCK
irq0-irq1
fiq
irq0-irq1
fiq
periph_irq[4..18]
periph_irq[2..18]
int
int
periph_nreset
periph_clk[4..18]
Embedded
Flash
flash_poe
jtag_nreset
flash_poe
gpnvm[0..2]
flash_wrdis
flash_wrdis
proc_nreset
periph_nreset
dbgu_txd
dbgu_rxd
pit_irq
rtt_irq
dbgu_irq
pmc_irq
rstc_irq
wdt_irq
rstc_irq
SLCK
gpnvm[1]
Boundary Scan
TAP Controller
jtag_nreset
debug
PCK
debug
idle
debug
Memory
Controller
MCK
proc_nreset
bod_rst_en
proc_nreset
power_on_reset
periph_nreset
idle
Debug
Unit
dbgu_irq
MCK
dbgu_rxd
periph_nreset force_ntrst
dbgu_txd
USB Device
Port
UDPCK
periph_nreset
periph_clk[11]
periph_irq[11]
usb_suspend
usb_suspend
Voltage
Regulator
standby
Voltage
Regulator
Mode
Controller
security_bit
cal
power_on_reset
power_on_reset
force_ntrst
cal
PB0-PB31
PC0-PC29
30 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
9.1 Reset Controller
• Based on one power-on reset cell and a double brownout detector
• Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog
Reset, Brownout Reset
• Controls the internal resets and the NRST pin output
• Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets
any requirement.
9.1.1 Brownout Detector and Power On Reset
The SAM7SE512/256/32 embeds one brownout detection circuit and a power-on reset cell. The
power-on reset is supplied with and monitors VDDCORE.
Both signals are provided to t he Flash to prevent any code corruptio n during power-u p or power-
down sequences or if brownouts occur on the VDDCORE power supply.
The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low
during power-up until VDDCORE go es over this voltage level. This signal goes to the reset con-
troller and allows a full re-initialization of the device.
The brownout detector monitors the VDDCORE an d VDDFLASH levels during operation by
comparing it to a fixed trigger level. It secures system operatio ns in the most difficult environ-
ments and preven ts code corruption in case of brownout on the VDDCORE or VDDFLASH.
When the brownout detector is enabled and VDDCORE decreases to a value below the trigger
level (Vbot18-, de fined as Vbot18 - hyst/2), the brownou t output is immediately acti vated.
When VDDCORE increases above the trigger level (Vbot18+, defined as Vbot18 + hyst/2), the
reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays
below the thresh old voltage for longer than about 1µs.
The VDDCORE threshold voltage has a hysteresis of about 50 mV, to ensure spik e free brown-
out detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of
± 2% and is factory calibrate d .
When the brownout detector is enabled and VDDFLASH decreases to a value below the trigger
level (Vbot33-, de fined as Vbot33 - hyst/2), the brownou t output is immediately acti vated.
When VDDFLASH increases above the trigger level (Vbot33+, defined as Vbot33 + hyst/2), the
reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays
below the thresh old voltage for longer than about 1µs.
The VDDFLASH threshold voltage h as a hyst er esis of a bou t 50 mV, t o ensur e spike free br own-
out detection. The typical value of the brownout detector threshold is 2.80V with an accuracy of
± 3.5% and is factory calibra te d .
The brownout detector is low-power, as it consumes less than 20 µA static current. However, it
can be deactivated to save its static current. In this case, it consum es less th an 1µA. T he deac-
tivation is configured through the GPNVM bit 0 of the Flash.
9.2 Clock Generator
The Clock Generator embe ds one low-power RC Oscillator, one Main Oscillator and o ne PLL
with the following characteristics:
• RC Oscillator ranges between 22 KHz and 42 KHz
31
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• Main Oscillator frequency ranges between 3 and 20 MHz
• Main Oscillator can be bypassed
• PLL output ranges between 80 and 220 MHz
It provides SLCK, MAI NCK an d PL LCK .
Figure 9-2. Clock Generator Block Diagram
9.3 Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide:
• the Processor Clock PCK
• the Master Clock MCK
• the USB Clock UDPCK
• all the peripheral clocks, independently controllable
• three programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre-
quency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing
reduced power consumption while waiting for an interrupt.
Power
Management
Controller
XIN
XOUT
PLLRC
Slow Clock
SLCK
Main Clock
MAINCK
PLL Clock
PLLCK
Control
Status
Embedded
RC
Oscillator
Main
Oscillator
PLL and
Divider
Clock Generator
32 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 9-3. Power Management Controller Block Diagram
9.4 Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Individually maskable and v ectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.)
– Other sources control the peripheral interrupts or ext ernal interrupts
– Programmable edge-triggered or level-sensitive internal sources
– Programmable positive/negative edge-triggered or high/low level-sensitive external
sources
• 8-level Priority Controller
– Drives the normal interrupt nIRQ of the processor
– Handles priority of the interrupt sources
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes interrupt service routine branch and execution
– One 32-bit vector register per interrupt source
– Interrupt vector register reads the co rresponding current interrupt vector
•Protect Mode
– Easy debugging by preventing automatic operations
•Fast Forcing
– Per m its re dir ecting any interru pt so ur ce on the fast interru pt
• General Interrupt Mask
– Provides processor synchronization on events without triggering an interrupt
MCK
periph_clk[2..14]
int
UDPCK
SLCK
MAINCK
PLLCK Prescaler
/1,/2,/4,...,/64
PCK
Processor
Clock
Controller
Idle Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
USB Clock Controller
ON/OFF
SLCK
MAINCK
PLLCK Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
PLLCK Divider
/1,/2,/4
pck[0..2]
usb_suspend
33
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
9.5 Debug Unit • Comprises:
– One two-pin UART
– One Interface for the Debug Communication Channel (DCC) support
– One set of Chip ID Regist er s
– One Interface providing ICE Access Prevention
•Two-pin UART
– USART-compatible User Interface
– Programmable Baud Rate Generator
– Par ity, Framing and Overrun Error
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
• Debug Communication Channel Support
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
• Chip ID Register s
– Identification of the de vice revision, sizes of the embed ded memories, set of
peripherals
– Chip ID is 0x272A 0A40 (VERSION 0) for SAM7SE512
– Chip ID is 0x272A 0940 (VERSION 0) for SAM7SE256
– Chip ID is 0x2728 0340 (VERSION 0) for SAM7SE32
9.6 Periodic Interval Timer
• 20-bit programmable counter plus 12-bit interval counter
9.7 Watchdog Timer
• 12-bit key-protected Programmable Counter running on prescaled SLCK
• Provides reset or interrupt signals to the system
• Counter may be stopped while the processor is in debug state or in idle mode
9.8 Real-time Timer• 32-bit free-running counter with alarm running on prescaled SLCK
• Programmable 16-bit prescaler for SLCK accuracy compensation
9.9 PIO Controllers• Three PIO Controllers. PIO A and B each control 32 I/O lines and PIO C controls 24 I/ O lines .
• Fully programmable through set/clear registers
• Multiplexing of two perip he ral funct i on s pe r I/O line
• For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)
– Input change interrupt
– Half a clock period glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull-up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
34 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• Synchronous output, pr ovides Set and Clear of several I/O lines in a single write
9.10 Voltage Regulator Controller
The purpose of this controller is to select the Power Mode of the Voltage Regulator between
Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).
35
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
10. Peripherals
10.1 User InterfaceThe User Peripherals are mapped in the 256 MBytes of the address space between
0xF000 0000 and 0xFFFF EFFF. Each perip heral is allocated 16 Kbytes of address space.
A complete memory map is presented in Figure 8-1 on page 22.
10.2 Peripheral Identifiers
The SAM7SE512/256/ 32 embed s a wide rang e of per ipherals. Table 10-1 defines the Peripheral
Identifiers of the SAM7SE512/256/32. Unique peripheral identifiers are defined for both the
Advanced Interrupt Controller and the Power Management Contr oller.
Note: 1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The Sys-
tem Controller is continuously clocked. The ADC clock is automatically started for the first
conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.
Table 10-1. Peripheral Identifiers
Peripheral
ID Peripheral
Mnemonic Peripheral
Name External
Interrupt
0 AIC Advanced Interrupt Controller FIQ
1 SYSC(1)
2 PIOA Parallel I/O Controller A
3 PIOB Parallel I/O Controller B
4 PIOC Parallel I/O Controller C
5 SPI Serial Peripheral Interface 0
6 US0 USART 0
7 US1 USART 1
8 SSC Synchronous Serial Controller
9 TWI Two-wire Interface
10 PWMC PWM Controller
11 UDP USB Device Port
12 TC0 Timer/Counter 0
13 TC1 Timer/Counter 1
14 TC2 Timer/Counter 2
15 ADC(1) Analog-to Digital Converter
16-28 reserved
29 AIC Advanced Interrupt Controller IRQ0
30 AIC Advanced Interrupt Controller IRQ1
36 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
10.3 Peripheral Multiplexing on PIO Lines
The SAM7SE512/256/32 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex
the I/O lines of the peripheral set.
PIO Controller A and B control 32 lines; PIO Controller C controls 24 lines. Each line can be
assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with
the analog inputs of the ADC Controller.
Table 10- 2 on pa ge 37 define s how th e I/O lines of th e per ipher als A and B or the analog inp uts
are multiplexed on the PIO Controller A, B and C. The two columns “Function” and “Comments”
have been inserted for the user’s own comments; they may be used to track how pins are
defined in an applica tio n.
Note that some peripheral functions that are output only may be duplicated in the table.
At reset, all I/O lines are automatically configured as input with the programmable pull-up
enabled, so that the device is maintained in a static state as soon as a reset is detected.
37
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
10.4 PIO Controller A Multiplexing
Table 10-2. Multiplexing on PIO Controller A
PIO Controller A A pplication Usage
I/O Line P eripheral A Peripheral B Comments Function Comments
PA0 PWM0 A0/NBS0 High-Drive
PA1 PWM1 A1/NBS2 High-Drive
PA2 PWM2 A2 High-Drive
PA3 TWD A3 High-Drive
PA4 TWCK A4
PA5 RXD0 A5
PA6 TXD0 A6
PA7 RTS0 A7
PA8 CTS0 A8
PA9 DRXD A9
PA10 DTXD A10
PA11 NPCS0 A11
PA12 MISO A12
PA13 MOSI A13
PA14 SPCK A14
PA15 TF A15
PA16 TK A16/BA0
PA17 TD A17/BA1 AD0
PA18 RD NBS3/CFIOW AD1
PA19 RK NCS4/CFCS0 AD2
PA20 RF NCS2/CFCS1 AD3
PA21 RXD1 NCS6/CFCE2
PA22 TXD1 NCS5/CFCE1
PA23 SCK1 NWR1/NBS1/CFIOR
PA24 RTS1 SDA10
PA25 CTS1 SDCKE
PA26 DCD1 NCS1/SDCS
PA27 DTR1 SDWE
PA28 DSR1 CAS
PA29 RI1 RAS
PA30 IRQ1 D30
PA31 NPCS1 D31
38 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
10.5 PIO Controller B Multiplexing
Table 10-3. Multiplexing on PIO Controller B
PIO Controller B Application Usage
I/O Line Peripheral A Peripheral B Comments Function Comments
PB0 TIOA0 A0/NBS0
PB1 TIOB0 A1/NBS2
PB2 SCK0 A2
PB3 NPCS3 A3
PB4 TCLK0 A4
PB5 NPCS3 A5
PB6 PCK0 A6
PB7 PWM3 A7
PB8 ADTRG A8
PB9 NPCS1 A9
PB10 NPCS2 A10
PB11 PWM0 A11
PB12 PWM1 A12
PB13 PWM2 A13
PB14 PWM3 A14
PB15 TIOA1 A15
PB16 TIOB1 A16/BA0
PB17 PCK1 A17/BA1
PB18 PCK2 D16
PB19 FIQ D17
PB20 IRQ0 D18
PB21 PCK1 D19
PB22 NPCS3 D20
PB23 PWM0 D21
PB24 PWM1 D22
PB25 PWM2 D23
PB26 TIOA2 D24
PB27 TIOB2 D25
PB28 TCLK1 D26
PB29 TCLK2 D27
PB30 NPCS2 D28
PB31 PCK2 D29
39
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
10.6 PIO Controller C Multiplexing
10.7 Serial Peripheral Interface
• Supports communication with external serial devices
– Four chip selects with external decoder allow communication with up t o 15
peripherals
– Serial memories, such as DataFlash ® and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
Multiplexing on PIO Controller C
PIO Controller C Application Usage
I/O Line Peripheral A Peripheral B Comments Function Comments
PC0 D0
PC1 D1
PC2 D2
PC3 D3
PC4 D4
PC5 D5
PC6 D6
PC7 D7
PC8 D8 RTS1
PC9 D9 DTR1
PC10 D10 PCK0
PC11 D11 PCK1
PC12 D12 PCK2
PC13 D13
PC14 D14 NPCS1
PC15 D15 NCS3/NANDCS
PC16 A18 NWAIT
PC17 A19 NANDOE
PC18 A20 NANDWE
PC19 A21/NANDALE
PC20 A22/REG/NANDCLE NCS7
PC21 NWR0/NWE/CFWE
PC22 NRD/CFOE
PC23 CFRNW NCS0
40 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays per chip select, between consecutive transfers and
between clock and data
– Programmable delay between consecutive transfers
– Selecta ble mode fault detection
– Maximum frequency at up to Master Clock
10.8 Two Wire Interface
• Master, Multi-Master and Slave Mode Operation
• Compatibility with standard two-wire serial memories
• One, two or three bytes for slave address
• Sequential read/write operations
• Bit Rate: Up to 400 Kbit/s
• General Call Supported in Slave Mode
10.9 USART • Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode
– 1 or 2 stop bits in Synchronous Mode
– Parity generati on and error detection
– Framing error detection, overrun error detection
– MSB or LSB first
– Optional br ea k ge ne ration an d de te ctio n
– By 8 or by 16 over-sampling receiver frequency
– Hardware handshaking RTS - CTS
– Modem Signals Management DTR-DSR-DCD-RI on USART1
– Receiver time-out and transmitter timeguard
– Multi-drop Mode with address generation and detection
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and ite ration limit
•IrDA
® modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
10.10 Serial Synchronous Controller
• Provides serial synchronous communication links used in audio and tele com applications
• Contains an independent receiver and transm itter and a common clock divider
41
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• Offers a configurable frame sync and data length
• Receiver and transmitt er can be programmed to start automatically or on det ection of
different ev ent on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a fram e synchronization
signal
10.11 Timer Counter • Three 16-bit Timer Counter Channels
– Two output compare or one input capture per channel
• Wide range of functions including:
– Frequency measurement
– Event counting
– Interval measurement
– Pulse generation
– Delay timing
– Pulse Width Modulation
– Up/down capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs, as defined in Table 10-4
– Two multi-purpose input/output signals
– Two global registers that act on all three TC channels
10.12 PWM Controller• Four channels, one 16-bit coun te r pe r cha n ne l
• Common clock generator, providing thirteen different clocks
– One Modulo n counter pro viding eleven clocks
– Two independent linear dividers working on modulo n coun ter outputs
• Independent channel programming
– Independent enable/disable commands
– Independent clock selection
– Independent period and duty cycle, with double buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
Table 10-4. Timer Counter Clocks Assignment
TC Clock input Clock
TIMER_CLOCK1 MCK/2
TIMER_CLOCK2 MCK/8
TIMER_CLOCK3 MCK/32
TIMER_CLOCK4 MCK/128
TIMER_CLOCK5 MCK/1024
42 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
10.13 USB Device Port
• USB V2.0 full-speed compliant ,12 Mbits per second.
• Embedded USB V2.0 full-speed transceiver
• Embedded 2688-byte dual-port RAM for endpoints
• Eight endpoints
– Endpoint 0: 64bytes
– Endpoint 1 and 2: 64 bytes p ing-pong
– Endpoint 3: 64 bytes
– Endpoint 4 and 5: 51 2 bytes ping-pong
– Endpoint 6 and 7: 64 bytes p ing-pong
– Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints
• Suspend/resume logic
• Integrated Pull-up on DDP
10.14 Analog-to-Digital Converter
• 8-channel ADC
• 10-bit 384 Ksamples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register
ADC
• ±2 LSB Integral Non Linearity, ±1 LSB Differen tial Non Linearity
• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger sources
– Hardware or software trigger
– External tr igger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
• Sleep Mode and conversion sequencer
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
• Each analog input shared with digital signals
43
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
11. A RM7TDMI Processor Overview
11.1 Overview The ARM7TDMI core executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing
the user to trade off between high performance and high code density.The ARM7TDMI proces-
sor implements Von Neum an architecture, using a three-stage pipeline consisting of Fetch,
Decode, and Execute stages.
The main features of the ARM7tDMI processor are:
• ARM7TDMI Based on ARMv4T Architecture
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
• Three-Stage Pipeline Architecture
– Instruction Fetch (F)
– Instruction Deco de (D)
– Execute (E)
44 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
11.2 ARM7TDMI Processor
For further details on ARM7TDMI, refer to the following ARM documents:
ARM Architecture Reference Manual (DDI 0100E)
ARM7TDMI Technical Reference Manual (DDI 0210B)
11.2.1 Instruction Type
Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
11.2.2 Data Type ARM7TDMI supports byte (8-b it), half -word (16- bit) and word (32-bit ) data t ypes. Wor ds must be
aligned to four-byte boundaries and half words to two-byte boundaries.
Unaligned data access behavior depends on which instruction is used wher e.
11.2.3 ARM7TDMI Operating Mode
The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes:
User: The normal ARM program execution state
FIQ: Designed to support high-speed data transfer or channel process
IRQ: Used for general-purpose interrupt handling
Supervisor: Protected mode for the operating system
Abort mode: Implements virtual memory and/or memory protection
System: A privileged user mode for the operating system
Undefined: Supports software emulation of hardware coprocessors
Mode changes may be made under software control, or may be brought about by external inter-
rupts or exception processing. Most application programs execute in User mode. The non-user
modes, or privileged modes, are entered in order to service interrupts or exceptions, or to
access protected resources.
11.2.4 ARM7TDMI Regist ers
The ARM7TDMI processor has a total of 37registers:
• 31 general-purpose 32-bit registers
• 6 status registers
These registers are not accessible at the same time. The processor st ate and operating mod e
determine which registers are available to the programmer.
At any one time 16 registers are visible to the user. The remainder are synonyms used to speed
up exception processing.
Register 15 is the Program Counter (PC) and can be used in all instructions to reference data
relative to the current instruction.
R14 holds the return address after a subroutine call.
R13 is used (by software convention) as a stack pointer.
45
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Registers R0 to R7 are un banked regist ers. This means that each of them re fers to the same 32-
bit physical register in all processor modes. They are general-purpose registers, with no special
uses managed by the architecture, an d can be used wherever an instruction allows a genera l-
purpose register to be specified.
Registers R8 to R14 are banked regist ers. T his means t hat each of them dep ends on the curre nt
mode of the processor.
11.2.4.1 Modes and Exception Handling
All exceptions have banked registers for R14 and R13.
After an exception, R14 holds the return address for exception processing. This address is used
to return after the exception is processed, as well as to address the instruction that caused the
exception.
R13 is banked across exception modes to provide each exception han dler with a private stack
pointer.
The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin with-
out having to save these registers.
Table 11-1. ARM7TDMI ARM Modes and Registers Layout
User and
System Mode Supervisor
Mode Abort Mode Undefined
Mode Interrupt
Mode Fast Interrupt
Mode
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
R8 R8 R8 R8 R8 R8_FIQ
R9 R9 R9 R9 R9 R9_FIQ
R10 R10 R10 R10 R10 R10_FIQ
R11 R11 R11 R11 R11 R11_FIQ
R12 R12 R12 R12 R12 R12_FIQ
R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ
R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ
PC PC PC PC PC PC
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ
Mode-specific banked registers
46 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
A seventh processing mode, System Mode, does not have a ny banked registers. It uses the
User Mode registers. System Mo de runs tasks that require a privileged processor mode an d
allows them to invoke all classes of exceptions.
11.2.4.2 Status Registers
All other processor states are held in status registers. The current operating processor status is
in the Current Program Status Register (CPSR). The CPSR holds:
• four ALU flags (Negative, Zero, Carry, and Overflow)
• two interrupt disable bits (one for each type of interrupt)
• one bit to indicate ARM or Thumb execution
• five bits to encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) that holds the
CPSR of the task immediately preceding the exception.
11.2.4.3 Exception Types
The ARM7TDMI supports five types of exception an d a privileged processing mode for each type.
The types of exceptions are:
• fast interrupt (FIQ)
• normal interrupt (IRQ)
• memory aborts (used to implement memory protection or virtual memory)
• attempted execution of an undefined instruction
• software interrupts (SWIs)
Exceptions are generated by internal and external sources.
More than one exception can occur in the same time.
When an exception occurs, the banked version of R14 and the SPSR for the exception mode
are used to save state.
To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to
the PC. This can be done in t wo ways:
• by using a data-processing instruction with the S-bit set, and the PC as the destination
• by using the Load Multiple with Restore CPSR instruction (LDM)
11.2.5 ARM Instruction Set Overview
The ARM instruction set is divided into:
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception- g en eratin g ins tructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bit[31:28]).
47
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Table 11-2 gives the ARM instruction mnemonic list.
11.2.6 Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store Multiple instructions
• Exception- g en erating instructio n
In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same
physical registers as R0 to R7 when executing ARM instructions. Som e Thumb instructions also
Table 11-2. ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
MOV Move CDP Coprocessor Data Processing
ADD Add MVN Move Not
SUB Subtract ADC Add with Carry
RSB Reverse Subtract SBC Subtract with Carry
CMP Compare RSC Reverse Subtract with Carry
TST Test CMN Compare Negated
AND Logical AND TEQ Test Equivalence
EOR Logical Exclusive OR BIC Bit Clear
MUL Multiply ORR Logical (inclusive) OR
SMULL Sign Long Multiply MLA Multiply Accumulate
SMLAL Signed Long Multiply Accumulate UMULL Unsigned Long Multiply
MSR Move to Status Register UMLAL Unsigned Long Multiply Accumulate
B Branch MRS Move From Status Register
BX Branch and Exchange BL Branch and Link
LDR Load Word SWI Software Interrupt
LDRSH Load Signed Halfword STR Store Word
LDRSB Load Signed Byte STRH Store Half Word
LDRH Load Half Word STRB Store Byte
LDRB Load Byte STRBT Store Register Byte with Translation
LDRBT Load Register Byte with Translation STRT Store Register with Translation
LDRT Load Register with Translation STM Store Multiple
LDM Load Multiple SWPB Swap Byte
SWP Swap Word MRC Move From Coprocessor
MCR Move To Coprocessor STC Store From Coprocessor
LDC Load To Coprocessor
48 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
access to the Program Counter ( ARM Regist er 15), th e Link Re gister (ARM Register 14) and t he
Stack Pointer ( ARM Reg ister 13 ). Furt her inst ructions allow limited access to the ARM regis ters
8 to 15.
Table 11-3 gives the Thumb instruction mnemonic list.
Table 11-3. Thumb Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
MOV Move MVN Move Not
ADD Add ADC Add with Carr y
SUB Subtract SBC Subtract with Carry
CMP Compare CMN Compare Negated
TST Test NEG Negate
AND Logical AND BIC Bit Clear
EOR Logical Exclusive OR ORR Logical (inclusive) OR
LSL Logical Shift Left LSR Logical Shift Right
ASR Arithmetic Shift Right ROR Rotate Right
MUL Multiply
B Branch BL Branch and Link
BX Branch and Exchange SWI Software Interrupt
LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word
LDRB Load Byte STRB Store Byte
LDRSH Load Signed Halfword LDRSB Load Signed Byte
LDMIA Load Multiple STMIA Store Multiple
PUSH Push Register to stack POP Pop Register from stack
49
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
12. D ebug and Test Features
12.1 Overview The SAM7SE Series Microcontrollers feature a number of complementary debug and test capa-
bilities. A common JTAG/ICE (Embedded ICE) port is used for standard debugging functions,
such as downloading code and single-stepping through programs. The Debug Unit provides a
two-pin UART that can be used to upload an applica tion into internal SRAM. It manages th e
interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the
Debug Communication Channel.
A set of dedicated debug and test input/output pins gives direct access to these capabilities from
a PC-based test environment.
12.2 Block Diagram
Figure 12-1. Debug and Test Block Diagram
ICE
PDC DBGU
PIO
DRXD
DTXD
TST
TMS
TCK
TDI
JTAGSEL
TDO
Boundary
TAP
ICE/JTAG
TAP
ARM7TDMI
Reset
and
Test
POR
50 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
12.3 Application Examples
12.3.1 Debug Environment
Figure 12-2 shows a complete debug environment example. The ICE/JTAG interface is used for
standard debugging functions, such as downloading code and single-stepping through the
program.
Figure 12-2. Application Debug Environment Example
ICE/JTAG
Interface
Host Debugger
ICE/JTAG
Connector
RS232
Connector
AT91SAMSExx
AT91SAM7Sxx-based Application Board
Terminal
51
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
12.3.2 Test Environment
Figure 12-3 sh ows a test environ ment exampl e. Test vecto rs are sent and int erpreted by t he tes-
ter. In this example, the “board in test” is designed using a number of JTAG-compliant devices.
These devices can be connected to form a single scan chain.
Figure 12-3. Application Test Environment Example
12.4 Debug and Test Pin Description
Chip 2
Chip n
Chip 1
AT91SAM7SExx
AT91SAM7SExx-based Application Board In Test
ICE/JTAG
Connector
Tester
Test Adaptor
JTAG
Interface
Table 12-1. Debug and Test Pin List
Pin Name Function Type Active Level
Reset/Test
NRST Microcontroller Reset Input/Output Low
TST Test Mode Select Input High
ICE and JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Sele ct Input
JTAGSEL JTAG Selection Input
Debug Unit
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
52 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
12.5 Functional Description
12.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure
that this pin is tied at low level to ensure normal operating conditions. Other values associated
with this pin are reserved for manufacturing test.
12.5.2 EmbeddedICE™ (Embedded In-circuit Emulator)
The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port.The internal state of the
ARM7TDMI is examined through an ICE/JTAG port.
The ARM7TDMI processor contains hardware extensions for advance d debugging features:
• In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports
the contents of the ARM7TDMI registers. This data can be serially shifted out without
affecting the rest of the system.
• In monitor mo de, the JTAG interf ace is used to transfer data between the debugger and a
simple monitor program running on the ARM7TDMI processor.
There are three scan chains inside the ARM7TDMI processor that support testing, debugging,
and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port.
Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly
between ICE and JTAG o perations. A ch ip reset must be pe rformed af ter JTAG SEL is changed.
For further det ails on the Embedde d ICE, see the ARM7TDMI (Rev4) Techn ical Reference Ma n-
ual (DDI0210B).
12.5.3 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several
debug and trace purposes and offers an ideal means for in-situ programming solutions and
debug monitor communication. More over, the association with two peripheral data controller
channels permits packet handling of these tasks with processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals
that come from the ICE and that trace the activity of the Debug Communication Channel.The
Debug Unit allows blocka g e of acce ss to th e sys tem thr o ug h th e ICE inte r fac e.
A specific register, the Debu g Unit Chip ID Re gister, gives infor mation about the produ ct ve rsion
and its internal configuration.
For further details on the Debug Unit, see the Debug Unit section.
12.5.4 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boun dary Scan allows pin-le vel access independent of the d evice packaging
technology.
Table 12-2. AT91SAM7SExx Chip IDs
Chip Name Chip ID
AT91SAM7SE32 0x27280340
AT91SAM7SE256 0x272A0940
AT91SAM7SE512 0x272A0A40
53
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST
and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
12.5.4.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains 353 bits that correspond to active pins and associ-
ated control signals.
Each AT91SAM7SExx input/outp ut pin correspo nds to a 3-bit reg ister in the BSR. The OUTPUT
bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data
applied to the pad. The CONTROL bit selects the di rection of the pad.
For more information, please refer to BDSL files which are available for the SAM7SE Series.
54 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
12.5.5 ID Code Register
Access: Read-only
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
• Bit[0] Required by IEEE Std. 1149.1.
Set to 0x1.
31 30 29 28 27 26 25 24
VERSION PART NUMBER
23 22 21 20 19 18 17 16
PART NUMBER
15 14 13 12 11 10 9 8
PART NUMBER MANUFACTURER IDENTITY
76543210
MANUFACTURER IDENTITY 1
Chip Name Chip ID
AT91SAM7SE32 0x5B1D
AT91SAM7SE256 0x5B15
AT91SAM7SE512 0x5B14
Chip Name JTAG ID Code
AT91SAM7SE32 05B1_D03F
AT91SAM7SE256 05B1_503F
AT91SAM7SE512 05B1_403F
55
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
13. Reset Controller (RSTC)
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys-
tem without any external components. It reports which reset occurred last.
The Reset Controller also driv es independently or simultaneously th e external reset and the
peripheral and processor resets.
A brownout detect ion is also a vailable to pr even t the pr ocessor fr om falling in to an unp redict able
state.
13.1 Block Diagram
Figure 13-1. Reset Controller Block Diagram
NRST
Startup
Counter
proc_nreset
wd_fault
periph_nreset
SLCK
Reset
State
Manager
Reset Controller
brown_out
bod_rst_en
rstc_irq
NRST
Manager exter_nreset
nrst_out
Main Supply
POR
WDRPROC
user_reset
Brownout
Manager bod_reset
56 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
13.2 Functional Description
13.2.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter
and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:
• proc_nreset: Processor reset line. It also resets the Watchdog Timer.
• periph_nreset: Affects the whole set of embedded peripherals.
• nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on soft-
ware action. The Reset State Manager controls the generation of reset signals and provides a
signal to the NRST Manager when an asser tion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling
external device resets.
The startup counter waits for the complete crystal oscillator startup. The wait delay is given by
the crystal oscillator startup time maximum value that can be found in the section Crystal Oscil-
lator Characteristics in the Electrical Characteristics section of the product documentation.
13.2.2 NRS T Ma nage rThe NRST Manager samples the NRST input pin and drives this pin low when required by the
Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager.
Figure 13-2. NRST Manager
13.2.2.1 NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low,
a User Reset is reported to the Reset State Manager.
However, the NRST Manager can be programme d to not trigger a reset when an assertion of
NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Rese t trigger.
The level of the pin NRS T can be read at any ti me in the bit NRSTL (NRS T lev el) in RSTC_SR.
As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only
when RSTC_SR is read.
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset
57
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The Reset Controller can also be programmed to generate an interrupt instead of generating a
reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.
13.2.2.2 NRST External Reset Contr o l
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this
occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the
field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts
2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs
and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
This featur e al lows th e Reset Con tr oller t o sh ape the NRST p in le ve l, and t hus t o gua ra nt ee that
the NRST line is drive n low for a time compliant wit h poten tial e xterna l device s conne cte d on the
system reset.
13.2.3 Brownout Manager
Brownout detection prevents the processo r from falling into an u npredictable state if the power
supply drops below a cer tain level. When VDDCORE drops below the brownout threshold, the
brownout manager requests a brownout reset by asserting the bod_reset signal.
The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.;
by locking the corresponding general-purpose NVM bit in the Flash. When the brownout reset is
disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS
of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read.
The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR.
At factory, the brownout reset is disabled.
Figure 13-3. Brownout Manager
13.2.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RST T YP is perfor m ed when the processor reset is released.
rstc_irq
brown_out
bod_reset
bod_rst_en
BODIEN
RSTC_MR
BODSTS
RSTC_SR
Other
interrupt
sources
58 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
13.2.4.1 Power-u p Res et
When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up
counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow
Clock oscillator is stable before starting up the device.
The startup time, as shown in F igure 13-4, is hardcoded to comply with the Slow Clock Oscillator
startup time. After the startup time, the reset signals are released and the field RSTTYP in
RSTC_SR reports a Power-up Reset.
When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted
immediately.
Figure 13-4. Power-up Reset
13.2.4.2 User Reset The User Reset is entered wh en a low level is de te ct ed on t he NRST pi n and t he b it URSTEN in
RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behav-
ior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset
and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-
cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register
(RSTC_SR) is loaded with the value 0x4, indicat ing a User Reset.
The NRST Manager guarantees that the NRST line is asserted for
EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-
ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low
externally, the inter nal reset lines remain asserted until NRST actually rises.
SLCK
periph_nreset
proc_nreset
Main Supply
POR output
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
Startup Time
MCK
Processor Startup
= 3 cycles
Any
Freq.
59
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 13-5. User Reset State
13.2.4.3 Brownout Reset
When the brown_out/bod_rese t signal is asserted, the Reset State Manager immediately enters
the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are
asserted.
The Brow nout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset
after a two-cycle resynchronization. An external reset is also triggered.
When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value
0x5, thus indicating that the last reset is a Brownout Reset.
SLCK
periph_nreset
proc_nreset
NRST
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
MCK
Processor Startup
= 3 cycles
Any
Freq.
Resynch.
2 cycles
RSTTYP Any XXX
Resynch.
2 cycles
0x4 = User Reset
60 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 13-6. Brownout Reset State
13.2.4.4 Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These
commands are perform ed by writing the Control Re gister (RSTC_CR) with the following b its at
1:
• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog ti mer.
• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory
system and, in particular, the Remap Command. The Peripheral Reset is generally used for
debug purposes. Except for Debug purposes, the PERRST must always be used in
conjunction with a PROCRST (PERRST and PROCRST bot h set at 1 simultaneously).
• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field
ERSTL in the Mode Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these com-
mands can be performed inde pendently or simultaneously. The software reset lasts 3 Slow
Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is
detected on the Mast er Clock (MCK). They are releas ed when the softwa re reset is lef t, i.e.; syn-
chronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field
ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.
If and only if th e PROCRST bit is se t, th e Re set Cont roller r epor ts th e soft ware stat us in the fi eld
RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in
RSTTYP.
SLCK
periph_nreset
proc_nreset
brown_out
or bod_reset
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP Any XXX 0x5 = Brownout Reset
Resynch.
2 cycles
61
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in
Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is
left. No other software reset can be pe rf ormed while the SRCMP bit is set, and wr iting an y value
in RSTC_CR has no effect.
Figure 13-7. Software Reset
13.2.4.5 Watchdog Res et
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock
cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in
WDT_MR:
• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST
line is also asserted, depending on the programming of the field ERSTL. However, the
resulting low level on NRST does not result in a User Reset state.
• If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a
processor reset if WDRSTEN is set, the Watchd og Timer is always reset after a Watchd og
Reset, and the Watch do g is enab le d by defa u lt and with a per iod set to a ma xim u m .
When the WDRSTEN in WDT_ MR bit is reset, the watchdog fault has no impact on the reset
controller.
SLCK
periph_nreset
if PERRST=1
proc_nreset
if PROCRST=1
Write RSTC_CR
NRST
(nrst_out)
if EXTRST=1 EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP Any XXX 0x3 = Software Reset
Resynch.
1 cycle
SRCMP in RSTC_SR
62 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 13-8. Watchdog Reset
13.2.5 Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources,
given in descending order:
• Power-up Reset
•Brownout Reset
• Watchdog Reset
• Software Reset
• User Reset
Particular cases are listed below:
• When in User Reset:
– A watchdog event is impossible because the Watchdog Timer is being reset by the
proc_nreset signal.
– A software reset is impossible, since the processor reset is being activated.
• When in Software Reset:
– A watchdog event has priority over the current state.
– The NRST has no effect.
• When in Watchdog Reset:
– The processor reset is active and so a Software Reset cannot be programmed.
– A User Reset cannot be entered.
13.2.6 Reset Controller Status Regist er
The Reset Controller status register (RSTC_SR) provides several status fields:
Only if
WDRPROC = 0
SLCK
periph_nreset
proc_nreset
wd_fault
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP Any XXX 0x2 = Watchdog Reset
63
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no
further software reset should be performed until the en d of the current one. This bit is
automatically cleared at the end of the current software reset.
• NRSTL bit: The NRSTL bit of the Status Registe r giv es the le vel of the NRST pin sampled on
each MCK rising edge.
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR
register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure
13-9). If th e User Reset is disabled (URST EN = 0) and if the interruption is enabled by the
URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Read ing the
RSTC_SR status register resets the URSTS bit and clears the interr upt.
• BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled
(bod_rst_e n = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables
the interrupt. Reading t he RSTC_SR register rese ts the BODSTS bit and cle ars the interrupt.
Figure 13-9. Reset Controller Statu s an d In te rru p t
13.3 Reset Controller (RSTC) User Interface
MCK
NRST
NRSTL
2 cycle
resynchronization 2 cycle
resynchronization
URSTS
read
RSTC_SR
Peripheral Access
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)
Table 13-1. Reset Controller (RSTC) Register Mapping
Offset Register Name Access Reset Value
0x00 Control Register RSTC_CR Write-only -
0x04 Status Register RSTC_SR Read-only 0x0000_0000
0x08 Mode Register RSTC_MR Read/Write 0x0000_0000
64 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
13.3.1 Reset Controller Control Register
Name: RSTC_CR
Access: Write-only
• PROCRST: Processor Reset
0 = No effect.
1 = If KEY is correct, resets the processor.
• PERRST: Peripheral Reset
0 = No effect.
1 = If KEY is correct, resets the peripherals.
• EXTRST: External Reset
0 = No effect.
1 = If KEY is correct, asserts the NRST pin.
•KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––– –
76543210
––––EXTRSTPERRST–PROCRST
65
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
13.3.2 Reset Controller Status Regist er
Name: RSTC_SR
Access: Read-only
• URSTS: User Reset Status
0 = No high-to-low edge on NRST happened since the last re ad of RSTC_SR.
1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• BODSTS: Brownout Detection Status
0 = No brownout high-to-low transition happened since the last read of RSTC_SR.
1 = A brownout high-to-low transition has be en detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
• NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress
0 = No software comman d is being performed by the r eset controller. The reset cont roller is ready for a soft ware command.
1 = A software reset command is being performed by the reset controller. The reset con troller is busy.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––SRCMPNRSTL
15 14 13 12 11 10 9 8
––––– RSTTYP
76543210
––––––BODSTSURSTS
RSTTYP Reset Type Comments
0 0 0 Power-up Reset VDDCORE rising
0 1 0 Watchdog Reset Watchdog fault occurred
0 1 1 Software Reset Processor reset required by the software
1 0 0 User Reset NRST pin detected low
1 0 1 Brownout Reset Brownout reset occurred
66 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
13.3.3 Reset Controller Mode Register
Name: RSTC_MR
Access: Read/Write
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• BODIEN: Brownout Detection Interrupt Enable
0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq.
• ERSTL: External Reset Length
This field de fines the exter nal reset le ngth. The external reset is asserted during a ti me of 2(ERSTL+1) Slow Clock cycles. This
allows assertion duration to be programmed between 60 µs and 2 seconds.
•KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
–––––––BODIEN
15 14 13 12 11 10 9 8
–––– ERSTL
76543210
– – URSTIEN – – – URSTEN
67
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
14. R eal-time Timer (RTT)
14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen-
erates a periodic inte rrupt or/and triggers an alarm on a programmed value.
14.2 Block Diagram
Figure 14-1. Real-time Timer
14.3 Functional Description
The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by
Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field
RTPRES of the Real-time Mode Register (RTT_MR).
Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz
signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corre-
sponding to more than 136 years, then roll over to 0.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best
accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but
may result in losing status events because the status register is cleared two Slow Clock cycles
after read. Thus if the RTT is co nfigured t o trigger an in terrupt, the interru pt occurs du ring 2 Slow
Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the
interrupt must be disabled in the interrupt handler and re-enabled when the status register is
clear.
SLCK
RTPRES
RTTINC
ALMS
16-bit
Divider
32-bit
Counter
ALMV =
CRTV
RTT_MR
RTT_VR
RTT_AR
RTT_SR
RTTINCIEN
RTT_MR
0
10
ALMIEN
rtt_int
RTT_MR
set
set
RTT_SR
read
RTT_SR
reset
reset
RTT_MR
reload
rtt_alarm
RTTRST
RTT_MR
RTTRST
68 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-tim e
Value Register). As this value can be updated asynchronously from the Master Clock, it is advis-
able to read this register twice at the same value to improve accuracy of the returned value.
The current value of the counter is compared with the value written in the alarm register
RTT_AR (Real-time Alarm Register). If the coun ter value matches the alarm , the bit ALMS in
RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FF FF,
after a reset.
The bit RTTINC in RTT_ SR is set each time the Real-time Time r counter is in cremented. This bit
can be used t o s tart a periodic in te rrupt, the period being one second when the RTPRES is pro-
grammed with 0x8000 and Slow Clock equal to 32.768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the
new programmed value. This also resets the 32-bit counter.
Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):
1) The restart of the counter and the reset of the RTT_VR current value register is effectiv e only 2
slow clock cycles after the write of the RTTRST bit in the RT T_MR register.
2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the
RTT_SR (Status Register).
Figure 14-2. RTT Counting
Prescaler
ALMVALMV-10 ALMV+1
0
RTPRES - 1
RTT
APB cycle
read RTT_SR
ALMS (RTT_SR)
APB Interface
MCK
RTTINC (RTT_SR)
ALMV+2 ALMV+3
...
APB cycle
69
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
14.4 Real-time Timer (R TT) User Interface
Table 14-1. Real-time Timer (RTT) Register Mapping
Offset Register Name Access Reset Value
0x00 Mode Register RTT_MR Read/Write 0x0000_8000
0x04 Alarm Register RT T_AR Read/Write 0xFFFF_FFFF
0x08 Value Register RTT_VR Read-only 0x0000_0000
0x0C Status Register RT T_SR Read-only 0x0000_0000
70 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
14.4.1 Real-time Timer Mode Register
Name: RTT_MR
Access: Read/Write
• RTPRES: Real-time Timer Prescaler Value
Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as fo llows:
RTPRES = 0: The Prescaler Period is equal to 216
RTPRES … 0: The Prescaler Period is equal to RTPRES.
• ALMIEN: Alarm Interrupt Enable
0 = The bit ALMS in RTT_SR has no effe ct on interrupt.
1 = The bit ALMS in RTT_SR asserts interrupt.
• RTTINCIEN: Real-time Timer Increment Interrupt Enable
0 = The bit RTTINC in RTT_SR has no effect on interrupt.
1 = The bit RTTINC in RTT_SR asserts interrupt.
• RTTRST: Real-time Time r Re st art
1 = Reloads and restarts the clock divider with the new programmed value. This al so resets the 32-bit counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––RTTRSTRTTINCIENALMIEN
15 14 13 12 11 10 9 8
RTPRES
76543210
RTPRES
71
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
14.4.2 Real-time Timer Alarm Register
Name: RTT_AR
Access: Read/Write
• ALMV: Alarm Value
Defines the alarm value (ALMV+1) compared with the Real-time Timer.
14.4.3 Real-time Timer Value Register
Name: RTT_VR
Access: Read-only
• CRTV: Current Real-time Value
Returns the current value of the Real-time Timer.
31 30 29 28 27 26 25 24
ALMV
23 22 21 20 19 18 17 16
ALMV
15 14 13 12 11 10 9 8
ALMV
76543210
ALMV
31 30 29 28 27 26 25 24
CRTV
23 22 21 20 19 18 17 16
CRTV
15 14 13 12 11 10 9 8
CRTV
76543210
CRTV
72 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
14.4.4 Real-time Timer Status Register
Name: RTT_SR
Access: Read-only
• ALMS: Real-time Ala rm Stat us
0 = The Real-time Alarm has not occurred since the last read of RTT_SR.
1 = The Real-time Alarm occurred since the last read of RTT_SR.
• RTTINC: Real-time Timer Increment
0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.
1 = The Real-time Timer has been incremented since the last read of the RTT_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––RTTINCALMS
73
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
15. Watchdog Timer (WDT)
15.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in
a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds
(slow clock at 3 2.768 kHz) . It can gener ate a ge nera l rese t or a p rocessor r eset on ly. In a dditio n,
it can be stopped while the processor is in debug mode or idle mode.
15.2 Block Diagram
Figure 15-1. Watchdog Timer Block Diagram
=0
10
set
reset
read WDT_SR
or
reset
wdt_fault
(to Reset Controller)
set
reset
WDFIEN
wdt_int
WDT_MR
SLCK
1/128
12-bit Down
Counter
Current
Value
WDD
WDT_MR
<= WDD
WDV
WDRSTT
WDT_MR
WDT_CR
reload
WDUNF
WDERR
reload
write WDT_MR
WDT_MR
WDRSTEN
74 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
15.3 Functional Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in
a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset.
The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in
the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock
divided by 128 to establish the maximum Watchdog p eriod to be 16 secon ds (with a typical Slow
Clock of 32.768 kHz).
After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of
the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup
Reset). This means that a default Watchd og is running at reset, i.e. , at power- up. The user must
either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must
reprogram it to meet the maximum Watchdog period the application requires.
The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset
resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode
parameters.
In normal operation, the user reloads the Watchdog at regular intervals before the timer under-
flow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The
Watchdog counter is the n immediately reloaded from WDT_MR and resta rted, and the Slow
Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result,
writing WDT_CR without the correct hard-coded key has no effect. If a n underflow does occur,
the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode
Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register
(WDT_SR).
To prevent a software deadlock tha t continuously triggers the Watchdog, the reload of the
Watchdog must occur while the Watchdog counter is within a window between 0 and WDD,
WDD is defined in the WatchDog Mode Register WDT_MR.
Any attempt to restart the Watchd og while the Watchdog counter is between WDV and WDD
results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the
WDT_SR and the “wdt_fault” signal to the Reset Controller is asserted.
Note that this feat ure can be disabled by prog ramming a WDD va lue gr eater t han or e qual to t he
WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole
range [0; WDV] and does not generate an error. This is the default configuration on reset (the
WDD and WDV values are equal).
The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an inter-
rupt, provided the bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset
controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset
controller programmer Datash eet. In that case, the processor and the Watchdog Timer are
reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared,
and the “wdt_fault” signal to the reset controller is deasserted.
Writing the WDT_MR reloads and restarts the down counter.
While the processor is in de bug stat e or in idle mode, the coun ter ma y be stopped depend ing on
the value program med for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.
75
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 15-2. Watchdog Behavior
0
WDV
WDD
WDT_CR = WDRSTT
Watchdog
Fault
Normal behavior
Watchdog Error Watchdog Underflow
FFF if WDRSTEN is 1
if WDRSTEN is 0
Forbidden
Window
Permitted
Window
76 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
15.4 Watchdog Timer (WDT) User Interface
15.4.1 Watchdog Timer Control Register
Name: WDT_CR
Access: Write-only
• WDRSTT: Watchdog Restart
0: No effect.
1: Restarts the Watchdog.
•KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
Table 15-1. Watchdog Timer (WDT) Register Mapping
Offset Register Name Access Reset Value
0x00 Control Register WDT_CR Write-only -
0x04 Mode Register WDT_MR Read/Write Once 0x3FFF_2FFF
0x08 Status Register WDT_SR Read-only 0x0000_0000
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––WDRSTT
77
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
15.4.2 Watchdog Timer Mode Register
Name: WDT_MR
Access: Read/Write Once
• WDV: Watchdog Counter Value
Defines the value loaded in the 12-bit Watchdog Counter.
• WDFIEN: Watchdog Fault Interrupt Enable
0: A Watchdog f ault (underflow or error) has no effect on interrupt.
1: A Watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable
0: A Watchdog f ault (underflow or error) has no effect on the resets.
1: A Watchdog fault (underflow or error) triggers a Watchdog reset.
• WDRPROC: Watchdog Reset Processor
0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.
1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.
• WDD: Watchdo g Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.
If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.
• WDDBGHLT: Watchdog Debug Halt
0: The Watchdog runs when the processor is in debug state.
1: The Watchdog stops when the processor is in debug state.
• WDIDLEHLT: Watchdog Idle Halt
0: The Watchdog runs when the system is in idle mode.
1: The Watchdog stops when the system is in idle state.
31 30 29 28 27 26 25 24
– – WDIDLEHLT WDDBGHLT WDD
23 22 21 20 19 18 17 16
WDD
15 14 13 12 11 10 9 8
WDDIS WDRPROC WDRSTEN WDFIEN WDV
76543210
WDV
78 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• WDDIS: Watchdog Disable
0: Enables the Watchdog Timer.
1: Disables the Watchdo g Timer.
15.4.3 Watchdog Timer Status Register
Name: WDT_SR
Access: Read-only
• WDUNF: Wa tchdog Underflow
0: No Watchdog underflow occurred since the last read of WDT_SR.
1: At least one Watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error
0: No Watchdog error occurred since the last read of WDT_SR.
1: At least one Watchdog error occurred since the last re ad of WDT_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––WDERRWDUNF
79
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
16. Periodic Interval Timer (PIT)
16.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is
designed to offer maximum accuracy and efficient management, even for systems with long
response time.
16.2 Block Diagram
Figure 16-1. Periodic Interval Timer
20-bit
Counter
MCK/16
PIV
PIT_MR
CPIV PIT_PIVR PICNT
12-bit
Adder
0
0
read PIT_PIVR
CPIV PICNT
PIT_PIIR
PITS
PIT_SR
set
reset
PITIEN
PIT_MR
pit_irq
1
0
10
MCK
Prescaler
= ?
80 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
16.3 Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built
around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at
Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the
field PIV of th e Mo de Re giste r (PIT _MR). Wh en th e count er CPIV reache s th is va lue, it r esets to
0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Regis-
ter (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in
PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register
(PIT_PIVR), the o verflow cou nter (PIC NT) is reset and the PITS is cleared, thus acknowledging
the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last
read of PIT_PIVR.
When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register
(PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For exam-
ple, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer
interrupt clears the interrupt by reading PIT_PIVR.
The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on
reset). The PITEN bit only becomes effe ctive when the CPIV value is 0. Figure 16-2 illustrates
the PIT counting. After the PIT Enable bit is re set (PITEN= 0), the CPIV goes on counting until
the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again.
The PIT is stopped when the core enters debug state.
81
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 16-2. Enabling/Disabling PIT with PITEN
MCK Prescaler
PIVPIV - 10
PITEN
10
0
15
CPIV 1
restarts MCK Prescaler
01
APB cycle
read PIT_PIVR
0
PICNT
PITS (PIT_SR)
MCK
APB Interface
APB cycle
82 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
16.4 Periodic Interval Timer (PIT) User Interface
Table 16-1. Periodic Interval Timer (PIT) Register Mapping
Offset Register Name Access Reset Value
0x00 Mode Register PIT_MR Read/Write 0x000F_FFFF
0x04 Status Register PIT_SR Read-only 0x0000_0000
0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000
0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000
83
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
16.4.1 Periodic Interval Timer Mode Register
Name: PIT_MR
Access: Read/Write
• PIV: Periodic Interval Value
Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to
(PIV + 1).
• PITEN: P eriod Interval Timer Enabled
0 = The Periodic Interval Timer is disabled when the PIV value is reached.
1 = The Periodic Interval Timer is enabled.
• PITIEN: Periodic Interval Timer Interrupt Enable
0 = The bit PITS in PIT_SR has no effect on interrupt.
1 = The bit PITS in PIT_SR asserts interrupt.
16.4.2 Periodic Interval Timer Status Register
Name: PIT_SR
Access: Read-only
• PITS: Periodic Interval Timer Status
0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR.
1 = The Periodic Interva l time r ha s re ached PIV since the last rea d of PIT_PIVR.
31 30 29 28 27 26 25 24
––––––PITIENPITEN
23 22 21 20 19 18 17 16
–––– PIV
15 14 13 12 11 10 9 8
PIV
76543210
PIV
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––PITS
84 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
16.4.3 Periodic Interval Timer Value Register
Name: PIT_PIVR
Access: Read-only
Reading this register clears PITS in PIT_SR.
• CPIV: Current Periodic Interval Value
Returns the current value of the periodic interval timer.
• PICNT: Pe ri odic In te r val Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
16.4.4 Periodic Interval Timer Image Registe r
Name: PIT_PIIR
Access: Read-only
• CPIV: Current Periodic Interval Value
Returns the current value of the periodic interval timer.
• PICNT: Pe ri odic In te r val Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
31 30 29 28 27 26 25 24
PICNT
23 22 21 20 19 18 17 16
PICNT CPIV
15 14 13 12 11 10 9 8
CPIV
76543210
CPIV
31 30 29 28 27 26 25 24
PICNT
23 22 21 20 19 18 17 16
PICNT CPIV
15 14 13 12 11 10 9 8
CPIV
76543210
CPIV
85
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
17. Voltage Regulator Mode Controller (VREG)
17.1 Overview The Voltage Regulator Mode Cont roller cont ains one Read /Write registe r, the Volt age Regu lator
Mode Register. Its offset is 0x60 with respect to the Syst em Controller offset.
This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage
Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake
up the Voltage Regulator in Normal Mode.
86 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
17.2 Voltage Regulator Power Controller (VREG) User Interface
17.2.1 Voltage Regulator Mode Register
Name: VREG_MR
Access: Read/Write
• PSTDBY: Periodic Interval Value
0 = Voltage regulator in normal mode.
1 = Voltage regulator in standby mode (low-power mode).
Table 17-1. Voltage Regulator Power Controller Register Mapping
Offset Register Name Access Reset Value
0x60 Voltage Regulator Mode Register VREG_MR Read/Write 0x0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––PSTDBY
87
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18. Memory Controller (MC)
18.1 Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the
masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a
simple bus arbiter, an address decoder, an abort status, a misalignment detector and an
Embedded Flash Controller. In addition, the MC contains a Memory Protection Unit (MPU) con-
sisting of 16 areas that can be protected against write and/or user accesses. Access to
peripherals can be protected in the same way.
18.2 Block Diagram
Figure 18-1. Memory Controller Block Diagram
ARM7TDMI
Processor
Bus
Arbiter
Peripheral
DMA
Controller
Memory Controller
Abort
ASB
Abort
Status
Address
Decoder
User
Interface
Peripheral 0
Peripheral 1
Internal
RAM
APB
APB
Bridge
Misalignment
Detector
From Master
to Slave
Peripheral N
Embedded
Flash
Controller
Internal
Flash
Memory
Protection
Unit
External
Bus
Interface
88 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.3 Functional Description
The Memory Controller handles the internal ASB bus and arbitrates the accesses of both
masters.
It is made up of:
• A bus arbiter
• An address decoder
• An abort status
• A misalignment detector
• A memory protection unit
• An Embedded Flash Controller
The MC handles only little-endia n mode accesses. The masters work in little-end ian mode only.
18.3.1 Bus Arbiter The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the
bus to one of the two masters. The Peripheral Data Controller has the highest priority; the ARM
processor has the lowest one.
18.3.2 Address Decoder
The Memory Controller fea tures an Address Decoder that first decodes the fou r highest bits of
the 32-bit address bus and defines 11 separate areas:
• One 256-Mbyte address space for the internal memories
• Eight 256-Mbyte address spaces, each assigned to one of the eight chip select lines of the
External Bus Interface
• One 256-Mbyte address space reserved for the embedded peripherals
• An undefined address space of 1536M bytes that returns an Abort if accessed
89
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.4 External Memory Areas
Figure 18-2 shows the assignment of the 256-Mbyte memory areas.
Figure 18-2. External Memory Areas
18.4.1 Internal Memory Mapping
Within the Intern al Memory address space, the Address Decoder of the Memory Controlle r
decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded
memories.
The allocated memor i es are accessed all a lon g t he 1 -Mb yte ad dr ess space and so are r epeat ed
n times within this addre ss sp ace , n equa lin g 1M byt es divided by the size of the me m ory.
When the address of the access is undefined within the internal memory area, the Address
Decoder retu rn s an Abor t to th e ma st er .
0x0000 0000
0x0FFF FFFF
0x1000 0000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
0x3000 0000
0x3FFF FFFF
0x4000 0000
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
0x7000 0000
0x7FFF FFFF
0x8000 0000
0x8FFF FFFF
0x9000 0000
0xEFFF FFFF
0xF000 0000
0xFFFF FFFF
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
6 x 256M Bytes
1,536 bytes
Internal Memories
Chip Select 0
Chip Select 1
Chip Select 2
Chip Select 3
Chip Select 4
Chip Select 5
Chip Select 6
Chip Select 7
Undefined
(Abort)
Peripherals
EBI
External
Bus
Interface
90 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 18-3. Internal Memor y Mapping
18.4.2 Internal Memory
Area 0 The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in
particular, the Reset Vector at address 0x0.
Before execution of the remap command, the internal ROM or the on-chip Flash is mapped into
Internal M emory Area 0, so that the ARM7T DMI reac hes an e xecutable instruction contained in
Flash. A gen eral purp ose bit (GPNVM Bit 2) is use d to boo t either on the RO M (def ault) or from
the Flash.
Setting the GPNVM Bit 2 selects the boot from the Flash, clearing it selects the boot from the
ROM. Asserting ERASE clears the GPNVM Bit 2 and thus selects the boot from the ROM by
default.
After the remap command, the internal SRAM at addr ess 0x0020 0000 is mapped into Internal
Memory Area 0. The memory mapped into Internal Memory Area 0 is accessible in both its orig-
inal location and at address 0x0.
18.4.3 Remap Command
After execution, the Remap Command causes the Internal SRAM to be accessed through the
Internal Memory Area 0.
As the ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
and Fast Int errupt) a re mapped f rom add ress 0x0 to address 0 x20, the Rema p Command a llows
the user to redefine dynamically these vectors unde r software control.
The Remap Com mand is accessible thro ugh the M emory Contro ller User Interface by writing the
MC_RCR (Remap Control Register) RCB field to one.
The Remap Command can be can celled by writing the MC_RCR RCB field to one, which acts as
a toggling command. This allows easy debug of the user-defined boot sequence by offering a
simple way to put the chip in the same configuration as after a reset.
256M Bytes
Internal Memory Area 0
Undefined Areas
(Abort)
0x000F FFFF
0x001F FFFF
0x002F FFFF
0x0FFF FFFF
1 M Bytes
1 M Bytes
1 M Bytes
252 M Bytes
Internal Memory Area 1
Internal Flash
Internal Memory Area 2
Internal SRAM
0x0000 0000
0x0010 0000
0x0020 0000
0x0030 0000 Internal Memory Area 3
Internal ROM
0x003F FFFF
0x0040 0000
1 M Bytes
91
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.4.4 Abort Status There are three reasons for an abort to occur:
• access to an undefined addre ss
• access to a protected area without the permitted state
• an access to a misaligned address.
When an abort occu rs, a sign al is se nt back t o all t h e maste rs, r egard less o f wh ich o ne ha s gen-
erated the access. However, only the ARM7TDMI can take an abort signal into account, and
only under the condition that it was generating an access. The Peripheral Data Controller does
not handle the abort input signal. Note that the connection is not represented in Figure 18-1.
To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates
an Abort Status register set.
The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in
MC_ASR and include:
• the size of the request (field ABTSZ)
• the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)
• whether the access is due to accessing an undefined address (bit UNDADD), a misaligned
address (bit MISADD) or a prot ection violation (bit MPU)
• the source of the access leading to the last abort (bits MST0 and MST1)
• whether or not an abort occurred for each master since the last read of the register (bit
SVMST0 and SVMST1) unless this information is loaded in MST bits
In the case of a Data Abort from the processor, the address of the data access is stored. This is
useful, as searching for which address generated the abort would require disassemblin g the
instructions and full knowledge of the processor context.
In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipe-
lined in the ARM proces so r. Th e ARM p rocessor takes t he pref et ch ab or t in to accou nt only if the
read instruction is execute d and it is prob able th at se veral abo rts have occur red during t his time.
Thus, in this case, it is preferable to use the content of the Abort Link register of the ARM
processor.
18.4.5 Memory Protection Unit
The Memory Protection Unit allows definition of up to 16 memory spaces within the internal
memories. Note that the external memories can not be protected.
After reset, the Memory Protection Unit is disabled. Enabling it requires writing the Protection
Unit Enable Register (MC_PUER) with the PUEB at 1.
Programming of the 16 memory spaces is done in the regist ers MC_PUIA0 to MC_PUIA15.
The size of each of the me mor y spaces is programmable by a power of 2 b etwe en 1K bytes and
4M bytes. The base address is also programmable on a number of bits according to the size.
The Memory Protection Unit also allows the protection of the peripherals by programming the
Protection Unit Peripheral Register (MC_PUP) with the field PROT at the appropriate value.
The peripher al address space and ea ch internal memory area can be protected again st write
and non-privile ged access of o ne of the mast ers. When one of the mast ers p erforms a for bidden
access, an Abort is generat ed and the Abort Status traces what has happened.
92 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
There is no priority in the protection of the memory spaces. In case of overlap between several
memory spaces, the strongest protection is taken into account. If an access is performed to an
address which is not contained in any of the 16 memory spaces, the Memory Protection Unit
generates an abort.
The reset value of MC_PUIAx registers is 0, which blocks all access to the first 1K of memory
starting at address 0, which prevents the core from reading exception vectors. Therefore, all
regions must be programmed to allow read/write access on the first 4M Bytes of the
memory range during MPU initialization.
18.4.6 Embedded Flash Controller
The Embedded Flash Controller is added to the Memory Controller and ensures the interface of
the flash block with the 32-bit internal bus. It allows an increase of performance in Thumb Mode
for Code Fetch with its system of 32-bit buffers. It also manages with the programming, erasing,
locking and unlocking sequences thanks to a full set of commands.
18.4.7 Misalignment Detector
The Memory Controller features a Misalignment Detector that checks the consistency of the
accesses.
For each access, regardless of the master, the size of the access and the bits 0 and 1 of the
address bus are checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0,
or if the type of t he access is a ha lf-wor d (16- bit) and t he bit 0 is not 0, an abo rt is re turned t o the
master and the access is cancelled. Note that the accesses of the ARM processor when it is
fetching instructions are not checked.
The misalignments are generally due to software bugs leading to wrong pointer handling. These
bugs are particularly difficult to detect in the debug phase.
As the requested address is saved in the Abort Status Register and the address of the instruc-
tion generating the misalignment is saved in the Abort Link Register of the processor, detection
and fix of this kind of software bugs is simplified.
93
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.5 Memory Controller (MC) User Interface
Base Address: 0xFFFFFF00
Table 18-1. Memory Controller (MC) Memory Mapping
Offset Register Name Access Reset State
0x00 MC Remap Control Register MC_RCR Write-only
0x04 MC Abort Status Register MC_ASR Read-only 0x0
0x08 MC Abort Address Status Register MC_AASR Read-only 0x0
0x0C Reserved
0x10 MC Protection Unit Area 0 MC_PUIA0 Read/Write 0x0
0x14 MC Protection Unit Area 1 MC_PUIA1 Read/Write 0x0
0x18 MC Protection Unit Area 2 MC_PUIA2 Read/Write 0x0
0x1C MC Protection Unit Area 3 MC_PUIA3 Read/Write 0x0
0x20 MC Protection Unit Area 4 MC_PUIA4 Read/Write 0x0
0x24 MC Protection Unit Area 5 MC_PUIA5 Read/Write 0x0
0x28 MC Protection Unit Area 6 MC_PUIA6 Read/Write 0x0
0x2C MC Protection Unit Area 7 MC_PUIA7 Read/Write 0x0
0x30 MC Protection Unit Area 8 MC_PUIA8 Read/Write 0x0
0x34 MC Protection Unit Area 9 MC_PUIA9 Read/Write 0x0
0x38 MC Protection Unit Area 10 MC_PUIA10 Read/Write 0x0
0x3C MC Protection Unit Area 11 MC_PUIA11 Read/Write 0x0
0x40 MC Protection Unit Area 12 MC_PUIA12 Read/Write 0x0
0x44 MC Protection Unit Area 13 MC_PUIA13 Read/Write 0x0
0x48 MC Protection Unit Area 14 MC_PUIA14 Read/Write 0x0
0x4C MC Protection Unit Area 15 MC_PUIA15 Read/Write 0x0
0x50 MC Protection Unit Peripherals MC_PUP Read/Write 0x0
0x54 MC Protection Unit Enable Register MC_PUER Read/Write 0x0
0x60 EFC0 Configuration Registers See EFC0 User Interface
0x70 EFC1 Configuration Registers See EFC1 User Interface
0x80 External bus Interface Registers See EBI User Interface
0x90 SMC Configuration Registers See SMC User Interface
0xB0 SDRAMC Configuration Registers See SDRAMC User Interface
0xDC ECC Configuration Registers See ECC User Interface
94 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.5.1 MC Remap Control Register
Name: MC_RCR
Access: Write-only
Absolute Address: 0xFFFF FF00
• RCB: Remap Command Bit
0: No effect.
1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero
memory devices.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––RCB
95
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.5.2 MC Abort Status Register
Name: MC_ASR
Access: Read-only
Reset Value:0x0
Absolute Address: 0xFFFF FF04
• UNDADD: Undefined Address Abort Status
0: The last abort was not due to the access of an undefined address in the address space.
1: The last abort was due to the access of an undefined address in the address space.
• MISADD: Misaligned Address Abort Status
0: The last aborted access was not due to an address misalignment .
1: The last aborted access was due to an address misalignment.
• MPU: Memory Protection Unit Abort Status
0: The last aborted access was not due to the Memory Protection Unit.
1: The last aborted access was due to the Memory Protection Unit.
• ABTSZ: Abort Size Status
• ABTTYP: Abort Type Status
31 30 29 28 27 26 25 24
––––––SVMST1SVMST0
23 22 21 20 19 18 17 16
––––––MST1MST0
15 14 13 12 11 10 9 8
– – – – ABTTYP ABTSZ
76543210
–––––MPUMISADDUNDADD
ABTSZ Abort Size
00 Byte
0 1 Half-word
10 Word
11 Reserved
ABTTYP Abort Type
0 0 Data Rea d
0 1 Data Write
1 0 Code Fetch
11 Reserved
96 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• MST0: PDC Abort Source
0: The last aborted access was not due to the PDC.
1: The last aborted access was due to the PDC.
• MST1: ARM7TDMI Abort Source
0: The last aborted access was not due to the ARM7TDMI.
1: The last aborted access was due to the ARM7TDMI.
• SVMST0: Saved PDC Abort Source
0: No abort due to the PDC occurred.
1: At least one abort due to the PDC occurred.
• SVMST1: Saved ARM7TDMI Abort Source
0: No abort due to the ARM7TDMI occurred.
1: At least one abort due to the ARM7TDMI occurred.
97
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.5.3 MC Abort Address Status Register
Name: MC_AASR
Access: Read-only
Reset Value:0x0
Absolute Address: 0xFFFF FF08
• ABTADD: Abort Address
This field contains the address of the last aborted access.
31 30 29 28 27 26 25 24
ABTADD
23 22 21 20 19 18 17 16
ABTADD
15 14 13 12 11 10 9 8
ABTADD
76543210
ABTADD
98 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.5.4 MC Protection Unit Area 0 to 15 Registers
Name: MC_PUIA0 - MC_PUIA15
Access: Read/Write
Reset Value:0x0
Absolute Address: 0xFFFFFF10 - 0xFFFFFF4C
•PROT: Protection
• SIZE: Internal Area Size
• BA: Internal Area Base Address
These bits define t he Base Address of t he area. Note t hat only the most significant bi ts of BA are significa nt. The number of
significant bits are in respect with the size of the area.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–– BA
15 14 13 12 11 10 9 8
BA – –
76543210
SIZE – – PROT
PROT
Processor Mode
Privilege User
0 0 No access No access
0 1 Read/Write No access
1 0 Read/Write Read-only
1 1 Read/Write Read/Write
SIZE Area Size LSB of BA
00001 KB 10
00012 KB 11
00104 KB 12
00118 KB 13
010016 KB 14
010132 KB 15
011064 KB 16
0111128 KB 17
1000256 KB 18
1001512 KB 19
10101 MB 20
10112 MB 21
11014 MB 22
99
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.5.5 MC Protection Unit Peripheral
Name: MC_PUP
Access: Read/Write
Reset Value: 0x000000000
Absolute Address: 0xFFFFFF50
•PROT: Protection
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––– PROT
PROT
Processor Mode
Privilege User
0 0 Read/Write No access
0 1 Read/Write No access
1 0 Read/Write Read-only
1 1 Read/Write Read/Write
100 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
18.5.6 MC Protection Unit Enable Register
Name: MC_PUER
Access: Read/Write
Reset Value: 0x000000000
Absolute Address: 0xFFFFFF54
• PUEB: Protection Unit Enable Bit
0: The Memory Controller Protection Unit is disabled.
1: The Memory Controller Protection Unit is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––PUEB
101
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
19. Embedded Flash Controller (EFC)
19.1 Overview The Embedded Flash Controller (EF C ) is a part of the Memory Cont roller and en sure s the inte r-
face of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for
Code Fetch wit h its system of 32-bit buf fers. It also ma nages the progra mming , erasing , locking
and unlocking sequences using a full set of commands.
The SAM7SE512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the
Security bit and GPNVM bits. The Security bit and GPNVM bits embedded only on EFC0 apply
to the two blocks in the SAM7SE512.
The SAM7SE256/32 is equipped with one EFC (EFC0).
19.2 Functional Description
19.2.1 Embedded Flash Organization
The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several
interfaces:
• One memory plane organized in sev eral pages of the same size
• Two 32-bit read buffers used f or code read optimization (see “Read Operations” on page
102).
• One write buffer that mana ges page programming. The write buffer size is equal to the page
size. This buffer is write-only and accessible all along the 1 MByte address space, so that
each word can be written to its final address (see “Write Operations” on page 104).
• Several lock bits used to protect write and erase operations on lock regions. A lock region is
composed of several consecutive pages, and each lock regi on has its associated lock bit .
• Se v er al gene ral-pu rpose NVM bits. Each bit cont rols a specific f eat ure in the device. Ref er to
the product definition section to get the GPNVM assignment.
The Embedded Flash size, the page size and the lock region organization are described in the
product definition section.
102 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 19-1. Embedded Flash Memory Mapping
19.2.2 Read Ope ra tio ns
An optimized contro ller manages embedd ed Flash rea ds. A system of 2 x 32-bit buffers is added
in order to start access at following address during the second read, thus increasing perfor-
mance when the processor is running in Thumb mode (16-bit instruction set). See Figure 19-2,
Figure 19-3 and Figure 19-4.
This optimization concerns only Code Fetch and not Data.
The read operations can be performed with or without wait state. Up to 3 wait states can be pro-
grammed in the field FWS (Flash Wait State) in the Flash M ode Register MC_FMR (see “MC
Flash Mode Register” on page 111). Defining FWS to be 0 enables the single-cycle access of
the embedded Flash.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the in ternal m emory area,
the embedded Flash wraps around the address space and appears to be repeated within it.
Lock Region 0
Lock Region
(n-1)
Page 0
Page (m-1)
Start Address
32-bit wide
Flash Memory
Page ( (n-1)*m )
Page (n*m-1)
Lock Bit 0
Lock Region 1 Lock Bit 1
Lock Bit n-1
103
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 19-2. Code Read Optimization in Thumb Mode for FWS = 0
Note: When FWS is equal to 0, all accesses are performed in a single-cycle access.
Figure 19-3. Code Read Optimization in Thumb Mode for FWS = 1
Note: When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for the
first one).
Flash Access
Buffer (32 bits)
Master Clock
ARM Request (16-bit)
Code Fetch
Data To ARM
Bytes 0-3 Bytes 4-7
Bytes 0-3
Bytes 0-1 Bytes 2-3 Bytes 4-5 Bytes 6-7 Bytes 8-9 Bytes 10-11 Bytes 12-13
@Byte 0 @Byte 2 @Byte 4 @Byte 6 @Byte 8 @Byte 10 @Byte 12 @Byte 14 @Byte 16
Bytes 14-15
Bytes 4-7
Bytes 8-11
Bytes 8-11
Bytes 12-15 Bytes 16-19
Bytes 12-15
Flash Access
Buffer (32 bits)
Master Clock
ARM Request (16-bit)
Code Fetch
Data To ARM
Bytes 0-3 Bytes 4-7
Bytes 0-3
Bytes 2-3 Bytes 4-5 Bytes 6-7 Bytes 8-9 Bytes 10-11
@Byte 0 @Byte 4 @Byte 6 @Byte 8 @Byte 10 @Byte 12 @Byte 14
Bytes 4-7
Bytes 8-11
Bytes 8-11
Bytes 12-15
1 Wait State Cycle
Bytes 0-1
1 Wait State Cycle 1 Wait State Cycle 1 Wait State Cycle
@Byte 2
Bytes 12-13
104 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3
Note: When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle , the
third access FWS cycles, the f ourth access one cycle, etc.
19.2.3 Writ e Ope rat ions
The internal memory area reserved for the embedded Flash can also be written through a write-
only latch buffer . Write ope rations take int o account only t he 8 lowest a ddress bits and t hus wrap
around within the internal memory area address space and appear to be repeated 1024 times
within it.
Write operations can be prevented by programming the Memory Protection Unit of the product.
Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in the number of wait states equal to the number of wait states
for read operations + 1, except for FWS = 3 (see “MC Flash Mode Register” on page 111).
19.2.4 Flash Commands
The EFC offers a co mma nd set to ma nag e pr ogr ammi ng the memor y flash, locking and unlo ck-
ing lock sectors, consecutive progr amming and locking, and full Flash erasing.
Flash Access
Master Clock
Data To ARM 0-1
@Byte 0 @2
Bytes 0-3 Bytes 4-7 Bytes 8-11 Bytes 12-15
Bytes 0-3
2-3 6-7
@4
8-9 10-11
4-5
@8 @12
Bytes 4-7
3 Wait State Cycles
Buffer (32 bits)
ARM Request (16-bit)
Code Fetch
Bytes 8-11
3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles
@6 @10
12-13
Table 19-1. Set of Commands
Command Value Mnemonic
Write page 0x01 WP
Set Lock Bit 0x02 SLB
Write Page and Lock 0x03 WPL
Clear Lock Bit 0x04 CLB
Erase al l 0x08 EA
Set General-purpose NVM Bit 0x0B SGPB
Clear General-purpose NVM Bit 0x0D CGPB
Set Security Bit 0x0F SSB
105
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
To run one of these commands, the field FCMD of the MC_FCR register has to be written with
the command number. As soon as the MC_FCR register is written, the FRDY flag is automati-
cally cleared. Once the current command is achie ved, then t he FRDY flag is automatically set. If
an interrupt has be en enab le d b y sett ing the bit FRDY in MC_FMR, the in terrupt line of th e Mem-
or y Controller is activated.
All the commands are protected by the same keyword, which has to be written in the eight high-
est bits of the MC_FCR register.
Writing MC_FCR with data that do es not con tain t he corr ect key an d/or with an invalid command
has no effect on the memory plane; however, the PROGE flag is set in the MC_FSR register.
This flag is automatically cleared by a read access to the MC_FSR register.
When the current command write s or erases a page in a locked region, the command has no
effect on the whole memor y plane; however, t he LO CKE flag is set in the MC_FSR regist er. This
flag is automatica lly cleared by a read access to the MC_ FSR register.
106 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 19-5. Command State Chart
In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle
Number (FMCN) in the Flash Mode Regi ster MC_FM R must be cor rectly prog ra mmed (see “MC
Flash Mode Register” on pa ge 111).
19.2.4.1 Flash Programming
Several commands can be used to program the Flash.
The Flash technology requires that an erase must be done before programming. The entire
memory plane can be erased at the same time, or a page can be automatically erased by clear-
ing the NEBP bit in the MC_FMR register before writing the command in the MC_FCR register.
By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps if
it has been erased before (see Figure 19-6).
Check if FRDY flag set No
Yes
Read Status: MC_FSR
Write FCMD and PAGENB in MC_FCR
Check if LOCKE flag set
Check if FRDY flag set No
Read Status: MC_FSR
Yes
Yes Locking region violation
No
Check if PROGE flag set Yes
No
Bad keyword violation and/or Invalid command
Command Successful
107
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 19-6. Example of Partial Page Programming:
The Partial Programming mode works only with 32-bit (or higher) boundaries. It cannot be used
with boundaries lo wer than 32 bits (8 or 16-bit for example).
After programming, the page (the whole lock region) can be locked to prevent miscellaneous
write or erase sequences. The lock bit can be automatically set after page programming using
WPL.
Data to be written is stored in an internal latch buffer. The size of the latch buffer corresponds to
the page size. The latch buffer wraps around within the internal memory area address space
and appears to be repeated by the number of pages in it.
Note: Writi ng of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Data is written to the lat ch buf fer be fo re the prog rammin g co mman d is written t o the Flash Com-
mand Register MC_FCR. The sequence is as follows:
• Write the full page, at any page add ress, within the internal memory area address space
using only 32-bit access .
• Progr amming starts as soon as the page n umber and th e progr amming command are written
to the Flash Command Register. The FRDY bit in the Flash Prog ramming Status Register
(MC_FSR) is automatically cleared.
• When programming is completed, the bit FRDY in the Flash Programming Status Register
(MC_FSR) rises. If an interrupt was enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: A bad keyword and/or an invalid command have been written in the
MC_FCR register.
• Lock Error: The page to be programmed belongs to a locked region. A command must be
previously run to unlock the corresponding region.
19.2.4.2 Erase All Command
The entire memory can be erased if the Erase All Command (EA) in the Flash Comma nd Regi s-
ter MC_FCR is written.
Erase All Flash Programming of the second part of Page 7 Programming of the third part of Page 7
32 bits wide 32 bits wide 32 bits wide
16 words
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
...
CA FE CA FE
CA FE CA FE
CA FE CA FE
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF CA FE CA FE
CA FE CA FE
CA FE CA FE
DE CA DE CA
DE CA DE CA
DE CA DE CA
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
Step 1. Step 2. Step 3.
...
...
...
...
...
...
...
...
...
...
...
(NEBP = 1) (NEBP = 1)
16 words
16 words
16 words
Page 7 erased
108 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Erase All operation is allowed only if t here are no lock bits set . Thus, if at least one lock regio n is
locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has
been writte n at 1 in MC_F M R, the int er ru pt line rise s.
When programming is complete, the bit FRDY bit in the Flash Programming Statu s Register
(MC_FSR) rises. If an inte rrupt has been enabled by setting the bit FRDY in MC_FMR, the inter-
rupt line of the Memory Controller is activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: A bad keyword and/or an invalid command have been written in the
MC_FCR register.
• Loc k Error: At least one lock re gion to be e rased is p rotected . The er ase command has b een
refused and no page has been erased. A Clear Lock Bit command must be executed
previously to unlock the corresponding lock regions.
19.2.4.3 Lock Bit Protection
Lock bits are associated with several pages in the embedded Flash memory plane. This defines
lock regions in the embedded Flash memory plane. They prevent writing/erasing protected
pages.
After producti on, the device may h ave some e mbedd ed Flash lo ck regi ons locke d. The se locked
regions are reserved for a default application. Refer to the product definition section for the
default embedded Flash mapping. Locked sectors can be unlocked to be erased and then pro-
grammed with another application or other data.
The lock sequence is:
• The Flash Command register must be written with the following value:
(0x5A << 24) | (lockPageNumber << 8 & PAG EN) | SLB
lock PageNumber is a page of the co rresponding lock region.
• When loc king completes , t he bit FRDY in the Flash Prog ramming Status Registe r (MC_FSR)
rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line
of the Memory Controller is activated.
A programming error, where a bad keyword and/or an invalid command have been written in the
MC_FCR register, may be detected in the MC_FSR register after a programming sequence.
It is possible to clear lock bits that were set previously. Then the locked region can be erased or
programmed. The unlock sequence is:
• The Flash Command register must be written with the following value:
(0x5A << 24) | (lockPageNumber << 8 & PAG EN) | CLB
lock PageNumber is a page of the co rresponding lock region.
• When the unlock completes, the bit FRDY in the Flash Programming Status Register
(MC_FSR) rises. If an interrupt has been enabl ed by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
A progr a mming er r or, whe re a ba d keywor d an d/or an in valid comman d ha ve been wr itt en in t he
MC_FCR register, may be detected in the MC_FSR register after a programming sequence.
The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR
reads 0. The Lock command programs the lock bit to 0; the corresponding bit LOCKSx in
MC_FSR reads 1.
Note: Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed.
109
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
19.2.4.4 General-purpose NVM Bits
General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not
apply to EFC1 on the SAM7SE512.) These general-purpose bits are dedicated to protect other
parts of the product. They can be set ( activated) or cleared individually. Refer to the produ ct def-
inition section for the general-purpose NVM bit action.
The activation sequence is:
• Start the Set Gener al Purpose Bit command (SGPB) b y writing the Flash Command Register
with the SEL command and the number of the general-purpose bit to be set in the PAGEN
field.
• When the bit is set, t he bit FRDY in the Flash Prog rammin g Status Register (MC_ FSR) rises.
If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the
Memory Controller is activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: A bad keyword and/or an invalid command have been written in the
MC_FCR register
• If the general-purpose bit number is greater than the total number of general-purpose bits,
then the command has no effect.
It is possible to deactivate a general-purpose NVM bit set previously. The clear sequence is:
• Start the Clear General-purpose Bit command (CGPB) by writing the Flash Command
Register with CGPB and the number of the general-purpose bit to be cleared in the PAGEN
field.
• When the clear completes, the bit FRDY in the Flash Programming Status Register
(MC_FSR) rises. If an interrupt has been enabl ed by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: a bad keyword and/or an invalid command have been written in the
MC_FCR register
• If the number of the general-purpose bit set in the PAGEN field is greater than the total
number of general-purpose bits, then the command has no effect.
The Clear G eneral-purp ose Bit command programs the gen eral-purpo se NVM bit to 0; the corr e-
sponding bit GPNVM0 t o GPNVM x in MC_FSR r ea ds 0. The Set G enera l-pur pose Bit comm and
programs the general-purpose NVM bit to 1; the corresponding bit GPNVMx in MC_FSR
reads 1.
Note: Access to the Flash in read mode is permitted when a Set, Clear or Get General-purpose NVM Bit
command is performed.
19.2.4.5 Security Bit The goal of the security bit is to prevent external access to the internal bus system. (Does not
apply to EFC1 on the SAM7SE5 12.) JTAG, Fast Flash Programming and Flash Serial Test In ter-
face features are disabled. Once set, this bit can be reset only by an external hardware ERASE
request to the ch ip. Refer to the product def inition section for the pin name that con trols the
ERASE. In this ca se, t he full me mory pla ne is erased and all lock an d gen eral-pur pose NVM bit s
are cleared. The security bit in the MC_FSR is cleared only after these operations. The activa-
tion sequence is:
• Start the Set Security Bit command ( SSB) by writing the Flash Command Register.
110 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• When the locking completes, the bit FRDY in the Flash Programming Status Register
(MC_FSR) rises. If an interrupt has been enabl ed by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
When the security bit is active, the SECURITY bit in the MC_FSR is set.
19.3 Embedded Flash Controller (EFC ) User Interface
The User Interface of the EFC is integrated within the Memory Controller with Base Address:
0xFFFF FF00.
The SAM7SE512 is equipped with two EFCs, EFC0 and EFC1, as d escribed in the Register
Mapping tables and Register descriptions that follow.
The SAM7SE256/32 is equipped with one EFC (EFC0).
Table 19-2. Embedded Flash Controller (EFC0) Register Mapping
Offset Register Name Access Reset State
0x60 MC Flash Mode Register MC_FMR Read/Write 0x0
0x64 MC Flash Command Register MC_FCR Write-only –
0x68 MC Flash Status Register MC_FSR Read-only –
0x6C Reserved – – –
Table 19-3. Embedded Flash Controller (EFC1) Register Mapping
Offset Register Name Access Reset State
0x70 MC Flash Mode Register MC_FMR Read/Write 0x0
0x74 MC Flash Command Register MC_FCR Write-only –
0x78 MC Flash Status Register MC_FSR Read-only –
0x7C Reserved – – –
111
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
19.3.1 MC Flash Mode Register
Name: MC_FMR
Access: Read/Write
Offset: (EFC0) 0x60
Offset: (EFC1) 0x70
• FRDY: Flash Ready Interrupt Enable
0: Flash Ready does not generate an interrupt.
1: Flash Ready generates an interrupt.
• LOCKE: Lock Error Interrupt Enable
0: Lock Error does not generate an interrupt.
1: Lock Error generates an interrupt.
• PROGE: Programming Error In terrupt Enable
0: Programming Error does not generate an int errupt.
1: Programming Error generates an interrupt.
• NEBP: No Erase Before Programming
0: A page erase is performed before programming.
1: No erase is perfor med before programming.
• FWS: Flash Wait State
This field defines the number of wait states for read and write operations:
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
FMCN
15 14 13 12 11 10 9 8
–––––– FWS
76543210
NEBP – – – PROGE LOCKE – FRDY
FWS Read Operations Write Operations
0 1 cycle 2 cycles
1 2 cycles 3 cycles
2 3 cycles 4 cycles
3 4 cycles 4 cycles
112 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• FMCN: Flash Microsecond Cycle Number
Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the
number of Master Clock cycles in one microsecond.
When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number
must be rounded up.
Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds.
Warning: In order to guarantee valid operations on the flash memory, the field Flash Microsecond Cycle Number (FMCN)
must be correctly programmed.
113
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
19.3.2 MC Flash Command Register
Name: MC_FCR
Access: Write-only
Offset: (EFC0) 0x64
Offset: (EFC1) 0x74
• FCMD: Flash Command
This field defines the Flash commands:
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
–––––– PAGEN
15 14 13 12 11 10 9 8
PAGEN
76543210
–––– FCMD
FCMD Operations
0000 No command.
Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR.
0001 Write Page Command (WP):
Starts the programming of the page specified in the PAGEN field.
0010 Set Lock Bit Command (SLB):
Starts a set lock bit sequence of the lock region specified in the PAGEN field.
0011 Write Page and Lock Command (WPL):
The lock sequence of the lock region associa te d with the page specified in the field PAGEN
occurs automatically after completion of the programming sequence.
0100 Clear Lock Bit Command (CLB):
Starts a clear lock bit sequence of the lock region specified in the PAGEN field.
1000 Erase All Command (EA):
Starts the erase of the entire Flash.
If at least one page is locked, the command is cancelled.
1011 Set General-purpose NVM Bit (SGPB):
Activates the general-purpose NVM bit corresponding to the number specified in the PAGEN
field.
1101 Clear General Purpose NVM Bit (CGPB):
Deactivates the general-purpose NVM bit corresponding to the number specified in the
PA GEN field.
1111 Set Security Bit Command (SSB):
Sets security bit.
Others Reserved.
Raises the Programming Error Status flag in the Flash Status Register MC_FSR.
114 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
•PAGEN: Page Number
Note: Depending on the command, all the possible unused bits of PAGEN are meaningless.
• KEY: Write Protection Key
This field shou ld be writte n with the va lue 0x5A to enable the comm and defin ed by the bits of the regist er. I f the f ield is writ-
ten with a different value, the write is not performed and no action is started.
Command PAGEN Description
Write Page Command PAGEN defines the page number to be written.
Write Page and Lock Command PAGEN defines the page number to be written and its associated
lock region.
Erase All Command This field is meaningless
Set/Clear Lock Bit Command PAGEN defines one page number of the lock region to be locked or
unlocked.
Set/Clear General Purpose NVM Bit Command PAGEN defines the general-purpose bit number.
Set Security Bit Command This field is meaningless
115
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
19.3.3 MC Flash Status Register
Name: MC_FSR
Access: Read-only
Offset: (EFC0) 0x68
Offset: (EFC1) 0x78
• FRDY: Flash Ready Status
0: The EFC is busy an d the application must wait before running a new command.
1: The EFC is ready to run a new command.
• LOCKE: Lock Error Status
0: No programming of at least one locked lock region has happened since the last read of MC_FSR.
1: Programming of at least one locked lock region has happened since the last read of MC_FSR.
• PROGE: Programming Error Status
0: No invalid commands and no bad keywords were written in the Flash Command Register MC_FCR.
1: An invalid command and/or a bad keyword was/were written in the Flash Command Register MC_FCR.
• SECURITY: Security Bit Status (Does not apply to EFC1 on the SAM7SE512.)
0: The security bit is inactive.
1: The security bit is active.
• GPNVMx: General-pur pose NVM Bit Status (Does not apply to EFC1 on the SAM7SE512.)
0: The corresponding general-purpose NVM bit is inactive.
1: The corresponding general-purpose NVM bit is active.
• EFC LOCKSx: Lock Region x Lock Status
0: The corresponding lock region is not locked.
1: The corresponding lock region is locked.
LOCKS 8-15 do not apply to SAM7SE32.
31 30 29 28 27 26 25 24
LOCKS15 LOCKS14 LOCKS13 LOCKS12 LOCKS11 LOCKS10 LOCKS9 LOCKS8
23 22 21 20 19 18 17 16
LOCKS7 LOCKS6 LOCKS5 LOCKS4 LOCKS3 LOCKS2 LOCKS1 LOCKS0
15 14 13 12 11 10 9 8
–––––GPNVM2 GPNVM1 GPNVM0
76543210
– – – SECURITY PROGE LOCKE – FRDY
116 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
117
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20. Fast Flash Programming Interface (FFPI)
20.1 Overview The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-vol-
ume programming using a standard gang programmer. The parallel interface is fully
handshaked and the d evice is considered to be a standard EEPROM. Additionally, the parallel
protocol offers an optimized access to all the embedded Flash functionalities. The serial inter-
face uses the standard IEEE 1149.1 JTAG protocol. It offers an optimized access to all the
embedded Flash functionalities.
Although the Fast Flas h Progra mmin g Mode is a ded ica ted mo de for high volume p rogra mmin g,
this mode not designed for in-situ programming.
118 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.2 Parallel Fast Flash Programming
20.2.1 Device Configuration
In Fast Flash Progr amming Mode, t he device is in a spe cific test mode . Only a certain set of pins
is significant. Other pins must be left unconn ected.
Figure 20-1. Parallel Programming Interface
NCMD PGMNCMD
RDY PGMRDY
NOE PGMNOE
NVALID PGMNVALID
MODE[3:0] PGMM[3:0]
DATA[15:0] PGMD[15:0]
XIN
TST
VDDIO PGMEN0
PGMEN1
0 - 50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
VDDFLASH
GND
VDDIO
Table 20-1. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDFLASH Flash Power Supply Power
VDDIO I/O Lines Pow er Supply Power
VDDCORE Core Power Supply Power
VDDPLL PLL Power Supply Powe r
GND Ground Ground
Clocks
XIN
Main Clock Input.
This input can be tied to GND. In this
case, the device is clocked by the internal
RC oscillator.
Input 32KHz to 50MHz
Test
TST Test Mode Select Input High Must be connected to VDDIO
PGMEN0 Test Mode Select Input High Must be connected to VDDIO
PGMEN1 Test Mode Select Input High Must be connected to VDDIO
119
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.2.2 Signal Names Depending on the MODE settings, DATA is latched in different internal re gisters.
PIO
PGMNCMD Valid command available Input Low Pulled-up input at reset
PGMRDY 0: Device is busy
1: Device is ready for a new command Output High Pulled-up input at reset
PGMNOE Output Enable (active high) Input Low Pulled-up input at reset
PGMNVALID 0: DATA[15:0] is in input mode
1: DATA[15:0] is in output mode Output Low Pulled-up input at reset
PGMM[3:0] Specifies DATA type (See Table 20-2) Input Pulled-up input at reset
PGMD[15:0] Bidirectional data bus Input/Output Pulled- up input at reset
Table 20-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
Table 20-2. Mode Coding
MODE[3:0] Symbol Data
0000 CMDE Command Register
0001 ADDR0 Address Register LSBs
0010 ADDR1
0101 D ATA Data Register
Default IDLE No register
120 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
When MODE is equal to CMDE, then a new comm and (stro bed on DATA[15 :0] signa ls) is stor ed
in the command register.
Note: 1. Applies to SAM7SE512.
20.2.3 Entering Programming Mode
The following algorithm puts the device in Parallel Programming Mode:
• Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL.
• Apply XIN clock within TPOR_RESET if an external clock is available.
•Wait for T
POR_RESET
• Start a read or write handshaking.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an
external clock (> 32 kHz) is connected to XIN, then the device switches on the external clock.
Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer
handshake.
20.2.4 Programmer Handshaking
An handshake is defined for read and write operations. When the device is ready to start a new
operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal.
The handshaking is achieved once NCMD signal is high and RDY is high.
Table 20-3. Command Bit Coding
DATA[15:0] Symbol Command Executed
0x0011 READ Read Flash
0x0012 WP Write Page Flash
0x0022 WPL Write Page and Lock Flash
0x0032 EWP Erase Page and Write Page
0x0042 EWPL Erase Page and Write Page then Lock
0x0013 EA Erase All
0x0014 SLB Set Lock Bit
0x0024 CLB Clear Lock Bit
0x0015 GLB Get Lock Bit
0x0034 SFB Set General Purpose NVM bit
0x0044 CFB Clear General Purpose NVM bit
0x0025 GFB Get General Purpose NVM bit
0x0054 SSE Set Security Bit
0x0035 GSE Get Security Bit
0x001F WRAM Write Memory
0x0016 SEFC Select EFC Controller (1)
0x001E GVE Get Version
121
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.2.4.1 Write Handshaking
For details on the write handshaking sequence, refer to Figure 20-2and Table 20-4.
Figure 20-2. Parallel Programming Timing, Write Sequence
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
Table 20-4. Write Handshake
Step Programmer Action Device Action Data I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latches MODE and DATA Input
3 Waits for RDY low Clears RDY signal Input
4 Releases MODE and DATA signals Executes command and polls NCMD high Input
5 Sets NCMD signal Executes command and polls NCMD high Input
6 Waits for RDY high Sets RDY Input
122 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.2.4.2 Read Handshaking
For details on the read handshaking sequence, refer to Figure 20-3 and Table 20-5.
Figure 20-3. Parallel Programming Timing, Read Sequence
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
6
7
9
8
ADDR
Adress IN Z Data OUT
10
11
XIN
12
13
Table 20-5. Read Handshake
Step Programmer Action Device Action DATA I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal L atch MODE and DATA Input
3 Waits for RDY low Clears RDY signal Input
4 Sets DATA signal in tristate Waits for NOE Low Input
5 Clears NOE signal Tristate
6 Waits for NVALID low Sets DATA bus in output mode and outputs
the flash contents. Output
7 Clears NVALID signal Output
8 Reads value on DATA Bus Waits for NOE high Output
9 S ets NOE signal Output
10 Waits f or NVALID high Sets DATA bus in input mode X
11 Sets DATA in output mode Sets NVALID signal Input
12 Sets NCMD signal Waits for NCMD high Input
13 Waits for RDY high Sets RDY signal Input
123
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.2.5 Device Operations
Several commands on the Flash memory are available. These command s are summarized in
Table 20-3 on page 120. Each comm a nd is driven by th e pr og ra m me r th ro ug h th e pa ra lle l int er -
face running several read/write handshaking sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining
a read command after a write automatically flushes the load buffer in the Flash.
20.2.5.1 Flash Read Command
This command is used to read the contents of the Flash memory. The read command can start
at any valid address in the memory plane and is optimized for consecutive reads. Read hand-
shaking can be chained; an internal address buffer is automatically increased.
20.2.5.2 Flash Write Command
This command is used to write the Flash contents.
The Flash memory plane is organized into several pages. Data to be written are stored in a load
buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the
Flash:
• before access to any page other th an the curr en t on e
• when a new command is validated (MODE = CMDE)
Table 20-6. Read Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE READ
2 Write handshaking ADDR0 32-bi t Memory Address First byte
3 Write handshaki ng ADDR1 32-bit Flash Address
6 Read handshaking DATA *Memory Address++
7 Read handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 32-bi t Memory Address First byte
n+1 Write handshaking ADDR1 32-bit Flash Address
n+2 Write handshaking ADDR2 32-bit Flash Address
n+3 Write handshaking ADDR3 32-bit Flash Address Last Byte
n+4 Read handshaking DATA *Memory Address++
n+5 Read handshaking DATA *Memory Address++
... ... ... ...
124 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The Write P age command (WP) is optimized for consecutive writes. Write handshaking can be
chained; an intern al address buffer is automatically increased.
The Flash command Write Page and Lock (WPL) is equivalen t to the Flash Write Com mand.
However, the lock b it is automa tically set at the end of the Flash write ope ration. As a lock region
is composed of several pages, the programmer writes to the first pages of the lock region using
Flash write command s and wr ites to the last pa ge of t he lock reg ion using a Flash write an d lock
command.
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command.
However, before programming the load buffer, the page is erased.
The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL
commands.
20.2.5.3 Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command.
Otherwise, the erase command is aborted and no page is erased.
Table 20-7. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WP or WPL or EWP or EWPL
2 Write handshaking ADDR0 32-bit Memory Address First byte
3 Write handshaking ADDR1 32-bit Flash Address
4 Write handshaking ADDR2 32-bit Flash Address
5 Write handshaking ADDR3 32-bit Flash Address Last Byte
6 Write handshaking DATA *Memory Address++
7 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 32-bit Memory Address First byte
n+1 Write handshaking ADDR1 32-bit Flash Address
n+2 Write handshaking ADDR2 32-bit Flash Address
n+3 Write handshaking ADDR3 32-bit Flash Address Last Byte
n+4 Write handshaking DATA *Memory Address++
n+5 Write handshaking DATA *Memory Address++
... ... ... ...
Table 20-8. Full Erase Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE EA
2 Write handshaking DATA 0
125
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.2.5.4 Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set
Lock command (SLB). With this command, seve ral lock bits can be activated. A Bit Mask is pro-
vided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is
activated.
In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are
also cleared by the EA command.
Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit
n of the bit mask is set..
20.2.5.5 Flash General-purpo se NVM Comm a nd s
General-purp ose NVM bits (GP NVM bits) can be set using the Set Fuse command (SFB). This
command also activates GP NVM bits. A bit mask is provided as argument to the command.
When bit 0 of the bit mask is set, the n the first GP NVM bit is activa te d.
In the same way, the Clear Fuse command (CFB) is used to clear general-purpose NVM bits.
All the general-purpose NVM bits are also cle ared by the EA command. The general-purpose
NVM bit is deactivated when the corresponding bit in the pattern value is set to 1.
General-purpose NVM bits can be read using the Get Fuse Bit command (GFB). The nth GP
NVM bit is active when bit n of the bit mask is set..
Table 20-9. Set and Clear Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handsha king CMDE SLB or CLB
2 Write handshaking DATA Bit Mask
Table 20-10. Get Lock Bit Command
Step Handshak e Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GLB
2 Read handshaking DATA Lock Bit Mask Status
0 = Lock bit is cleared
1 = Lock bit is set
Table 20-11. Set/Clear GP NVM Command
Step Handshak e Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SFB or CFB
2 Wri te handshaking DATA GP NVM bit pattern value
Table 20-12. Get GP NVM Bit Command
Step Handshak e Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GFB
2 Read handshaking DATA GP NVM Bit Mask Status
0 = GP NVM bit is cleared
1 = GP NVM bit is set
126 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.2.5.6 Flash Secur ity Bit Command
A security bit can be set using the Set Security Bit command (SSE). On ce the security bit is
active, the Fast Flash programming is disabled. No other command can be run. An event on the
Erase pin can eras e th e sec ur i ty bit onc e the contents of the Flash have been erased.
The SAM7SE512 security bit is controlled by the EFC0. To use the Set Security Bit command,
the EFC0 must be selected using the Select EFC command.
20.2.5.7 SAM7SE512 Select EFC Command
The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default
EFC controller is EFC0. The Select EFC command (SEFC) allows selection of the current EFC
controller.
20.2.5.8 Memor y Write Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write han dshaking
can be chained; an internal address buffer is automatically increased.
Table 20-13. Set Security Bit Command
Step Handshak e Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SSE
2 Write handshaking DATA 0
Table 20-14. Select EFC Command
Step Handshak e Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SEFC
2 Write handshaking DATA 0 = Select EFC0
1 = Select EFC1
Table 20-15. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WRAM
2 Write handshaking ADDR0 32-bit Memory Address First byte
3 Write handshaking ADDR1 32-bit Flash Address
4 Write handshaking ADDR2 32-bit Flash Address
5 Write handshaking ADDR3 32-bit Flash Address Last Byte
6 Write handshaking DATA *Memory Address++
7 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 32-bit Memory Address First byte
n+1 Write handshaking ADDR1 32-bit Flash Address
n+2 Write handshaking ADDR2 32-bit Flash Address
n+3 Write handshaking ADDR3 32-bit Flash Address Last Byte
127
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.2.5.9 Get Version Comm a nd
The Get Version (GVE) command retrieves the version of the FFPI inte rface.
n+4 Write handshaking DATA *Memory Address++
n+5 Write handshaking DATA *Memory Address++
... ... ... ...
Table 20-15. Write Command (Contin ued)
Step Handshake Sequence MODE[3:0] DATA[15:0]
Table 20-16. Get Version Command
Step Handshak e Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GVE
2 Write handshaking DATA Version
128 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.3 Serial Fast Flash Programming
The Serial Fast Flash progra mming interface is based on IEEE Std. 1149.1 “Standard Test
Access Port and Boundary-Scan Architecture” . Refer to this stan dard for a n explanat ion of ter ms
used in this chapter and for a description of the TAP controller states.
In this mode, data read/written from/to the embedded Flash of the device are transmitted
through the JTAG interface of the device.
20.3.1 Device Configuration
In Serial Fast Flash Programming Mode, the device is in a specific test mode. Only a distinct set
of pins is significant. Other pins must be left unconnected.
Figure 20-4. Serial Programing
TDI
TDO
TMS
TCK
XIN
TST
VDDIO PGMEN0
PGMEN1
0-50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
VDDFLASH
GND
VDDIO
Table 20-17. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDFLASH Flash Power Supply Power
VDDIO I/O Lines Pow er Supply Power
VDDCORE Core Power Supply Power
VDDPLL PLL Power Supply Powe r
GND Ground Ground
Clocks
XIN
Main Clock Input.
This input can be tied to GND. In this
case, the device is clocked by the internal
RC oscillator.
Input 32 kHz to 50 MHz
129
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.3.2 Entering Serial Programming Mode
The following algorithm puts the device in Serial Programming Mode:
• Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL.
• Apply XIN clock within TPOR_RESET + 32(TSCLK) if an external clock is available.
•Wait for T
POR_RESET.
• Reset the TAP controller clocking 5 TCK pulses with TMS set.
• Shift 0x2 into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-
Idle state.
• Shift 0x2 into the DR register (DR is 4 bits long, LSB first) without going through the Run-
Test-Idle state.
• Shift 0xC into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-
Idle state.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an
external clock (> 32 kHz) is connected to XIN, then the device will switch on the external clock.
Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer
handshake.
Test
TST Test Mode Select Input High Must be connected to VDDIO.
PGMEN0 Test Mode Select Input High Must be connected to VDDIO
PGMEN1 Test Mode Select Input High Must be connected to VDDIO
JTAG
TCK JTAG TCK Input - Pulled-up input at reset
TDI JTAG Test Data In Input - Pulled-up inpu t at rese t
TDO JTAG Test Data Out Output -
TMS JTAG Test Mode Select Input - Pulled-up input at rese t
Table 20-17. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
Table 20-18. Reset TAP Controller and Go to Select-DR-Scan
TDI TMS TAP Controller State
X1
X1
X1
X1
X 1 Test-Logic Reset
X 0 Run-Test/Idle
Xt 1 Select-DR-Scan
130 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.3.3 Read/Write Handshake
The read/write handshake is d one by carrying out read/write operations on two registers of the
device that ar e accessible through the JTAG:
• Debug Comms Control Register: DCCR
• Debug Comms Data Register: DCDR
Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data
field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit
data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A
register is read by scanning its address into the address fie ld and 0 into th e rea d/writ e bi t, goin g
through the UPDATE- DR TAP state, then scanning out the data.
Refer to the ARM7TDMI r eference manuel for more information on Comm channel operations.
Figure 20-5. TAP 8-bit DR Register
A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE
1149.1 for mor e details on JTAG operations.
• The address of the Debug Comms Control Register is 0x04.
• The address of th e Debug Comms Data Register is 0x05.
The Debug Comms Control Register is read- only and allows synchronized handshaking
between the processor and the debugger.
– Bit 1 (W): Denotes whether the programmer can read a data through the Debug
Comms Data Register. If the device is busy W = 0, then the progr ammer must poll
until W = 1.
– Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms
Data Register. If R = 1, data previously placed there through the scan chain has n ot
been collected by the device and so the programmer must wait.
The write handshake is done by polling the Debug Comms Control Register until the R bit is
cleared. Once cleared, data can be written to the Debug Comms Data Register.
The read handshake is done by polling the Debug Comms Control Register until the W bit is set.
Once set, data can be rea d in th e Deb u g Comm s Da ta Re gis ter .
20.3.4 Device Operations
Several commands on the Flash memory are available. These command s are summarized in
Table 20-3 on pag e 120. Commands are run by the programmer through the serial interface that
is reading and writing the Debug Comms Registers.
TDI TDO
40
r/w Address 31 Data 0
Address
Decoder
Debug Comms Control Register
Debug Comms Data Register
32
5
131
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.3.4.1 Flash Read Command
This command is use d to read the Flash contents. The memory map is accessible through this
command. Memory is seen a s an array of words (32 -bit wide). The read command can start at
any valid address in the memory plane. This addre ss must be word-aligned. The address is
automatically incremen ted.
20.3.4.2 Flash Write Command
This command is used to write the Flash contents. The address transmitted must be a valid
Flash address in the memory plane.
The Flash memory plane is organized into several pages. Data to be written is stored in a load
buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the
Flash:
• before access to any page than the current one
• at the end of the number of words transmitted
The Write P age command (WP) is optimized for consecutive writes. Write handshaking can be
chained; an intern al address buffer is automatically increased.
Flash Write Page and Lock command (WPL) is equivalent to the Flash Write Command. How-
ever, the lock bit is automatically set at the end of the Flash write operation. As a lock region is
composed of several pages, the programmer write s to the first pages of the lock region using
Flash write command s and wr ites to the last pa ge of t he lock reg ion using a Flash write an d lock
command.
Flash Erase Page and Write command (EWP) is equivalent t o the Flash Write Command. How-
ever, before pr ogramming the load buffer, the page is erased.
Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL
commands.
Table 20-19. Read Command
Read/Write DR Data
Write (Number of W ords to Read) << 16 | READ
Write Address
Read Memo ry [address]
Read Memory [address+4]
... ...
Read Memory [address+ (Number of Words to Read - 1)* 4]
Table 20-20. Write Command
Read/Write DR Data
Write (Number of Words to Write) << 16 | (WP or WPL or EWP or EWPL)
Write Address
Write Memory [address]
Write Memory [address+4]
Write Memory [address+8]
Write Memory [address+(Number of Words to Write - 1)* 4]
132 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.3.4.3 Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock bits must be deactivated before using the Full Erase comma nd. This can be done by
using the CLB command.
20.3.4.4 Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set
Lock command (SLB). With this command, several lock bits can be activated at the same time.
Bit 0 of Bit Mask corresponds to the first lock bit and so on.
In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits can
also be cleared by the EA command.
Lock bits can be read using Ge t Lock Bit command (GLB). When a bit set in the Bit Mask is
returned, then the corresponding lock bit is active.
20.3.4.5 Flash General-purpo se NVM Comm a nd s
General-purpose NVM bits (GP NVM) can be set with the Set Fuse command (SFB). Using this
command, several GP NVM bits can be activated at the same time. Bit 0 of Bit Mask corre-
sponds to the first fuse bit and so on.
In the same wa y, the Clea r Fuse command (CFB) is used to cl ear GP NVM bit s. All the gener al-
purpose NVM bits are also cleared by the EA command.
Table 20-21. Full Erase Command
Read/Write DR Data
Write EA
Table 20-22. Set and Clear Lock Bit Command
Read/Write DR Data
Write SLB or CLB
Write Bit Mask
Table 20-23. Get Lock Bit Command
Read/Write DR Data
Write GLB
Read Bit Mask
Table 20-24. Set and Clear General-purpose NVM Bit Command
Read/Write DR Data
Write SFB or CFB
Write Bit Mask
133
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
GP NVM bits can be read using Get Fuse Bit command (GFB). When a bit set in the Bit Mask is
returned, t hen the corresponding fuse bit is set.
20.3.4.6 Flash Secur ity Bit Command
Security bits can be set using Set Security Bit command (SSE). Once the security bit is active,
the Fast Flash programming is disabled. No other command can be run. Only an event on the
Erase pin can eras e th e sec ur i ty bit onc e the contents of the Flash have been erased.
The SAM7SE512 security bit is controlled by the EFC0. To use the Set Security Bit command,
the EFC0 must be selected using the Select EFC command.
20.3.4.7 SAM7SE512 Select EFC Command
The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default
EFC controller is EFC0. The Select EFC command (SEFC) allows selection of the current EFC
controller.
20.3.4.8 Memor y Write Command
This command is used to perform a write access to any memory location.
The Memory Write command (W RAM) is optimized for consecutive writes. An internal address
buffer is automatically increased.
Table 20-25. Get General-purpose NVM Bit Command
Read/Write DR Data
Write GFB
Read Bit Mask
Table 20-26. Set Security Bit Command
Read/Write DR Data
Write SSE
Table 20-27. Select EFC Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SEFC
2 Write handshaking DATA 0 = Select EFC0
1 = Select EFC1
Table 20-28. Write Command
Read/Write DR Data
Write (Number of Words to Write) << 16 | (WRAM)
Write Address
Write Memory [address]
Write Memory [address+4]
Write Memory [address+8]
Write Memory [address+(Number of Words to Write - 1)* 4]
134 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20.3.4.9 Get Version Comm a nd
The Get Version (GVE) command retrieves the version of the FFPI inte rface.
Table 20-29. Get Version Command
Read/Write DR Data
Write GVE
Read Version
135
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21. External Bus Interface (EBI)
21.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between
several external devices and the embedded Memory Controller of an ARM-based device. The
Static Memory, SDRAM and ECC Controllers are all featured external Memory Co ntrollers on
the EBI. These external Memory Controllers are capable of handling several types of external
memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and
SDRAM.
The EBI also supp orts th e Compact Flash® an d the NAND Flash pr otocols via integ rated circui try
that greatly reduces the requirements for external components. Furthermore, the EBI handles
data transfers with up to eight external devices, each assigned to eight address spaces defined
by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit
data bus, an address bus of up to 23 bits, up to eight chip select lines (NCS[7:0]) and several
control pins that are generally multiplexed between the different external Memory Controllers.
136 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.2 Block Diagram
Figure 21-1. Organization of the External Bus Interface
External Bus Interface
D[31:0]
A[15:2], A[20:18]
MUX
Logic
NAND Flash
Logic
CompactFlash
Logic
User Interface
Chip Select
Assignor
Static
Memory
Controller
SDRAM
Controller
Memory
Controller
APB
ASB
Address Decoder
A16/BA0
A0/NBS0
A1/NBS2
A17/BA1
NCS0/CFRNW
NCS3/NANDCS
NRD/CFOE
NCS1/SDCS
NCS2/CFCS1
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NBS3/CFIOW
SDCKE
RAS
CAS
SDWE
NCS4/CFCS0
NCS5/CFCE1
NCS6/CFCE2
NCS7
NANDOE
NANDWE
NWAIT
SDA10
PIO
ECC
Controller A22/REG/NANDCLE
A21/NANDALE
SDCK
137
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.3 I/O Lines Description
Table 21-1. I/O Lines Description
Name Function Type Active Level
EBI
D[31:0] Data Bus I/O
A[22:0] Address Bus Output
NWAIT External Wait Signal Input Low
SMC
NCS[7:0] Chip Select Lines Output Low
NWR[1:0] Write Signals Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NUB NUB: Upper Byte Select Output Low
NLB NLB: Lower Byte Select Output Low
EBI for CompactFlash Support
CFCE[2:1] CompactFlash Chip Enable Output Low
CFOE CompactFlash Output Enable Output Low
CFWE CompactFlash Write Enable Output Low
CFIOR CompactFl ash I/O Read Signal Output Low
CFIOW CompactFlash I/O Write Signal Output Low
CFRNW CompactFlash Read Not Write Signal Output
CFCS[1:0] CompactFlash Chip Select Lines Output Low
EBI for NAND Flash Support
NANDCS NAND Flash Chip Select Line Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
NANDCLE NAND Flash Command Line Enable Output Low
NANDALE NAND Flash Address Line Enable Output Low
SDRAM Controller
SDCK SDRAM Clock Output
SDCKE SDRAM Clo ck Enable Output High
SDCS SDRAM Controller Chip Select Line Output Low
BA[1:0] Bank Select Output
SDWE SDRAM Write Enable Output Low
RAS - CAS Row and Column Signal Output Low
NBS[3:0] Byte Mask Signals Output Low
SDA10 SDRAM Address 10 Line Output
138 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The connection of some signals through the Mux logic is not direct and depends on the Memory
Controller in use at the moment.
Table 21-2 details th e connections between the two Memory Controllers and the EBI pins.
21.4 Application Example
21.4.1 Hardware Interface
Table 21-3 details the connections to be applied between the EBI pins and the external devices
for each Memory Controller
Table 21-2. EBI Pins and Memory Controllers I/O Lines Connections
EBI Pins SDRAMC I/O Lines SMC I/O Lines
NWR1/NBS1/CFIOR NBS1 NWR1/NUB
A0/NBS0 Not Supported A0/NLB
A1/NBS2 Not Supported A1
A[11:2] A[9:0] A[11:2]
SDA10 A10 Not Supported
A12 Not Supported A12
A[14:13] A[12:11] A[14:13]
A[22:15] Not Supported A[22:15]
D[31:16] D[31:16] Not Supported
D[15:0] D[15:0] D[15:0]
Table 21-3. EBI Pins and External Static Device Connections
Pin
Pins of the Interfaced Device
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit
Static
Device SDRAM(1) CompactFlash CompactFlash
True IDE Mode NAND
Flash(2)
Controller SMC SDRAMC SMC
D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 I/O0 - I/O7
D8 - D15 – D8 - D15 D8 - D15 D8 - D15 D8 - 15 D8 - 15 I/O8 - I/O15(3)
D16 - D31 – – – D16 - D31 – – –
A0/NBS0 A0 – NLB DQM0 A0 A0 –
A1/NBS2 A1 A0 A0 DQM2 A1 A1 –
A2 - A9 A2 - A9 A1 - A8 A1 - A8 A0 - A7 A2 - A9 A2 - A9 –
A10 A10 A9 A9 A8 A10 A10 –
A11 A11 A10 A10 A9 – – –
SDA10 – – – A10 – – –
A12 A12 A11 A11 – – – –
A13 - A14 A13 - A14 A12 - A13 A12 - A13 A11 - A12 – – –
A15 A15 A14 A14 – – – –
A16/BA0 A16 A15 A15 BA0 – – –
A17/BA1 A17 A16 A16 BA1 – – –
139
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Notes: 1. For SDRAM connection examples, refer to “Using SDRAM on AT91SAM7SE Microcontrolle rs”, application note.
2. For NAND Flash connection examples, refer to “NAND Flash Support on AT91SAM7SE Microcontrollers”, application note.
3. I/O8 - I/O15 bits used only for 16-bit NAND Flash.
4. Not directly connected to the CompactFlash slot. P ermits the control of the bidirectional buff er between the EBI data bus and
the CompactFlash slot.
5. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
6. Any free PIO line.
7. CE connection depends on the Nand Flash.
For standard Nand Flash devices, it must be connected to any free PIO line.
For “CE don’t care” 8-bit Nand Flash devices, it can be either connected to NCS3/NANDC S or to any free PIO line.
F or “CE don’t care” 16-bit Nand Flash devices, it must be connected to any free PIO line.
A18 - A20 A18 - A20 A17 - A19 A17 - A19 – – – –
A21/NANDALE A21 A20 A20 – – – ALE
A22/REG/NANDCLE A22 A21 A21 – REG – CLE
NCS0 CS CS CS – CFRNW(4) CFRNW(4) –
NCS1/SDCS CS CS CS CS – – –
NCS2/CFCS1 CS CS CS – CFCS1(4) CFCS1(4) –
NCS3/NANDCS CS CS CS – – – CE(7)
NCS4/CFCS0 CS CS CS – CFCS0(4) CFCS0(4) –
NCS5/CFCE1 CS CS CS – CE1 CS0 –
NCS6/CFCE2 CS CS CS – CE2 CS1 –
NCS7 CS CS CS – – – –
NANDOE – – – – – – RE
NANDWE – – – – – – WE
NRD/CFOE OE OE OE – OE –
NWR0/NWE/CFWE WE WE(5) WE – WE – (8)
NWR1/NBS1/CFIOR WE WE(5) NUB DQM1 IOR IOR –
NBS3/CFIOW – – – DQM3 IOW IOW –
SDCK – – – CLK – – –
SDCKE – – – CKE – – –
RAS – – – RAS – – –
CAS – – – CAS – – –
SDWE – – – WE – – –
NWAIT – – – – WAIT WAIT –
Pxx(6) – – – – CD1 or CD2 CD1 or CD2 –
Pxx(6) –––– – – CE
(7)
Pxx(6) –––– – – RDY
Table 21-3. EBI Pins and External Static Device Connections (Continued)
Pin
Pins of the Interfaced Device
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit
Static
Device SDRAM(1) CompactFlash CompactFlash
True IDE Mode NAND
Flash(2)
Controller SMC SDRAMC SMC
140 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
8. When the NAND Flash Logic is used, NWR0/NWE/CFWE must be kept as PIO Input Mode with Pull-up enabled (default
state after reset) or as PIO Output set at logic level 1. The PIO cannot be used in PIO Mode.
21.4.2 Connection Examples
Figure 21-2 shows an example of connections between the EBI and external devices.
Figure 21-2. EBI Connections to Memory Devices
EBI
D0-D31
A2-A15
RAS
CAS
SDCK
SDCKE
SDWE
A0/NBS0
2M x 8
SDRAM
D0-D7
A0-A9, A11
RAS
CAS
CLK
CKE
WE
DQM
CS
BA0
BA1
NWR1/NBS1
A1/NBS2
NBS3
NCS1/SDCS
D0-D7 D8-D15
A16/BA0
A17/BA1
A18-A22
A10
SDA10
SDA10
A2-A11, A13
NCS0
NCS2
NCS3
NCS4
NCS5
NCS6
NCS7
A16/BA0
A17/BA1
2M x 8
SDRAM
D0-D7
A0-A9, A11
RAS
CAS
CLK
CKE
WE
DQM
CS
BA0
BA1
A10 SDA10
A2-A11, A13
A16/BA0
A17/BA1
2M x 8
SDRAM
D0-D7
A0-A9, A11
RAS
CAS
CLK
CKE
WE
DQM
CS
BA0
BA1
D16-D23 D24-D31
A10 SDA10
A2-A11, A13
A16/BA0
A17/BA1
2M x 8
SDRAM
D0-D7
A0-A9, A11
RAS
CAS
CLK
CKE
WE
DQM
CS
BA0
BA1
A10 SDA10
A2-A11, A13
A16/BA0
A17/BA1
NBS0 NBS1
NBS3
NBS2
NRD
NWR0/NWE
128K x 8
SRAM 128K x 8
SRAM
D0-D7 D0-D7
A0-A16 A0-A16
A1-A17 A1-A17
CS CS
OE
WE
D0-D7 D8-D15
OE
WE
NRD/NOE
A0/NWR0/NBS0 NRD/NOE
NWR1/NBS1
SDWE
SDWE
SDWE
SDWE
141
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.5 Product Dependencies
21.5.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica-
tion, they can be used for other purposes by the PIO Controller.
21.6 Functional Description
The EBI transfers data between the internal ASB Bus (handled by the Memory Controller) and
the external memories or peripheral devices. It controls the waveforms and the parameters of
the external address, data and control busses and is composed of the following elements:
• The Static Memory Controller (SMC)
• The SDRAM Controller (SDRAMC)
• The ECC Controller (ECC)
• A chip select assign m en t feature that assigns an ASB add re ss space to the external devices
• A multiplex controller circuit that shares the pins between the different Memory Controllers
• Programmable CompactFlash support logic
• Programmable NAND Flash support logic
21.6.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address
lines of up to 23 bits and the cont rol signals through a multiplex logic opera ting in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output contro l lines at a st ab le stat e wh ile n o ex ternal access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAM Controller without
delaying the other external Memory Controller accesses.
21.6.2 Static Memory Controller
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
21.6.3 SDRAM Controller
For information on the SDRAM Controller, refer to the SDRAMC Section.
21.6.4 ECC ControllerFor information on the ECC Controller, refer to the ECCC Section.
21.6.5 CompactFlash Support
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or
NCS2 address space. Progr amming the CS4A and/or CS2A bit of the Chip Select Assignment
Register (See “EBI Chip Select Assignment Register” on page 158.) to the appropriate value
enables this logic. Access to an external CompactFlash device is then made by accessing the
142 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
address space r eserved to NCS4 and/or NCS2 (i.e., between 0x50 00 0000 and 0x5FFF FF FF
for NCS4 and between 0x3000 0000 and 0x3FFF FFFF for NCS2).
When multiplexed with CFCE1 and CFCE2 signals, the NCS5 and NCS6 signals become
unavailable. Performing an access within the address space reserved to NCS5 and NCS6 (i.e.,
between 0x6000 0000 and 0x7FFF FFFF) may lead to an unpredictable ou tcome.
All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup-
ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are
not handled.
21.6.5.1 I/O Mode, Common Memory Mode, Attribute Memory and True IDE Mode
Within the NCS4 and /or NCS2 addre ss space, the curren t transf er address is use d to distingu ish
I/O mode, common memory mode, attribute memory mode and True IDE mode.
The different modes are accessed through a specific memory mapping as illustrated in Figure
21-3.
Figure 21-3. CompactFlash Memory Mapping
Note: The A22 pin of the EBI is used to drive the REG signal of the CompactFlash Device (except in
True IDE mode).
21.6.5.2 CFCE1 and CFCE2 signals
To cover all types of access, the SMC must be alternatively set to drive the 8-bit data bus or 16-
bit data bus. The o dd byte access on t he D[7:0] bus is only possible when the SMC is co nfigured
to drive 8-bit memory devices on the corresponding NCS pin (NCS4 and/or NCS2). The DBW
field in the corresponding Chip Select Register of the NCS4 and/or NCS2 address space must
be set as shown in Table 21-4 to enable the required access type.
NUB and NLB ar e the byte selectio n sig nals from SMC a nd are available when th e SMC is set in
Byte Select mode on the corresponding Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For
details on these waveforms and timings, refer to the Static Memory Controller Section.
CF Address Space
Attribute Memory Mode Space
Common Memory Mode Space
I/O Mode Space
True IDE Mode Space
True IDE Alternate Mode Space
Offset 0x00E0 0000
Offset 0x00C0 0000
Offset 0x0080 0000
Offset 0x0040 0000
Offset 0x0000 0000
143
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.6.5.3 Read/Write Signals
In I/O mode and True IDE mode, the Com pactFlash logic drives the read and write comma nd
signals of the SMC on CF IOR and CFIO W signals, wh ile the CFOE and CFWE signals are d eac-
tivated. Likewise, in com mon memory mode and at tribute memory mode, th e SMC signals are
driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. Figure
21-4 on page 144 shows a schematic representation of this logic and Table 21-5 on page 144
presents the signal decoding.
Attribute memory mode, common memory mode and I/O mode are supported by setting the
address setup and hold time on the NCS4 (and/or NCS2) chip select to the appropriate values.
For details on these signal waveforms, please refer to the section: Setup and Hold Cycles of the
Static Memory Controller Section.
Table 21-4. CFCE1 and CFCE2 Truth Table
Mode CFCE2 CFCE1 DBW Comment SMC Access Mode
Attribute Memory NUB NLB 16 bits Access to Even Byte on D[7:0] Byte Select
Common Memory NUB NLB 16bits Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8] Byte Select
1 0 8 bits Access to Odd Byte on D[7:0] Don’t Care
I/O Mode NUB NLB 16 bits Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8] Byte Select
1 0 8 bits Access to Odd Byte on D[7:0] Don’t Care
True IDE Mode
Task File 1 0 8 bits Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0] Don’t Care
Data Register 1 0 16 bits Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8] Byte Select
Alternate True IDE Mode
Control Register
Alter nate Status Read 01
Don’t
Care Access to Even Byte on D[7:0] Don’t Care
Drive Address 0 1 8 bits Access to Odd Byte on D[7:0] Don’t Care
Standb y Mo de or
Address Space is not
assigned to CF 11
Don’t
Care Don’t Care Don’t Care
144 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 21-4. CompactFlash Read/Write Control Signals
21.6.5.4 Multiplexing of CompactFlash Signals on EBI Pins
Table 21-6 and Tabl e 21-7 on page 145 describe the multiple xing of the Com pactFlash logic sig-
nals with other EBI signals on the EBI pi ns. The EBI pins in Table 21-6 are strictly dedicated to
the CompactFlash interface as soon as the CS4A and/or CS2A field of the Chip Select Assign-
ment Register is set (See “EBI Chip Select Assignment Register” on page 158.). These pins
must not be used to drive any other memory devices.
The EBI pins in Table 21-7 remain shared between all memory areas when the corresponding
CompactFlash interface is e nabled (CS4A = 1 and/or CS2A = 1).
SMC
NRD
NWR0_NWE
A22
CFIOR
CFIOW
CFOE
CFWE
1
1
CompactFlash Logic
External Bus Interface
1
1
1
0
A21
1
0
1
0
1
0
Table 21-5. CompactFlash Mode Selection
Mode Base Address CFOE CFWE CFIOR CFIOW
Attribute Memory
Common Memory NRD NWR0_NWE 1 1
I/O Mode 1 1 NRD NWR0_NWE
True ID E Mode 0 1 NRD NWR0_NWE
Table 21-6. Dedicated CompactFlash Interface Multiplexing
Pins
CompactFlash Signals EBI Signals
CS4A = 1 CS2A = 1 CS4A = 0 CS2A = 0
NCS4/CFCS0 CFCS0 NCS4
NCS2/CFCS1 CFCS1 NCS2
145
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.6.5.5 Application Example
Figure 21 -5 on page 145 illustrates an example of a CompactFlash application. CFCS0 and
CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc-
tion and the output enable of the buffers between the EBI and the CompactFlash Device. The
timing of the CFCS0 signal is identical to the NCS4 signal. Moreover, the CFRNW signal
remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT sig-
nal is connected to the NWAIT input of the Static Memory Controller. For details on these
waveforms and tim i ngs, refer to the Static Memo ry Con tr olle r Section.
Figure 21-5. CompactFlash Application Example
Table 21-7. Shared CompactFlash Interface Multiplexing
Pins
Access to CompactFlash Device Access to Other EBI Devices
CompactFlash Signals EBI Signals
NRD/CFOE CFOE NRD
NWR0/NWE/CFWE CFWE NWR0/NWE
NWR1/NBS1/CFIOR CFIOR NWR1/NBS1
NBS3/CFIOW CFIOW NBS3
NCS0/CFRNW CFRNW NCS0
D[15:0]
/OEDIR
_CD1
_CD2
/OE
D[15:0]
NCS0/CFRNW
NCS4/CFCS0
CD (PIO)
A[10:0]
A22/REG
NRD/CFOE
A[10:0]
_REG
_OE
_WE
_IORD
_IOWR
_CE1
_CE2
NWE/CFWE
NWR1/CFIOR
CFIOW
NCS5/CFCE1
NCS6/CFCE2
_WAIT
NWAIT
146 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.6.6 NAND Flash Support
The EBI integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space.
Programming the CS3A field in the Chip Select Assignment Register to the appropriate valu e
enables the NAND Flash logic (See “EBI Chip Select Assignment Register” on page 158.).
Access to an external NAND Flash device is then made by accessing the address space
reserved to NCS3 (i.e., between 0x4000 0000 an d 0x4FFF FFFF).
The NAND Flash Logic drives the r ead and write co mma nd signa ls of the SMC on the NANDOE
and NANDWE signals when the NCS3 signal is active. NANDOE and N ANDWE are invalidated
as soon as the transfer address fails to lie in the NCS3 address space. For details on these
waveforms, refer to the Static Memory Controller Section.
Figure 21-6. NAND Flash Signal Multiplexing on EBI Pins
(1) When the NAND Flash Logic is used, NWR0/NWE/CFWE must be kept as PIO Input Mode with Pull-up
enabled (default state after reset) or as PIO Output set at logic level 1. The PIO cannot be used in PIO
Mode.
The address latch enable and command latch enable signals on the NAND Flash device are
driven respectively by address bits A21 and A22 of the EBI address bus. The command,
address or data words on the data bus of the NAND Flash device are distinguished by using
their address withi n the NCS3 addre ss spa ce. The chip ena ble (CE) signal o f the d evice and t he
ready/busy (R/B) signa ls are connected to PIO lines. The CE signal the n remain s asser ted even
when NCS3 is not selected, preventing the device from returning to standby mode.
SMC
NRD
NWR0_NWE(1)
NANDOE
NANDWE
NAND Flash Logic
NCS3
MUX Logic
CS3A
NANDWE
NANDOE
CS3A
147
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 21-7. NAND Flash Application Example
Note: The External Bus Interface is also able to support 16-bit devices.
D[7:0]
CLE
NANDWE
NANDOE NOE
NWE
A22/REG/NANDCLE
ALE
AD[7:0]
PIO R/B
EBI
CE
NAND Flash
PIO
NCS3/NANDCS Not Connected
A21/NANDALE
148 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.7 Implementation Examples
21.7.1 16-bit SDRAM
21.7.1.1 Hardware Configuratio n
21.7.1.2 Software Configuration
The following configuration must be respected:
• Address lines A[0..11], A[13-14], BA0, BA1, SDA10, SDCS_NCS1, SDWE, SDCKE, NBS1,
RAS, CAS, and data lines D[8. .15 ] ar e multiplexed with PIO lines and thus dedicated PIOs
must be programmed in peripheral mode in the PIO controller.
• Assign the EBI CS1 to the SDRAM cont roller by setting the bit EBI_CS1A in the EBI Chip
Select Assignment Register.
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The data bus width is to be programmed to 16 bits.
The SDRAM initialization sequence is described in the “SDRAM D evice Initialization” section of
the SDRAM Controller.
D13
D12
D8
D7
D3
D11
D2
D14
D4
D0
RAS
D1
D10
CAS
SDA10
SDCK
D9
SDWE
SDCKE
D5
D15
D6
A4
A9
A14
A5
A2
A6
A3
BA0
A10
A13
A8
BA1
A7
A11
A0
RAS
CAS
SDA10
SDWE
SDCKE
SDCK
CFIOR_NBS1_NWR1
SDCS_NCS1
BA0
BA1
D[0..15]
A[0..14]
3V3
256 Mbits
(Not used A12)
TSOP54 PACKAGE
C1 100NFC1 100NF
C7 100NFC7 100NF
C2 100NFC2 100NF
MT48LC16M16A2
U1
MT48LC16M16A2
U1
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A10
22
BA0
20
A12
36
DQ0 2
DQ1 4
DQ2 5
DQ3 7
DQ4 8
DQ5 10
DQ6 11
DQ7 13
DQ8 42
DQ9 44
DQ10 45
DQ11 47
DQ12 48
DQ13 50
DQ14 51
DQ15 53
VDD 1
VSS 28
VSS 41
VDDQ 3
VDD 27
N.C
40
CLK
38
CKE
37
DQML
15
DQMH
39
CAS
17
RAS
18
WE
16
CS
19
VDDQ 9
VDDQ 43
VDDQ 49
VSSQ 6
VSSQ 12
VSSQ 46
VSSQ 52
VDD 14
VSS 54
A11
35
BA1
21
C3 100NFC3 100NF
C4 100NFC4 100NF
C5 100NFC5 100NF
C6 100NFC6 100NF
149
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.7.2 32-bit SDRAM
21.7.2.1 Hardware Configuratio n
21.7.2.2 Software Configuration
The following configuration must be respected:
• Address lines A[0..11], A[13-14], BA0, BA1, SDA10, SDCS_NCS1, SDWE, SDCKE, NBS1,
RAS, CAS, and data lines D[8. .31 ] ar e multiplexed with PIO lines and thus dedicated PIOs
must be programmed in peripheral mode in the PIO controller.
• Assign the EBI CS1 to the SDRAM cont roller by setting the bit EBI_CS1A in the EBI Chip
Select Assignment Register located in the bus matrix memory space.
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
The data bus width is to be programmed to 32 bits.
The SDRAM initialization sequence is described in the “SDRAM D evice Initialization” section of
the SDRAM Controller.
CAS
SDCKE
SDCK
RAS
SDWE
SDA10
D13
D18
D12
D22
D8
D7
D3
D28
D11
D26
D21
D2
D14
D4
D24
D0
D23
RAS
D27
D1
D19
D10
D31
D17
CAS
SDA10
D25
D29
D16
SDCK
D9
D20
SDWE
SDCKE
D5
D30
D15
D6
A5
BA0
A2
A11
A7
A4
A9
A14
A8
A1
A5
A2
BA1
A13
A6
A3A3
A10
BA0
A10
A13
A8
BA1
A6
A4
A14
A9
A7
A11
A0
RAS
CAS
SDA10
SDWE
SDCKE
SDCK
CFIOW_NBS3_NWR3CFIOR_NBS1_NWR1
SDCS_NCS1
BA0
BA1
D[0..31]
A[0..14]
3V33V3
256 Mbits 256 Mbits
(Not used A12)
TSOP54 PACKAGE
C11 100NFC11 100NF
C9 100NFC9 100NF
C1 100NFC1 100NF
C12 100NFC12 100NF
MT48LC16M16A2
U2
MT48LC16M16A2
U2
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A10
22
BA0
20
A12
36
DQ0 2
DQ1 4
DQ2 5
DQ3 7
DQ4 8
DQ5 10
DQ6 11
DQ7 13
DQ8 42
DQ9 44
DQ10 45
DQ11 47
DQ12 48
DQ13 50
DQ14 51
DQ15 53
VDD 1
VSS 28
VSS 41
VDDQ 3
VDD 27
N.C
40
CLK
38
CKE
37
DQML
15
DQMH
39
CAS
17
RAS
18
WE
16
CS
19
VDDQ 9
VDDQ 43
VDDQ 49
VSSQ 6
VSSQ 12
VSSQ 46
VSSQ 52
VDD 14
VSS 54
A11
35
BA1
21
C7 100NFC7 100NF
C13 100NFC13 100NF
C8 100NFC8 100NF
C14 100NFC14 100NF
MT48LC16M16A2
U1
MT48LC16M16A2
U1
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A10
22
BA0
20
A12
36
DQ0 2
DQ1 4
DQ2 5
DQ3 7
DQ4 8
DQ5 10
DQ6 11
DQ7 13
DQ8 42
DQ9 44
DQ10 45
DQ11 47
DQ12 48
DQ13 50
DQ14 51
DQ15 53
VDD 1
VSS 28
VSS 41
VDDQ 3
VDD 27
N.C
40
CLK
38
CKE
37
DQML
15
DQMH
39
CAS
17
RAS
18
WE
16
CS
19
VDDQ 9
VDDQ 43
VDDQ 49
VSSQ 6
VSSQ 12
VSSQ 46
VSSQ 52
VDD 14
VSS 54
A11
35
BA1
21
C2 100NFC2 100NF
C3 100NFC3 100NF
C4 100NFC4 100NF
C5 100NFC5 100NF
C6 100NFC6 100NF
C10 100NFC10 100NF
150 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.7.3 8-bit NAND Flash
21.7.3.1 Hardware Configuratio n
21.7.3.2 Software Configuration
The following configuration must be respected:
• CLE, ALE, NANDOE and NANDWE signals are multiplexed with PIO lines and thus the
dedicated PIOs must be programmed in peripheral mode in the PIO controller.
• Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select
Assignment Register.
• Reserve A21/A22 for ALE/CLE functions. Address an d Command Latches are controlled
respectively by setting to 1 the address bit A21 and A22 during accesses.
• Configure a PIO line as an input to manage the Ready/Busy signal.
• Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND
Flash timings, the data bus width and the system bus frequency.
D6
D0
D3
D4
D2
D1
D5
D7
NANDOE
NANDWE
(ANY PIO)
(ANY PIO)
ALE
CLE
D[0..7]
3V3
3V3
2 Gb
TSOP48 PACKAGE
U1 K9F2G08U0MU1 K9F2G08U0M
WE
18
N.C
6
VCC 37
CE
9
RE
8
N.C
20
WP
19
N.C
5
N.C
1
N.C
2
N.C
3
N.C
4
N.C
21
N.C
22
N.C
23
N.C
24
R/B
7
N.C
26
N.C 27
N.C 28
I/O0 29
N.C 34
N.C 35
VSS 36
PRE 38
N.C 39
VCC 12
VSS 13
ALE
17
N.C
11 N.C
10
N.C
14
N.C
15
CLE
16
N.C
25
N.C 33
I/O1 30
I/O3 32
I/O2 31
N.C 47
N.C 46
N.C 45
I/O7 44
I/O6 43
I/O5 42
I/O4 41
N.C 40
N.C 48
R2 10KR2 10K
C2
100NF
C2
100NF
R1 10K
R1 10K
C1
100NF
C1
100NF
151
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.7.4 16-bit NAND Flash
21.7.4.1 Hardware Configuratio n
21.7.4.2 Software Configuration
The software configuration is the same as for an 8-bit NAND Flash except the data bus width
programmed in t he mode reg ister of the Static Memo ry Controller an d the se lection of D[ 8..15] in
the PIO controller.
D6
D0
D3
D4
D2
D1
D5
D7
D14
D8
D11
D12
D10
D9
D13
D15
NANDOE
NANDWE
(ANY PIO)
ALE
CLE
D[0..15]
(ANY PIO)
3V3
3V3
2 Gb
TSOP48 PACKAGE
R1 10K
R1 10K
R2 10KR2 10K
C2
100NF
C2
100NF
C1
100NF
C1
100NF
U1 MT29F2G16AABWP-ETU1 MT29F2G16AABWP-ET
WE
18
N.C
6
VCC 37
CE
9
RE
8
N.C
20
WP
19
N.C
5
N.C
1
N.C
2
N.C
3
N.C
4
N.C
21
N.C
22
N.C
23
N.C
24
R/B
7
I/O0 26
I/O8 27
I/O1 28
I/O9 29
N.C
34
N.C
35
N.C 36
PRE 38
N.C 39
VCC 12
VSS 13
ALE
17
N.C
11 N.C
10
N.C
14
N.C
15
CLE
16
VSS 25
I/O11 33
I/O2 30
I/O3 32
I/O10 31
I/O15 47
I/O7 46
I/O14 45
I/O6 44
I/O13 43
I/O5 42
I/O12 41
I/O4 40
VSS 48
152 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.7.5 NOR Flash on NCS0
21.7.5.1 Hardware Configuratio n
21.7.5.2 Software Configuration
• Address lines A[1..22], NCS0, NRD, NWE and data lines D[8..15] are multiplexed with PIO
lines and thus dedicated PIOs must be programmed in peripheral mode in t he PIO controller.
The default configura tion for the Static Memory Controller, byte select mod e, 16-bit data bus,
Read/Write controlled by Chip Select, allows access on 16-bit non-volatile memory at slow
clock.
For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and
Mode depending on Flash timings and system bus fre quency.
A21
A22
A1
A2
A3
A4
A5
A6
A7
A8
A15
A9
A12
A13
A11
A10
A14
A16
D6
D0
D3
D4
D2
D1
D5
D7
D14
D8
D11
D12
D10
D9
D13
D15
A17
A20
A18
A19
D[0..15]
A[1..22]
NRST
NWE
NCS0
NRD
3V3
3V3
TSOP48 PACKAGE
C2
100NF
C2
100NF
C1
100NF
C1
100NF
AT49BV6416
U1
AT49BV6416
U1
A0
25
A1
24
A2
23
A3
22
A4
21
A5
20
A6
19
A7
18
A8
8
A9
7
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
48
A17
17
A18
16
A21
9A20
10 A19
15
WE
11 RESET
12
WP
14
OE
28 CE
26 VPP
13
DQ0 29
DQ1 31
DQ2 33
DQ3 35
DQ4 38
DQ5 40
DQ6 42
DQ7 44
DQ8 30
DQ9 32
DQ10 34
DQ11 36
DQ12 39
DQ13 41
DQ14 43
DQ15 45
VCCQ 47
VSS 27
VSS 46
VCC 37
153
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.7.6 CompactFlash
21.7.6.1 Hardware Configuration
D15
D14
D13
D12
D10
D11
D9
D8
D7
D6
D5
D4
D2
D1
D0
D3
A10
A9
A8
A7
A3
A4
A5
A6
A0
A2
A1
CD1
CD2
CD2
CD1
WE
OE
IOWR
IORD
CE2
CE1
REG
WAIT#
RESET
CF_D3
CF_D2
CF_D1
CF_D0
CF_D7
CF_D6
CF_D5
CF_D4
CF_D11
CF_D10
CF_D9
CF_D8
CF_D15
CF_D14
CF_D13
CF_D12
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
REG
WE
OE
IOWR
IORD
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
CF_D4
CF_D13
CF_D15
CF_D14
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
CF_D7
CF_D6
CF_D5
CF_D3
CF_D2
CF_D1
CF_D0
CE2
CE1
RESET
RDY/BSY
RDY/BSY
WAIT#
CFWE
(ANY PIO)
CFRNW
D[0..15]
A[0..10]
CFCSx
A22/REG
CFOE
CFIOW
CFIOR
NWAIT
(ANY PIO)
CFCE2
CFCE1
(ANY PIO)
3V3
3V3
3V3
3V3
3V3
3V3
CARD DETECT
CFIRQ
CFRST
MEMORY & I/O MODE
(CFCS0 or CFCS1)
MN2A
SN74ALVC32
MN2A
SN74ALVC32
31
2
C2
100NF
C2
100NF
MN1D
74ALVCH32245
MN1D
74ALVCH32245
4DIR
T3 4OE
T4
4A1
N5 4A2
N6 4A3
P5 4A4
P6 4A5
R5 4A6
R6 4A7
T6 4A8
T5
4B1 N2
4B2 N1
4B3 P2
4B4 P1
4B5 R2
4B6 R1
4B7 T1
4B8 T2
MN1C
74ALVCH32245
MN1C
74ALVCH32245
3DIR
J3 3OE
J4
3A1
J5 3A2
J6 3A3
K5 3A4
K6 3A5
L5 3A6
L6 3A7
M5 3A8
M6
3B1 J2
3B2 J1
3B3 K2
3B4 K1
3B5 L2
3B6 L1
3B7 M2
3B8 M1
R2
47K
R2
47K
MN3B
SN74ALVC125
MN3B
SN74ALVC125
6
4
5
R147K
R147K
MN1B
74ALVCH32245
MN1B
74ALVCH32245
2DIR
H3 2OE
H4
2A1 E5
2A2 E6
2A3 F5
2A4 F6
2A5 G5
2A6 G6
2A7 H5
2A8 H6
2B1
E2 2B2
E1 2B3
F2 2B4
F1 2B5
G2 2B6
G1 2B7
H2 2B8
H1
VCC
GND
MN4
SN74LVC1G125-Q1
VCC
GND
MN4
SN74LVC1G125-Q1
5 1
2
3
4
MN3A
SN74ALVC125
MN3A
SN74ALVC125
3
1
2
R3
10K
R3
10K
MN2B
SN74ALVC32
MN2B
SN74ALVC32
6
4
5
MN3C
SN74ALVC125
MN3C
SN74ALVC125
89
10
R4
10K
R4
10K
C1
100NF
C1
100NF
J1
N7E50-7516VY-20
J1
N7E50-7516VY-20
GND 1
D3
2D4
3D5
4D6
5D7
6
CE1#
7
A10
8
OE#
9
A9
10 A8
11 A7
12
VCC 13
A6
14 A5
15 A4
16 A3
17 A2
18 A1
19 A0
20
D0
21 D1
22 D2
23
WP
24
CD2#
25 CD1#
26
D11
27 D12
28 D13
29 D14
30 D15
31
CE2#
32
VS1# 33
IORD#
34 IOWR#
35
WE#
36
RDY/BSY 37
VCC 38
CSEL# 39
VS2# 40
RESET
41
WAIT#
42
INPACK# 43
REG#
44
BVD2 45
BVD1 46
D8
47 D9
48 D10
49 GND 50
MN1A
74ALVCH32245
MN1A
74ALVCH32245
1A1 A5
1A2 A6
1A3 B5
1A4 B6
1A5 C5
1A6 C6
1A7 D5
1A8 D6
1DIR
A3 1OE
A4
1B1
A2 1B2
A1 1B3
B2 1B4
B1 1B5
C2 1B6
C1 1B7
D2 1B8
D1
MN3D
SN74ALVC125
MN3D
SN74ALVC125
11 12
13
154 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.7.6.2 Software Configuration
The following configuration must be respected:
• Assign the EBI CS4 and /o r EBI_CS5 to t he Com pact Flash Slot 0 and/ or Slot 1 by setting t he
bit EBI_CS4A and/or EBI_CS5A in the EBI Chip Select Assignment Register.
• Select the mode by using the corresponding address (refer to Figure 21.3).
• Address lines A[0..1 0], A22, CFWE, CFOE, CFIOW, CFIOR, NWAIT, CFRNW, CFS0,
CFCS1, CFCE1, CFCE2 and data lines D[8..15] are multiplexed with PIO line s an d th us the
dedicated PIOs must be programmed in peripheral mode in the PIO Controller.
• Configure a PIO line as an output f or CFRST and two others as an input for CFIRQ and
CARD DETECT functions respectively.
• Configure SMC CS4 and/or SMC_CS5 (f or Slot 0 or 1) Setup, Pulse, Cycle and Mode
accordingly to CompactFlash timings and system bus frequency.
155
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.7.7 CompactFlash True IDE
21.7.7.1 Hardware Configuratio n
D15
D14
D13
D12
D10
D11
D9
D8
D7
D6
D5
D4
D2
D1
D0
D3
A10
A9
A8
A7
A3
A4
A5
A6
A0
A2
A1
CD1
CD2
CF_D3
CF_D2
CF_D1
CF_D0
CF_D7
CF_D6
CF_D5
CF_D4
CF_D11
CF_D10
CF_D9
CF_D8
CF_D15
CF_D14
CF_D13
CF_D12
RESET#
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
CD2
CD1
IOWR
IORD
CE2
CE1
REG
WE
OE
IOWR
IORD
IORDY
CF_A0
CF_A2
CF_A1
CF_D4
CF_D13
CF_D15
CF_D14
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
CF_D7
CF_D6
CF_D5
CF_D3
CF_D2
CF_D1
CF_D0
CE2
CE1
RESET#
INTRQ
IORDY
INTRQ
CFWE
(ANY PIO)
CFRNW
D[0..15]
A[0..10]
CFCSx
A22/REG
CFOE
CFIOW
CFIOR
NWAIT
(ANY PIO)
CFCE2
CFCE1
(ANY PIO)
3V3
3V3
3V3
3V3
3V3
3V3
3V3
CARD DETECT
CFIRQ
CFRST
TRUE IDE MODE
(CFCS0 or CFCS1)
C2
100NF
C2
100NF
MN1D
74ALVCH32245
MN1D
74ALVCH32245
4DIR
T3 4OE
T4
4A1
N5 4A2
N6 4A3
P5 4A4
P6 4A5
R5 4A6
R6 4A7
T6 4A8
T5
4B1 N2
4B2 N1
4B3 P2
4B4 P1
4B5 R2
4B6 R1
4B7 T1
4B8 T2
VCC
GND
MN4
SN74LVC1G125-Q1
VCC
GND
MN4
SN74LVC1G125-Q1
5 1
2
3
4
MN3C
SN74ALVC125
MN3C
SN74ALVC125
89
10
R4
10K
R4
10K
MN1C
74ALVCH32245
MN1C
74ALVCH32245
3DIR
J3 3OE
J4
3A1
J5 3A2
J6 3A3
K5 3A4
K6 3A5
L5 3A6
L6 3A7
M5 3A8
M6
3B1 J2
3B2 J1
3B3 K2
3B4 K1
3B5 L2
3B6 L1
3B7 M2
3B8 M1
R3
10K
R3
10K
J1
N7E50-7516VY-20
J1
N7E50-7516VY-20
GND 1
D3
2D4
3D5
4D6
5D7
6
CS0#
7
A10
8
ATA SEL #
9
A9
10 A8
11 A7
12
VCC 13
A6
14 A5
15 A4
16 A3
17 A2
18 A1
19 A0
20
D0
21 D1
22 D2
23
IOIS16#
24
CD2#
25 CD1#
26
D11
27 D12
28 D13
29 D14
30 D15
31
CS1#
32
VS1# 33
IORD#
34 IOWR#
35
WE#
36
INTRQ 37
VCC 38
CSEL# 39
VS2# 40
RESET#
41
IORDY
42
INPACK# 43
REG#
44
DASP# 45
PDIAG# 46
D8
47 D9
48 D10
49 GND 50
MN1A
74ALVCH32245
MN1A
74ALVCH32245
1A1 A5
1A2 A6
1A3 B5
1A4 B6
1A5 C5
1A6 C6
1A7 D5
1A8 D6
1DIR
A3 1OE
A4
1B1
A2 1B2
A1 1B3
B2 1B4
B1 1B5
C2 1B6
C1 1B7
D2 1B8
D1
MN1B
74ALVCH32245
MN1B
74ALVCH32245
2DIR
H3 2OE
H4
2A1 E5
2A2 E6
2A3 F5
2A4 F6
2A5 G5
2A6 G6
2A7 H5
2A8 H6
2B1
E2 2B2
E1 2B3
F2 2B4
F1 2B5
G2 2B6
G1 2B7
H2 2B8
H1
MN2A
SN74ALVC32
MN2A
SN74ALVC32
31
2
C1
100NF
C1
100NF
R2
47K
R2
47K
R147K
R147K
MN3B
SN74ALVC125
MN3B
SN74ALVC125
6
4
5
MN3D
SN74ALVC125
MN3D
SN74ALVC125
11 12
13
MN2B
SN74ALVC32
MN2B
SN74ALVC32
6
4
5
MN3A
SN74ALVC125
MN3A
SN74ALVC125
3
1
2
156 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.7.7.2 Software Configuration
The following configuration must be respected:
• Address lines A[0..1 0], A22, CFWE, CFOE, CFIOW, CFIOR, NWAIT, CFRNW, CFS0,
CFCS1, CFCE1, CFCE2 and data lines D[8..15] are multiplexed with PIO line s an d th us the
dedicated PIOs must be programmed in peripheral mode in the PIO controller.
• Assign the EBI CS4 and/or EBI CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the
bit EBI_CS4A and/or EBI_CS5A in the EBI Chip Select Assignment Register.
• Select the mode by using the corresponding address (refer to Figure 21-3).
• Configure a PIO line as an output f or CFRST and two others as an input for CFIRQ and
CARD DETECT functions respectively.
• Configure SMC CS4 and/or SMC_CS5 (f or Slot 0 or 1) Setup, Pulse, Cycle and Mode
according to CompactFlash timings and system bus frequency.
157
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.8 External Bus Interface (EBI) User Interface
EBI User Interface Base Addr ess: 0xFFFF FF80
Table 21-8. External Bus Interface Me mory Map
Offset Register Name Access Reset State
0x00 Chip Select Assignment Register EBI_CSA Read/Write 0x0
0x04 Reserved –
0x08 Reserved –
0x0C Reserved –
0x10 - 0x2C SMC User Interface Refer to the Static Memory Controller User Interface
0x30 - 0x58 SDRAMC User Interface Refer to the SDRAM Controller User Interface
0x5C - 0x6C ECC User Interface Refer to the Error Code Corrected Controller User interface
0x70 - 0x7C Reserved –
158 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
21.8.1 EBI Chip Select Assignment Register
Name: EBI_CSA
Access: Read/Write
Reset Value: 0x0
Offset: 0x0
Absolute Address : 0xFFFF FF80
• CS1A: Chip Select 1 Assignment
0 = Chip Select 1 is assigned to the Static Memory Controller.
1 = Chip Select 1 is assigned to the SDRAM Controller.
• CS2A: Chip Select 2 Assignment
0 = Chip Select 2 is assig ne d to t he Sta tic Memo ry Contr oller and NCS2, NCS5 and NCS6 be have a s def ined b y the SMC.
1 = Chip Select 2 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
Accessing the address space reserved to NCS5 and NCS6 may lead to an unpredictable outcome.
• CS3A: Chip Select 3 Assignment
0 = Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behave as defined by the SMC.
1 = Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash Logic is activated.
• CS4A: Chip Select 4 Assignment
0 = Chip Select 4 is assig ne d to t he Sta tic Memo ry Contr oller and NCS4, NCS5 and NCS6 be have a s def ined b y the SMC.
1 = Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
Accessing the address space reserved to NCS5 and NCS6 may lead to an unpredictable outcome.
• NWPC: NWAIT Pin Configuration
0 = The NWAIT device pin is not connected to the External Wait Request input of the Static Memory Controller, this multi-
plexed pin can be used as a PIO.
1 = The NWAIT device pin is conn ec te d to th e Exte rn a l Wait Req u es t input of the Sta tic Me m or y Con tr oller.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––NWPC
15 14 13 12 11 10 9 8
––––––––
76543210
– – – CS4A CS3A CS2A CS1A –
159
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
160 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
161
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22. Static Memory Controller (SMC)
22.1 Overview The Static Memory Controller (SMC) generates the signals that control the access to external
static memory or peripheral devices. The SMC is fully programmable. It has eight chip selects
and a 23-bit address bus. The 16-bit dat a bus can be configured to inte rface with 8- or 16-bit
external devices. Separat e read an d writ e contr ol signals a llow for dir ect memory and periphe ra l
interfacing. The SMC supports different access protocols allowing single clock cycle memory
accesses. It also provides an external wait request capability.
22.2 Block Diagram
Figure 22-1. Static Memory Controller Block Diagram
APB
NCS[7:0]
NWR0/NWE
SMC PIO
Controller
NWR1/NUB
NRD
A0/NLB
A[22:1]
D[15:0]
NWAIT
User Interface
PMC MCK
Memory
Controller SMC
Chip Select
162 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.3 I/O Lines Description
22.4 Multiplexed Signals
Table 22-1. I/O Lines Description
Name Description Type Active Level
NCS[7:0] Static Memory Contro ller Chip Select Lines Output Low
NRD Read Signal Output Low
NWR0/NWE Write 0/Write Enable Signal Output Low
NWR1/NUB Write 1/Upp er Byte Select Signal Output Low
A0/NLB Address Bit 0/Lower Byte Select Signal Output Low
A[22:1] Address Bus Output
D[15:0] Data Bus I/O
NWAIT External Wait Signal Input Low
Table 22-2. Static Memory Controller Multiplexed Signals
Multiplexed Signals Related Function
A0 NLB 8-bit or 16-bit data bus, see 22.6.1.3 “Data Bus Width” on page 164.
NWR0 NWE Byte-write or byte-select access, see 22.6.2.1 “Write Access Type” on page 165.
NWR1 NUB Byte-write or byte-select access, see 22.6.2.1 “Write Access Type” on page 165.
163
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.5 Product Dependencies
22.5.1 I/O Lines The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO
lines. The programmer must first program the PIO controller to assign the Static Memory Con-
troller pins to their peripheral function. If I/O lines of the Static Memory Contr oller are not used by
the application, they can be used for other purposes by the PIO Controller.
22.6 Functional Description
22.6.1 External Memory Interface
22.6.1.1 External Memory Mapping
The memory map is defined by hardware and associates the internal 32-bit address space with
the external 23-bit address bus. Note that A[22:0] is only significant for 8-bit memory. A[22:1] is
used for 16-bit mem ory. If the physical me mory device is smaller th an the page size, it wra ps
around and appears to be repeated within the page. The SMC correctly handles any valid
access to the memory device within the page. See Figure 22-2.
Figure 22-2. Case of an External Memory Smaller than Page Size
1M Byte Device
1M Byte Device
1M Byte Device
1M Byte Device
Memory
Map
Hi
Low
Hi
Low
Hi
Low
Hi
Low Base
Base + 1M Byte
Base + 2M Bytes
Base + 3M Bytes
Base + 4M Bytes
Repeat 1
Repeat 2
Repeat 3
164 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.6.1.2 Chip Select Lines
The Static Memory Controller provides up to eight chip select lines: NCS0 to NCS7.
Figure 22-3. Memory Conne ctio ns for Eigh t Exte rn a l Device s (1)
Note: 1. The maximum address space per device is 8 Mbytes.
22.6.1.3 Data Bus Width
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by
the DBW field in the SMC_CSR f or the cor r espondin g chip select. Se e “SMC Chip Select Regis-
ters” on page 196.
Figure 22-4 shows how to connect a 512K x 8-bit memory on NCS2 (DBW = 10).
Figure 22-4. Memory Connection for an 8-bit Data Path Device
Figure 22-5 shows how to connect a 512K x 16-bit memory on NCS2 (DBW = 01).
NRD
NWR[1:0]
A[22:0]
D[15:0]
8 or 16
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[22:0]
D[15:0] or D[7:0]
NCS3
NCS0
NCS1
NCS2
NCS7
NCS4
NCS5
NCS6
NCS[7:0]
SMC
SMC A0
NWR0
NRD
NCS2
A0
Write Enable
Output Enable
Memory Enable
NWR1
D[7:0] D[7:0]
D[15:8]
A[22:1]
A[22:1]
165
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-5. Memory Connection for a 16-bit Data Path Device
22.6.2 Writ e Ac ce ss
22.6.2.1 Write Access Type
Each chip select with a 16-bit data bus can operate with one of two different types of write
access:
• Byte Write Access supports two byte write and a single read signal.
• Byte Select Access selects upper and/or lower byte with two byte select lines, and separate
read and write signals.
This option is controlled by the BAT field in the SMC_CSR for the corresponding chip select.
See “SMC Chip Select Registers” on page 196.
22.6.2.2 Byte Write Access
Byte Write Access is used to con ne ct 2 x 8-bi t de vice s as a 16-b it me m ory page .
• The signal A0/ NL B is not use d .
• The signal NWR1/NUB is used as NWR1 and enables upper byte writes.
• The signal NWR0/NWE is used as NWR0 and enables lower byte writes.
• The signal NRD enables half-word and byte reads.
Figure 22-6 shows how to connect two 512K x 8-bit devices in parallel on NCS2 (BAT = 0)
SMC NLB
NWE
NRD
NCS2
Low Byte Enable
Write Enable
Output Enable
Memory Enable
NUB High Byte Enable
D[7:0] D[7:0]
D[15:8] D[15:8]
A[22:1] A[22:0]
166 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-6. Memory Connection for 2 x 8-bit Data Path Devices
22.6.2.3 Byte Select Access
Byte Select Access is used to connect 16-bit devices in a memory page.
• The signal A0/NLB is used as NLB and enables the lower byte for both read and write
operations.
• The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write
operations.
• The signal NWR0/NWE is used as NWE and enables writing for byte or half-word.
• The signal NRD enables reading for byte or half-word.
Figure 22-7 shows how to connect a 16-bit device with byte and half-word access (e.g., SRAM
device ty pe) on NCS2 (BAT = 1).
Figure 22-7. Connection to a 16-bit Data Path Device with Byte and Half-word Access
SMC A0
NWR0
NRD
NCS2
Write Enable
Read Enable
Memory Enable
NWR1
Write Enable
Read Enable
Memory Enable
D[7:0] D[7:0]
D[15:8]
D[15:8]
A[22:1]
A[18:0]
A[18:0]
SMC NLB
NWE
NRD
NCS2
Low Byte Enable
Write Enable
Output Enable
Memory Enable
NUB High Byte Enable
D[7:0] D[7:0]
D[15:8] D[15:8]
A[19:1] A[18:0]
167
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-8 shows how to connect a 16-bit device without byte access (e.g., Flash device type)
on NCS2 (BAT = 1).
Figure 22-8. Connection to a 16-bit Data Path Device without Byte Write Capability
22.6.2.4 Write Data Hold Time
During write cycles, data output becomes valid after the rising edge of MCK and remains valid
after the rising edge of NWE. During a write access, the data rem ain on the bus 1/2 period of
MCK after the rising edge of NWE. See Figure 22-9 and Figure 22-10.
Figure 22-9. Write Access with 0 Wait State
SMC
D[7:0] D[7:0]
D[15:8] D[15:8]
A[19:1]
NLB
NWE
NRD
NCS2
Write Enable
Output Enable
Memory Enable
NUB
A[18:0]
A[22:0]
NCS
MCK
NWE
D[15:0]
168 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-10. Write Access with 1 Wait State
22.6.3 Read Access
22.6.3.1 Read Protocols
The SMC provides two alternative protoco ls for external memory read accesses: standard and
early read. The difference between the two protocols lies in the behavior of the NRD signal.
For write accesses, in both protocols, NWE has the same behavior. In the second half of the
master clock cycle, NWE always goes low (see Figure 22 -18 on page 173).
The protocol is selected by the DRP field in SMC_CSR (See “SMC Chip Select Registers” on
page 196.). Standard read protocol is the default protocol after reset.
Note: In the following waveforms and descriptions NWE represents NWE, NWR0 and NWR1 unless
NWR0 and NWR1 are otherwise represented. In addition, NCS represents NCS[7:0] (see 22.5.1
“I/O Lines” on page 163, Table 22-1 and Table 22-2).
22.6.3.2 Standard Read Protocol
Standard read protocol implements a read cycle during which NRD and NWE are similar. Both
are active during the second half of the clock cycle. The first half of the clock cycle allows time to
ensure comple tion of th e previous access as well as the o utput of address line s and NCS befo re
the read cycle begins.
During a standard read protocol, NCS is set low and address lines are valid at the beginning of
the external memory acc ess, while NRD goes low only in the second half of the master clock
cycle to avoid bus conflict. See Figure 22-11.
A[22:0]
NCS
NWE
MCK
D[15:0]
169
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-11. Standard Read Protocol
22.6.3.3 Early Read Protocol
Early read protocol provides more time for a read access from the memory by asserting NRD at
the beginning of the clock cycle. In the case of successive read cycles in the same memory,
NRD remains active continuous ly. Since a read cycle normally limits the speed of operation of
the external memory system, early read protocol can allow a faster clock frequency to be used.
However, an extra wait st ate is r equir ed in some cases t o avoi d conte ntion s o n the ext ernal bus.
Figure 22-12. Early Read Protocol
22.6.4 Wait State Management
The SMC can automatically insert wait states. The different types of wait states managed are
listed below:
• Standard wait states
• External wait states
• Data float wait states
• Chip select change wait states
• Early Read wait states
A[22:0]
NCS
MCK
NRD
D[15:0]
A[22:0]
NCS
MCK
NRD
D[15:0]
170 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.6.4.1 Standard Wait States
Each chip select can be programmed to insert one or more wait states during an access on the
corresponding memory area. This is done by setting the WSEN field in the corresponding
SMC_CSR (“SMC Chip Select Registers” on page 196). The number of cycles to insert is pro-
grammed in the NWS field in the same register.
Below is the corres pondenc e between th e number of s tandard wait sta tes program med and th e
number of clock cycles during which the NWE pulse is held low:
0 wait states 1/2 clock cycle
1 wait state 1 clock cycle
For each additional wait state programmed, an additional cycle is added.
Figure 22-13. One Standard Wait State Access
Notes: 1. Early Read Protocol
2. Standard Read Protocol
22.6.4.2 External W ait States
The NWAIT input pin is used to insert wait states beyon d the maximum st andard wait states pr o-
grammable or in additio n to. If NWAIT is asserted low, then the SMC adds a wait state and no
changes are made to the output signals, the internal counters or the state. When NWAIT is de-
asserted, the SMC completes the access sequence.
WARNING: Asserting NWAIT low stops the core’s clock and thus stops program execu tion.
The input of the NWAIT signal is an asynchronous input. To avoid any metastability problems,
NWAIT is synchronized before using it. This operation results in a two-cycle delay.
NWS must be prog rammed as a f unction o f synchroniza tion tim e and delay between NWAI T fall-
ing and control signals falling (NRD/NWE), otherwise SMC will not function correctly.
Note: Where external NWAIT synchronization is equal to 2 cycles.
The minimum value for NWS if NWAIT is used, is 3.
WARNING: If NWAIT is asserted during a setup or hold timing, the SMC does not function
correctly.
A[22:0]
NCS
NWE
MCK
1 Wait State Access
NRD (1) (2)
NWS Wait Delay from nrd/nwe external_nwait Synchronization Delay 1++≥
171
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-14. NWAIT Behavior in Read Access [NWS = 3]
Notes: 1. Early Read Protocol
2. Standard Read Protocol
Figure 22-15. NWAIT Behavior in Write Access [NW S = 3]
22.6.4.3 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to
add wait states (data float wait states) after a read access be fore starting a write access o r a
read access to a diff er en t external memor y .
The Data Float Output Time (tDF) for each external memory device is programmed in the TDF
field of the SMC_CSR register for the co rresponding chip select (“SMC Chip Select Registers”
on page 196). The value of TDF indicates the number of data float wait cycles (between 0 and
A[22:0]
NWAIT
NWAIT
internally synchronized
NRD
NCS
(1) (2)
Wait Delay from NRD
NWAIT
Synchronization Delay
MCK
A[22:0]
NWAIT
NWAIT
internally synchronized
NWE
D[15:0]
Wait Delay
from NWE NWAIT
Synchronization Delay
MCK
172 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
15) to be inserted and represents the time allowed for the data output to go to h igh impedance
after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an
external memory with long tDF will not slow down the execution of a program from internal
memory.
To ensure that the external memory system is not accessed while it is still busy, the SMC keeps
track of the programmed external data float time during internal accesses.
Internal memory accesses and consecutive read accesses to the same external memory do not
add data float wait states.
Figure 22-16. Data Float Output Delay
Notes: 1. Early Read Protocol
2. Standard Read Protocol
22.6.4.4 Chip Select Change Wait State
A chip select wait state is automatically inserted when consecutive accesses are made to two
different external memories (if no other type of wait state has already been inserted). If a wait
state has already b een inserted (e.g., data fl oat wait state), then no more wait sta tes are added.
A[22:0]
NRD
D[15:0]
MCK
tDF
(1) (2)
NCS
173
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-17. Chip Select Wait State
Notes: 1. Early Read Protocol
2. Standard Read Protocol
22.6.4.5 Early Read Wait State
In early read protocol, an early read wait state is automatically inserted when an external write
cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent
read cycle begins (see Figure 22-18). This wait state is gener ated in addition to any other pro-
grammed wait states (i.e., data float wait state).
No wait state is added when a read cycle is followed by a write cycle, between consecutive
accesses of the same type, or between external and internal memory accesses.
Figure 22-18. Early Read Wait States
NCS1
NCS2
MCK
Mem 1 Chip Select Wait Mem 2
NRD
NWE
(1) (2)
A[22:0] addr Mem 1 addr Mem 2
A[22:0]
NCS
NWE
MCK
Write Cycle Early Read Wait Read Cycle
NRD
D[15:0]
174 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.6.5 Setup and Hold Cycl es
The SMC allows some memor y devices to be interfaced with differen t setu p, hold and pulse
delays. These parame ters are programmable and define the timing of each portio n of the read
and write cycles. However, it is not possible to use this feature in early re ad protocol.
If an attempt is made to program the setup parameter as not equal to zero and the hold parame-
ter as equal to zero with WSEN = 0 (0 standard wait state), the SMC does not operate correctly.
If consecutive accesses are made to two different external memories and the second memory is
programmed with setup cycles, then no chip select change wait state is inserted (see Figure 22-
23 on page 176).
When a data float wait state (tDF) is programmed on the first memo ry bank an d when the second
memory bank is programmed with setup cycles, the SMC behaves as follows:
• If the number of tDF is higher or equal to the number of setup cycles, the number of setup
cycles inserted is equal to 0 (see Figure 22-24 on page 176).
• If the nu mber of the se tup cycle is high er than the n umber of tDF, the number of tDF inserted is
0 (see Figure 22-25 on page 177).
22.6.5.1 Read AccessThe read cycle can be divided into a setup, a pulse length and a hold. The setup parameter can
have a value between 1.5 and 7.5 clock cycles, the hold parameter between 0 and 7 clock
cycles and the pulse length between 1.5 and 128.5 clock cycles, by increments of one.
Figure 22-19. Read Access with Setup and Hold
Figure 22-20. Read Access with Setup
NRD Setup Pulse Length
NRD
A[22:0]
NRD Hold
MCK
NRD Setup Pulse Length
NRD
A[22:0]
MCK
175
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.6.5.2 Write AccessThe write cycle can be divided into a setup, a pulse length and a hold. The setup parameter can
have a value between 1.5 and 7.5 clock cycles, the hold parameter between 0.5 and 7 clock
cycles and the pulse length between 1 and 128 clock cycles by increments of one.
Figure 22-21. Write Access with Setup and Hold
Figure 22-22. Write Access with Setup
NWR Setup Pulse Length
NWE
A[22:0]
NWR Hold
D[15:0]
MCK
NWR Setup Pulse Length
NWE
A[22:0]
NWR
Hold
D[15:0]
MCK
176 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.6.5.3 Data Float Wait States with Setup Cycle s
Figure 22-23. Consecutive Accesses with Setup Programmed on the Second Access
Figure 22-24. First Access with Data Float Wait States (TDF = 2) and Second Access with Setup (NRDSETUP = 1)
Setup
NCS1
A[22:0]
MCK
NCS2
NRD
NWE
Setup
NCS1
A[22:0]
MCK
NCS2
D[15:0]
NRD
Data Float Time
177
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-25. First Access with Data Float Wait States (TDF = 2) and Second Access with Setup (NRDSETUP = 3)
Setup
NCS1
A[22:0]
MCK
NCS2
D[15:0]
NRD
Data Float Time
178 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.6.6 LCD Interface Mode
The SMC can be configured to work with an external liquid crystal display (LCD) controller by
setting the ACSS (Address to Chip Select Setup) bit in the SMC_CSR registers (“SMC C hip
Select Registers” on page 196).
In LCD mode, NCS is sh or te ne d by on e /tw o/ thr e e clo ck cycles at the leading an d tr ailin g edg e s,
providing positive address setup and hold. For read accesses, the data is latched in the SMC
when NCS is raised at the end of the access.
Additionally, WSEN must be set and NWS programmed with a value of two or more superior to
ACSS. In LCD mode, it is not re comme nded to use RWHOL D or RWSETUP. If the abo ve condi-
tions are not satisfied, SMC does not operate correctly.
Figure 22-26. Read Access in LCD Interface Mode
Figure 22-27. Write Access in LCD Interface Mode
NRD
A[22:0]
NCS
Data from LCD Controller
ACSS
ACSS = 3, NWEN = 1, NWS = 10
ACSS
MCK
NWE
A[22:0]
ACCS = 2, NWEN = 1, NWS = 10
ACCS ACCS
NCS
D[15:0]
MCK
179
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.6.7 Memory Access Waveforms
22.6.7.1 Read Accesses in Standard and Early Protocols
Figure 22-28 on page 179 through Figure 22-31 on page 182 show examples of the alternatives
for external memory read protocol.
Figure 22-28. Standard Read Protocol without tDF
Read Mem 1 Write Mem 1 Read Mem 1 Read Mem 2 Write Mem 2 Read Mem 2
Chip Select
Change Wait
A[22:0]
NRD
NWE
NCS1
NCS2
D[15:0] (Mem 1)
D[15:0] (Mem 2)
D[15:0] (to write)
MCK
tWHDX tWHDX
180 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-29. Early Read Prot oc ol with ou t tDF
Read
Mem 1 Write
Mem 1 Early Read
Wait Cycle Read
Mem 1 Read
Mem 2 Write
Mem 2 Early Read
Wait Cycle Read
Mem 2
Chip Select
Change Wait
Long tWHDX
A[22:0]
NRD
NWE
NCS1
NCS2
D[15:0] (Mem 1)
D[15:0] (Mem 2)
D[15:0] (to write)
MCK
tWHDX
181
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-30. Standard Read Protocol with tDF
Read Mem 1 Write
Mem 1
Data
Float Wait
Read Mem 1
Data
Float Wait
Read
Mem 2 Read Mem 2
Data
Float Wait
Write
Mem 2 Write
Mem 2
tWHDX
tDF tDF
tDF
A[22:0]
NRD
NWE
NCS1
NCS2
D[15:0]
(Mem 1)
D[15:0]
(Mem 2)
D[15:0]
MCK
(tDF = 2)
(tDF = 1)
(tDF = 1)
(to write)
182 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-31. Early Read Prot oc ol with tDF
Read
Mem 2
A[22:0]
NRD
NWE
NCS1
NCS2
D[15:0]
(Mem 1)
D[15:0]
(Mem 2)
D[15:0]
MCK
(tDF = 2)
(to write)
Read Mem 1 Write
Mem 1
Data
Float Wait
Early
Read Wait Read Mem 1
Data
Float Wait
Read Mem 2
Data
Float Wait
Write
Mem 2 Write
Mem 2
tDF tDF
tDF
183
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.6.7.2 Accesses with Setup and Hold
Figure 22-32 and Figure 22-33 show an example of read and write accesses with Setup and
Hold Cycles.
Figure 22-32. Read Accesses in Standard Read Protocol with Setup and Hold(1)
Note: 1. Read access, memory data bus width = 8, RWSETUP = 1, RWHOLD = 1,WSEN= 1, NWS = 0
Figure 22-33. Write Accesses with Setup and Hold(1)
Note: 1. Write access, memory data bus width = 8, RWSETUP = 1, RWHOLD = 1, WSEN = 1, NWS = 0
MCK
A[22:1]
A0/NLB
NRD
NWR0/NWE
NWR1/NUB
NCS
D[15:0]
00d2b 00028 00d2c
e59f 0001 0002
Hold
Setup Setup Hold
MCK
A[22:1]
A0/NLB
NRD
NWR0/NWE
NWR1/NUB
NCS
D[15:0]
008cb 00082 008cc
3000 e3a0 0605 0606
Setup Hold Setup Hold
184 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.6.7.3 Accesses Using NWAIT Input Signal
Figure 22 -3 4 o n pa ge 184 through Figure 22-37 on page 187 show examples of accesses using
NWAIT.
Figure 22-34. Write Access using NWAIT in Byte Select Type Access(1)
Note: 1. Write access memory, data bus width = 16 bits, WSEN = 1, NWS = 6
A[22:1]
NRD
NWR0/NWE
A0/NLB
NWR1/NUB
NCS
D[15:0]
MCK
NWAIT
NWAIT
internally
synchronized
000008A
1312
Wait Delay Falling
from NWR0/NWE
Chip Select
Wait
185
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-35. Write Access using NWAIT in Byte Write Type Access(1)
Note: 1. Write access memory, data bus width = 16 bits, WSEN = 1, NWS = 5
A[22:1]
NRD
NWR0/NWE
A0/NLB
NWR1/NUB
NCS
D[15:0]
MCK
NWAIT
NWAIT
internally
synchronized
000008C
1716
Wait Delay Falling from NWR0/NWE/NWR1/NUB
Chip Select
Wait
186 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-36. Write Access using NWAIT(1)
Note: 1. Write access memo ry, data bus width = 8 bits, WSEN = 1, NWS = 4
NCS
A[22:1]
NRD
NWR0/NWE
A0/NLB
NWR1/NUB
D[15:0]
MCK
NWAIT
NWAIT
internally
synchronized
0000033
0403
Wait Delay Falling from NWR0/NWE
Chip Select
Wait
187
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-37. Read Access in Standard Protocol using NWAIT(1)
Note: 1. Read access, memory data bus width = 16, NWS = 5, WSEN = 1
22.6.7.4 Memory Access Example Waveforms
Figure 22 -38 on page 188 through Figure 22-44 on page 194 show the wavefo rms for re ad and
write accesses to the various associated external memory devices. The configurations
described are shown in Table 22-3.
NCS
A[22:1]
NRD
NWR0/NWE
A0/NLB
NWR1/NUB
D[15:0]
MCK
NWAIT
NWAIT
internally
synchronized
0002C44
0003
Wait Delay Falling from NRD/NOE
Table 22-3. Memory Access Waveforms
Figure Number Number of Wait
States Bus Width Size of Data Transfer
Figure 22-38 016Word
Figure 22-39 116Word
Figure 22-40 116Half-word
Figure 22-41 08Word
Figure 22-42 18Half-word
Figure 22-43 18Byte
Figure 22-44 0 16 Byte
188 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-38. 0 Wait State, 16-bit Bus Width, Word Transfer
B2 B1 B
4 B3
B2 B1B4 B3
B2 B1 B4 B3
MCK
NCS
NRD
Read Access
NRD
Write Access
NWE
D[15:0]
NLB
NUB
· Standard Read Protocol
· Early Read Protocol
· Byte Write/
Byte Select Option
D[15:0]
D[15:0]
A[22:1] addr addr+1
189
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-39. 1 Wait State, 16-bit Bus Width, Word Transfer
B
2
B
1
B
4
B
3
1 Wait State 1 Wait State
B
4
B
3
B
2
B
1
B
4
B
3
B
2
B
1
MCK
NCS
NRD
Read Access
NRD
Write Access
NWE
D[15:0]
NLB
NUB
·
Standard Read Protocol
·
Early Read Protocol
·
Byte Write/
Byte Select Option
D[15:0]
D[15:0]
A[22:1] addr addr+1
190 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-40. 1 Wait State, 16-bit Bus Width, Half-Word Transfer
B2 B1
1 Wait State
B2 B1
B2 B1
MCK
NCS
NRD
Read Access
NRD
Write Access
NWE
D[15:0]
NLB
NUB
· Standard Read Protocol
· Early Read Protocol
· Byte Write/
Byte Select Option
D[15:0]
D[15:0]
A[22:1]
191
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-41. 0 Wait State, 8-bit Bus Width, Word Transfer
addr
X B1
addr+2 addr+3
X B2 X B3X B4
X B1X B2 X B3X B4
X B1X B2 X B3X B4
addr+1
MCK
NCS
NRD
Read Access
NRD
Write Access
NWR1
D[15:0]
· Standard Read Protocol
· Early Read Protocol
D[15:0]
D[15:0]
A[22:0]
NWR0
192 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-42. 1 Wait State, 8-bit Bus Width, Half-Word Transf er
Addr
X B1
1 Wait State
Addr+1
1 Wait State
X B2
X B1X B2
X B1X B2
MCK
NCS
NRD
Read Access
NRD
Write Access
NWR1
D[15:0]
· Standard Read, Protocol
· Early Read Protocol
D[15:0]
D[15:0]
A[22:0]
NWR0
193
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-43. 1 Wait State, 8-bit Bus Width, Byte Transfer
XB1
1 Wait State
X B1
X B1
MCK
NCS
NRD
Read Access
NRD
Write Access
NWR1
D[15:0]
· Standard Read Protocol
· Early Read Protocol
D[15:0]
D[15:0]
A[22:0]
NWR0
194 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-44. 0 Wait State, 16-bit Bus Width, Byte Transfer
X B1 B2X
addr X X X 0 addr X X X 0
addr X X X 0 addr X X X 1
XB1B2X
B1B1B2B2
MCK
NCS
NRD
Read Access
NRD
Write Access
NWR1
D[15:0]
· Standard Read Protocol
· Early Read Protocol
D[15:0]
D[15:0]
A[22:1]
NWR0
· Byte Write Option
· Byte Select Option
Internal Address Bus
NLB
NUB
NWE
195
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.7 Static Memory Controller (SMC) User Interface
The Static Memory Controller is programmed using the registers listed in Table 22-4. Eight Chip Select Registers
(SMC_CSR0 to SMC_ CSR7 ) ar e us ed to pr og ra m the par am e ter s fo r the indiv idu al external memor ies.
Table 22-4. Static Memory Controller Register Mapping
Offset Register Name Access Reset State
0x00 SMC Chip Select Register 0 SMC_CSR0 Read/Write 0x00002000
0x04 SMC Chip Select Register 1 SMC_CSR1 Read/Write 0x00002000
0x08 SMC Chip Select Register 2 SMC_CSR2 Read/Write 0x00002000
0x0C SMC Chip Select Register 3 SMC_CSR3 Read/Write 0x00002000
0x10 SMC Chip Select Register 4 SMC_CSR4 Read/Write 0x00002000
0x14 SMC Chip Select Register 5 SMC_CSR5 Read/Write 0x00002000
0x18 SMC Chip Select Register 6 SMC_CSR6 Read/Write 0x00002000
0x1C SMC Chip Select Register 7 SMC_CSR7 Read/Write 0x00002000
196 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
22.7.1 SMC Chip Select Registers
Name: SMC_CSR0..SMC_CSR7
Access: Read/Write
Reset Value: See Table 22-4 on page 195
• NWS: Number of Wait States
This field defines the Read and Write signal pulse length from 1 cycle up to 128 cycles.
Note: When WSEN is 0, NWS will be read to 0 whichever the previous programmed value should be.
Note: 1. Assuming WSEN Field = 0.
• WSEN: Wait State Enable
0: Wait states are disabled.
1: Wait states are enabled.
• TDF: Data Float Time
The external bus is marked occupied and cannot be used by anothe r chip select during TDF cycles. Up to 15 cycles can be
defined and represents the time allowed for the data output to go to high impedance after the memory is disabled.
• BAT: Byte Access Type
This field is used only if DBW defines a 16-bit data bus.
0: Chip select line is connected to two 8-bit wide devices.
1: Chip select line is connected to a 16-bit wide device.
31 30 29 28 27 26 25 24
–RWHOLD–RWSETUP
23 22 21 20 19 18 17 16
–––––– ACSS
15 14 13 12 11 10 9 8
DRP DBW BAT TDF
76543210
WSEN NWS
Number of Wait States NWS Field NRD Pulse Length
Standard Read Protocol NRD Pulse Length
Early Read Protocol NWR Pulse Length
0(1) Don’t Care ½ cycle 1 cycle ½ cycle
1 0 1 + ½ cycles 2 cycles 1 cycle
2 1 2 + ½ cycles 3 cycles 2 cycles
X + 1 Up to X = 127 X + 1+ ½ cycles X + 2 cycles X + 1 cycle
197
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• DBW: Data Bus Width
• DRP: Data Read Protocol
0: Standard Read Protocol is used.
1: Early Read Protocol is used.
• ACSS: Address to Chip Select Setup
• RWSETUP: Read and Write Signal Setup Time
See definition an d de sc rip tio n be low .
• RWHOLD: Read and Write Signal Hold Time
See definition an d de sc rip tio n be low.
Notes: 1. For a visual description, please refer to “Setup and Hold Cycles” on page 174 and the diagrams in Figure 22-45 and Figure
22-46 and Fi gure 22-47 on page 198.
2. In Standard Read Protocol.
3. In Early Read Proto c ol. (It is not possible to use the parameters RWSETUP or RWHOLD in this mode.)
4. When the ECC Controller is used, RWHOLD must be programmed to 1 at least.
DBW Data Bus Width
0 0 Reserved
0116-bit
108-bit
11Reserved
ACSS Chip Select Waveform
0 0 Standard, asserted at the beginning of the access and deasserted at the end.
0 1 One cycle less at th e beginning and the end of the access.
1 0 Two cycles less at the beginning and the end of the access.
1 1 Three cycles less at the beginning and the end of the access.
RWSETUP(1) NRD Setup NWR Setup RWHOLD(1) (4) NRD Hold NWR Hold
000
½ cycle(2)or
0 cycles(3) ½ cycle 0 0 0 0 ½ cycle
0 0 1 1 + ½ cycles 1 + ½ cycles 0 0 1 1 cycles 1 cycle
0 1 0 2 + ½ cycles 2 + ½ cycles 0 1 0 2 cycles 2 cycles
0 1 1 3 + ½ cycles 3 + ½ cycles 0 1 1 3 cycles 3 cycles
1 0 0 4 + ½ cycles 4 + ½ cycles 1 0 0 4 cycles 4 cycles
1 0 1 5 + ½ cycles 5 + ½ cycles 1 0 1 5 cycles 5 cycles
1 1 0 6 + ½ cycles 6 + ½ cycles 1 1 0 6 cycles 6 cycles
1 1 1 7 + ½ cycles 7 + ½ cycles 1 1 1 7 cycles 7 cycles
198 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 22-45. Read/Write Setup
Figure 22-46. Read Hold
Figure 22-47. Write Hold
NRD
A[22:0]
MCK
RWSETUP
NWE
NRD
A[22:0]
MCK
RWHOLD
NWE
A[22:0]
MCK
RWHOLD
D[15:0]
199
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23. SDRAM Controller (SDRAMC)
23.1 Overview The SDRAM Controller (SDRAMC) extends the memor y capabilities of a chip by providing the
interface to an exter nal 16-bit or 32-bit SDRAM device. The page size suppor ts ranges from
2048 to 8192 and the number of columns from 256 to 2048 . It suppor ts byte (8-bit), half-word
(16-bit) and word (32-bit) accesses.
The SDRAM Controller supports a read or wr ite burst length of one location. It does not support
byte Read/Write bursts or half-word write bursts. It keeps track of the active row in each bank,
thus maximizing SDRAM performance, e .g., the ap plication may be placed in one bank an d data
in the other banks. So as to optimize performance, it is advisable to avoid accessing different
rows in the same bank.
The SDRAM Controller also supports Mobile SDRAM if VDDIO is set at 1.8V with the fr eq ue n cy
limitation as given in the product Electrical Characteristics. However, the SDRAMC does not
support the low-power extended mode registe r and deep power-down mode.
23.2 Block Diagram
Figure 23-1. SDRAM Controller Block Diagram
Memory
Controller
APB
SDRAMC
Interrupt
SDCK
SDCS
A[12:0]
SDRAMC
PIO
Controller
BA[1:0]
SDCKE
RAS
CAS
SDWE
NBS[3:0]
User Interface
PMC MCK
D[31:0]
SDRAMC
Chip Select
200 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.3 I/O Lines Description
Note: 1. SDCK is tied low after reset.
23.4 Application Example
23.4.1 Soft ware Inte rfa ce
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user. Table 23-2 to Table 23-7 illustrate the SDRAM device memory mapping theref ore seen
by the user in correlation with the device str ucture. Various configurations are illustrated.
23.4.1.1 32-bit Memory Data Bus Width
Table 23-1. I/O Line Description
Name Description Type Active Level
SDCK SDRAM Clock Output(1)
SDCKE SDRAM Cloc k Enable Output High
SDCS SDRAM Controller Chip Select Output Low
BA[1:0] Bank Select Signals Output
RAS Row Signal Output Low
CAS Column Signal Output Low
SDWE SDRAM Write Enable Output Low
NBS[3:0] Data Mask Enable Signals Output Low
A[12:0] Address Bus Output
D[31:0] Data Bus I/O
Table 23-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
2
72
62
52
42
32
22
12
01
91
81
71
61
51
41
31
21
11
09876543210
Bk[1:0] Row[10:0] Column[7:0] M[1:0]
Bk[1:0] Row[10:0] Column[8:0] M[1:0]
Bk[1:0] Row[10:0] Column[9:0] M[1:0]
Bk[1:0] Row[10:0] Column[10:0] M[1:0]
Table 23-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
2
72
62
52
42
32
22
12
01
91
81
71
61
51
41
31
21
11
09876543210
Bk[1:0] Row[11:0] Column[7:0] M[1:0]
Bk[1:0] Row[11:0] Column[8:0] M[1:0]
Bk[1:0] Row[11:0] Column[9:0] M[1:0]
Bk[1:0] Row[11:0] Column[10:0] M[1:0]
201
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Notes: 1. M[1:0] is the byte address inside a 32-bit word.
2. Bk[1] = BA1, Bk[0] = BA0.
23.4.1.2 16-bit Memory Data Bus Width
Notes: 1. M0 is the byte address inside a 16-bit half-word.
2. Bk[1] = BA1, Bk[0] = BA0.
Table 23-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
2
72
62
52
42
32
22
12
01
91
81
71
61
51
41
31
21
11
09876543210
Bk[1:0] Row[12:0] Column[7:0] M[1:0]
Bk[1:0] Row[12:0] Column[8:0] M[1:0]
Bk[1:0] Row[12:0] Column[9:0] M[1:0]
Bk[1:0] Row[12:0] Column[10:0] M[1:0]
Table 23-5. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
2726252423222120191817161514131211109876543210
Bk[1:0] Row[10:0] Column[7:0] M0
Bk[1:0] Row[10:0] Column[8:0] M0
Bk[1:0] Row[10:0] Column[9:0] M0
Bk[1:0] Row[10:0] Column[10:0] M0
Table 23-6. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[11:0] Column[7:0] M0
Bk[1:0] Row[11:0] Column[8:0] M0
Bk[1:0] Row[11:0] Column[9:0] M0
Bk[1:0] Row[11:0] Column[10:0] M0
Table 23-7. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[12:0] Column[7:0] M0
Bk[1:0] Row[12:0] Column[8:0] M0
Bk[1:0] Row[12:0] Column[9:0] M0
Bk[1:0] Row[12:0] Column[10:0] M0
202 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.5 Product Dependencies
23.5.1 SDRAM Device Initialization
The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:
1. SDRAM Characteristics must be set in the Configuration Register: asynchronous tim-
ings (TRC, TRAS,...), number of columns, rows, and CAS latency. The data bus width
must be set in the Mode Regi st er.
2. A minimum pause of 200 µs is provided to precede any signal toggle.
3. (1) A NOP command is issued to the SDRAM de vices . The application must set Mode to
1 in the Mode Register and perform a write access to any SDRAM addr ess.
4. An All Banks Precha rge command is issued to the SDRAM devices. The application
must set Mode to 2 in the Mode Register and perform a write access to any SDRAM
address.
5. Eight au to-refresh (CBR) cycles are prov ided. The application must set th e Mode to 4 in
the Mode Register and performs a write access to an y SDRAM location height times.
6. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM
de vices , in particular CAS latency and bur st length. The application m ust set Mode to 3
in the Mode Register and perform a write access to the SDRAM.
7. The app lication must go into Normal Mode, se tting Mode to 0 in the Mod e Register and
performing a wr ite access at any location in the SDRAM.
8. Write the refresh rate into the count field in the SDRAMC Refresh Timer Re gister.
(Refresh rate = delay between ref resh cycles). The SDRAM device requires a refresh
every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the Refresh Timer Counter
Register must be set with the value 1562(15.652 µs x 100 MHz) or 781(7.81 µs x 100
MHz).
After initialization, the SDRAM devices ar e fully functional.
Note: 1. It is strongly recommended to respect the instructions stated in step 3 of the initialization pro-
cess in order to be certain that the following commands issued by the SDRAMC will be well
taken into account.
203
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 23-2. SDRAM Devices Initialization Sequence
23.5.2 I/O Lines The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The
programmer must first program the PIO controller to assign the SDRAM Con troller pins to their
peripheral funct ion. If I/O lines of the SDRAM Controller ar e not used b y t he application, th ey can
be used for other purposes by the PIO Contr oller.
23.5.3 Interrupt The SDRAM Controller interrupt (Refresh Error notifica tion) is connected to the Me mory Control-
ler. This interrupt may be ORed with other System Peripheral interrupt lines and is finally
provided as the System Interrupt Source (Source 1) to the AIC (Advanced Interrupt Controller).
Using the SDRAM Controller interrupt requires the AIC to be programmed first.
SDCK
SDRAMC_A[9:0]
A10
SDRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
NBS
Inputs Stable for
200 μsec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command
SDCKE tRP tRC tMRD
204 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.6 Functional Description
23.6.1 SDRAM Controller Write Cycle
The SDRAM Controller allows burst access or single access. To initiate a burst access, the
SDRAM Controller uses the tra nsfer type signal pro vide d b y the mast er request ing the access . If
the next access is a sequential write access, writing to the SDRAM device is carr ied out. If the
next access is a write-sequential access, but the current access is to a boundary page, or if the
next access is in another row, then the SDRAM Controller generates a precharge command,
activ ates the new ro w and initiates a write command. To comply with SDRAM timing parameters,
additional clock cycles are inserted between precharge/active (tRP) commands and active/write
(tRCD) commands. For definition of these timing par ame ters , refer to the “SDRAMC Configuration
Register” on page 213. This is described in Figure 23-3 below.
Figure 23-3. Write Burst, 32-bit SDRAM Access
SDCK
SDCS
RAS
CAS
A[12:0]
D[31:0]
t
RCD
= 3
Dna
SDWE
Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl
Row n col a col b col c col d col e col f col g col h col i col j col k col l
205
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.6.2 SDRAM Controller Read Cycle
The SDRAM Controller allows burst access or single access. To initiate a burst access, the
SDRAM Controller uses the tra nsfer type signal pro vide d b y the mast er request ing the access . If
the next access is a sequential read access, reading to the SDRAM device is carr ied out. If the
next access is a sequential read access, but the current access is to a boundar y page, or if the
next access is in another row, then the SDRAM Controller generates a precharge command,
activates the new row and initiates a read command. To comply with SDRAM timing parameters,
an additional clock cycle is inser ted between the precharge/active (tRP) command and the
activ e/read (tRCD) command, Aft er a read comma nd, addition al wait sta tes are gener ated to com-
ply with CAS latency. The SDRAM Cont roller suppor ts a CAS latency of two. Fo r definition of
these timing parameters, refer to “SDRAMC Configuration Register” on page 213. This is
described in Figure 23-4 below.
Figure 23-4. Read Burst, 32-bit SDRAM access
SDCK
SDCS
RAS
CAS
A[12:0]
D[31:0]
(Input)
t
RCD
= 3
Dna
SDWE
Dnb Dnc Dnd Dne Dnf
Row n col a col b col c col d col e col f
CAS = 2
206 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.6.3 Border Management
When the memory row boundary has been reached, an automati c page br eak is inse rted. In this
case, the SDRAM controller generates a precharge command, activates the new row and ini-
tiates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inser ted between the precharge/active (tRP) command and the active/read (tRCD) com-
mand. This is described in Figure 23-5 below.
Figure 23-5. Read Burst with Boundary Row Access
SDCK
SDCS
RAS
CAS
A[12:0]
D[31:0]
T
RP
= 3
SDWE
Row m
col a col a col b col c col d col e
Dna Dnb Dnc Dnd
T
RCD
= 3 CAS = 3
col b col c col d
Dma Dmb Dmc Dmd
Row n
Dme
207
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.6.4 SDRAM Controller Refresh Cycles
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated inter nally by the SDRAM device and incremented after each auto-refresh automatically.
The SDRAM Controller generates these auto -refresh commands per iodically. A timer is loade d
with the value in the register SDRAMC_TR that indicates the number of clock cycles between
refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perfor m.
It will be acknowledged by reading the Interrupt Status Register (SDRAMC_ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory
accesses are not delayed. However, if the CPU tries to access the SDRAM, the slave will indi-
cate that the device is busy and the ARM BWAIT signal will be asserted. See Figure 23-6 below.
Figure 23-6. Refresh Cycle Followed by a Read Access
SDCK
SDCS
RAS
CAS
A[12:0]
D[31:0]
(input)
t
RP
= 3
SDWE
Dnb Dnc Dnd
col c col d
CAS = 2
Row m col a
t
RC
= 8 t
RCD
= 3
Dma
Row n
208 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.6.5 Power Management
23.6.5.1 Self-refresh Mode
Self-refresh mode is used in power-down mode, i.e., when no access to the SDRAM device is
possible. In this case, power consumption is ver y low. The mode is activated by programming
the self-refresh command bit (SRCB) in SDRAMC_SRR. In self-refresh mode, the SDRAM
device retains data without external clocking and provides its own inter nal clocking, thus per-
for ming its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care”
except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM
Controller provides a sequence of commands and exits self-refresh mode, so the self-refresh
command bit is disabled.
To re -a ctivate this mode, the self-ref re sh com ma n d bit must be re- pr ogrammed.
The SDRAM device must remain in self-refresh mode for a minimum period of t RAS and may
remain in self-refresh mode for an indefinite period. This is described in Figure 23-7 below.
Figure 23-7. Self-refresh Mode Behavior
SDCK
SDCS
RAS
CAS
A[12:0]
Self Refresh Mode
SDWE
Row
T
XSR
= 3
SDCKE
Write
SDRAMC_SRR
SRCB = 1
Access Request
to the SDRAM Controller
209
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.6.5.2 Low-power Mode
Low-power mode is us ed in power-down mode, i.e., when no access to the SDRAM device is
possib le . In this mode , po w er consumptio n is grea ter than in self-refre sh mode . This stat e is sim-
ilar to nor mal mode (No low-power mode/No self-refresh mode), but the SDCKE pin is low and
the input and output buffers are deactivated as soon as the SDRAM device is no longer accessi-
ble. In contrast to self-refresh mode, the SDRAM device cannot remain in low-power mode
longer than the refresh period (64 ms for a whole device refresh operation). As no auto-refresh
operations are perfor med in this mode, the SDRAM Controller carries out the refresh operation.
In order to exit low-power mode, a NOP command is required. The exit procedure is faster than
in self-refresh mode.
When self-refresh mode is enabled, it is recommended to avoid enabling low-power mode.
When low-power mode is enabled, it is recommended to avoid enabling self-refresh mode.
This is described in Figure 23-8 below.
Figure 23-8. Low-power Mode Behavior
SDCK
SDCS
RAS
CAS
A[12:0]
D[31:0]
(input)
T
RCD
= 3
Dna Dnb Dnc Dnd Dne Dnf
Row n col a col b col c col d col e col f
CAS = 2
SDCKE
Low Power Mode
210 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.7 SDRAM Controller (SDRAMC) User Interface
Table 23-8. SDRAM Controller Memory Mapping
Offset Register Name Access Reset State
0x00 SDRAMC Mode Register SDRAMC_MR Read/Write 0x00000010
0x04 SDRAMC Refresh Timer Register SDRAMC_TR Read/Write 0x00000800
0x08 SDRAMC Configuration Register SDRAMC_CR Read/Write 0x2A99C140
0x0C SDRAMC Self Refresh Register SDRAMC_SRR Write-only –
0x10 SDRAMC Low Power Register SDRAMC_LPR Read/Write 0x0
0x14 SDRAMC Interrupt Enable Register SDRAMC_IER Write-only –
0x18 SDRAMC Interrupt Disable Register SDRAMC_IDR Write-only –
0x1C SDRAMC Interrupt Mask Register SDRAMC_IMR Read-only 0x0
0x20 SDRAMC Interrupt Status Register SDRAMC_ISR Read-only 0x0
0x24 - 0xFC Reserved – – –
211
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.7.1 SDRAMC Mode Register
Name: SDRAMC_MR
Access: Read/Write
Reset Value: 0x00000010
• MODE: SDRAMC Command Mode
This field define s the command issued by the SDRAM Controller when the SDRAM device is accessed.
• DBW: Data Bus Width
0: Data bus width is 32 bits.
1: Data bus width is 16 bits.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––DBW MODE
MODE Description
0000Normal mode. Any access to the SDRAM is decoded normally.
0001
The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the
cycle.
0010
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle.
0011
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. The address offset with respect to the SDRAM device base address is used to
program the Mode Register. F or instance, when this mode is activated, an access to the “SDRAM_Base +
offset” address generates a “Load Mode Register” command with the value “offset” writte n to the SDRAM
device Mode Register.
0100
The SDRAM Controller issues a “Refresh” Command when the SDRAM device is accessed regardless of
the cycle. Previously, an “All Banks Precharge” command must be issued.
212 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.7.2 SDRAMC Refresh Ti me r Re gi st er
Name: SDRAMC_TR
Access: Read/Write
Reset Value: 0x00000800
• COUNT: SDRAMC Refresh Timer Count
This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh
burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate
of the SDRAM device and the refresh burst length where 15.6 µs per row is a t ypical value for a burst of length one.
To refresh the SDRAM device even if the reset valu e is not equal to 0, this 12-bit field mu st be written. If this cond ition is not
satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– COUNT
76543210
COUNT
213
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.7.3 SDRAMC Configuration Register
Name: SDRAMC_CR
Access: Read/Write
Reset Value: 0x2A99C140
• NC: Number of Column Bits
Reset value is 8 column bits.
• NR: Number of Row Bits
Reset value is 11 row bits.
• NB: Number of Banks
Reset value is two banks.
• CAS: CAS Latency
Reset value is two cycles.
In the SDRAMC, only a CAS latency of two cycles is managed. In any case, another value must be programmed.
31 30 29 28 27 26 25 24
– TXSR TRAS
23 22 21 20 19 18 17 16
TRAS TRCD TRP
15 14 13 12 11 10 9 8
TRP TRC TWR
76543210
TWR CAS NB NR NC
NC Column Bits
008
019
1010
1111
NR Row Bits
00 11
01 12
10 13
11 Reserved
NB Number of Banks
02
14
214 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• TWR: Write Recovery Delay
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 2 and 15.
If TWR is less than or equal to 2, two clock pe riods are inserted by default.
• TRC: Row Cycle Delay
Reset value is eight cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is
between 2 and 15.
If TRC is less than or equal to 2, two clock periods are inserted by default.
• TRP: Row Prec harge Delay
Reset value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles
is between 2 and 15.
If TRP is less than or equal to 2, two clock periods are inserted by default.
• TRCD: Row to Column Delay
Reset value is three cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 2 and 15.
If TRCD is less than or equal to 2, two clock periods are inserted by default.
• TRAS: Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 2 and 15.
If TRAS is less than or equal to 2, two clock periods are inserted by default.
• TXSR: Exit Self Refresh to Active Delay
Reset value is five cycles.
This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is
between 1/2 and 15.5.
If TXSR is equal to 0, 1/2 clock period is inserted by default.
CAS CAS Latency (Cycles)
00 Reserved
01 Reserved
10 2
11 Reserved
215
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.7.4 SDRAMC Self-refresh Register
Name: SDRAMC_SRR
Access: Write-only
• SRCB: Self-refresh Command Bit
0: No effect.
1: The SDRAM Controller is sues a self-refresh command to the SDRAM device, the SDCK clock is inactivated an d the
SDCKE signal is set low. The SDRAM device leaves self-refresh mode when accessed again.
23.7.5 SDRAMC Low-power Register
Name: SDRAMC_LPR
Access: Read/Write
Reset Value:0x0
• LPCB: Low-power Command Bit
0: The SDRAM Controller low-power feature is inhibited: no low-power command is issued to the SDRAM device.
1: The SDRAM Controller issues a low-power command to the SDRAM device after each burst access, the SDCKE signal
is set low. The SDRAM device will leave low-power mode when accessed and enter it after the access.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SRCB
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––LPCB
216 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.7.6 SDRAMC Interrupt Enable Register
Name: SDRAMC_IER
Access: Write-only
• RES: Refresh Error Status
0: No effect.
1: Enables the refr esh error interrupt.
23.7.7 SDRAMC Interrupt Disable Register
Name: SDRAMC_IDR
Access: Write-only
• RES: Refresh Error Status
0: No effect.
1: Disables the refresh error interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––RES
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––RES
217
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.7.8 SDRAMC Interrupt Mask Register
Name: SDRAMC_IMR
Access: Read-only
• RES: Refresh Error Status
0: The refresh error interrupt is disabled.
1: The refresh er ror interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––RES
218 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
23.7.9 SDRAMC Interrupt Status Register
Name: SDRAMC_ISR
Access: Read-only
• RES: Refresh Error Status
0: No refresh error has been detected since the register was last rea d.
1: A refresh error has been detected since the register was last read.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––RES
219
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
24. Error Corrected Code Controller (ECC)
24.1 Overview NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more
invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur
which can be detected/correcte d by ECC code.
The ECC Controller is a mechanism that encodes data in a manner that makes possib le the
identification and correction of certain errors in data. The ECC controller is capable of single bit
error correction and 2-bit r andom detection. When NAND Flash/SmartMedia have more than 2
bits of errors, the data cannot be corrected.
The ECC user interface is compliant with the ARM Advanced Peripheral Bus (APB rev2).
24.2 Block Diagram
Figure 24-1. Block Diagram
User Interface
Ctrl/ECC Algorithm
Static
Memory
Controller
APB
NAND Flash
SmartMedia
Logic
ECC
Controller
220 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
24.3 Functional Description
A page in NAND Flash and SmartMedia memories contains an area for main data and an addi-
tional area used fo r redunda ncy (ECC). Th e page is organ ized in 8- bit or 16- bit words. The p age
size corresponds to the number of words in the main area plus the number of words in the extra
area used for redundancy.
The only configuration required for ECC is the NAND Flash or the SmartMedia page size
(528/1056/2112/4224). Page size is configured setting the PAGESIZE field in the ECC Mode
Register (ECC_MR).
ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND
Flash or the SmartMedia is detected. Read and write access must start at a page boundary.
ECC results are available as soon as the counter reaches the end of the main area. Values in
the ECC Parity Register (ECC_PR) and ECC NParity Register (ECC_NPR) are then valid and
locked until a new start condition occurs (read/write command followed by address cycles).
24.3.1 Writ e Ac ce ss Once the flash memory page is written, the computed ECC code is available in the ECC Parity
Error (ECC_PR) and ECC_NParity Error (ECC_NPR) registers. The ECC code value must be
written by the software application in the extra area used for redundancy.
24.3.2 Read Access After reading the whole data in the main area , the applica tion must pe rform read accesses to the
extra area where ECC code has been previously stored. Error detection is automatically per-
formed by the ECC controller. Please note that it is mandatory to read consecutively the entire
main area and the locations where Parity and NParity values have been previously stored to let
the ECC controller perform error detection.
The application can check the ECC Status Register (ECC_SR) for any detected errors.
It is up to the application to correct any detected error. ECC computation can detect four differ-
ent circumstances:
• No error: XOR between the ECC computation and the ECC code stored at the end of the
NAND Flash or SmartMedia page is equal to 0. No error flags in the ECC Status Register
(ECC_SR).
• Recoverable error: Only the RECERR flag in the ECC Status register (ECC_SR) is set. The
corrupted word offset in th e read pa ge is define d by the WORDADDR field in the ECC Parity
Register (ECC_P R). The corrupted bit position in the concerned word is defined in the
BITADDR field in the ECC Parity Register (ECC_PR).
• ECC error: The ECCERR flag in the ECC Status Register is set . An err or has bee n de tecte d
in the ECC code stored in the Flash memory. The position of the corrupted bit can be found
by the application performing an XOR between the Parity and the NParity contained in the
ECC code stored in the flash memory.
• Non correctable error: The MULERR flag in the ECC Status Register is set. Seve ral
unrecoverable errors have been detected in the flash memory page.
ECC Status Register, ECC Parity Register and ECC NParity Register are cleared when a
read/write command is detected or a software reset is performed.
For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) hsiao code is used.
32-bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-
221
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
bit words. Of the 32 ECC bits, 26 b its are for line p arity a nd 6 bits are for colum n parity . They are
generated acco rding to the schemes shown in Figure 24-2 and Figure 24-3.
Figure 24-2. Parity Generation for 512/1024/2048/4096 8-bit Words1
To calculate P8’ to PX’ and P8 to PX, apply t he algorithm that follows.
Page size = 2n
for i =0 to n
begin
for (j = 0 to page_size_byte)
begin
if(j[i] ==1)
P[2i+3]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]
else
P[2i+3]’=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]'
end
end
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8
P8'
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8
P8'
P16
P16'
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8
P8'
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8
P8'
P16
P16'
P32
P32
1st byte
P32
2nd byte
3rd byte
4 th byte
Page size th byte
(page size -1 )th byte
PX
PX'
Page size = 512 Px = 2048
Page size = 1024 Px = 4096
Page size = 2048 Px = 8192
Page size = 4096 Px = 16384
(page size -2 )th byte
(page size -3 )th byte
P1 P1' P1'
P1 P1 P1' P1'
P1
P2 P2' P2 P2'
P4 P4'
P1=bit7(+)bit5(+)bit3(+)bit1(+)P1
P2=bit7(+)bit6(+)bit3(+)bit2(+)P2
P4=bit7(+)bit6(+)bit5(+)bit4(+)P4
P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1'
P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2'
P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'
222 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 24-3. Parity Generation for 512/1024/2048/4096 16-bit Words
1st word
2nd word
3rd word
4th word
(Page size -3 )th word
(Page size -2 )th word
(Page size -1 )th word
Page size th word
(+)(+)
223
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
To calculate P8’ to PX’ and P8 to PX, apply t he algorithm that follows.
Page size = 2n
for i =0 to n
begin
for (j = 0 to page_size_word)
begin
if(j[i] ==1)
P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+)
bit11(+)bit10(+)bit9(+)bit8(+)
bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2n+3]
else
P[2i+3]’=bit15(+)bit14(+)bit13(+)bit12(+)
bit11(+)bit10(+)bit9(+)bit8(+)
bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]'
end
end
224 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
24.4 ECC User Interface
Table 24-1. ECC Register Mapping
Offset Register Register Name Access Reset
0x00 ECC Control Register ECC_CR Write-only 0x0
0x04 ECC Mode Register ECC_MR Read/Write 0x0
0x8 ECC Status Register ECC_SR Read-only 0x0
0x0C ECC Parity Register ECC_PR Read-only 0x0
0x10 ECC NParity Register ECC_NPR Read-only 0x0
0x14 - 0xFC Reserved – – –
225
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
24.4.1 ECC Control Register
Name: ECC_CR
Access: Write-only
• RST: RESET Parity
Provides reset to current ECC by software.
1: Reset sECC Parity and ECC NParity register
0: No effect
24.4.2 ECC Mode Register
Name: ECC_MR
Access: Read/Write
• PAGESIZE: Page Size
This field defines the page size of the NAND Flash device.
A word has a value of 8 bits or 16 bits, depending on t he NAND Flash or Smartmedia memory organization.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––RST
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––– PAGESIZE
Page Size Description
00 528 words
01 1056 words
10 2112 words
11 4224 words
226 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
24.4.3 ECC Status Register
Name: ECC_SR
Access: Read-only
• RECERR: Recoverable Error
0 = No Errors Detected
1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple u ncorrected errors
were detected
• ECCERR: ECC Error
0 = No Errors Detected
1 = A single bit error occurred in the ECC bytes.
Read both ECC Parity and ECC NParity register, the error occurred at the location which contains a 1 in the least signifi-
cant 16 bits.
• MULERR: Multiple Error
0 = No Multiple Errors Detected
1 = Multiple Errors Detected
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––MULERRECCERRRECERR
227
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
24.4.4 ECC Parity Register
Name: ECC_PR
Access: Read-only
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
• BITADDR
During a page read, this value contains the corrupte d bit offset where an e rror occurred, if a sing le error was d etected. If
multiple errors were detected, this value is meaningless.
• WORDADDR
During a page read, this value contains the word address (8-bit or 16-bit word depending on the memory plane organiza-
tion) where an error occu rred, if a single error was detected. If multiple errors were detected, this value is meaningless.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
WORDADDR
76543210
WORDADDR BITADDR
228 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
24.4.5 ECC NParity Register
Name: ECC_NPR
Access: Read-only
• NPARITY:
Once the entire main area of a page is written with data, the register content must be stored at any free location of the
spare area.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
NPARITY
76543210
NPARITY
229
6222F–ATARM–10-Jan-11
SAM7SE512/256/32 Preliminary
25. AT91SAM Boot Program
25.1 Overview The Boot Program integrates different programs permitting download and/or upload into the dif-
ferent memori es of the product.
First, it initializes the Debug Unit serial port (DBGU ) an d th e USB Device Port.
SAM-BA® Boot is then executed. It waits for transactions either on the USB de vice, or on the
DBGU serial port.
25.2 Flow Diagram The Boot Program implements the algorithm in Figure 25-1.
Figure 25-1. Boot Program Algorithm Flow Diagram
25.3 Device Initialization
Initialization follows the steps described below:
1. FIQ initialization
1. Stack setup for ARM supervisor mode
2. Setup the Embedded Flash Controller
3. External Clock detection
4. Main oscillator frequency detection if no external clock detected
5. Switch Master Cloc k on Main Oscillator
6. Copy code into SRAM
7. C variable initialization
8. PLL setup: PLL is initialized to generate a 48 MHz clock necessary to use the USB
Device
9. Disable of the Watchdog and enab le of the user reset
10. Initialization of the USB Device Por t
11. Jump to SAM-BA Boot sequence (see “SAM-BA Boot” on page 230)
Device
Setup
AutoBaudrate
Sequence Successful ?
Run SAM-BA Boot Run SAM-BA Boot
USB Enumeration
Successful ?
Yes Yes
No
No
230 6222F–ATARM–10-Jan-11
SAM7SE512/256/32 Preliminary
25.4 SAM-BA Boot The SAM-BA boot principle is to:
– Check if USB Device enumeration has occurred
– Check if the AutoBaudrate seq uence has succeeded (see Figure 25-2)
Figure 25-2. AutoBaudrate Flow Diagram
– Once the communication interface is identified, the application runs in an infinite
loop waiting for different commands as in Table 25-1.
Device
Setup
Character '0x80'
received ? No
Yes
Character '0x80'
received ? No
Yes
Character '#'
received ?
Yes
Run SAM-BA Boot
Send Character '>'
No
1st measurement
2nd measurement
Test Communication
UART operational
231
6222F–ATARM–10-Jan-11
SAM7SE512/256/32 Preliminary
• Write commands: Write a byte (O), a halfword (H) or a word (W) to the target.
–Address: Address in he xadecimal.
–Value: Byte, halfword or word to write in he xadecimal.
–Output: ‘>’.
• Read commands: Read a byte (o), a halfword (h) or a word (w) from the target.
–Address: Address in hexadecimal
–Output: The byte, halfword or word read in hexadecimal following by ‘>’
• Send a file (S): Send a file to a specified address
–Address: Address in hexadecimal
–Output: ‘>’.
Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the
end of the command execution.
• Receive a file (R): Receive data into a file from a specified addr ess
–Address: Address in hexadecimal
–NbOfBytes: Number of bytes in hexadecimal to rece ive
–Output: ‘>’
•Go (G): Jump to a specified address and execute the code
–Address: Address to jump in hexadecimal
–Output: ‘>’
• Get Version (V): Return the SAM-BA boot version
–Output: ‘>’
25.4.1 DBGU Serial Port
Communication is performed through the DBGU seri al port initialized to 115200 Baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal
performing this protocol can be used to send the application file to the target. The size of the
binary file to send depends on the SRAM size embedded in the product. In all cases, the size of
Table 25-1. Commands Available through the SAM-BA Boot
Command Action Argument(s) Example
O write a byte Address, Value# O200001,CA#
o read a byte Addr ess,# o200001,#
H write a half word Address, Value# H200002,CAFE#
h read a half word Address,# h200002,#
W write a wor d Ad dress, Value# W200000,CAFEDECA#
w read a word Address,# w200000,#
S send a file Address,# S200000,#
R receive a file Address, NbOfBytes# R200000,1234#
G go Address# G200200#
V display version No argument V#
232 6222F–ATARM–10-Jan-11
SAM7SE512/256/32 Preliminary
the binary file must be lower than the SRAM size because the Xmodem protocol requires some
SRAM memory to work.
25.4.2 Xmodem Protocol
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-charac-
ter CRC-16 to guarantee detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver report successful
transmission . E ach blo ck of th e tra n sfe r loo ks like :
<SOH><blk #><255-blk #><--128 data bytes --><ch e cks um > in w hic h:
– <SOH> = 01 hex
– <blk #> = bin ary number, starts at 01, increme nts b y 1, and wr aps 0FFH t o 00H (not
to 01)
– <255-blk #> = 1’s complement of the blk#.
– <checksum> = 2 bytes CRC16
Figure 25-3 shows a transmission using this protocol.
Figure 25-3. Xmodem Transfer Example
25.4.3 USB Device Port
A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier
in the device initialization procedure with PLLB configuration.
The device uses the USB communication device class (CDC) drivers to take advantage of the
installed PC RS-232 software to talk over the USB. The CDC class is implemented in all
releases of Windows®, from Windows 98SE to Windows XP®. The CDC document, available at
www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM
ports.
The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are
used by the host operating system to mount the correct driver. On Windows systems, the INF
files contain the correspondence between vendor ID and product ID.
Host Device
SOH 01 FE Data[128] CRC CRC
C
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
233
6222F–ATARM–10-Jan-11
SAM7SE512/256/32 Preliminary
25.4.3.1 Enumeratio n Process
The USB protocol is a master/slave protocol. This is the host that starts the enumeration send-
ing requests to the device through the control endpoint. The device handles standar d requests
as defined in the USB Specification.
The device also handles some class requests defined in the CDC class.
Unhandled request s are STALLed.
25.4.3.2 Communication Endpoints
There are two communication endpoints and endpoin t 0 is used for the enumeration process.
Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-
BA Boot commands are sent by the ho st thr ough the endp oint 1 . If r equire d, the message is split
by the host into several data payloads by the host driver.
If the command requir es a response, the host can send IN transactions to pick up the response.
25.5 Hardware and Software Constraints
• SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM f or variables and
stacks. The remaining available size for the user code is 24576 bytes for SAM7SE512/256,
8192 bytes for SAM7SE32.
– The SAM7SE512/256 user area extends from address 0x202000 to address
0x208000.
– The SAM7SE32 user area extends from address 0x201400 to address 0x201C00.
• USB requirements:
– 18.432 MHz Quart z
Table 25-2. Handled Standard Requests
Request Definition
GET_DESCRIPTOR Re turns the current device configuration value.
SET_ADDRESS Sets the device address for all future device access.
SET_CONFIGURATION Sets the device configuration.
GET_CONFIGURATION Returns the current device configuration value.
GET_STATUS Returns status for the specified recipient.
SET_FEATURE Used to set or enable a specific feature.
CLEAR_FEATURE Used to cle ar or dis able a specific feature.
Table 25-3. Handled Class Requests
Request Definition
SET_LINE_CODING Configures DTE rate, stop bits, parity and number of
character bits.
GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of
character bits.
SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device
is now present.
234 6222F–ATARM–10-Jan-11
SAM7SE512/256/32 Preliminary
Table 25-4. Pins Driven during Boot Program Execution
Peripheral Pin PIO Line
DBGU DRXD PA9
DBGU DTXD PA10
235
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
26. Peripheral DMA Controller (PDC)
26.1 Overview The Peripheral DMA Controller (PDC) transfers data between on- chip serial peripherals such as
the UART, USART, SSC, SPI, MCI an d the on- and off-chip memories. Using the Peripheral
DMA Controller avoi ds processor intervention and re moves the processor interrupt-hand ling
overhead. This significantly reduces the number of clock cycles required for a data transfer and,
as a result, improve s the performance of the microcontroller and makes it more power efficient.
The PDC channels are implemented in pairs, each pair being dedicated to a particular periph-
eral. One channel in the pair is dedicated to the receiving channel and one to the transmitting
channel of each UART, USART, SSC and SPI.
The user interface of a PDC channel is integrated in the memory space of each peripheral. It
contains:
• two 32-bit memory pointer registers (sen d and receive)
• two 16-bit transfer count register (send and receive)
• two 32-bit register for next memory pointer (send and receive)
• two 16-bit register for next transfer count (send and receive)
The peripheral triggers PDC transfers using transmit and receive signals. When the pro-
grammed data is transferred, an end of transfer interrupt is generated by the corresponding
peripheral.
26.2 Block Diagram
Figure 26-1. Block Diagram
Control
PDC Channel 0
PDC Channel 1
THR
RHR
Control Status & Control
Peripheral Peripheral DMA Controller
Memory
Controller
236 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
26.3 Functional Description
26.3.1 Configuration
The PDC channels use r interface ena bles the user to con figure and contr ol the data t ransfers for
each channel. The user interface of a PDC cha nnel is integrated into the user interface of the
peripheral (offset 0x100), which it is related to.
Per peripheral, it contains four 32-bit Pointer Registers (RPR, RNPR, TPR, and TNPR) and four
16-bit Counter Registers (RCR, RNCR, TCR, and TNCR).
The size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter
register, and it is possible, at any moment, to read the number of transfers left for each channel.
The memory base address is configured in a 32-bit memory pointer by defining the location of
the first address to access in the memory. It is possible, at any moment, to read the location in
memory of the current transfer and the number of remaining transfers. The PDC has dedicated
status registers which indicate if the transfer is enabled or disabled for each channel. The status
for each channel is lo cated in the peripheral status register. T ransfers can be enabled and/or
disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC Transfer Control Register.
These control bits enable reading the pointer and counter registers safely without any risk of
their changing between both reads.
The PDC sends status flags to the peripheral visible in its status-register (ENDRX, ENDTX,
RXBUFF, and TXBUFE).
ENDRX flag is set when the PERIPH_RCR register reaches zero.
RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
ENDTX flag is set when the PERIPH_TCR register reaches zero.
TXBUFE flag is set when both PERIPH _TCR and PERIPH_TNCR reach zero.
These status flags are described in the peripheral status register.
26.3.2 Memory Pointers
Each peripheral is connected to the PDC by a receiver data channel and a transmitter data
channel. Each channel has an internal 32-bit memory pointer. Each memory pointer points to a
location anywhere in the memory space (on-chip memory or external bus interface memory).
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented
by 1, 2 or 4, respectively for peripheral transfers.
If a memory pointer is reprogram med while the PDC is in operation, the transfer address is
changed, and th e PDC pe rforms transfers using the new addr es s.
26.3.3 Transfer Counters
There is one internal 16-bit transfer counter for each channel used to count the size of the block
already transferred by its associated peripheral. These counters are decremented after each
data transfer. When the counter r eaches zero, the tra nsfer is comp lete an d the PDC stops trans-
ferring data.
If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the
related peripheral end flag.
237
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
If the counter is reprogrammed while the PDC is operating, the number of transfers is updated
and the PDC counts transfers from the new value.
Programming the Next Counter/Pointer registers chains the buffers. The counters are decre-
mented after each data transfer as stated above, but when the transfer counter reaches zero,
the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to
re-enable the triggers.
For each channel, two status bits indicate the end of the current buffer (ENDRX, ENDTX) and
the end of both current and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to
the peripheral status register and can trigger an interrupt request to the AIC.
The peripheral en d flag is automatically clea red when one of the cou nter-registers (Cou nter or
Next Counter Register) is written.
Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero.
26.3.4 Data TransfersThe peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals.
When the peripheral r eceives an external chara cter, it sends a Receive Ready signal to the PDC
which then requests access to the system bus. When access is granted, the PDC starts a read
of the peripheral Receive Holding Register (RHR) and then trigger s a writ e in the memory.
After each transfer, the re levant PDC memory pointer is incremented and the number of trans-
fers left is decremented. When the memory block size is reached, a signal is sent to the
peripheral and the transfer stops.
The same procedure is followed, in reverse, for t ransmit transfers.
26.3.5 Priority of PDC Transfer Requests
The Peripheral DMA Controller handles transfer requests from the channel according to priori-
ties fixed for each product.These priorities are defined in the product datasheet.
If simultaneous request s of the same type (receiver or transmitte r) occur on identical peripher-
als, the priority is determined by the numbering of the peripherals.
If transfer requests are not simultaneous, they are treated in the order they occurred. Requests
from the receivers are handled first and then followed by transmitter requests.
238 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
26.4 Peripheral DMA Controller (PDC) User Interface
Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc).
Table 26-1. Register Mapping
Offset Register Register Name Read/Write Reset
0x100 Receive Pointer Register PERIPH(1)_RPR Read/Write 0x0
0x104 Receive Counter Register PERIPH_RCR Read/Write 0x0
0x108 Transmit Pointer Regi ster PERIPH_TPR Read/Write 0x0
0x10C Transmit Counter Register PERIPH_TCR Read/Write 0x0
0x110 Receive Next Pointer Register PERIPH_RNPR Read/Write 0x0
0x114 Receive Next Counter Register PERIPH_RNCR Read/W rite 0x0
0x118 Transmit Next Pointer Register PERIPH_TNPR Read/Write 0x0
0x11C Transmit Next Counter Register PERIPH_TNCR Read/Write 0x0
0x120 PDC Transfer Control Register PERIPH_PTCR Write-only -
0x124 PDC Transfer Status Register PERIPH_PTSR Read-only 0x0
239
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
26.4.1 PDC Receive Pointer Register
Name: PERIPH_RPR
Access: Read/Write
• RXPTR: Receive Pointer Address
Address of the next receive transfer.
26.4.2 PDC Receive Counter Register
Name: PERIPH_RCR
Access: Read/Write
• RXCTR: Receive Counter Value
Number of receive transfers to be performed.
31 30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
76543210
RXPTR
31 30 29 28 27 26 25 24
--
23 22 21 20 19 18 17 16
--
15 14 13 12 11 10 9 8
RXCTR
76543210
RXCTR
240 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
26.4.3 PDC Transmit Pointer Register
Name: PERIPH_TPR
Access: Read/Write
• TXPTR: Transmit Pointer Address
Address of the tr ansmit buffer.
26.4.4 PDC Transmit Counter Register
Name: PERIPH_TCR
Access: Read/Write
• TXCTR: Transmit Counter Value
TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral data transfer is stopped.
31 30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
76543210
TXPTR
31 30 29 28 27 26 25 24
--
23 22 21 20 19 18 17 16
--
15 14 13 12 11 10 9 8
TXCTR
76543210
TXCTR
241
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
26.4.5 PDC Receive Next Pointer Register
Name: PERIPH_RNPR
Access: Read/Write
• RXNPTR: Receive Next Pointer Address
RXNPTR is the address of the next buffer to fill with received data when the current buffer is full.
26.4.6 PDC Receive Next Counter Register
Name: PERIPH_RNCR
Access: Read/Write
• RXNCR: Receive Next Counter Value
RXNCR is the size of the next buffer to receive.
31 30 29 28 27 26 25 24
RXNPTR
23 22 21 20 19 18 17 16
RXNPTR
15 14 13 12 11 10 9 8
RXNPTR
76543210
RXNPTR
31 30 29 28 27 26 25 24
--
23 22 21 20 19 18 17 16
--
15 14 13 12 11 10 9 8
RXNCR
76543210
RXNCR
242 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
26.4.7 PDC Transmit Next Pointer Register
Name: PERIPH_TNPR
Access: Read/Write
• TXNPTR: Transmit Next Pointer Address
TXNPTR is the address of the next buffer to transmit when the current buffer is empty.
26.4.8 PDC Transmit Next Counter Register
Name: PERIPH_TNCR
Access: Read/Write
• TXNCR: Transmit Next Counter Value
TXNCR is the size of the next buffer to transmit.
31 30 29 28 27 26 25 24
TXNPTR
23 22 21 20 19 18 17 16
TXNPTR
15 14 13 12 11 10 9 8
TXNPTR
76543210
TXNPTR
31 30 29 28 27 26 25 24
--
23 22 21 20 19 18 17 16
--
15 14 13 12 11 10 9 8
TXNCR
76543210
TXNCR
243
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
26.4.9 PDC Transfer Control Register
Name: PERIPH_PTCR
Access: Write-only
• RXTEN: Receiver Transfer Enable
0 = No effect.
1 = Enables the receiver PDC transfer requests if RXTDIS is not set.
• RXTDIS: Receiver Transfer Disable
0 = No effect.
1 = Disables the receiver PDC transfer requests.
• TXTEN: Transmitter Transfer Enable
0 = No effect.
1 = Enables the transmitter PDC transfer requests.
• TXTDIS: Transmitter Transfer Disable
0 = No effect.
1 = Disables the tran smitter PDC transfer requests.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––TXTDISTXTEN
76543210
––––––RXTDISRXTEN
244 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
26.4.10 PDC Transfer Status Register
Name: PERIPH_PTSR
Access: Read-only
• RXTEN: Receiver Transfer Enable
0 = Receiver PDC transfer requests are disabled.
1 = Receiver PDC tra nsfer requests are enabled.
• TXTEN: Transmitter Transfer Enable
0 = Transmitter PDC transfer requests are disabled.
1 = Transmitter PDC transfer requests are enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––TXTEN
76543210
–––––––RXTEN
245
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27. Advanced Interrupt Controller (AIC)
27.1 Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored
interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to sub-
stantially reduce the software and real-time overhead in handling internal and external
interrupts.
The AIC drives the nFI Q (fa st in te rr upt re que st) an d t he n IRQ (stand ar d inter rup t requ est) in puts
of an ARM pro cesso r. Inp uts o f the AI C are e ither inter nal pe riph eral in terrup ts or exter nal int er-
rupts coming from the pr oduct's pins.
The 8-level Priority Contro ller allows the user to def ine the pr iorit y for each inte rrupt source, th us
permitting higher priority interrupts to be serviced even if a lowe r priority interrupt is being
treated.
Internal interrupt sources can be programmed to be level sensitive or edge triggered. External
interrupt sources can be programm ed to be positive-edge or negative-edge trigge red or high-
level or low-level sensitive.
The fast forcing feature redirects any internal or external interrupt source to provide a fast inter-
rupt rather than a normal interrupt.
27.2 Block Diagram
Figure 27-1. Block Diagram
AIC
APB
ARM
Processor
FIQ
IRQ0-IRQn
Embedded
PeripheralEE
Peripheral
Embedded
Peripheral
Embedded
Up to
Thirty-two
Sources nFIQ
nIRQ
246 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.3 Application Block Diagram
Figure 27-2. Description of the Application Block
27.4 AIC Detailed Block Diagram
Figure 27-3. AIC Detailed Block Diagram
27.5 I/O Line Description
Advanced Interrupt Controller
Embedded Peripherals External Peripherals
(External Interrupts)
Standalone
Applications RTOS Drivers Hard Real Time Tasks
OS-based Applications
OS Drivers
General OS Interrupt Handler
FIQ
PIO
Controller
Advanced Interrupt Controller
IRQ0-IRQn PIOIRQ
Embedded
Peripherals
External
Source
Input
Stage
Internal
Source
Input
Stage
Fast
Forcing Interrupt
Priority
Controller
Fast
Interrupt
Controller
ARM
Processor
nFIQ
nIRQ
Power
Management
Controller
Wake Up
User Interface
APB
Processor
Clock
Table 27-1. I/O Line Description
Pin Name Pin Description Type
FIQ Fast Interrupt Input
IRQ0 - IRQn Interrupt 0 - Interrupt n Input
247
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.6 Product Dependencies
27.6.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO control-
lers. Depending on the features of the PIO cont roller used in the product, the pins must be
programmed in accordance with their assigned interrupt function . This is not applicable when
the PIO controller used in the product is transparent on the input path.
27.6.2 Power Management
The Advanced Interrupt Contro ller is continuously clocked. The Power Man agement Controller
has no effect on the Advanced Interr upt Controller behavior.
The assertion o f the Advanced Interr upt Controller outpu ts, either nIRQ or n FIQ, wakes up th e
ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to
wake up the processor without asserting the interrupt line of the processor, thus providing syn-
chronization of the processor on an event.
27.6.3 Interrupt Sources
The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the
Interrupt Sou rc e 0 ca nn ot be use d .
The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring
of the system peripheral interrupt lines, such as the System Timer, the Real Tim e Clock, the
Power Management Controller and the Memory Controller. When a system interrupt occurs, the
service routine must firs t distinguish the cause of th e interrupt. This is perfor med by reading suc-
cessively the statu s re gis ter s of th e ab o ve me n tio ne d sys te m pe rip h er als .
The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an emb edded
user peripheral or to external interrupt lines. The external interrupt lines can be connected
directly, or thro ug h th e PIO Cont ro ller .
The PIO Controllers are considered as user peripherals in the scope of interrupt handling.
Accordingly, the PIO Controller interrupt lines are connected t o the Interrupt Sources 2 to 31.
The peripheral identification defined at the product level corresponds to the interrupt source
number (as well as the bit number controlling the clock of the peripheral). Consequently, to sim-
plify the description of the functional operations and the user interface, the interrupt sources are
named FIQ, SYS, and PID2 to PID31.
248 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.7 Functional Description
27.7.1 Interrupt Source Control
27.7.1.1 Interrupt Source Mode
The Advanced Interrupt Controller in dependently programs each interrupt source. The SRC-
TYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt
condition of each source.
The internal int errupt sources wired on th e interr upt ou tputs of the embe dded per iphera ls can be
programmed either in level-sensitive mode or in edge-triggered mode. The active level of the
internal inte r ru pt s is not imp o rta n t for the user.
The external interru pt sources can be programmed ei ther in high level-sensitive or low level-se n-
sitive modes, or in positive edge-triggered or negative edge-triggered modes.
27.7.1.2 Interrupt Source Enabling
Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the
command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt
Disable Command Register). This set of regist ers condu cts enab ling or disab ling in one in struc-
tion. The interr upt mask can be re ad in the AIC_IMR registe r. A disabled interru pt does not affect
servicing of othe r int er ru pt s.
27.7.1.3 Interrupt Clearing and Setting
All interrupt sources programme d to be edge-triggered (including the FIQ in source 0) can be
individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clear-
ing or setting interrupt sources programmed in level-sensitive mode has no effect.
The clear operation is perfunctory, as the software must perform an action to reinitialize the
“memorization” circuitry activated when the source is progra mmed in edge-triggered mode.
However, the set operation is available for auto-test or software debug purposes. It can also be
used to execute an AIC-implementation of a software interrupt.
The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector
Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is
affected by this operation. (See “Priority Controller” on page 252.) The automatic clear reduces
the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note
that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature
enabled as it is considered uniquely as a FIQ source. (For further details, See “Fast Forcing” on
page 256.)
The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.
27.7.1.4 Interrupt Status
For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its
mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources,
whether masked or not.
The AIC_ISR register reads the n umber of the cur rent int errupt (see “Prior ity Controller ” on page
252) and the register AIC_ CISR gives an image of the signals nIRQ and nFIQ driven on the
processor.
Each status referred to above can be used to optimize the interrupt handling of the systems.
249
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.7.1.5 Internal Interrupt Source Input Stage
Figure 27-4. Internal Interrupt Source Input Stage
27.7.1.6 External Interrupt Sourc e In pu t Stag e
Figure 27-5. External Interrupt Source Input Stage
Edge
Detector
ClearSet
Source i AIC_IPR
AIC_IMR
AIC_IECR
AIC_IDCR
AIC_ISCR
AIC_ICCR
Fast Interrupt Controller
or
Priority Controller
FF
Level/
Edge
AIC_SMRI
(SRCTYPE)
Edge
Detector
ClearSet
Pos./Neg.
AIC_ISCR
AIC_ICCR
Source i
FF
Level/
Edge
High/Low AIC_SMRi
SRCTYPE
AIC_IPR
AIC_IMR
AIC_IECR
AIC_IDCR
Fast Interrupt Controller
or
Priority Controller
250 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.7.2 Interrupt Latencies
Global interrup t latencies depend on several parameters, including:
• The time the software masks the interrupts.
• Occurrence, either at the processor level or at the AIC level.
• The execution time of the ins truction in pr ogres s whe n the inte rrupt occ ur s.
• The treatment of higher priority interrupts and the resynchronization of the hardware signals.
This section addresses only the hardware resynchronizations. It gives details of the latency
times between th e event on an ext ernal int errupt leading in a valid int errupt (edge or level ) or the
assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the pro-
cessor. The resynchronization time depends on the programming of the interrupt source and on
its type (internal or external). For the standard interrupt, resynchronization times are given
assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt
sources.
27.7.2.1 External Interrupt Edge Triggered Source
Figure 27-6. External Interrupt Edge Triggered Source
Maximum FIQ Latency = 4 Cycles
Maximum IRQ Latency = 4 Cycles
nFIQ
nIRQ
MCK
IRQ or FIQ
(Positive Edge)
IRQ or FIQ
(Negative Edge)
251
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.7.2.2 External Interrupt Level Sensitive Source
Figure 27-7. External Interrupt Level Sensitive Source
27.7.2.3 Internal Interrupt Edge Triggered Source
Figure 27-8. Internal Interrupt Edge Triggered Sour ce
27.7.2.4 Internal Interrupt Level Sensitive Source
Figure 27-9. Internal Interrupt Level Sensitive Sour ce
Maximum IRQ
Latency = 3 Cycles
Maximum FIQ
Latency = 3 cycles
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level)
nIRQ
nFIQ
MCK
nIRQ
Peripheral Interrupt
Becomes Active
Maximum IRQ Latency = 4.5 Cycles
MCK
nIRQ
Maximum IRQ Latency = 3.5 Cycles
Peripheral Interrupt
Becomes Active
252 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.7.3 Normal Interrupt
27.7.3.1 Priority Controller
An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt
conditions occurring o n the interrupt sources 1 to 31 (except for those program med in Fast
Forcing).
Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writ-
ing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the
highest priority and level 0 the lowest.
As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR
(Source Mode Re gist er) , t he nIRQ line is asser ted. As a new inte rr up t condit ion mig ht ha ve ha p-
pened on other interrupt sources since the nIRQ has been asserted, the priority controller
determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The
read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider
that the interrupt has been taken into acco unt by the software.
The current pr iority level is defined as the priority level of the current interrupt.
If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read,
the interrupt with the lowest interrupt source number is serviced first.
The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a
higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in
progress, it is delayed until the software indicates to the AIC the end of the current service by
writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the
exit point of the interrupt handling.
27.7.3.2 Interrupt Nesting
The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled
during the service of lower priority interrupts . This requires the inter rupt service routines of th e
lower interrupts to re-enable the interrupt at the processor level.
When an interrupt of a higher priority happens during an already occurring interrupt service rou-
tine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current
execution is interrupte d and the new interrupt service routine should read th e AIC_IVR. At this
time, the current interrupt number and its priority level are pushed into an embedded hardware
stack, so that they are saved and restored when the higher priority interrupt servicing is finished
and the AIC_EOICR is written.
The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt
nestings pursuant to having eight priority levels.
27.7.3.3 Interrupt Vectoring
The interrupt ha ndler addre sses corresponding to each interrupt source ca n be stored in th e reg-
isters AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads
AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the cur-
rent interrupt is returned.
This feature offers a way to branch in one single instruction to the handler corresponding to the
current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus acces-
sible from the ARM interrupt vector at address 0x0000 0018 through the following instruction:
LDR PC,[PC,# -&F20]
253
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
When the processor executes this instruction, it loads the read value in AIC_IVR in its program
counter, thus branching the execution on the correct interrupt handler.
This feature is often not used when the application is based on an operating system (either real
time or not). Operating systems often have a single entry point for all the interrupts and the first
task performed is to discern the source of the interrupt.
However, it is strongly recommended to port the oper ating system on AT91 products by suppor t-
ing the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt
source to be handled by the operat ing system at the address of its interrupt handler. When doing
so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very
fast handler and not onto the operating system’s general interrupt handler. This facilitates the
support of hard r eal-time tasks (inp ut/outputs of voice/audio buffers a nd software periph eral han-
dling) to be handled efficiently and independently of the application running under an operating
system.
27.7.3.4 Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is
assumed that the programmer understands the architecture of the ARM processor, and espe-
cially the processor interrupt modes and the associated status bits.
It is assumed that:
1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are
loaded with corresponding interrupt service routine addresses and in terrupts are
enabled.
2. The instruction at the ARM interrupt exception vector address is required to work with
the vectoring
LDR PC, [PC, # -&F20]
When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:
1. The CPSR is stored in SPSR_irq, the current value of the Program Coun ter is loaded in
the Interrupt link register (R14_irq) and the Prog ram Counter (R15) is lo aded with 0x18.
In the follo wing cycl e during fetch at a ddress 0x1C, the ARM core adjusts R14_ irq, de c-
rementing it by four.
2. The ARM core enters Interrupt mode, if it has not already done so.
3. When the instruction loaded at address 0x18 is executed, the program counter is
loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects:
– Sets the current inter rupt to be the pending and enabled interrupt with the highest
priority. The current level is the priority level of the current interrupt.
– De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR
must be read in order to de-assert nIRQ.
– Automatically clears the interrupt, if it has been progr ammed to be edge-triggered.
– Pushes the current level and the current interrupt numbe r on to the stack.
– Returns the value written in the AIC_ SVR corresponding to the current interrupt.
4. The previous step has the effect of branching to the corresponding interrupt service
routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link
register must be decreme nted by four when it is sa ved if it is to be rest ored d ire ctly int o
the program counter at the end of the interrupt. For example, the in struction SUB PC,
LR, #4 may be used.
254 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-
assertion of the nIRQ to be taken into account by the core. This can happen if an inter-
rupt with a higher priority than the current interrupt occurs.
6. The interrupt handler can then proceed as required, saving the registers that will be
used and restoring them at the end. During this phase, an interrupt of higher priority
than the current level will restart the sequence from step 1.
Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared dur-
ing this phase.
7. The “ I” bit in CPSR m ust be set in order t o mask inte rrupts before exiting t o ensur e that
the interrupt is completed in an orderly manner.
8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indi-
cate to the AIC that the current interrupt is finished. This causes the current level to be
popped from the stack, restoring the previous current level if one exists on the stack. If
another interrupt is pending, with lower or equal priority than the old current level but
with higher priority than the ne w current le v e l, the nIRQ line is re-asserted, but the inter-
rupt sequence does not immediately start because the “I” bit is set in the core.
SPSR_irq is restored. Finally, the save d value of the link register is restored directly into
the PC. This has the effect of returning fro m the int er rupt to what ever was being exe -
cuted before, and of loading the CPSR with the stored SPSR, masking or unmasking
the interrupts depending on the state saved in SPSR_irq.
Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of
masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored,
the mask instruction is completed (interrupt is masked ).
255
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.7.4 Fast Interrupt
27.7.4.1 Fast Interrupt Source
The interrupt so urce 0 is the only source which can ra ise a fast inter rupt request to the processor
except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the
product, either directly or through a PIO Con troller.
27.7.4.2 Fast Interrupt Control
The fast interrupt logi c of the AIC has no priority controller. Th e mode of interrupt source 0 is
programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads
what has been written. The field SRCTYPE of AIC_SMR0 enables programming the fast inter-
rupt source to be positive-edg e triggered or negative-edge trigg ered or high-level sensitive or
low-level sensitive
Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt
Disable Command Register) respectively enables and disables the f ast interrupt. Th e bit 0 of
AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is ena bled or disabled.
27.7.4.3 Fast Interrupt Vectoring
The fast interrupt handler address can be stored in AIC_SVR0 (Source Ve ctor Register 0). Th e
value written into th is regist er is retu rn ed whe n the pr ocessor r ead s AIC_ FVR (Fast Vect o r Reg-
ister). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR
is mapped at the ab solute address 0xFFFF F104 and thus a ccessible from the ARM fast inter-
rupt vector at address 0x0000 001C through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction it loads the value read in AIC_FVR in its program
counter, thus branching the execution on the fast interrupt handler. It also automatically per-
forms the clear of the fast in terrupt source if it is programmed in edge-triggered mode.
27.7.4.4 Fast Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is
assumed that the programmer understands the architecture of the ARM processor, and espe-
cially the processor interrupt modes and associated status bits.
Assuming that:
1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with
the fast interrupt service routine address, and the interrupt source 0 is enabled.
2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector
the fast interrupt:
LDR PC, [PC, # -&F20]
3. The user does not need nested fast interrupts.
When nFIQ is asserte d, if the bit “F ” of CPSR is 0, the sequ e nce is:
1. The CPSR is stored in SPSR_f iq, t he cur rent value of the pr og ram counter is loaded in
the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In
the following cycle, during f etch at address 0x20, the ARM core adjusts R14_fiq, decre-
menting it by four.
2. The ARM core enters FIQ mode.
3. When th e instruction loaded at addr ess 0x1 C is executed, the program counter is
loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati-
256 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
cally clearing the fast interrupt, if it has been programmed to be edge triggered. In this
case only, it de-asserts the nFIQ line on the processor.
4. The p revious ste p enable s branching to th e corresponding interrupt service routine. It is
not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts
are not needed.
5. The Interrupt Handler can then proceed as requir ed. It is not necessary to save regis-
ters R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to
R13 are banked. The other registers, R0 to R7, m ust be saved before being used, and
restored at th e en d (b efore the next step). Note that if the fast interrupt is programmed
to be level sensitive, the source of the interrupt must be cleared during this phase in
order to de-assert the interrupt source 0.
6. Finally, the Link Register R14_f iq is restored into the PC after decrementing it by four
(with instruction SUB PC, LR, #4 for example). This has the effect of returning from
the interrupt to whatever was being executed before, loading the CPSR with the SPSR
and masking or unmasking the fast interrupt depending on the state saved in the
SPSR.
Note: The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask
FIQ interrupts when the mask instruction was interrupted. Hence whe n the SPSR is restored, the
interrupted instruction is completed (FIQ is masked).
Another way to handle the fast interrupt is to map the interrupt service routine at the address of
the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must
be performed at the very beginning of the handler operation. However, this method saves the
execution of a branch instruction.
27.7.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal
Interrupt source on the fast interrupt controller.
Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER)
and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an
update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each inter-
nal or external interrupt source.
When Fast Forcing is disabled, the interrupt sources are handled as described in the previous
pages.
When Fast Forcing is enab led, the edge/level progra mming and, in certain cases, edg e detec-
tion of the interrupt source is still active but the source cannot trigger a normal interrupt to the
processor and is not seen by the priority handler.
If the interrupt source is programmed in level-sensitive mode and an active level is sampled,
Fast Forcing results in the assertion of the nFIQ line to the core.
If the interrupt source is programmed in edge-triggered m ode and an active edge is detected,
Fast Forcing results in the assertion of the nFIQ line to the core.
The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Reg-
ister (AIC_IPR).
The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0
(AIC_SVR0), whatever the source of the fast interrupt may be. Th e read of the FVR does not
clear the Source 0 when the fast forcing feature is used and the interrupt source should be
cleared by writing to the Interrupt Clear Command Register (AIC_ICCR).
257
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
All enabled and pending in terrup t sources t hat have t he fast forcing feat ure enab led and tha t are
programmed in edge- trigger ed mode must b e cleared by writing t o the I nterru pt Clear Comm and
Register. In doing so, they are cleared independently and thus lost interrupts are prevented.
The read of AIC_IVR doe s not clear the source that has the fast forcing feature enabled.
The source 0, reserved to the fast interrupt, continues ope rating normally and becomes one of
the Fast Interrupt sources.
Figure 27-10. Fast Forcing
Source 0 _ FIQ Input Stage
Automatic Clear
Input Stage
Automatic Clear
Source n
AIC_IPR
AIC_IMR
AIC_FFSR
AIC_IPR
AIC_IMR
Priority
Manager
nFIQ
nIRQ
Read IVR if Source n is the current interrupt
and if Fast Forcing is disabled on Source n.
Read FVR if Fast Forcing is
disabled on Sources 1 to 31.
258 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.7.5 Protect Mode The Protect Mode perm its reading the Interrup t Vector Register without performing the associ-
ated automatic operations. This is necessary when working with a debug system. When a
debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applica-
tions and updates the opened windows, it might read the AIC User Interface and thus the IVR.
This has undesirable consequences:
• If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
• If there is no enabled pending interrupt, the spurious vector is returned.
In either case, an End of Interrupt command is necessary to acknowledge and to restore the
context of the AIC. This operation is generally not performed by the debug system as the debug
system would become strongly intr usive and cause the application to enter an undesired state.
This is avoided by using the Pro tect Mode. Writing DBG M in AIC_DCR (Debug Control Registe r)
at 0x1 enables the Protect Mode.
When the Protect Mode is enabled, the AIC performs in terrupt stacking only when a wr ite access
is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary
data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the
Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is
written.
An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the
AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommende d to
not stop the proc essor between the rea d and the write of AIC_IVR of th e interrupt service rout ine
to make sure the debugger does not modify the AIC context.
To summarize, in normal operating mode, the read of AIC_IVR performs the following opera-
tions within the AI C:
1. Calculates active interrupt (higher than current or spurious).
2. Determines and returns the vector of the active interrupt.
3. Memorizes the interrupt.
4. Pushes the current priority level onto the internal stack.
5. Acknowledges the interrupt.
However, while the Protect Mode is activated, only operations 1 to 3 are performed when
AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written.
Software that has been written and debugge d using the Protect Mode runs correctly in Normal
Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can
be removed to optimize the code.
27.7.6 Spurious Interrupt
The Advanced Interrupt Controller features protection against spurious interrupts. A spurious
interrupt is defined as being the assertion of an interrupt source long enough for the AIC to
assert the nIRQ, but no long er present when AIC_IVR is r ead. This is most pro ne to occur when:
• An e xternal interrupt sour ce is programmed in lev el-sensitiv e mode and an activ e le vel occurs
for only a sho rt time.
259
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• An internal interrupt source is programmed in level sensitive and the output signal of the
corresponding embe dded peripheral is activated for a short time. (As in the case for the
Watchdog.)
• An interrupt occurs just a fe w cycles before the software b egins t o mask it, thus re sultin g in a
pulse on the interrupt source.
The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt
source is pending. When this happens, the AIC returns the value stored by the programmer in
AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious
interrupt handle r in AIC_SPU as part of the application, to enable an as fast as possible retur n to
the normal execution flow. This handler writes in AIC_EOICR and performs a return from
interrupt.
27.7.7 G enera l Inte rrupt Ma s k
The AIC features a Gen eral In te rr upt Ma sk bit to preve nt int errup ts f rom rea ch ing the pro cesso r.
Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR
(Debug Control Regi ster) is set. Ho wever, this mask d oes not prevent waking up the p rocessor if
it has entered Idle Mode. This function facilitates synchronizing the processor on a next event
and, as soon as the event occurs, performs subsequent operations without having to handle an
interrupt. It is strong ly re co mm e nd e d to use th is ma sk wi th caution .
260 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8 Advanced Interrupt Controll er (AIC) User Interface
27.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This
permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor
support only an ± 4-Kbyte offset.
27.8.2 Register Mapping
Notes: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset,
thus not pending.
2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet.
Table 27-2. Register Mapping
Offset Register Name Access Reset Value
0000 Source Mode Register 0 AIC_SMR0 Read/Write 0x0
0x04 Source Mode Register 1 AIC_SMR1 Read/Write 0x0
--- --- --- --- ---
0x7C Source Mode Register 31 AIC_SMR31 Read/Write 0x0
0x80 Source Vector Register 0 AIC_SVR0 Read/Write 0x0
0x84 Source Vector Register 1 AIC_SVR1 Read/Write 0x0
--- --- --- --- ---
0xFC Source Vector Regi ster 31 AIC_SVR31 Read/Write 0x0
0x100 I nterrupt Vector Register AIC_IVR Read-only 0x0
0x104 FIQ Interrupt Vector Register AIC_FVR Read-only 0x0
0x108 I nterrupt Status Register AIC_ISR Read-only 0x0
0x10C Interrupt Pending Register(2) AIC_IPR Read-only 0x0(1)
0x110 I nterrupt Mask Register(2) AIC_IMR Read-only 0x0
0x114 Core Interrupt Status Register AIC_CISR Read-only 0x0
0x118 Reserved --- --- ---
0x11C Reserved --- --- ---
0x120 I nterrupt Enable Command Register(2) AIC_IECR Write-only ---
0x124 I nterrupt Disable Command Register(2) AIC_IDCR Write-only ---
0x128 Interrupt Clear Comman d Register(2) AIC_ICCR Write-only ---
0x12C Interrupt Set Command Register(2) AIC_ISCR Write-only ---
0x130 E nd of Interrupt Command Register AIC_EOICR Write-only ---
0x134 Spurious Interrupt Vector Register AIC_SPU Read/Write 0x0
0x138 Debug Control Register AIC_DCR Read/Write 0x0
0x13C Reserved --- --- ---
0x140 Fast Forcing Enable Register(2) AIC_FFER Write-only ---
0x144 Fast Forcing Disable Register(2) AIC_FFDR Write-only ---
0x148 Fast Forcing Status Register(2) AIC_FFSR Read-only 0x0
261
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.3 AIC Source Mode Register
Name: AIC_SMR0..AIC_SMR31
Access: Read/Write
Reset Value: 0x0
• PRIOR: Priority Level
Programs the priority level for all sources except FIQ source (source 0).
The priority level can be between 0 (lowest) and 7 (highest).
The priority level is not used for the FIQ in the related SMR register AIC_SMRx.
• SRCTYPE: Interrupt Source Type
The active level or edge is not programmable for the internal interrupt sources.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– SRCTYPE – – PRIOR
SRCTYPE Internal Interrupt Sources External Interrupt Sources
0 0 High lev el Sensitive Low le vel Sensitive
0 1 Positive edge triggered Negative edge triggered
1 0 High level Sensitive High level Sensitive
1 1 Positive edge triggered Positive edge triggered
262 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.4 AIC Source Vector Register
Name: AIC_SVR0..AIC_SVR31
Access: Read/Write
Reset Value: 0x0
• VECTOR: Source Vector
The user may store in these registers the addresses of the corresponding handler for each interrupt source.
27.8.5 AIC Interrupt Vector Register
Name: AIC_IVR
Access: Read-only
Reset Value: 0x0
• IRQV: Interrupt Vector Register
The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to
the current inte rr u pt .
The Source Vector Register is indexed using the current interrupt number when the Interr upt Vector Register is read.
When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU.
31 30 29 28 27 26 25 24
VECTOR
23 22 21 20 19 18 17 16
VECTOR
15 14 13 12 11 10 9 8
VECTOR
76543210
VECTOR
31 30 29 28 27 26 25 24
IRQV
23 22 21 20 19 18 17 16
IRQV
15 14 13 12 11 10 9 8
IRQV
76543210
IRQV
263
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.6 AIC FIQ Vector Register
Name: AIC_FVR
Access: Read-only
Reset Value: 0 x0
• FIQV: FIQ Vector Register
The FIQ Vector Register contains the vecto r programmed by the user in the Source Vector Register 0. When the re is no
fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
27.8.7 AIC Interrupt Status Register
Name: AIC_ISR
Access: Read-only
Reset Value: 0x0
• IRQID: Current Interrupt Identifier
The Interrupt Status Register returns the current interrupt source number.
31 30 29 28 27 26 25 24
FIQV
23 22 21 20 19 18 17 16
FIQV
15 14 13 12 11 10 9 8
FIQV
76543210
FIQV
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––– IRQID
264 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.8 AIC Interrupt Pending Register
Name: AIC_IPR
Access: Read-only
Reset Value: 0x0
• FIQ , SYS, PID2-PID31: Interrupt Pending
0 = Corresponding int errupt is not pending.
1 = Corresponding interrupt is pending.
27.8.9 AIC Interrupt Mask Register
Name: AIC_IMR
Access: Read-only
Reset Value: 0x0
• FIQ , SYS, PID2-PID31: Interrupt Mask
0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
265
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.10 AIC Core Interrupt Status Register
Name: AIC_CISR
Access: Read-only
Reset Value: 0x0
• NFIQ: NFIQ Status
0 = nFIQ line is deactivated.
1 = nFIQ line is active.
• NIRQ: NIRQ Status
0 = nIRQ line is deactivated.
1 = nIRQ line is active.
27.8.11 AIC Interrupt Enable Command Register
Name: AIC_IECR
Access: Write-only
• FIQ , SYS, PID2-PID3: Interrupt Enable
0 = No effect.
1 = Enables corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––NIRQNIFQ
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
266 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.12 AIC Interrupt Disable Command Register
Name: AIC_IDCR
Access: Write-only
• FIQ , SYS, PID2-PID31: Interrupt Disable
0 = No effect.
1 = Disables corresponding interrupt.
27.8.13 AIC Interrupt Clear Command Register
Name: AIC_ICCR
Access: Write-only
• FIQ , SYS, PID2-PID31: Interrupt Clear
0 = No effect.
1 = Clears corresponding interrupt.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
267
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.14 AIC Interrupt Set Command Register
Name: AIC_ISCR
Access: Write-only
• FIQ , SYS, PID2-PID31: Interrupt Set
0 = No effect.
1 = Sets corresponding interrupt.
27.8.15 AIC End of Interrupt Command Register
Name: AIC_EOICR
Access: Write-only
The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt
treatment.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––––
268 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.16 AIC Spurious Interrupt Vector Register
Name: AIC_SPU
Access: Read/Write
Reset Value: 0x0
• SIQV: Spurious Interrupt Vector Register
The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in
case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
27.8.17 AIC Debug Contr ol Register
Name: AIC_DEBUG
Access: Read/Write
Reset Value: 0x0
• PROT: Protection Mode
0 = The Protection Mode is disabled.
1 = The Protection Mode is enabled .
• GMSK: General Mask
0 = The nIRQ and nFIQ lines are normally controlled by the AIC.
1 = The nIRQ and nFIQ lines are tied to their inactive state.
31 30 29 28 27 26 25 24
SIQV
23 22 21 20 19 18 17 16
SIQV
15 14 13 12 11 10 9 8
SIQV
76543210
SIQV
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––GMSKPROT
269
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.18 AIC Fast Forcin g Enable Register
Name: AIC_FFER
Access: Write-only
• SYS, PID2-PID31: Fast Forcing Enable
0 = No effect.
1 = Enables the fast forcing feature on the corresponding interrupt.
27.8.19 AIC Fast F orcing Disable Register
Name: AIC_FFDR
Access: Write-only
• SYS, PID2-PID31: Fast Forcing Disable
0 = No effect.
1 = Disables the Fast Forcing feature on the corresponding interrupt.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS –
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS –
270 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
27.8.20 AIC Fast Forcing Status Register
Name: AIC_FFSR
Access: Read-only
• SYS, PID2-PID31: Fast Forcing Status
0 = The Fast Forcing feature is disabled on the corresponding interru pt.
1 = The Fast Forcing feature is enabled on the corresponding interrupt.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS –
271
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
28. Clock Generator
28.1 Overview The Clock Generator is made up of 1 PLL, a Main Oscillator, as well as an RC Oscillator.
It provides the following clocks:
• SLCK, the Slow Clock, which is the only permanent clock within the system
• MAINCK is the output of the Main Oscillator
• PLLCK is the output of the Divider and PLL block
The Clock Generator User Interface is embedded within the Power Management Controller and
is described in Section 29.9. However, the Clock Generator registers are named CKGR_.
28.2 Slow Clock RC Oscillator
The user has to take into account the possible drifts of the RC Oscillator. More details are given
in the section “DC Characterist ics” of the product datasheet.
28.3 Main Oscillator
Figure 28-1 shows the Main Oscillator block diagram.
Figure 28-1. Main Oscillator Block Diagram
28.3.1 Main Osc illa t or Connect ions
The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental
crystal. The typical crystal connection is illustrated in Fi gure 28-2. Fo r furt he r det ails on the elec-
trical characteristics of the Main Oscillator, see the section “DC Characteristics” of the product
datasheet.
XIN
XOUT
MOSCEN
Main
Oscillator
Counter
OSCOUNT
MOSCS
MAINCK
Main Clock
Main Clock
Frequency
Counter
MAINF
MAINRDY
SLCK
Slow Clock
Main
Oscillator
272 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 28-2. Typical Crystal Connection
28.3.2 Main Oscillator Startup Time
The startup time of the Main Oscillator is given in the DC Characteristics section of the product
datasheet. The startup time depends on the crystal frequency and decreases when the fre-
quency rises.
28.3.3 M ai n Osc illa t or Co nt rol
To minimize the power required to start up the sy stem, the main oscillator is disabled after reset
and slow clock is selected.
The software enables or disables the main oscillator so as to reduce power consumption by
clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR).
When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit
in PMC_SR is automatically cleared, indicating the main clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a value
corresponding to the startup time of the oscillator. This startup time depends on the crystal fre-
quency connected to the main oscillator.
When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable t he main oscil-
lator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts countin g
down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is
coded with 8 bits, the maximum startup time is about 62 ms.
When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Set-
ting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor.
28.3.4 Main Clock Frequency Counter
The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency
connected to the Main Oscillator. Generally, this value is know n by the system designer; how-
ever, it is useful for the boot program to configure the device with the correct clock speed,
independen tly of th e ap plic at ion .
The Main Clock frequ ency counter starts incrementing at t he Main Clock speed aft er the next ris-
ing edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the MOSCS
bit is set. Then, at the 16th falling edge of Slow Cloc k, the MAINRDY bit in CKGR_MC FR (Main
Clock Frequency Register) is set and the counter stops cou nting. Its value can be re ad in the
MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of
1K
XIN XOUT GND
AT91SAM7SE Microcontroller
273
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be
determined.
28.3.5 Mai n Osc illa t or Bypass
The user can input a clock on the device instead of con necting a crystal. In this case, the user
has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin
under these conditions are given in the product electrical characteristics section. The program-
mer has to be sure to set the OSCBYPASS bit to 1 and the MOSCE N bit to 0 in the Main OSC
register (CKGR_MOR) for the external clock to operate properly.
28.4 Divider and PLL Block
The PLL embeds an input divider to increase the accur acy of the resulting clock signals. How-
ever, the user must respect the PLL minimum input frequency when programming the divider.
Figure 28-3 shows the block diagram of the divider and PLL block.
Figure 28-3. Divider and PLL Block Diagram
28.4.1 PLL Filter The PLL requires connection to an external second-order filter through the PLLRC pin. Figure
28-4 shows a schematic of these filters.
Figure 28-4. PLL Capacitors and Resistors
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of
the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be
found between output signal overshoot and startup time.
Divider
PLLRC
DIV
PLL
MUL
PLLCOUNT
LOCK
OUT
SLCK
MAINCK PLLCK
PLL
Counter
GND
C1
C2
PLL
PLLRC
R
274 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
28.4.2 Divider and Phase Lock Loop Programming
The divider can be set be tween 1 and 255 in steps of 1 . When a divid er field (DIV ) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that
depends on the respective source signal frequency and on the parameters DIV and MUL. The
factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the
corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be
performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in PMC_SR
is automatically cleared. The values written in the PLLCOUNT field in CKGR_PLLR are loaded
in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it
reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the pro-
cessor. The user has to load the number of Slow Clock cycles required to cover the PLL
transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial
state of the PLL and its target frequency can be calculated using a specific tool provided by
Atmel.
275
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29. Power Management Controller (PMC)
29.1 Overview The Power Manage ment Controller (PMC) optimizes p ower consumption by co ntrolling all sys-
tem and user peripheral clocks. The PMC enables/disables the clock inputs to many of the
peripherals and the ARM Processor.
The Power Management Controller provides the following clocks:
• MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating
frequency of the device . It is available to the modules running permanently, such as the AIC
and the Memory Controller.
• Processor Clock (PCK), switched off when entering processor in idle mode.
• Peripheral Clocks, typically MCK, provided to the embedded peripherals ( USART, SSC, SPI,
TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock
names in a product, the Peripheral Clocks are named MCK in the product datasheet.
• UDP Clock (UDPCK), required by USB Device Port operations.
• Programmable Clock Outputs can be selected from the clocks provided by the clock
generator and driven on the PCKx pins.
29.2 Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLL.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The presca ler supp orts t he division by a power of 2 of t he
selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKR DY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a high-speed
clock to a lower one to inform the software when the change is actually done.
Figure 29-1. Master Clock Contr oller
SLCK Master Clock
Prescaler MCK
PRESCSS
MAINCK
PLLCK
To the Processor
Clock Controller (PCK)
PMC_MCKR PMC_MCKR
276 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.3 Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt . The Processor I dle Mode is ac hi eved by disab ling the Pr ocessor Clo ck, wh ich
is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the
product.
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
29.4 USB Clock Controller
The USB Source Clock is the PLL output. If using the USB, the user must program the PLL to
generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on
the USBDIV bit in CKGR_PLLR.
When the PLL output is stable, i.e., the LOCK bit is set:
• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP
bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48
MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
Figure 29-2. USB Clock Controller
29.5 Peripheral Clock Controller
The Power Management Con troller cont r ols the clocks of each embed ded per iph eral by th e way
of the Peripheral Clock Controller. The user can individually enable and disable the Master
Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and Periph-
eral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be
read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, t he clock is imme diate ly st op ped. The p eri phe ral clocks a re
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral
has executed its last programm ed opera tion befor e disabling the clock. This is to avoid data cor-
ruption or erroneous behavior of the system.
USB
Source
Clock UDP Clock (UDPCK)
UDP
USBDIV
Divider
/1,/2,/4
277
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and
PMC_PCSR) is the Perip heral Identifier defined at the product le vel. Generally, the bit nu mber
corresponds to the interrupt source number assigned to the peripheral.
29.6 Pr ogrammable Clock Output Controller
The PMC controls 3 signals to be output on external pins PCKx. Each signal can be indepen-
dently programmed via the PMC_PCKx registers.
PCKx can be independently selected between the Slow clock, the PLL output and the main
clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power
of 2 between 1 and 64 by writ ing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the correspond ing bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks
are given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actu-
ally what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the Programmable Clock before any configuration
change and to re-enable it after the change is actually performed.
29.7 Programming Sequence
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In
some cases it may be advantageous to define a start-up time. This can be achieved by writ-
ing a value in the OSCOU N T field in th e CK GR _M O R regi st er .
Once this register has been correctly configured, the user must wait for MOSCS field in the
PMC_SR register to be set. This can be done either by polling the status register or by wait-
ing the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in
the PMC_IER register.
Code Example:
write_register(CKGR_MOR,0x00000701)
Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles.
So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.
2. Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main oscillator frequency.
This measure can be accomplished via the CKGR_MCFR register .
Once the MAINRDY fi eld is set in CKGR_MCFR register , the user may read t he MAINF fi eld
in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow
clock cycles.
278 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
3. Setting PLL and divider:
All parameters needed to configure PLL and the divider are located in the CKGR_PLLR
register.
The DIV field is used to control divider itself. A value between 0 and 255 can be pro-
grammed. Divider output is divider input divided by DIV parameter. By default DIV
parameter is set to 0 which means that divider is turned off.
The OUT field is used to select the PLL B output frequency range.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0
and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is
PLL input frequency multiplied by (MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before LOCK bit is set in the
PMC_SR register after CKGR_PLLR register has been written.
Once the PMC_PLL register has been written, the user must wait for the LOCK bit to be set
in the PMC_SR register. This can be done either by polling the status register or by waiting
the interrupt line to be raised if the associated interrupt to LOCK has been enabled in the
PMC_IER regis ter. All parameters in CKGR_ PLLR can be program med in a single write
operation. If a t some sta ge o ne of t he following par amete rs, MUL, DI V is m odifi ed, L OCK bit
will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again.
The user is constrained to wait for LOCK bit to be set before using the PLL output clock.
The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the
USB clock(s).
Code Example:
write_register(CKGR_PLLR,0x00040805)
If PLL and divider are enabled, th e PLL input clo ck is the main clock. PLL output clock is PLL
input clock multiplied by 5. Once CKGR_PLLR has been written, LOCK bit will be set after
eight slow clock cycles.
4. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the Master Clock divider source. By default, the selected
clock source is slow clock.
The PRES field is used to control th e Master Clock presca ler. The user ca n choose between
different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by
PRES paramet er. By default , PRES parame ter is set to 1 w hich means t hat master c lock is
equal to slow clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to
be set in the PMC_SR register. This can be done either by pollin g the status register or by
waiting for the inter rupt line to be raised if the a ssociated interrupt to MCKRDY has been
enabled in the PMC_IER register.
The PMC_MCKR register must not be programmed in a single write operation. The pre-
ferred programming sequence for the PMC_MCKR register is as follows:
279
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• If a new value for CSS field corresponds to PLL Clock,
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
• If a new value for CSS field corresponds to Main Clock or Slow Clock,
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY
bit will go low to indicate that the Master Clock an d the Processor Clock are not ready yet.
The user must wait for MCKRDY bit to be set again before using the Master and Processor
Clocks.
Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in
CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again,
LOCK goes high and MCKRDY is set.
While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. F or fur-
ther information, see Section 29.8.2. “Clock Switching Waveforms” on page 281.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The Master Clock is main clock divided by 16.
The Processor Clock is the Master Clock.
5. Selection of Programmable clocks
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and
PMC_SCSR.
Programmable clocks can b e enabled and/ or disabled via the PMC_SCER and PMC_ SCDR
registers. Depending on the system used, 3 Programmable clocks can be enabled or dis-
abled. The PMC_SCSR provides a clear indication as to which Programmable clock is
enabled. By default all Programmable clocks are disabled.
PMC_PCKx registers are used to configure Programmable clocks.
The CSS field is used to select the Programmable clock divider source. Four clock options
are available: main clock, slow clock, PLLCK. By default, the clock source selected is slow
clock.
The PRES field is used to cont rol the Progra mmable clock prescaler. It is possible t o choose
between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler
280 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
input divided by PRES p aramete r. By defa ult, th e PRES pa rameter is set to 1 which m eans
that master clock is equal to slow clock.
Once the PMC_PCKx register has been programmed, The corresponding Programmable
clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in
the PMC_SR reg ister . This ca n be do ne eith er by po lling the st atu s regi ster or by wait ing the
interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the
PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write
operation.
If the CSS and PRES parameters are to be modified, the corresponding Programmable
clock must be disabled first. T he parameters can then be modified. Once this has bee n
done, the user must re-enable the Programmable clock and wait for the PCKRDYx bit to be
set.
Code Example:
write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32.
6. Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled
and/or disabled via registers PMC_PCER and PMC_PCDR.
Depending on the system used, AT91SAM7SE512,14 peripheral clocks and for
AT91SAM7SE256/32,12 peripheral clocks can be enabled or disabled. The PMC_PCSR
provides a clear view as to which peripheral clock is enabled.
Note: Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
281
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.8 Clock Switching Details
29.8.1 Master Clock Switching Timings
Table 29-1 gives the worst case timings required for the Master Clock to switch from one
selected clock to another one. This is in the even t that the prescaler is de-activated. When the
prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be
added.
29.8.2 Clock Switching Waveforms
Figure 29-3. Switch Master Clock from Slow Clock to PLL Clock
Table 29-1. Clock Switching Timings (Worst Case)
From Main Clock SLCK PLL Clock
To
Main Clock – 4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK 0.5 x Main Clock +
4.5 x SLCK –3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Slow Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
PLL Clock
282 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 29-4. Switch Master Clock from Main Clock to Slow Clock
Figure 29-5. Change PLL Programming
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
Main Clock
Main Clock
PLL Clock
LOCK
MCKRDY
Master Clock
Write CKGR_PLLR
283
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 29-6. Programmable Clock Output Programming
PLL Clock
PCKRDY
PCKx Output
Write PMC_PCKx
Write PMC_SCER
Write PMC_SCDR PCKx is disabled
PCKx is enabled
PLL Clock is selected
284 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9 Power Management Controller (PMC) User Interface
Table 29-2. Register Mapping
Offset Register Name Access Reset Value
0x0000 System Clock Enable Register PMC_SCER W rite-only –
0x0004 System Clock Disable Register PMC_SCDR Write-only –
0x0008 System Clock Status Register PMC _SCSR Read-only 0x01
0x000C Reserved – – –
0x0010 Peripheral Clock Enab le Register PMC _PCER Write-only –
0x0014 Peripheral Clock Disab le Register PMC_PCDR Write-only –
0x0018 Peripheral Clock Status Register PMC_PCSR Read-only 0x0
0x001C Reserved – – –
0x0020 Main Oscillator Register CKGR_MOR Read-write 0x0
0x0024 Main Clock Frequency Register CKGR_MCFR Read-only 0x0
0x0028 Reserved – – –
0x002C PLL Register CKGR_PLLR Read-write 0x3F00
0x0030 Master Clock Register PMC_MCKR Read-write 0x0
0x0038 Reserved – – –
0x003C Reserved – – –
0x0040 Programmable Clock 0 Register PMC_PCK0 Read-wri te 0x0
0x0044 Programmable Clock 1 Register PMC_PCK1 Read-wri te 0x0
... ... ... ... ...
0x0060 Interrupt Enable Register PMC_IER Write-only --
0x0064 Interrupt Disable Register PMC_IDR Write-only --
0x0068 Status Register PMC_SR Read-only 0x0 8
0x006C Interrupt Mask Register PMC_IMR Read-only 0x0
0x0070 - 0x007C Reserved – – –
285
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.1 PMC System Clock Enable Register
Name: PMC_SCER
Access: Write-only
• UDP: USB Device Port Clock Enable
0 = No effect.
1 = Enables the 48 MHz clock of the USB Device Port.
• PCKx: Programmable Clock x Output Enab le
0 = No effect.
1 = Enables the corresponding Programmable Clock output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
UDP–––––––
286 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.2 PMC System Clock Disable Register
Name: PMC_SCDR
Access: Write-only
• PCK: Processor Clock Disable
0 = No effect.
1 = Disables the Processor clock. This is used to enter the processor in Idle Mode.
• UDP: USB Device Port Clock Disable
0 = No effect.
1 = Disables the 48 MHz clock of the USB Device Port.
• PCKx: Programmable Clock x Output Disable
0 = No effect.
1 = Disables the corresponding Programmable Clock output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
UDP––––––PCK
287
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.3 PMC System Clock Stat us Register
Name: PMC_SCSR
Access: Read-only
• PCK: Processor Clock Status
0 = The Processor clock is disabled.
1 = The Processor clock is enabled.
• UDP: USB Device Port Clock Status
0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled.
1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled.
• PCKx: Programmable Clock x Output Status
0 = The corresponding Programmable Clock output is disabled.
1 = The corresponding Programmable Clock output is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
UDP––––––PCK
288 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.4 PMC Peripheral Clock Enable Register
Name: PMC_PCER
Access: Write-only
• PIDx: Peripheral Clock x Enable
0 = No effect.
1 = Enables the corresponding peripheral clock.
Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 – –
289
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.5 PMC Peripheral Clock Disable Register
Name: PMC_PCDR
Access: Write-only
• PIDx: Peripheral Clock x Disable
0 = No effect.
1 = Disables the corresponding peripheral clock.
Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
29.9.6 PMC Peripheral Clock Status Register
Name: PMC_PCSR
Access: Read-only
• PIDx: Peripheral Clock x Status
0 = The corresponding peripheral clock is disabled.
1 = The corresponding peripheral clock is enabled.
Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 – –
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 – –
290 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.7 PMC Clock Generator Main Oscillator Register
Name: CKGR_MOR
Access: Read-write
• MOSCEN: Main Oscillator Enable
A crystal must be connected between XIN and XOUT.
0 = The Main Oscillator is disabled.
1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0.
When MOSCEN is set, the MOSCS flag is set once the Main Oscillator startup time is achieved.
• OSCBYPASS: Oscillator Bypass
0 = No effect.
1 = The Main Oscillator is bypassed. MOSCEN must be set to 0. An external clock must be connected on XIN.
When OSCBYPASS is set, the MOSCS flag in PMC _SR is automatically set.
Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag.
• OSCOUNT: Main Oscillator Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
OSCOUNT
76543210
––––––OSCBYPASSMOSCEN
291
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.8 PMC Clock Generator Main Clock Frequency Register
Name: CKGR_MCFR
Access: Read-only
• MAINF: Main Clock Frequency
Gives the number of Main Clock cycles within 16 Slow Clock periods.
• MAINRDY: Main Clock Ready
0 = MAINF value is not valid or the Main Oscillator is disabled.
1 = The Main Oscillator has been enabled previously and MAINF value is available.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––MAINRDY
15 14 13 12 11 10 9 8
MAINF
76543210
MAINF
292 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.9 PMC Clock Generator PLL Register
Name: CKGR_PLLR
Access: Read-write
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
•DIV: Divider
• PLLCOUNT: PLL Counter
Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• OUT: PLL Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1.
• USBDIV: Divider for USB Clock
31 30 29 28 27 26 25 24
– – USBDIV – MUL
23 22 21 20 19 18 17 16
MUL
15 14 13 12 11 10 9 8
OUT PLLCOUNT
76543210
DIV
DIV Divider Selected
0 Divider output is 0
1 Divider is bypassed
2 - 255 Divider output is the selected clock divided by DIV.
USBDIV Divider for USB Clock(s)
0 0 Divider output is PLL clock output.
0 1 Divider output is PLL clock output divided by 2.
1 0 Divider output is PLL clock output divided by 4.
1 1 Reserved.
293
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.10 PMC Master Clock Register
Name: PMC_MCKR
Access: Read-write
• CSS: Master Clock Selection
• PRES: Processor Clock Prescaler
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – PRES CSS
CSS Clock Source Selection
0 0 Slow Clock is selected
0 1 Main Clock is selected
10Reserved
1 1 PLL Clock is selected.
PRES Processor Clock
0 0 0 Selected clock
0 0 1 Selected clock divided by 2
0 1 0 Selected clock divided by 4
0 1 1 Selected clock divided by 8
1 0 0 Selected clock divided by 16
1 0 1 Selected clock divided by 32
1 1 0 Selected clock divided by 64
111Reserved
294 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.11 PMC Programmable Clock Register
Name: PMC_PCKx
Access: Read-write
• CSS: Master Clock Selection
• PRES: Programmable Clock Prescaler
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – PRES CSS
CSS Clock Source Selection
0 0 Slow Clock is selected
0 1 Main Clock is selected
10Reserved
1 1 PLL Clock is selected
PRES Programmable Clock
0 0 0 Selected clock
0 0 1 Selected clock divided by 2
0 1 0 Selected clock divided by 4
0 1 1 Selected clock divided by 8
1 0 0 Selected clock divided by 16
1 0 1 Selected clock divided by 32
1 1 0 Selected clock divided by 64
111Reserved
295
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.12 PMC Interrupt Enable Register
Name: PMC_IER
Access: Write-only
• MOSCS: Main Oscillator Status Interrupt Enable
• LOCK: PLL Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• PCKRDYx: Programmable Clock Ready x Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDYLOCK–MOSCS
296 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.13 PMC Int e rru p t Dis able Register
Name: PMC_IDR
Access: Write-only
• MOSCS: Main Oscillator Status Interrupt Disable
• LOCK: PLL Lo ck Interru p t Dis able
• MCKRDY: Master Clock Ready Interrupt Disable
• PCKRDYx: Programmable Clock Ready x Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDY
LOCK – MOSCS
297
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.14 PMC Status Register
Name: PMC_SR
Access: Read-only
• MOSCS: MOSCS Flag Status
0 = Main oscillator is not stabilized.
1 = Main oscillator is stabilized.
• LOCK: PLL Lock Status
0 = PLL is not locked
1 = PLL is locked.
• MCKRDY: Master Clock Status
0 = Master Clock is not ready.
1 = Master Clock is ready.
• PCKRDYx: Programmable Clock Ready Status
0 = Programmable Clock x is not ready.
1 = Programmable Clock x is ready.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDY
LOCK – MOSCS
298 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
29.9.15 PMC Interrupt Mask Register
Name: PMC_IMR
Access: Read-only
• MOSCS: Main Oscillator Status Interrupt Mask
• LOCK: PLL Lo ck Interru p t Ma s k
• MCKRDY: Master Clock Ready Interrupt Mask
• PCKRDYx: Programmable Clock Ready x Interrupt Mask
0 = The corresponding interrupt is enabled.
1 = The corresponding interrupt is disabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDY
LOCK – MOSCS
299
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30. Debug Unit (DBGU)
30.1 Overview The Debug Unit provides a single entry point from the processor for access to all the debug
capabilities of Atmel’s ARM-based systems.
The Debug Unit featu res a two-pin UART that can be used f or several debug an d trace purposes
and offers an ideal medium for in-situ programming solutions and debug monitor communica-
tions. The Debug Unit two-pin UART can be used stand-alone for general purpose serial
communication. Moreover, the association with two peripheral data controller channels permits
packet handling f or these tasks with processor time reduced to a minimum.
The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the
In-circuit Emulator of the ARM processor visible to the software. These signals indicate the sta-
tus of the DCC read and write registers and generate an interrupt to the ARM processor, making
possible the handling of the DCC under interrupt control.
Chip Identifier registers permit recognition of the device and its revision. These registers inform
as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals.
Finally, the Debug Unit feature s a Force NTRST capability that enables the software to decide
whether to prevent access to the system via the In-circuit Emulator. This permits protection of
the code, stored in ROM.
300 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.2 Block Diagram
Figure 30-1. Debug Unit Functional Block Diagram
Debug Unit Application Example
Peripheral DMA Controller
Baud Rate
Generator
DCC
Handler
ICE
Access
Handler
Transmit
Receive
Chip ID
Interrupt
Control
Peripheral
Bridge
Parallel
Input/
Output
DTXD
DRXD
Power
Management
Controller
ARM
Processor
force_ntrst
COMMRX
COMMTX
MCK
nTRST
Power-on
Reset
dbgu_irq
APB Debug Unit
R
Table 30-1. Debug Unit Pin Description
Pin Name Description Type
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
Debug Unit
RS232 Drivers
Programming Tool Trace Console Debug Console
Boot Program Debug Monitor Trace Manager
301
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.3 Product Dependencies
30.3.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lin es. In this
case, the programmer must first configure the corresponding PIO Controller to enable I/O lines
operations of the Debug Unit.
30.3.2 Power Management
Depending on product integration, the Debug Unit clock may be controllable through the Power
Management Contr oller. In this case, t he programmer must first configur e the PMC to enable t he
Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.
30.3.3 Interrupt Source
Depending on product integration, the Debug Unit interrupt line is connected to one of the inter-
rupt sources of the Advanced Interrupt Contr oller. Interrupt handling requires programming of
the AIC before con figur ing the De bug Unit. Usually, the Debug Unit interrupt line connects to the
interrupt source 1 of th e AIC, which may be shared with th e real-time clock, the system timer
interrupt lines and other system peripheral interrupts, as shown in Figure 30-1. This sh aring
requires th e p rogra mme r t o de termin e t he sou rce of th e in t errup t wh en th e so urce 1 is t r igge re d.
30.4 UART Operations
The Debug Unit operat es as a UART, (asynchronous mode o nly) and supports only 8 -bit charac-
ter handling (with pa rity). It has no clock pin.
The Debug Unit's UART is made up of a receiver and a transmitter that operate independently,
and a common baud rate generator. Receiver timeout and transmitter time guard are not imple-
mented. However, all t he implemented f eatures are compa tible with those of a stand ard USART.
30.4.1 Baud Ra te Genera t or
The baud rate generator provides th e bit pe riod clock nam ed baud rate clock to both the receiver
and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in
DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set t o 0, the baud rate clo ck
is disabled and the Deb ug Unit's UART remains inactive. The maximum allo wable baud rate is
Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x
65536).
Baud Rate MCK
16 CD×
----------------------=
302 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 30-2. Baud Rate Generator
30.4.2 Receiver
30.4.2.1 Receiver Reset, Enable and Disable
After device reset, the Debug Unit receiver is disabled and must be enabled before being used.
The receiver can be en ab led by wr iting t he cont ro l regist er DBGU_CR with t he bit RXEN at 1. At
this command, the receiver starts looking for a start bit.
The programmer ca n disable the receiver by writ ing DBGU_CR with the bit RXDIS at 1. If the
receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already
detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its
operation.
The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit
RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled,
whatever its current state. If RSTRX is applied when data is being processed, this data is lost.
30.4.2.2 Start Detectio n an d Data Samp lin g
The Debug Unit only supports asynchronous operations, and this affects only its receiver. The
Debug Unit receiver detects the start of a received ch aracte r by samp ling the DRXD signal until
it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is
detected for mor e tha n 7 cycle s of th e samp ling clo ck, wh ich is 16 t ime s th e ba ud r ate. Hence , a
space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is
7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the DRXD at the theoretical mid-
point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period)
so the bit sampling point is e ight cycles (0.5-bit pe riod) after the start of the bit. T he first sampling
point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
MCK 16-bit Counter
0
Baud Rate
Clock
CD
CD
OUT
Divide
by 16
0
1
>1
Receiver
Sampling Clock
303
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 30-3. Start Bit Detection
Figure 30-4. Character Reception
30.4.2.3 Receiver Ready
When a complete cha ract er is re ceived, it is tra nsferr ed t o the DBG U_RHR a nd th e RXRDY st a-
tus bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the
receive holding register DBGU_RHR is read.
Figure 30-5. Receiver Ready
30.4.2.4 Receiver Overrun
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in
DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with
the bit RSTSTA (Reset St atus) at 1.
Figure 30-6. Receiver Overrun
30.4.2.5 Parity Error Each time a character is re ceived, the receiv er calculates th e parity of the re ceived data bits, in
accordance with the field PAR in DBGU_MR. It then compa res the result with the received parity
Sampling Clock
DRXD
True Start
Detection D0
Baud Rate
Clock
D0 D1 D2 D3 D4 D5 D6 D7
DRXD
True Start Detection
Sampling Parity Bit Stop Bit
Example: 8-bit, parity enabled 1 stop
1 bit
period
0.5 bit
period
D0 D1 D2 D3 D4 D5 D6 D7 PS SD0 D1 D2 D3 D4 D5 D6 D7 P
DRXD
Read DBGU_RHR
RXRDY
D0 D1 D2 D3 D4 D5 D6 D7 PS SD0 D1 D2 D3 D4 D5 D6 D7 P
DRXD
RSTSTA
RXRDY
OVRE
stop stop
304 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
bit. If different , th e pa rit y e rr or bit PARE in DBG U_ S R is se t at th e sa me tim e the RXRDY is set.
The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA
(Reset Status) at 1. If a new character is received before the reset status command is written,
the PARE bit remains at 1.
Figure 30-7. Parity Error
30.4.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been
sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error)
bit in DBGU_SR is set at the same time the RXRDY bit is set. T he bit FRAME remains high until
the control register DBGU_CR is written with the bit RSTSTA at 1.
Figure 30-8. Receiver Framing Error
30.4.3 Transmitter
30.4.3.1 Transmitter Reset, Enable and Disable
After device reset, the Debug Unit transmitter is disabled and it must be enabled before being
used. The transmit ter is enabled by writing the control reg ister DBGU_CR wit h the bit TXEN at 1.
From this command, the transmitter waits for a character to be written in the Transmit Holding
Register DBGU_THR before actually starting the transmission.
The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the
transmitter is not operating, it is immedia tely stopped. However, if a character is being pro-
cessed into the Shift Register and/or a character has been written in the Transm it Holding
Register, the characters are completed before the transmitter is actually stopped.
The program mer can also put t he t ransmit ter in its r eset stat e by writing t he D BGU _C R with the
bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing
characters.
30.4.3.2 Transmit Format
The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven
depending on the format defined in the Mode Register and the data stored in the Shift Register.
One start bit at level 0 , the n the 8 dat a bi ts, fr om the lowest to the hig hest bit, one opt ion al parit y
bit and one stop bit at 1 ar e con secut ively s hifte d out as shown on the following figure. The field
stop
D0 D1 D2 D3 D4 D5 D6 D7 PS
DRXD
RSTSTA
RXRDY
PARE
Wrong Parity Bit
D0 D1 D2 D3 D4 D5 D6 D7 PS
DRXD
RSTSTA
RXRDY
FRAME
Stop Bit
Detected at 0
stop
305
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a
parity bit is enab led, it can be selected b etween an odd p arity, an e ven parity, o r a fixed space or
mark bit.
Figure 30-9. Character Transmission
30.4.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register
DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Regis-
ter DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift
Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As
soon as the first character is completed, the last character written in DBGU_THR is transferred
into the shift register and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in
DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been
completed.
Figure 30-10. Transmitter Control
30.4.4 Peripheral Data Controller
Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a
Peripheral Data Controller (PDC) channel.
The peripheral da ta controller channels are programmed via registe rs that are mapped within
the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug
Unit status register DBGU_SR and can generate an interrupt.
D0 D1 D2 D3 D4 D5 D6 D7
DTXD
Start
Bit Parity
Bit Stop
Bit
Example: Parity enabled
Baud Rate
Clock
DBGU_THR
Shift Register
DTXD
TXRDY
TXEMPTY
Data 0 Data 1
Data 0
Data 0
Data 1
Data 1S SPP
Write Data 0
in DBGU_THR Write Data 1
in DBGU_THR
stop
stop
306 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of
the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmit-
ter. This results in a write of a data in DBGU_THR.
30.4.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by
using the field CHMODE (Channel Mode) in the mode register DBGU_MR.
The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD
line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the
DTXD line.
The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD
pins are not used and the outp ut of the transmitter is internally connected to the in put of the
receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state.
The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter
and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.
Figure 30-11. Test Modes
30.4.6 Debug Communication Channel Support
The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Com-
munication Channel of the ARM Processor and are driven by the In-circuit Emulator.
Receiver
Transmitter Disabled
RXD
TXD
Receiver
Transmitter Disabled
RXD
TXD
VDD
Disabled
Receiver
Transmitter Disabled
RXD
TXD
Disabled
Automatic Echo
Local Loopback
Remote Loopback VDD
307
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The Debug Communication Channel contains two registers that are accessible through the ICE
Breaker on the JTAG side and thr ough the coprocessor 0 on the ARM Processor side.
As a reminder, the following instructions ar e used to read and write the Debug Co mmunication
Channel:
MRC p14, 0, Rd, c1, c0, 0
Returns the debug commun ication data read register into Rd
MCR p14, 0, Rd, c1, c0, 0
Writes the value in Rd to the debug communication data write register.
The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been
written by the debugger but not yet read by the processor, and that the write register has been
written by the processor and not yet read by the debugger, are wired on the two highest bits of
the status register DBGU_SR. These bits can generate an interrupt. This feature permits han-
dling under interrupt a debug link between a debug monitor running on the target system and a
debugger.
30.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and
DBGU_EXID (Extension ID). Both registers con tain a hard-wir ed value that is read-only. The first
register contains the fo llowing fields:
• EXT - shows the use of the extension identifier register
• NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size
• ARCH - identifies the set of embedded peripheral
• SRAMSIZ - indicates the siz e of the embedded SRAM
• EPROC - indicates the embedded ARM processor
• VERSION - gives the revision of the silicon
The second register is device-dependent and reads 0 if the bit EXT is 0.
30.4.8 ICE Access Pre vention
The Debug Unit allows blockage of access to the system through the ARM processor's ICE
interface. This feature is implemen ted via the register Force NTRST (DBGU_FNR), that allows
assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1
in this register prevents any activity on the TAP controller.
On standard devices, the FNTRST bit resets to 0 and thus does not prevent ICE access.
This feature is especially useful on custom ROM devices for customers who do not want their
on-chip code to be visible.
308 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5 Debug Unit User Interface
Table 30-2. Debug Unit Memory Map
Offset Register Name Access Reset Value
0x0000 Control Re g i ster DBGU_CR Write-only –
0x0004 Mode Register DBGU_MR Read/Write 0x0
0x0008 Interrupt Enable Register DBGU_IER Write-only –
0x000C Interr upt Disable Register DBGU_IDR Write-only –
0x0010 Interrupt Mask Register DBGU_IMR Read-only 0x0
0x0014 Status Register DBGU_SR Read-only –
0x0018 Receive Holding Register DBGU_RHR Read-only 0x0
0x001C Transmit Holding Register DBGU_THR Write-only –
0x0020 Baud Rate Generator Register DBGU_BRGR Read/Write 0x0
0x0024 - 0x003C Reserved – – –
0x0040 Chip ID Register DBGU_CIDR Read-only –
0x0044 Chip ID Extension Register DBGU_EXID Re ad-only –
0x0048 Force NTRST Register DBGU_FNR Read/Write 0x0
0x004C - 0x00FC Reserved – – –
0x0100 - 0x0124 P DC Area – – –
309
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.1 Debug Unit Control Register
Name: DBGU_CR
Access: Write-only
• RSTRX: Reset Receiver
0 = No effect.
1 = The receiver logic is reset and disa bled. If a character is being received, the reception is aborted.
• RSTTX: Rese t Tra nsm it te r
0 = No effect.
1 = The transmitter logic is reset and disabled. If a character is be ing transmitted, the transmission is aborted.
• RXEN: Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Dis able
0 = No effect.
1 = The receive r is d isa bled . If a ch aracte r is b eing processed and RSTRX is not set, the character is completed before the
receiver is stopped.
• TXEN: Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0 = No effect.
1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and
RSTTX is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––
RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX ––
310 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.2 Debug Unit Mode Register
Name: DBGU_MR
Access: Read/Write
• PAR: Parity Type
Parity Type
• CHMODE: Channel Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CHMODE –– PAR –
76543210
––––––––
PAR
0 0 0 E ven parity
001Odd parity
0 1 0 Space: parity forced to 0
0 1 1 Mark: parity forced to 1
1 x x No parity
CHMODE Mode Description
00Normal Mode
0 1 Automatic Echo
1 0 Local Loopback
1 1 Remote Loopback
311
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.3 Debug Unit Interrupt Enable Register
Name: DBGU_IER
Access: Write-only
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• TXBUFE: Enable Buffer Empty Interrupt
• RXBUFF: Enable Buffer Full Interrupt
• COMMTX: Enable COMMTX (from ARM) Interrupt
• COMMRX: Enable COMMRX (from ARM) Interrupt
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
COMMRX COMMTX ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
312 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.4 Debug Unit Interrupt Disable Register
Name: DBGU_IDR
Access: Write-only
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transf er Interrupt
• ENDTX: Disable End of Transmit Interrupt
• OVRE: Disable Overrun Err or Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• TXBUFE: Disable Buffer Empty Interrupt
• RXBUFF: Disable Buffer Full Interrupt
• COMMTX: Disable COMMTX (from ARM) Interrupt
• COMMRX: Disable COMMRX (from ARM) Interrupt
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
COMMRX COMMTX ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
313
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.5 Debug Unit Interrupt Mask Register
Name: DBGU_IMR
Access: Read-only
• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Mask End of Receive Transfer Interrupt
• ENDTX: Mask End of Transmit Interrupt
• OVRE: Mask Overrun Err or Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt
• TXBUFE: Mask TXBUFE Interrupt
• RXBUFF: Mask RXBUFF Interrupt
• COMMTX: Mask COMMTX Interrupt
• COMMRX: Mask COMMRX Interrupt
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
COMMRX COMMTX ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
314 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.6 Debug Unit Status Regi st er
Name: DBGU_SR
Access: Read-only
• RXRDY: Receiver Rea dy
0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read.
• TXRDY: Transmitter Ready
0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled.
1 = There is no character written to DBGU_THR not yet transferred to the Shift Register.
• ENDRX: End of Receiver Transfer
0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active.
• ENDTX: End of Transmitter Transfer
0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal fr om the transmitter Peripheral Data Controller channel is active.
• OVRE: Overrun Error
0 = No overrun erro r ha s oc c ur re d sin ce the las t RS TS TA.
1 = At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0 = No framing error has occurred since the last RSTSTA.
1 = At least one framing error has occurred since the last RSTSTA.
• PARE: Parity Error
0 = No parity error has occurred since the last RSTSTA.
1 = At least one parit y error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled.
1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter.
31 30 29 28 27 26 25 24
COMMRX COMMTX ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
315
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• TXBUFE: Transmission Buffer Empty
0 = The buffer empty signal from the transmitter PDC channel is inactive.
1 = The buffer empty signal from the transmitter PDC channel is active.
• RXBUFF: Receive Buffer Full
0 = The buffer full signa l from the receiver PDC channel is inactive.
1 = The buffer full signa l from the receiver PDC channel is active.
• COMMTX: Debug Communication Channel Write Status
0 = COMMTX from the ARM processor is inactive.
1 = COMMTX from the ARM processor is active.
• COMMRX: Debug Communicat ion Channel Read Status
0 = COMMRX from the ARM processor is inactive.
1 = COMMRX from the ARM processor is active.
316 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.7 Debug Unit Receiv er Holding Register
Name: DBGU_RHR
Access: Read-only
• RXCHR: Received Character
Last received character if RXRDY is set.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
RXCHR
317
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.8 Debug Unit Transmit Holding Register
Name: DBGU_THR
Access: Write-only
• TXCHR: Character to be Transmitted
Next character to be transmitted after t he current character if TXRDY is not s et.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TXCHR
318 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.9 Debug Unit Baud Rate Generator Register
Name: DBGU_BRGR
Access: Read/Write
• CD: Clock Divisor
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CD
76543210
CD
CD Baud Rate Clock
0 Disabled
1MCK
2 to 65535 MCK / (CD x 16)
319
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.10 Debug Unit Chip ID Register
Name: DBGU_CIDR
Access: Read-only
• VERSION: Version of the Device
• EPROC: Embedded Processor
• NVPSIZ: Non volatile Program Memory Size
31 30 29 28 27 26 25 24
EXT NVPTYP ARCH
23 22 21 20 19 18 17 16
ARCH SRAMSIZ
15 14 13 12 11 10 9 8
NVPSIZ2 NVPSIZ
76543210
EPROC VERSION
EPROC Processor
0 0 1 ARM946ES™
0 1 0 ARM7TDMI®
100ARM920T
™
1 0 1 ARM926EJS™
NVPSIZ Size
0000None
00018K bytes
001016K bytes
001132K bytes
0100Reserved
010164K bytes
0110Reserved
0111128K bytes
1000Reserved
1001256K bytes
1010512K bytes
1011Reserved
11001024K bytes
1101Reserved
11102048K bytes
1111Reserved
320 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• NVPSIZ2 Second Nonvolatile Program Memory Size
• SRAMSIZ: Internal SRAM Size
NVPSIZ2 Size
0000None
00018K bytes
001016K bytes
001132K bytes
0100Reserved
010164K bytes
0110Reserved
0111128K bytes
1000Reserved
1001256K bytes
1010512K bytes
1011Reserved
11001024K bytes
1101Reserved
11102048K bytes
1111Reserved
SRAMSIZ Size
0000Reserved
00011K bytes
00102K bytes
00116K bytes
0100112K bytes
01014K bytes
011080K bytes
0111160K bytes
10008K bytes
100116K bytes
101032K bytes
101164K bytes
1100128K bytes
1101256K bytes
111096K bytes
1111512K bytes
321
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• ARCH: Architecture Identifier
• NVPTYP: Nonvolatile Program Memory Type
• EXT: Extension Flag
0 = Chip ID has a single register definition without extension
1 = An extended Chip ID exists.
ARCH
ArchitectureHex Bin
0x19 0001 1001 AT91SAM9xx Series
0x29 0010 1001 AT91SAM9XExx Series
0x34 0011 0100 AT91x34 Series
0x37 0011 0111 CAP7 Series
0x39 0011 1001 CAP9 Series
0x3B 0011 1011 CAP11 Series
0x40 0100 0000 AT91x40 Series
0x42 0100 0010 AT91x42 Series
0x55 0101 0101 AT91x55 Series
0x60 0110 0000 AT91SAM7Axx Series
0x61 0110 0001 AT91SAM7AQxx Series
0x63 0110 0011 AT91x63 Series
0x70 0111 0000 AT91SAM7Sxx Series
0x71 0111 0001 AT91SAM7XCxx Series
0x72 0111 0010 AT91SAM7SExx Series
0x73 0111 0011 AT91SAM Lxx Series
0x75 0111 0101 AT91SAM7Xxx Series
0x92 1001 0010 AT91x92 Series
0xF0 1111 0000 AT75Cxx Series
NVPTYP Memory
000ROM
0 0 1 ROMless or on-chip Flash
1 0 0 SRAM emulating ROM
0 1 0 Embedded Flash Memory
011
ROM and Embedded Flash Memory
NVPSIZ is ROM size
NVPSIZ2 is Flash size
322 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30.5.11 Debug Unit Chip ID Extension Register
Name: DBGU_EXID
Access: Read-only
• EXID: Chip ID Extension
Reads 0 if the bit EXT in DBGU_CIDR is 0.
30.5.12 Debug Unit Force NTRST Register
Name: DBGU_FNR
Access: Read/Write
• FNTRST: Force NTRST
0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal.
1 = NTRST of the ARM processor’s TAP controller is held low.
31 30 29 28 27 26 25 24
EXID
23 22 21 20 19 18 17 16
EXID
15 14 13 12 11 10 9 8
EXID
76543210
EXID
31 30 29 28 27 26 25 24
––––––– –
23 22 21 20 19 18 17 16
––––––– –
15 14 13 12 11 10 9 8
––––––– –
7654321 0
–––––––
FNTRST
323
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31. Serial Peripheral Interface (SPI)
31.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides com-
munication with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift regi ster that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master
Protocol where one CPU is always the master while all of the others are always slaves) and one
master may simu ltaneo usly shift data into multiple slaves. However, only one slave may drive its
output to write data back to the master at any gi ven time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
into the input(s) of the slave(s).
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input
of the master. There may be no more than one slave transmitting data during any particular
transfer.
• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the
data bits . The master may transmit data at a v ariety of baud r ates; the SPCK line cycles once
for each bit that is transmitted.
• Slave Select (NSS): This control line allows slaves to be turned on and off b y hardware.
324 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.2 Block Diagram
Figure 31-1. Block Diagram
31.3 Application Block Diagram
Figure 31-2. Application Block Diagram: Single Master/Multiple Slave Implementation
SPI Interface
Interrupt Control
PIO
PDC
PMC MCK
SPI Interrupt
SPCK
MISO
MOSI
NPCS0/NSS
NPCS1
NPCS2
NPCS3
APB
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
MISO
MOSI
NSS
Slave 0
SPCK
MISO
MOSI
NSS
Slave 1
SPCK
MISO
MOSI
NSS
Slave 2
NC
NPCS3
325
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.4 Signal Description
31.5 Product Dependencies
31.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the SPI pins to their peripheral
functions.
31.5.2 Power Management
The SPI may be clocked through the Power Manageme nt Controller (PMC), thus the program-
mer must first conf igure the PMC to enable the SPI clock.
31.5.3 Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling the SPI interrupt requires programming the AIC before configuring the SPI.
Table 31-1. Signal Description
Pin Name Pin Description
Type
Master Slave
MISO Master In Slave Out Input Output
MOSI Master Out Sla ve In Output Input
SPCK Serial Clock Output Input
NPCS1-NPCS3 P eripheral Chip Selects Output Unused
NPCS0/NSS Peripheral Chip Select/Slave Select Output Input
326 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.6 Functional Description
31.6.1 Modes of Operation
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register.
The pins NPCS 0 to NP CS3 are a ll co nfig ured as outputs, the SPCK pin is driven, the MISO line
is wired on the receive r input and the MOSI line driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the
transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the
transmitter to synchronize the receiver. The NPCS0 pin becomes an inp ut, and is used as a
Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other
purposes.
The data transfers are iden tically programmable for both mod es of operations. The baud rate
generator is a ctivated only in Master Mode.
31.6.2 Data Transfer Four combination s of polarity and phase are avai lable for data transfers. The clock po larity is
programmed with t he CPOL bit in the Chip Select Regi ster. The clock phase is progr ammed with
the NCPHA bit. These two parameters determine the edges of the clock signal on which data is
driven and sampled . Each of t he two pa ra meter s ha s two possible state s, r esultin g in four po ssi-
ble combinations th at are incom patible with one an other. Thus, a mast er/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different
configurations, the master must reconfigure itself each time it needs to communicate with a dif-
ferent slave.
Table 31-2 shows the four modes and corresponding parameter settings.
Figure 31-3 and Figure 31-4 show examples of data transfers.
Table 31-2. SPI Bus Protocol Mode
SPI Mode CPOL NCPHA
001
100
211
310
327
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 31-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Figure 31-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
6
*
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
* Not defined, but normally MSB of previous character received.
1 2345 786
*
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
1 2345 7
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference) 8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
* Not defined but normally LSB of previous character transmitted.
2
2
6
328 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.6.3 Master Mode Operations
When configured in Master Mode, the SPI operates on the clock generated by the internal pro-
grammable baud rate generator. It fully controls the data tr ansfers to and from the slave(s)
connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock
signal (SPCK).
The SPI features two h olding r egist ers, the Transmit Dat a Regist er and t he Re ceive Dat a Regis-
ter, and a single Shift Regist er. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a da ta transfe r begins wh en the proce ssor writes to the SPI_TDR (Tr ans-
mit Data Register). The written data is immediately transferred in the Shift Register and transfer
on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO
line is sampled and shifted in the Shift Register. Transmission cannot occur without reception.
Before writing the TDR, the PCS field must be set in order to select a slave.
If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is
completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data
in SPI_TDR is loaded in the Shift Register and a new transfer starts.
The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit
(Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in
SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel.
The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay
(DLYBCT) is greater than 0 for the last tra nsfer, TXEMPTY is set after the completion of said
delay. The master clock (MCK) can be switched off at this time.
The transfer of re ceived data from th e Shift Register in SPI_RD R is indicated by the RDRF bi t
(Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read,
the RDRF bit is cleared.
If the SPI_RDR (Receive Data Register) has not been read before new data is received, the
Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in
SPI_RDR. The user has to read the status register to clear the OVRES bit.
Figure 31-5 on pag e 329 shows a block diagram o f the SPI when oper ating in Master Mod e. Fig-
ure 31-6 on page 330 shows a flow chart describing how transfers are handled.
329
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.6.3.1 Master Mode Block Diagram
Figure 31-5. Master Mode Block Diag ram
Shift Register
SPCK
MOSI
LSB MSB
MISO
SPI_RDR RD
SPI
Clock
TDRE
SPI_TDR TD
RDRF
OVRES
SPI_CSR0..3
CPOL
NCPHA
BITS
MCK Baud Rate Generator
SPI_CSR0..3
SCBR
NPCS3
NPCS0
NPCS2
NPCS1
NPCS0
0
1
PS
SPI_MR PCS
SPI_TDR PCS
MODF
Current
Peripheral
SPI_RDR PCS
SPI_CSR0..3
CSAAT
PCSDEC
MODFDIS
MSTR
330 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.6.3.2 Master Mode Flow Diagram
Figure 31-6. Master Mode Flow Diagram S
SPI Enable
CSAAT ?
PS ?
1
0
0
1
1
NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD)
TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer
RDRF = 1
TDRE ?
NPCS = 0xF
Delay DLYBCS
Fixed
peripheral
Variable
peripheral
Delay DLYBCT
0
1CSAAT ?
0
TDRE ? 1
0
PS ? 0
1
SPI_TDR(PCS)
= NPCS ?
no
yes SPI_MR(PCS)
= NPCS ?
no
NPCS = 0xF
Delay DLYBCS
NPCS = SPI_TDR(PCS)
NPCS = 0xF
Delay DLYBCS
NPCS = SPI_MR(PCS),
SPI_TDR(PCS)
Fixed
peripheral
Variable
peripheral
- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the Current Chip Select
- When NPCS is 0xF, CSAAT is 0.
331
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.6.3.3 Clock Generation
The SPI Baud rate clock is generate d by dividing the Maste r Clock (MCK), by a value between 1
and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating
baud rate of MCK divided by 255.
Programming the SCBR field at 0 is forbidden . Tri gge rin g a transfer while SCBR is at 0 can lead
to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first
transfer.
The divisor can be defined in depen dently for e ach chip select, as it has to be progr ammed in t he
SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud
rate for each interfaced peripheral without reprogramming.
31.6.3.4 Transfer Delays
Figure 31 -7 shows a chip select transfer change and consecutive transfers on the same chip
select. Three delays can be programmed to modify the transfer waveforms:
• The delay between chip selects, prog rammable only once for all the chip selects by writing
the DLYBCS field in the Mo de Register. Allows insertion of a delay between release of one
chip select and before assertion of a new one.
• The dela y bef ore SPCK, inde pendently prog rammab le f or each chip select by writing the f ield
DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.
• The delay between consecutive transfers, independently programmable for each chip select
by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on
the same ch ip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
Figure 31-7. Programmab le Dela ys
31.6.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals ar e high before and after each transfer.
The peripheral selection can be performed in two differ ent ways:
• Fixed Per ip he ral Select: SPI exchanges data with only one pe ripheral
DLYBCS DLYBS DLYBCT DLYBCT
Chip Select 1
Chip Select 2
SPCK
332 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In
this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the
SPI_TDR has no effect .
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is
used to select the curr ent p eriphe ral. This mean s that th e perip heral select ion can be define d for
each new data.
The Fixed Peripheral Select ion allo ws bu ffer tr an sfer s with a si ngle peri phera l. Usin g t he PDC is
an optimal means, as the size of the data transfer between the memory and the SPI is either 8
bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be
reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro-
gramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data
to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit
wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, how-
ever the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI
lines with the chip select configuration registers. This is not the optimal means in term of mem-
ory size for the buffers, but it provides a very effective means to exchange data with several
peripherals without any intervention of the processor.
31.6.3.6 Peripheral Chip Select Decoding
The user can program the SPI to o perate with up to 15 peripherals by decoding the four Chip
Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCS-
DEC bit at 1 in the Mode Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line
is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest
numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field of
either the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip se lect lines (i.e. all chip se lect lines at 1) when
not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0
defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the
PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on
the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
31.6.3.7 Peripheral Deselection
When operating normally, as soon as the transfer of the last data written in SPI_TDR is com-
pleted, the NPCS lines all rise. This might lead to runtime error if the processor is too long in
responding to an interrupt, and thu s might lead to difficulties for in terfacing with some s erial
peripherals requir ing the chip select line to remain active du ring a full set of transfers.
To facilitate interfacing with such devices, the Chip Select Register can be programmed with the
CSAAT bit (Chip Select Active After Transfer) at 1. This allo ws the chip selec t lines to remain in
their curren t state (low = active) until transfer to another peripheral is required.
333
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 31-8 shows different peripheral deselection cases and the effect of the CSAAT bit.
Figure 31-8. Peripheral Deselection
31.6.3.8 Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven
by an external master on the NPCS0/NSS sign al. NPCS0, MOSI , MISO and SPCK m ust be con-
figured in open drain through the PIO controller, so that external pull up resistors are needed to
guarantee high level.
When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and
the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Con-
trol Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault
detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
31.6.4 SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
A
NPCS[0..3]
Write SPI_TDR
TDRE
NPCS[0..3]
Write SPI_TDR
TDRE
NPCS[0..3]
Write SPI_TDR
TDRE
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
DLYBCT
PCS=A
ADLYBCS
DLYBCT
A
PCS = A
AA
DLYBCT
AA
CSAAT = 0
DLYBCT
AA
CSAAT = 1
A
334 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
defined by the BITS field of the C hip Select Register 0 (SPI_CSR0). These bits are proc essed
following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the
SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no
effect when the SPI is programmed in Slave Mode.
The bits are shifted ou t on the MISO line and sampled on the MOSI line.
When all the bits are processed, the received data is transferred in the Receive Data Register
and the RDRF bit rises. If RDRF is already high when the data is transferred, the Overrun bit
rises and the data transfer to SPI_RDR is aborted.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data
has been written in the Transmit Data Register (SPI_TDR), the last da ta r ece ive d is tra n sfe rr ed .
If no data has been received since the last reset, all bits are transmitted low, as the Shift Regis-
ter resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the
TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls
and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in
SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent
updates of cr itical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no
character is ready to be transmit ted, i.e. n o characte r has been writ ten in SPI_TDR since the last
load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received
character is retransmitted.
Figure 31-9 shows a block diagram of the SPI when operating in Slave Mode.
Figure 31-9. Slave Mode Functional Block Diagram
Shift Register
SPCK
SPIENS
LSB MSB
NSS
MOSI
SPI_RDR RD
SPI
Clock
TDRE
SPI_TDR TD
RDRF
OVRES
SPI_CSR0
CPOL
NCPHA
BITS
SPIEN
SPIDIS
MISO
335
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7 Serial Peripheral Interface (SPI) User Interface
Table 31-3. SPI Register Mapping
Offset Register Register Name Access Reset
0x00 Control Register SPI_CR Write-only ---
0x04 Mode Register SPI_MR Read/Write 0x0
0x08 Receive Data Register SPI_RDR Read-only 0x0
0x0C Transmit Data Register SPI_TDR Write-only ---
0x10 Status Register SPI_SR Read-only 0x000000F0
0x14 Interrupt Enable Register SPI_IER Write-only ---
0x18 Interrupt Disable Register SPI_IDR Write-only ---
0x1C Interrupt Mask Register SPI_IMR Read-only 0x0
0x20 - 0x2C Reserved
0x30 Chip Select Register 0 SPI_CSR0 Read/Write 0x0
0x34 Chip Select Register 1 SPI_CSR1 Read/Write 0x0
0x38 Chip Select Register 2 SPI_CSR2 Read/Write 0x0
0x3C Chip Select Register 3 SPI_CSR3 Read/Write 0x0
0x004C - 0x00F8 Reserved – – –
0x004C - 0x00FC Reserved – – –
0x100 - 0x124 Reserved for the PDC
336 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7.1 SPI Control Register
Name: SPI_CR
Access: Write-only
• SPIEN: SPI Enable
0 = No effect.
1 = Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable
0 = No effect.
1 = Disables the SPI.
As soon as SPIDIS is set, SPI finishes its transfer.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control r egister is written, the SPI is disabled.
• SWRST: SPI Software Reset
0 = No effect.
1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.
The SPI is in slave mode after soft wa re reset.
PDC channels are not affected by software reset.
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this
allows to close the communication with the current serial peripheral by raising the correspo ndi n g NPCS line as soon as TD
transfer has completed.
31 30 29 28 27 26 25 24
–––––––LASTXFER
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST–––––SPIDISSPIEN
337
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7.2 SPI Mode Register
Name: SPI_MR
Access: Read/Write
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a per ipheral device.
1 = The four chip select lines are conn ected to a 4- to 16-bit decoder.
When PCSDEC equals one, up t o 15 Chip Select sign als can be g enerate d with the four lines using an exter nal 4- to 16-bit
decoder. The Chip Select Regist ers define the characteristics of the 15 chip selects according to the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• LLB: Local Loopback Enable
0 = Local loopback path disabled.
1 = Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on
MOSI.)
31 30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
–––– PCS
15 14 13 12 11 10 9 8
––––––––
76543210
LLB – – MODFDIS PCSDEC PS MSTR
338 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• DLYBCS: Delay Between Chip Selects
This field def ines the d elay from NPCS inac tive to the ac tivation o f another NPCS. The DLYBCS time gua rantees non-over-
lapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six MCK periods will be inserted by default.
Otherwise, the following equation determines the delay:
Delay Between Chip Selects DLYBCS
MCK
-----------------------=
339
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7.3 SPI Re ceiv e Da ta Regis ter
Name: SPI_RDR
Access: Read-only
• RD: Receive Data
Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
• PCS: Peripheral Chip Select
In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read
zero.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– PCS
15 14 13 12 11 10 9 8
RD
76543210
RD
340 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7.4 SPI Trans mit Dat a Regi st er
Name: SPI_TDR
Access: Write-only
• TD: Transmit Data
Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the
transmit data reg iste r in a right-justified format.
PCS: Peripheral Chip Select
This field is only used if Variable Peripheral Select is active (PS = 1).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this
allows to close the communication with the current serial peripheral by raising the correspo ndi n g NPCS line as soon as TD
transfer has completed.
This field is only used if Variable Peripheral Select is active (PS = 1).
31 30 29 28 27 26 25 24
–––––––LASTXFER
23 22 21 20 19 18 17 16
–––– PCS
15 14 13 12 11 10 9 8
TD
76543210
TD
341
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7.5 SPI Status Register
Name: SPI_SR
Access: Read-only
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Tr an sm it Dat a Re gist er has bee n transfe r re d to th e se ria lizer .
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has be en detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has be en detected since the last read of SPI_S R.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_R DR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
• RXBUFF: RX Buffer Full
0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0.
1 = Both SPI_RCR(1) and SPI_RNCR(1) have a va lue of 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––SPIENS
15 14 13 12 11 10 9 8
––––––TXEMPTYNSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
342 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• TXBUFE: TX Buffer Empty
0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0.
1 = Both SPI_TCR(1) and SPI_TNCR (1) have a value of 0.
• NSSR: NSS Rising
0 = No rising edge detected on NSS pin since last read.
1 = A rising edge occurred on NSS pin since last read.
• TXEMPTY: Transmission Registers Empty
0 = As soon as data is written in SPI_TDR.
1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of
such delay.
• SPIENS: SPI Enable Status
0 = SPI is disabled.
1 = SPI is enabled.
Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC.
343
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7.6 SPI Interrupt Enable Regi st er
Name: SPI_IER
Access: Write-only
• RDRF: Receive Data Register Full Interrupt Enable
• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Interrupt Enable
• ENDRX: End of Rece ive Buffer In terrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empt y Interrupt Enable
• TXEMPTY: Transmission Registers Empty Enabl e
• NSSR: NSS Rising Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––TXEMPTYNSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
344 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7.7 SPI Interrupt Disable Register
Name: SPI_IDR
Access: Write-only
• RDRF: Receive Data Register Full Interrupt Disable
• TDRE: SPI Transmit Data Register Empty Interrupt Disable
• MODF: Mode Fault Error Interrupt Disable
• OVRES: Overrun Error Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• TXEMPTY: Transmission Registers Empty Disable
• NSSR: NSS Rising Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––TXEMPTYNSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
345
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7.8 SPI Interrupt Mask Register
Name: SPI_IMR
Access: Read-only
• RDRF: Receive Data Register Full Interrupt Mask
• TDRE: SPI Transmit Data Register Empty Interrupt Mask
• MODF: Mode Fault Error Interrupt Mask
• OVRES: Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• TXEMPTY: Transmission Registers Empty Mask
• NSSR: NSS Rising Interrupt Mask
0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––TXEMPTYNSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
346 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
31.7.9 SPI Chip Select Register
Name: SPI_CSR0... SPI_CSR3
Access: Read/Write
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the le ading edge of SPCK and captured o n the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the fo llowing edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce t he required clock/data relationship between master and slave devices.
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as th e last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a diffe rent chip select.
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
76543210
BITS CSAAT – NCPHA CPOL
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
347
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The
Baud rate is selected by writin g a value f rom 1 to 255 in th e SCBR field. The following equat ions deter mine the SPCK baud
rate:
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero , no delay betwee n consecutive t ransfe rs is inserted and th e clock keeps it s duty cycle over the
character tra n sfe rs.
Otherwise, the following equation determines the delay:
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
BITS Bits Per Transfer
SPCK Baudrate MCK
SCBR
---------------=
Delay Before SPCK DLYBS
MCK
-------------------=
Delay Between Consecutive Transfers 32 DLYBCT×MCK
-------------------------------------=
348 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
349
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32. Two Wire Interface (TWI)
32.1 Overview The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made
up of one clock line and one data line with speeds of up to 40 0 Kbits per second, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial
EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD
Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master
or a slave with sequential or single-byte acc ess . Multiple master capability is supported. Arbitra-
tion of the bus is performed internally and puts the TWI in slave mode automatically if the bus
arbitration is lost.
A configurable ba ud ra te gener ator permits t he ou tput da ta r ate to be ada pted to a wid e ran ge of
core clock frequencies.
Below, Table 32-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and
a full I2C compatible device.
Note: 1. START + b000000001 + Ack + Sr
32.2 List of Abbreviations
Table 32-1. Atmel TWI compatibility with i2C Standard
I2C Standard Atmel TWI
Standard Mode Speed (100 KHz) Supported
Fast Mode Speed (400 KHz) Supported
7 or 10 bits Slave Addressing Supported
STAR T BYTE (1) Not Supported
Repeated Start (Sr) Condition Supported
ACK and NACK Management Supported
Slope control and input filtering (Fast mode) Not Supported
Clock stretching Supported
Table 32-2. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
PStop
SStart
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
RRead
WWrite
350 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.3 Block Diagram
Figure 32-1. Block Diagram
32.4 Application Block Diagram
Figure 32-2. Application Block Diagram
32.4.1 I/O Lines Description
APB Bridge
PMC MCK
Two-wire
Interface
PIO
AIC
TWI
Interrupt
TWCK
TWD
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM I²C RTC I²C LCD
Controller
Slave 1 Slave 2 Slave 3
VDD
I²C Temp.
Sensor
Slave 4
Rp: Pull up value as given by the I²C Standard
Rp Rp
Table 32-3. I/O Lines Description
Pin Name Pin Description Type
TWD Two-wire Serial Data Input/Output
TWCK Two-wire Serial Clock Input/Output
351
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.5 Product Dependencies
32.5.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current
source or pull-up resistor (see Figure 32-2 on page 350). When the bus is free, both lines are
high. The output stages of devices connected to the bus must have an open-drain or open-col-
lector to perform t he wired-AND function.
TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer
must perfor m the following steps:
• Program the PIO controller to:
– Dedicate TWD and TWCK as peripheral lines.
– Define TWD and TWCK as open-drain.
32.5.2 Power Management
• Enable the peripheral clock.
The TWI interface may be clocked through the Power Mana gement Controller (PMC), thus the
programme r mu st first configure the PMC to enable the TW I clo ck .
32.5.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In
order to handle interrupts, the AIC must be programmed before configuring the TWI.
352 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.6 Functional Description
32.6.1 Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
32-4).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
32-3).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 32-3. START and STOP Conditions
Figure 32-4. Transfer Format
32.6.2 Modes of Operation
The TWI has six modes of op erations:
• Master transmitter mode
• Master rece iver mode
• Multi-ma ste r transm itt er mod e
• Multi-m a ste r re ceiver mode
• Slave transmitter mode
• Slave receiver mode
These modes are described in the following chapters.
TWD
TWCK
Start Stop
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop
353
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.7 Master Mode
32.7.1 Definition The Master is the device which starts a transfer, generates a clock and stops it.
32.7.2 Application Block Diagram
Figure 32-5. Master Mode Typical Application Block Diagram
32.7.3 Programming Master Mode
The following registers have to be programmed before entering Master mode:
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used
to access slave devices in read or write mode.
2. CKDIV + CHDIV + CLDIV: Clock Waveform.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
32.7.4 Master Transmitter Mode
After the master initiates a Start condition when writing into the Transmit Holding Register,
TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in
TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer
direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse (9th pulse), th e master releases th e data line (HIGH), enab ling the slave to pu ll
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not
acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in
the interrupt enable register (TWI_ IER). If the slave acknowledges the byte, the data writ ten in
the TWI_THR, is then shifted in the interna l shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR. When no more data is written
into the TWI_THR, the master generates a stop condition to end the transfer. The end of the
complete transf er is marked by the TW I_TXCOMP bit set to on e. See Figure 32-6, Figure 32-7,
and Figure 32-8.
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM I²C RTC I²C LCD
Controller
Slave 1 Slave 2 Slave 3
VDD
I²C Temp.
Sensor
Slave 4
Rp: Pull up value as given by the I²C Standard
Rp Rp
354 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 32-6. Master Write with One Data Byte
Figure 32-7. Master Write with Multiple Data Byte
Figure 32-8. Master Write with One Byte Internal Address and Multiple Data Bytes
32.7.5 Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), th e master releases th e data line (HIGH), enab ling the slave to pu ll
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is rece ived, the master is then ready to r eceive data fr om the slave. Af ter data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See Figure 32-9. When the
RXRDY bit is set in the status r egister, a charact er has be en rece ived in the receive-hold ing re g-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
TXCOMP
TXRDY
Write THR (DATA) STOP sent automaticaly
(ACK received and TXRDY = 1)
TWD A DATA AS DADR W P
A DATA n AS DADR W DATA n+5 A PDATA n+x A
TXCOMP
TXRDY
Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x)
Last data sent STOP sent automaticaly
(ACK received and TXRDY = 1)
TWD
A IADR(7:0) A DATA n AS DADR W DATA n+5 A PDATA n+x A
TXCOMP
TXRDY
TWD
Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x)
Last data sent STOP sent automaticaly
(ACK received and TXRDY = 1)
355
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bi ts must be set at th e same time . See Figure 32-9 . When a multiple d ata byte read is
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See Figure 32-10. For Internal Address usage see Section 32.7.6.
Figure 32-9. Master Read with One Data Byte
Figure 32-10. Master Read with Multiple Data Bytes
32.7.6 Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
32.7.6.1 7-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for exa mple . When per form ing r ead oper ation s with an in te rn al addre ss,
the TWI performs a write operation to set the internal address in to the slave device, and then
switch to Maste r Re ceiver mo de. No te tha t th e se cond sta rt condit ion ( after sending the I ADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 32-12. See
Figure 32-11 and Figure 32-13 for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
AS DADR R DATA N P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
TWD
N
AS DADR R DATA n A ADATA (n+1) A DATA (n+m)DATA (n+m)-1 PTWD
TXCOMP
Write START Bit
RXRDY
Write STOP Bit
after next-to-last data read
Read RHR
DATA n Read RHR
DATA (n+1) Read RHR
DATA (n+m)-1 Read RHR
DATA (n+m)
356 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
In the figures below the following abbreviation s are used:
Figure 32-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 32-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
32.7.6.2 10-bit Slave Addressing
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and
set the other slave address bits in the internal address register (TWI_IADR). The two remaining
Internal address bytes, IADR[1 5:8] and IADR[23:16] can be used the same as in 7-bit Slav e
Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit
address)
•S Start
•Sr Repeated Start
•P Stop
•W Write
•R Read
•A Acknowledge
•N Not Acknowledge
•DADR Device Address
•IADR Internal Address
S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P
S DADR W A IADR(15:8) A IADR(7:0) A P
DATA A
A IADR(7:0) A P
DATA AS DADR W
TWD Three bytes internal address
Two bytes internal address
One byte internal address
TWD
TWD
S DADR WA IADR(23:16) A IADR(15:8) AIADR(7:0) A
S DADR W A IADR(15:8) A IADR(7:0) A
AIADR(7:0) A
S DADR W
DATA N P
Sr DADR R A
Sr DADR R A DATA N P
Sr DADR RA DATA NP
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
357
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 32-13 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates
the use of internal addresses to access the device.
Figure 32-13. Internal Address Usage
S
T
A
R
T
M
S
B
Device
Address
0
L
S
B
R
/
W
A
C
K
M
S
B
W
R
I
T
E
A
C
K
A
C
K
L
S
B
A
C
K
FIRST
WORD ADDRESS SECOND
WORD ADDRESS DATA
S
T
O
P
358 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.7.7 Read-write Flowcharts
The following flowcharts shown in Figure 32-14, Figu re 32-15 on page 359, Figure 32-16 on
page 360, Figure 32-17 on page 361, Figure 32-18 on page 362 and Figure 32-19 on page 363
give examples for read and write operations. A polling or interrupt method can be used to check
the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be
configured first.
Figure 32-14. TWI Write Operation with Single Data Byte without Internal Address
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Transfer direction bit
Write ==> bit MREAD = 0
Load Transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Read Status register
TXCOMP = 1?
Transfer finished
Yes
Yes
BEGIN
No
No
359
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 32-15. TWI Write Operation with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Internal address size (IADRSZ)
- Transfer direction bit
Write ==> bit MREAD = 0
Load transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Read Status register
TXCOMP = 1?
Transfer finished
Set the internal address
TWI_IADR = address
Yes
Yes
No
No
360 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 32-16. TWI Write Operation with Multiple Data Bytes with or without Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
Internal address size = 0?
Load Transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Data to send?
Read Status register
TXCOMP = 1?
END
BEGIN
Set the internal address
TWI_IADR = address
Yes
TWI_THR = data to send
Yes
Yes
Yes
No
No
No
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
361
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 32-17. TWI Read Operation with Single Data Byte without Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (IADRSZ)
- Transfer direction bit
Read ==> bit MREAD = 1
Read Status register
TXCOMP = 1?
END
BEGIN
Yes
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Yes
Set the internal address
TWI_IADR = address
Start the transfer
TWI_CR = START | STOP
Read Status register
RXRDY = 1?
Read Receive Holding register
No
No
362 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 32-18. TWI Read Operation with Single Data Byte and Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (IADRSZ)
- Transfer direction bit
Read ==> bit MREAD = 1
Read Status register
TXCOMP = 1?
END
BEGIN
Yes
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Yes
Set the internal address
TWI_IADR = address
Start the transfer
TWI_CR = START | STOP
Read Status register
RXRDY = 1?
Read Receive Holding register
No
No
363
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 32-19. TWI Read Operation with Multiple Data Bytes with or without Internal Address
Internal address size = 0?
Start the transfer
TWI_CR = START
Stop the transfer
TWI_CR = STOP
Read Status register
RXRDY = 1?
Last data to read
but one?
Read status register
TXCOMP = 1?
END
Set the internal address
TWI_IADR = address
Yes
Yes
Yes
No
Yes
Read Receive Holding register (TWI_RHR)
No
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
No
Read Status register
RXRDY = 1?
Yes
Read Receive Holding register (TWI_RHR)
No
364 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.8 Multi-master Mode
32.8.1 Definition More than one master may handle the bus at the same time without data corruption by using
arbitration.
Arbitration start s as soon as tw o or more master s place infor mation on the bus at the same time,
and stops (arbitration is lost) for the master that intends to send a logical one while the other
master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to
detect a stop. When the stop is detecte d, the maste r who has lost arbit rat ion ma y pu t its data on
the bus by respecting arbitration.
Arbitration is illustrated in Figure 32-21 on pa ge 365.
32.8.2 Different Multi-master Modes
Two multi-master modes may be distinguished:
1. TWI is considered as a Master only and will never be addressed.
2. TWI may be either a Master or a Slave and may be addressed.
Note: In both Multi-master modes arbitration is supported.
32.8.2.1 TWI as Master Only
In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven
like a Master with the ARBLST (ARBitration Lost) flag in addition.
If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer.
If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the
TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 32-
20 on page 365).
Note: The state of the bus (busy or free) is not indicated in the user interface.
32.8.2.2 TWI as Master or Slave
The automatic reversal from Master to Slave is not supported in case of a lost arbitration.
Then, in the case where TWI may be either a Master or a Slave, the programmer must manage
the pseudo Multi-m aster mode described in the steps below.
1. Program TWI in Slave mode (SADR + MSDIS + SVEN) an d pe rfor m Slave Access (if
TWI is addressed).
2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1.
3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START +
Write in THR).
4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is
busy or free. When the bus is conside re d as free, TWI initiates the transfer.
5. As soon as the transfer is initiated an d un til a S TOP condition is sent, the arbitration
becomes relevant and the user must monitor the ARBLST flag.
6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave
mode in the case where the Master that won the arbitration wanted to access the TWI.
7. If TWI has to be set in Sla ve mode , wait u ntil TXCOMP flag is at 1 and then progr am the
Slave mode.
365
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it
is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat
SADR.
Figure 32-20. Programmer Sends Data While the Bus is Busy
Figure 32-21. Arbitration Cases
The flowchart sh own in Figure 32- 22 on page 3 66 gives an example of read and write operations
in Multi-master mode.
TWCK
TWD DATA sent by a master
STOP sent by the master START sent by the TWI
DATA sent by the TWI
Bus is busy
Bus is free
A transfer is programmed
(DADR + W + START + Write THR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
TWCK
Bus is busy Bus is free
A transfer is programmed
(DADR + W + START + Write THR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
Data from a Master
Data from TWI S0
S00
1
1
1
ARBLST
S0
S00
1
1
1
TWD S00
1
11
11
Arbitration is lost
TWI stops sending data
P
S0
1
P0
11
11
Data from the master Data from the TWI
Arbitration is lost
The master stops sending data
Transfer is stopped Transfer is programmed again
(DADR + W + START + Write THR)
TWCK
TWD
366 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 32-22. Multi-master Flowchart
Programm the SLAVE mode:
SADR + MSDIS + SVEN
SVACC = 1 ?
TXCOMP = 1 ?
GACC = 1 ?
Decoding of the
programming sequence
Prog seq
OK ?
Change SADR
SVREAD = 0 ?
Read Status Register
RXRDY= 0 ?
Read TWI_RHR
TXRDY= 1 ?
EOSACC = 1 ?
Write in TWI_THR
Need to perform
a master access ?
Program the Master mode
DADR + SVDIS + MSEN + CLK + R / W
Read Status Register
ARBLST = 1 ?
MREAD = 1 ?
TXRDY= 0 ?
Write in TWI_THR
Data to send ?
RXRDY= 0 ?
Read TWI_RHR Data to read?
Stop transfer
Read Status Register
TXCOMP = 0 ?
GENERAL CALL TREATMENT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
START
367
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.9 Slave Mode
32.9.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from
another device calle d the master.
In this mode, the device never initiates and never completes the transmission (START,
REPEATED_START and STOP conditions are always provided by the master).
32.9.2 Application Block Diagram
Figure 32-23. Slave Mode Typical Application Block Diagram
32.9.3 Programming Slave Mode
The following fields must be programmed before entering Slave mode:
1. SADR (TWI_SMR): The slave device address is use d in order to be accessed by mas-
ter devices in read or write mode.
2. MSDIS (TWI_CR): Disable the master mode.
3. SVEN (TWI_CR): Enable the slave mode.
As the device receives the clock, values written in TWI_CWGR are not taken into account.
32.9.4 Receiving DataAfter a Start or Repeated Start condition is detected and if the address sent by the Master
matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave
ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer.
SVACC remains high until a STOP con dition or a repeated START is detected. When such a
condition is detected, EOSACC (End Of Slave ACCess) flag is set.
32.9.4.1 Read Sequence
In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR
(TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address
different from SADR is detected. Note tha t at the end of the re ad sequence TXCO MP (Transmis-
sion Complete) flag is set and SVACC reset.
As soon as data is written in the TWI_THR, TXRDY (Transmit Holding R egister Ready) flag is
reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the
data is not acknowledged, the NACK flag is set.
Host with
TWI
Interface
TWD
TWCK
LCD Controller
Slave 1 Slave 2 Slave 3
RR
VDD
Host with TWI
Interface Host with TWI
Interface
Master
368 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Note that a STOP or a repeated START always follows a NACK.
See Figure 32-24 on page 369.
32.9.4.2 Write Sequence
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register
Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive
Holding Register). RXRDY is reset when reading the TWI _RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address dif-
ferent from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set
and SVACC reset.
See Figure 32-25 on page 369.
32.9.4.3 Clock Synchronization Sequence
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock
synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See Figure 32-27 on page 371 and Figure 32-28 on page 372.
32.9.4.4 General Call In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL
and to decode the new address programming sequence.
See Figure 32-26 on page 370.
32.9.5 Data Transfer
32.9.5.1 Read Operation
The read mode is defined as a data requirement from th e master.
After a START or a REPEATED START condition is detected, the decoding of the address
starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direc-
tion of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded
in the TWI_THR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 32-24 on page 369 describes the write operation.
369
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 32-24. Read Access Ordered by a MASTER
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
32.9.5.2 Write Operation
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address
is decoded, SVACC is set and SVREAD in dicates the direction of the transfer (SVREAD is low in
this case).
Until a STOP or REPEATED START condition is de tected, TWI stores the received data in the
TWI_RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 32-25 on page 369 describes the Write operation.
Figure 32-25. Write Access Ordered by a Master
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.
Write THR Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
TXRDY
NACK
SVACC
SVREAD
EOSVACC
SADRS ADR R NA R A DATA A A DATA NA S/SrDATA NA P/S/Sr
SADR matches,
TWI answers with an ACK
SADR does not match,
TWI answers with a NACK ACK/NACK from the Master
RXRDY
Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
SVACC
SVREAD
EOSVACC
SADR does not match,
TWI answers with a NACK
SADRS ADR W NA W A DATA A A DATA NA S/SrDATA NA P/S/Sr
SADR matches,
TWI answers with an ACK
370 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.9.5.3 General Call The general call is performed in order to change the address of the slave.
If a GENERAL CALL is detected, GACC is set.
After the detection of General Call, it is up to the programmer to decode the commands which
come afterwards.
In case of a WRITE command, the programmer has to decode the programming sequence and
program a new SADR if the programming sequence matches.
Figure 32-26 on page 370 describes the General Call access.
Figure 32-26. Master Performs a General Call
Note: This method allows the user to create an own programming sequence by choosing the program-
ming bytes and the number of them. The programming sequence has to be provided to the
master.
0000000 + W
GENERAL CALL P
SA
GENERAL CALL Reset or write DADD A New SADR
DATA1 A DATA2 A
A
New SADR
Programming sequence
TXD
GCACC
SVACC
RESET command = 00000110X
WRITE command = 00000100X
Reset after read
371
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.9.5.4 Clock Synchronization
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emp-
tied before the emission/reception of a new character. In this case, to avoid sending/receiving
undesired data, a clock stretching mechanism is implemented.
Clock Synchronization in Read Mode
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition
was not detected. It is tied low until the shift register is loaded.
Figure 32-27 on page 371 describes the clock synchronizati on in Read mode.
Figure 32-27. Clock Synchronization in Read Mode
Notes: 1. TXRDY is reset when data has been written in the TWI_TH to the shift register and set when this data has been acknowl-
edged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
3. SCLWS is automatically set when the clock synchronization mechanism is started.
DATA1
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
SCLWS
SVACC
SVREAD
TXRDY
TWCK
TWI_THR
TXCOMP
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register Ack or Nack from the master
DATA0DATA0 DATA2
1
2
1
CLOCK is tied low by the TWI
as long as THR is empty
SSADR
SRDATA0AADATA1 ADATA2 NA S
XXXXXXX
2
Write THR
As soon as a START is detected
372 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Clock Synchronization in Write Mode
The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or
REPEATED_START condition was not detected, it is tied low until TWI_RHR is read.
Figure 32-28 on page 372 describes the clock synchronizati on in Read mode.
Figure 32-28. Clock Synchronization in Write Mode
Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
nism is finished.
Rd DATA0 Rd DATA1 Rd DATA2
SVACC
SVREAD
RXRDY
SCLWS
TXCOMP
DATA1 DATA2
SCL is stretched on the last bit of DATA1
As soon as a START is detected
TWCK
TWD
TWI_RHR
CLOCK is tied low by the TWI as long as RHR is full
DATA0 is not read in the RHR
ADRS SADR W ADATA0A A DATA2DATA1 S
NA
373
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.9.5.5 Reversal after a Repeated Start
Reversal of Read to Write
The master initiates the communication by a read command and finishes it by a write command.
Figure 32-29 on page 373 describes the repeated start + reversal from Read to Write mode.
Figure 32-29. Repeated Start + Reversal from Read to Write Mode
1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected agai n.
Reversal of Write to Read
The master initiates the communication by a write comma nd and finishes it by a read com-
mand.Figure 32-30 on page 373 describes the repeated start + reversal from Write to Read
mode.
Figure 32-30. Repeated Start + Reversal from Write to Read Mode
Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before
the ACK.
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
S SADR R ADATA0A DATA1 SADRSr
NA
W A DATA2 A DATA3 A P
Cleared after read
DATA0 DATA1
DATA2 DATA3
SVACC
SVREAD
TWD
TWI_THR
TWI_RHR
EOSACC
TXRDY
RXRDY
TXCOMP
As soon as a START is detected
S SADR W ADATA0A DATA1 SADRSr
A
R A DATA2 A DATA3 NA P
Cleared after read
DATA0
DATA2 DATA3
DATA1
TXCOMP
TXRDY
RXRDY
As soon as a START is detected
Read TWI_RHR
SVACC
SVREAD
TWD
TWI_RHR
TWI_THR
EOSACC
374 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.9.6 Read Write Flowchar ts
The flowchart sh own in Figure 32- 31 on page 3 74 gives an example of read and write operations
in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt
method requires that the interrupt enable register (TWI_IER) be config ured first.
Figure 32-31. Read Write Flowchart in Slave Mode
Set the SLAVE mode:
SADR + MSDIS + SVEN
SVACC = 1 ?
TXCOMP = 1 ?
GACC = 1 ?
Decoding of the
programming sequence
Prog seq
OK ?
Change SADR
SVREAD = 0 ?
Read Status Register
RXRDY= 0 ?
Read TWI_RHR
TXRDY= 1 ?
EOSACC = 1 ?
Write in TWI_THR
END
GENERAL CALL TREATMENT
375
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10 Two-wire Interface (TWI) User Interface
Table 32-4. Register Mapping
Offset Register Name Access Reset
0x00 Control Regi ster TWI_CR Write-only N / A
0x04 Master Mode Register TWI_MMR Read-write 0x00000000
0x08 Slave Mode Register TWI_SMR Read-write 0x00000000
0x0C Internal Address Register TWI_IADR Read-write 0x00000000
0x10 Clock Waveform Generator Register TWI_CWGR Read-write 0x00000000
0x20 Status Register TWI_SR Read-only 0x0000F009
0x24 Interrupt Enable Register TWI_IER Write-only N / A
0x28 Interrupt Disable Register TWI_IDR Write-only N / A
0x2C Interrupt Mask Register TWI_IMR Read-only 0x0000000 0
0x30 Receive Holding Register TWI_RHR Read-only 0x00000000
0x34 Transmit Holding Register TWI_THR Write-only 0x00000000
0x38 - 0xFC Reserved – – –
376 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.1 TWI Control Register
Name: TWI_CR
Access: Write-only
Reset Value: 0x00000000
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is ne ce ssary whe n the TWI per iphe ra l wan ts to read da ta fro m a slave. Whe n conf igu red in Ma ster M ode with a
write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
– In single data byte master read, the START and STOP must both be set.
– In multiple data bytes master read, the STOP must be set after the last data received but one.
– In master read mode, if a NACK bit is received, the STOP is automatically performed.
– In multiple dat a write operation, when both THR and shif t register ar e empty, a STOP cond ition is automat ically
sent.
• MSEN: TWI Master Mode Enabled
0 = No effect.
1 = If MSDIS = 0, the ma ster mode is enabled.
Note: Switching from Slave to Master mod e is only permitted when TXCOMP = 1.
• MSDIS: TWI Master Mod e Disabled
0 = No effect.
1 = The master mode is d isa ble d, all pen ding da ta is t ransmit ted. Th e shift er and ho ldin g chara cter s (if it con ta ins da ta) a re
transmitted in case of write op eration. In read operation, the characte r being transferred must be completely received
before disabling.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST – SVDIS SVEN MSDIS MSEN STOP START
377
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• SVEN: TWI Slave Mode Enabled
0 = No effect.
1 = If SVDIS = 0, the slave mod e is enabled.
Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1.
• SVDIS: TWI Slave Mode Disabled
0 = No effect.
1 = The slave mode is disa bled. The shift er and ho lding char acter s (if it contai ns data) ar e transmit ted in ca se of re ad oper-
ation. In write operation, the character being transferred must be complet ely received before disabling.
• SWRST: Software Reset
0 = No effect.
1 = Equivalent to a system reset.
378 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.2 TWI Master Mode Register
Name: TWI_MMR
Access: Read-write
Reset Value: 0x00000000
• IADRSZ: Internal Device Address Size
• MREAD: Master Read Direction
0 = Master write direction.
1 = Master read direction.
• DADR: Device Address
The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–DADR
15 14 13 12 11 10 9 8
–––MREAD–– IADRSZ
76543210
––––––––
IADRSZ[9:8]
0 0 No inter nal device address
0 1 One-byte internal device address
1 0 Two-byte inter nal device address
1 1 Three-byte internal device address
379
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.3 TWI Slave Mode Register
Name: TWI_SMR
Access: Read-write
Reset Value: 0x00000000
• SADR: Slave Address
The slave device address is us ed in Slave mode in order to be accessed by master devices in read or write mode.
SADR must be progra mmed before enabling the Slave mode or after a general call. Writes at other times have no effect.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–SADR
15 14 13 12 11 10 9 8
––––––
76543210
––––––––
380 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.4 TWI Inte rna l Addres s Re gi st er
Name: TWI_IADR
Access: Read-write
Reset Value: 0x00000000
• IADR: Internal Address
0, 1, 2 or 3 bytes depending on IADRSZ.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
IADR
15 14 13 12 11 10 9 8
IADR
76543210
IADR
381
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.5 TWI Clock Waveform Generator Register
Name: TWI_CWGR
Access: Read-write
Reset Value: 0x00000000
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Cloc k High Divider
The SCL high period is defined as follows:
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CKDIV
15 14 13 12 11 10 9 8
CHDIV
76543210
CLDIV
Tlow CLDIV(2CKDIV
×()4)+TMCK
×=
Thigh CHDIV(2CKDIV
×()4)+TMCK
×=
382 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.6 TWI Status Register
Name: TWI_SR
Access: Read-only
Reset Value: 0x0000F009
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holdin g and shifte r re gis te rs ar e em p ty an d STOP co nd itio n ha s be en sen t.
TXCOMP behavior in Master mode can be seen in Figure 32-8 on page 354 and in Figure 32-10 on page 355.
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in Figure 32-27 on page 371, Figure 32-28 on page 372, Figure 32-29 on
page 373 a nd Figure 32-30 on page 373.
• RXRDY: Receiv e Ho ld ing Reg is te r Ready (aut om at ic al ly set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in Figure 32-10 on page 355.
RXRDY behavior in Slave mode can be seen in Figure 32-25 on page 369, Figure 32-28 on page 372, Figure 32-29 on
page 373 a nd Figure 32-30 on page 373.
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in Figure 32-8 on page 354.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
EOSACC SCLWS ARBLST NACK
76543210
– OVRE GACC SVACC SVREAD TXRDY RXRDY TXCOMP
383
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
TXRDY used in Slave mode:
0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK) .
1 = It indicates that the TWI_THR is empty and that data has been transmitt ed and acknowledged.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the
programmer must not fill TWI_THR to avoid losing it.
TXRDY behavior in Slave mode can be seen in Figure 32-24 on page 369, Figure 32-27 on page 371, Figure 32-29 on
page 373 a nd Figure 32-30 on page 373.
• SVREAD: Slave Read (automatically set / reset)
This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
0 = Indicates that a write access is performed by a Master.
1 = Indicates that a read access is performed by a Master.
SVREAD behavior can be seen in Figure 32-24 on page 369, Figure 32 -25 on page 369, Figure 32- 29 on page 373 and
Figure 32-30 on page 373.
• SVACC: Slave Access (automatically set / reset)
This bit is only used in Slave mode.
0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.
1 = Indicates that the address de coding sequence has matched (A Master has sent SADR). SVACC remains high until a
NACK or a STOP condition is detected.
SVACC behavior can be seen in Figure 32-24 on page 369, Figure 32-25 on pa ge 369 , Figure 32-29 o n page 3 73 and Fig-
ure 32-30 on page 373.
• GACC: General Call Access (c lear on read)
This bit is only used in Slave mode.
0 = No General Call has been det ected.
1 = A General Call ha s been detecte d. After the det ection of Gener al Call, the progr ammer deco ded the commands that fol-
low and the program ming sequence.
GACC behavior can be seen in Figure 32-26 on page 370.
• OVRE: Overrun Error (clear on read)
This bit is only used in Master mode.
0 = TWI_RHR has not been loaded while RXRDY was set
1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged (clear on read)
NACK used in Master mode:
0 = Each data byte has been correctly received by the fa r-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
384 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
NACK used in Slave Read mode:
0 = Each data byte has been correctly received by the Master.
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill
TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.
Note that in Slave Write mode all d ata is acknowledged by the TWI.
• ARBLST: Arbitration Lost (clear on read)
This bit is only used in Master mode.
0: Arbitration won.
1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
• SCLWS: Clock Wait State (automatically set / reset)
This bit is only used in Slave mode.
0 = The clock is not stretched.
1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new
character.
SCLWS behavior can be seen in Figure 32-27 on page 371 and Figure 32-28 on page 372.
• EOSACC: End Of Slav e Access (clear on rea d)
This bit is only used in Slave mode.
0 = A slave access is being performing.
1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in Figure 32-29 on page 373 and Figure 32-30 on page 373
385
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.7 TWI Inte rru p t Enable Register
Name: TWI_IER
Access: Write-only
Reset Value: 0x00000000
• TXCOMP: Transmission Completed Interrupt En able
• RXRDY: Receive Ho ld in g Regis te r Ready Interru p t Enable
• TXRDY: Transmit Holding Register Ready Interrupt Enable
• SVACC: Slave Access Interrupt Enable
• GACC: Genera l Call Access Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• NACK: Not Acknowledge Interrupt Enable
• ARBLST: Arbitration Lost Interrupt Enable
• SCL_WS: Clock Wait State Interrupt Enable
• EOSACC: End Of Slave Access Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
EOSACC SCL_WS ARBLST NACK
76543210
– OVRE GACC SVACC – TXRDY RXRDY TXCOMP
386 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.8 TWI Interrupt Disable Register
Name: TWI_IDR
Access: Write-only
Reset Value: 0x00000000
• TXCOMP: Transmission Completed Interrupt Disable
• RXRDY: Receive Holding Register Ready Interrupt Disable
• TXRDY: Transmit Holding Register Ready Interrupt Disable
• SVACC: Slave Access Interrupt Disable
• GACC: General Call Access Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• NACK: Not Acknowledge Interrupt Disable
• ARBLST: Arbitration Lost Interrupt Disable
• SCL_WS: Clock Wait State Interrupt Disable
• EOSACC: End Of Slave Access Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
EOSACC SCL_WS ARBLST NACK
76543210
– OVRE GACC SVACC – TXRDY RXRDY TXCOMP
387
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.9 TWI Interrupt Mask Register
Name: TWI_IMR
Access: Read-only
Reset Value: 0x00000000
• TXCOMP: Transmission Completed Interrupt Mask
• RXRDY: Receive Holding Register Ready Interrupt Mask
• TXRDY: Transmit Holding Register Ready Interrupt Mask
• SVACC: Slave Access Interrupt Mask
• GACC: General Call Access Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• NACK: Not Acknowledge Interrupt Mask
• ARBLST: Arbitration Lost Interrupt Mask
• SCL_WS: Clock Wait State Interrupt Mask
• EOSACC: End Of Slave Access Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
EOSACC SCL_WS ARBLST NACK
76543210
– OVRE GACC SVACC – TXRDY RXRDY TXCOMP
388 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
32.10.10 TWI Receive Holding Register
Name: TWI_RHR
Access: Read-only
Reset Value: 0x00000000
• RXDATA: Master or Slave Receive Holding Data
32.10.11 TWI Transmit Holding Register
Name: TWI_THR
Access: Read-write
Reset Value: 0x00000000
• TXDATA: Master or Slave Transmit Holding Data
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
RXDATA
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TXDATA
389
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33. Universal Synchronous Asynchronous Receiver Transceiver (USART)
33.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full
duplex universal synchro nous asynchronous seria l link. Data fr ame format is widely progr amma-
ble (data length, parity, number of stop bits) to support a maximum of standards. The receiver
implements pari ty error, framing e rror and overrun error detectio n. The receiver time- out enables
handling variable-length frames and the transmitter timeguard facilitates communications with
slow remote devices. Multidrop communications are also supported through address bit han-
dling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485 buses, with
ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports.
The hardware han dshaking feature enables a n out-of-band flow control by a utomatic manage-
ment of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data
transfers to the tr ansmitter and from the re ceiver. The PDC provides chain ed buffer manage-
ment without any intervention of the processor.
390 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.2 Block Diagram
Figure 33-1. USART Block Diagram
Peripheral DMA
Controller
Channel Channel
AIC
Receiver
USART
Interrupt
RXD
TXD
SCK
USART PIO
Controller
CTS
RTS
DTR
DSR
DCD
RI
Transmitter
Modem
Signals
Control
Baud Rate
Generator
User Interface
PMC MCK
SLCK
DIV MCK/DIV
APB
391
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.3 Application Block Diagram
Figure 33-2. Application Block Diagram
33.4 I/O Lines Description
Table 33-1. I/O Line Description
Name Description Type Active Level
SCK Serial Clock I/O
TXD Transmit Serial Data I/ O
RXD Receiv e Serial Data Input
RI Ring Indicator Input Low
DSR Data Set Ready Input Low
DCD Data Carrier Detect Input Low
DTR Data Terminal Ready Output Low
CTS Clear to Send Input L ow
RTS Request to Send Output Low
Smart
Card
Slot
USART
RS232
Drivers
Modem
RS485
Drivers
Differential
Bus
IrDA
Transceivers
Modem
Driver
Field Bus
Driver EMV
Driver IrDA
Driver
IrLAP
RS232
Drivers
Serial
Port
Serial
Driver
PPP
PSTN
392 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.5 Product Dependencies
33.5.1 I/O Lines The pins use d for interfacing the USART may be multiplexed with the PIO lines. The progr am-
mer must first program the PIO controller to assign the desired USART pins to their peripheral
function. If I/O lines of the USART are not used by the application, they can be used for other
purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up
is mandatory.
All the pins of the modems may or may not be implemented on the USART. Only USART1 is
fully equipped with a ll the mode m signals. On USARTs not equ ipped wit h the co rrespondin g pin,
the associated control bits and statuses have no effect on the behavior of th e USART.
33.5.2 Power Management
The USART is not continuously clocked. The programmer must first enable the USART Clock in
the Power Management Controller (PMC) before using the USART. However, if the application
does not require USART op erat ion s, th e USART clock can be stop pe d wh en no t need ed and be
restarted later. In this case, the USART will resume its operations where it left off.
Configuring the USART does not require the USART clock to be enabled.
33.5.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt
Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not
recommended to use the USART interrupt line in edge sensitive mode.
393
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.6 Functional Description
The USART is capable of managing several types of serial synchronous or asynchronous
communications.
It supports the following communication modes:
• 5- to 9-bit full-duplex asynchronous serial communication
– MSB- or LSB-first
– 1, 1.5 or 2 stop bits
– Parity e ven, odd, marked, space or none
– By 8 or by 16 over-sampling receiver frequency
– Optional hardware handshaking
– Optional modem signals management
– Optional br ea k ma n ag em e nt
– Optional multidrop serial communication
• High-speed 5- to 9-bit full-duplex synchronous serial communication
– MSB- or LSB-first
– 1 or 2 stop bits
– Parity e ven, odd, marked, space or none
– By 8 or by 16 over-sampling frequency
– Optional hardware handshaking
– Optional modem signals management
– Optional br ea k ma n ag em e nt
– Optional multidrop serial communication
• RS485 with driver control signal
• ISO7816, T0 or T1 pr otocols for interfacing with smart cards
– NACK handling, error counter with repetition and ite ration limit
• InfraRed IrDA Modulation and Demodulation
• Test modes
– Remote loopback, local loopback, automatic echo
33.6.1 Baud Ra te Gene rat or
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the
receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode
Register (US_MR) between:
• the Master Clock MCK
• a division of the Master Clock, the divider being product dependent, but generally set to 8
• the external clock, available on the SCK pin
The Baud Rate Gener ator is base d upon a 1 6-bit divide r, which is p rogra mme d with t he CD f ield
of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate
Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and
becomes inactive.
394 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
If the external SCK clock is selected, the duration of the low and high levels of the signal pro-
vided on the SCK pi n must be longer than a Ma ster Clock (MCK) period. Th e frequency of the
signal provided on SCK must be at least 4.5 times lower than MCK.
Figure 33-3. Baud Rate Generator
33.6.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possi-
ble clock and that OVER is programme d at 1.
MCK/DIV 16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
30
1
0
1
FIDI
Baudrate SelectedClock
82 Over–()CD()
--------------------------------------------=
395
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.6.1.2 Baud Rate Calculation Example
Table 33-2 shows calcula tions of CD to obtain a baud rate at 38400 bauds for differen t source
clock frequencies. This table also shows the actual resulting baud rate and the error.
The baud rate is calculated with the following formula:
The baud rate error is calculated with the following formula. It is not recommended to work with
an error higher than 5%.
33.6.1.3 Fractional Baud Rate in Asynchronous Mode
The Baud Rate generator previously defined is subject to the following limitation: the output fre-
quency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is mod ified to obtain Baud Rate change s by a fractio n of t he ref erence sour ce clock.
This fractional part is programmed with the FP field in the Baud Rate Generator Register
Table 33-2. Baud Rate Example (OVER = 0)
Source Clock Expected Baud
Rate Calculation Result CD Actual Baud Rate Erro r
MHz Bit/s Bit/s
3 686 400 38 400 6.00 6 38 400.00 0.00%
4 915 200 38 400 8.00 8 38 400.00 0.00%
5 000 000 38 400 8.14 8 39 062.50 1.70%
7 372 800 38 400 12.00 12 38 400.00 0.00%
8 000 000 38 400 13.02 13 38 461.54 0.16%
12 000 000 38 400 19.53 20 37 500.00 2.40%
12 288 000 38 400 20.00 20 38 400.00 0.00%
14 318 180 38 400 23.30 23 38 908.10 1.31%
14 745 600 38 400 24.00 24 38 400.00 0.00%
18 432 000 38 400 30.00 30 38 400.00 0.00%
24 000 000 38 400 39.06 39 38 461.54 0.16%
24 576 000 38 400 40.00 40 38 400.00 0.00%
25 000 000 38 400 40.69 40 38 109.76 0.76%
32 000 000 38 400 52.08 52 38 461.54 0.16%
32 768 000 38 400 53.33 53 38 641.51 0.63%
33 000 000 38 400 53.71 54 38 194.44 0.54%
40 000 000 38 400 65.10 65 38 461.54 0.16%
50 000 000 38 400 81.38 81 38 580.25 0.47%
60 000 000 38 400 97.66 98 38 265.31 0.35%
70 000 000 38 400 113.93 114 38 377.19 0.06%
BaudRate MCK CD 16×⁄=
Error 1ExpectedBaudRate
ActualBaudRate
---------------------------------------------------
⎝⎠
⎛⎞
–=
396 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
(US_BRGR). If FP is not 0, the fractiona l part is activated. The resolution is one eighth of the
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
The modified architecture is presented below:
Figure 33-4. Fractional Baud Rate Generator
33.6.1.4 Baud Rate in Synchronous Mode
If the USART is programmed to operate in synchronou s mode, the selected clo ck is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 4.5 times lowe r than the
system clock.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the
value programmed in CD must be even if the user has to ensure a 50 :50 mark/space ratio on the
SCK pin. If the internal clock M CK is selected, the Baud Rate Gene rator ensures a 50:50 du ty
cycle on the SCK pin, even if the value programmed in CD is odd.
33.6.1.5 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
Baudrate SelectedClock
82 Over–()CD FP
8
-------+
⎝⎠
⎛⎞
⎝⎠
⎛⎞
-----------------------------------------------------------------=
MCK/DIV 16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
30
1
0
1
FIDI
glitch-free
logic
Modulus
Control
FP
FP
BaudRate SelectedClock
CD
--------------------------------------=
397
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
where:
• B is the bit rate
• Di is the bit-rate adjustment factor
• Fi is the clock frequency division factor
• f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 33-3.
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 33-4.
Table 33-5 shows the result ing Fi/Di Ratio , which is th e ratio between th e ISO7816 clock and t he
baud rate clock.
If the USART is configured in ISO7816 Mode, the clock selected by the USCL KS field in the
Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud
Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to
feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR.
This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio
register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up
to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the
user must program the FI_ DI_ RAT IO field to a value as close as possible to the expect ed value.
The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common
divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1).
Figure 33-5 shows the relation between the Elementary Time Unit, corresponding to a bit time,
and the ISO 7816 clock.
BDi
Fi
------f×=
Table 33-3. Binary and Decimal Values for Di
DI field 0001 0010 0011 0100 0101 0110 1000 1001
Di (decimal)1 2 4 8 163212 20
Table 33-4. Binary and Decimal Values for Fi
FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101
Fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048
Table 33-5. Possible Values for the Fi/Di Ratio
Fi/Di 372 558 774 1116 1488 1806 512 768 1024 1536 2048
1 372 558 744 1116 1488 1860 512 768 1024 1536 2048
2 186 279 372 558 744 930 256 384 512 768 1024
4 93 139.5 186 279 372 465 128 192 256 384 512
8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256
16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128
32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64
12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6
20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
398 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 33-5. Elementary Time Unit (ET U)
33.6.2 Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit
in the Control Regist er (US_CR). However, the receiver regist ers can be programme d before the
receiver clock is enabled.
After reset, the tran smitter is disabled. The user must en able it by setting the TXEN bit in the
Control Register (US_CR). However, the transmitter registers can be programmed before being
enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the so ftwar e can p er form a re se t o n the re ce iver o r t he tran smit t er of th e USART by
setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register
(US_CR). The reset commands have the same effect as a hardware reset on the corresponding
logic. Regardless of what the receiver or the transmitter is performing, the communication is
immediately stopped.
The user can also indepe ndently disable the receiv er or the transmitter by setting RXDIS and
TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the
USART waits until the end of reception of the current character, then the reception is stopped. If
the transmitter is disabled while it is operating, the USART waits the end of transmission of both
the current character and character being stored in the Transmit Holding Register (US_THR). If
a timeguard is progr ammed, it is handled normally.
33.6.3 Synchronous and Asynchronous Modes
33.6.3.1 Transmitter Operations
The transmitter performs the same in both synchronous and asynchronous operating modes
(SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two
stop bits are successively shifted out on the TXD pin at each falling edge of the programmed
serial clock.
The number of da ta b its is s ele ct ed by the CHRL fiel d a n d t he M ODE 9 bit in the Mo de Re g i ste r
(US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The
parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none
parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If
written at 1, the most sig nificant bit is sent fir st. At 0, the less significant bit is sent first. The num-
ber of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in
asynchronous mode only.
1 ETU
ISO7816 Clock
on SCK
ISO7816 I/O Line
on TXD
FI_DI_RATIO
ISO7816 Clock Cycles
399
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 33-6. Character Transmit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter
reports two status bits in the Channel Status Regist er (US_CSR): TXR DY (Transmitte r Ready),
which indicates that US_THR is empty and T XEMPTY, which indicates that all the characters
written in US_THR have been processed. When the current character processing is completed,
the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY raises.
Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in
US_THR while TXRDY is active has no effect and the written character is lost.
Figure 33-7. Transmitter Status
33.6.3.2 Asynchronous Rece iver
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver over-
samples the RXD inpu t line. The oversampling is either 16 or 8 times the Baud Rate clock,
depending on the OVER bit in the Mode Register (US_MR).
The receiver samples t he RXD line. If the line is sampled during one half of a bit t ime at 0, a st art
bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data
bits, parity bi t and stop bit are samp led on each 1 6 sampling clock cycle. I f the ove rsampling is 8
(OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop
bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits
as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization
mechanism only, the number of stop bits has no effect on the receiver as it considers only one
stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Start
Bit
Write
US_THR
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
TXEMPTY
400 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking
for a new start bit so that resynchronization can also be accomplished when the transmitter is
operating with one stop bit.
Figure 33-8 and Figure 33-9 illustrate start detection and character reception when USART
operates in asynchro nous mode.
Figure 33-8. Asynchronous Start Detection
Figure 33-9. Asynchronous Character Reception
33.6.3.3 Synchronous Receiver
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity
bit and the stop b its ar e sa mpled an d t he rece ive r waits f or the n ext st art bit . Synchron ous m ode
operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 33-10 illustrates a character reception in synchronous mode.
Sampling
Clock (x16)
RXD
Start
Detection
Sampling
Baud Rate
Clock
RXD
Start
Rejection
Sampling
12345678
123456701234
123456789 10111213141516D0
Sampling
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled
Baud Rate
Clock
Start
Detection 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples
401
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 33-10. Synchronous Mode Character Reception
33.6.3.4 Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding Register
(US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is com-
pleted while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is
transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing
the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
Figure 33-11. Receiver Status
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Sampling
Parity Bit Stop Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
RXRDY
OVRE
D0 D1 D2 D3 D4 D5 D6 D7
Start
Bit Parity
Bit Stop
Bit
RSTSTA = 1
Read
US_RHR
402 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.6.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode
Register (US_MR ). The PAR field also enables the Multidrop m ode, see “Multidrop Mo de” on
page 403. Even and odd parity bit generation and error detection are supported.
If even parity is sele cte d, t he pa rit y ge ne rato r o f t he tr an sm itte r d rives the p ar ity bit at 0 if a n um-
ber of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the
receiver parity checker counts the number of received 1s and reports a parity error if the sam-
pled parity bit does not correspond. If odd parity is selected, the parity generator of the
transmitter d rive s th e pa rit y b it a t 1 if a number o f 1s in the charac te r d a ta bit is ev en , and at 0 if
the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received
1s and report s a parity error if the sampled pari ty bit does not corresp ond. If the mark pa rity is
used, the parity generator of the tra nsmitter drives the parity bit at 1 for all characters. The
receiver parity checker repo rts an error if the parity bit is sampled at 0. If the space p arity is
used, the parity generator of the tra nsmitter drives the parity bit at 0 for all characters. The
receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the
transmitter do es not generate any parity bit and the receiver does not report any parity error.
Table 33-6 shows an example of the parity bit for the character 0x41 (character ASCII “A”)
depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added
when a parity is odd, or 0 is added when a parity is even.
When the rece iver det ects a pa rity er ror, it sets t he PARE (Par ity Erro r) bit in the Cha nnel St atus
Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with
the RSTSTA bit at 1. Figure 33- 12 illustrates the parity bit status setting and clearing.
Table 33-6. Parity Bit Examples
Character Hexa Binary Parity Bit Parity Mode
A 0x41 0100 0001 1 Odd
A 0x41 0100 0001 0 Ev en
A 0x41 0100 0001 1 Mark
A 0x41 0100 0001 0 Space
A 0x41 0100 0001 None None
403
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 33-12. Parity Error
33.6.3.6 Multidrop Mode
If the PAR field in the Mo de Register (US_MR) is programm ed to the value 0x6 or 0 x07, the
USART runs in Multidrop Mode. This mode differentiates the data characters and the address
characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the
parity bit at 1.
If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when
the parity bit is high and the transmitter is able to send a character with the parity bit high when
the Control Register is written with the SENDA bit at 1.
To handle parity e rror, the PARE bit is clea red when the Control Register is written with the bit
RSTSTA at 1.
The transmitte r sends an addr ess byte (pa rity bit set) when SENDA is writ ten to US_C R. In this
case, the next byte written to US_THR is transmitted as an address. Any character written in
US_THR without having written the command SENDA is transmitted normally with the parity at
0.
33.6.3.7 Transmitter Timeguard
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between
two character s. T his idle stat e ac tu ally acts as a long stop bit.
The duration o f th e id le stat e is pr og rammed in the TG fie ld o f th e Tran sm itt er Time gu ard Regis-
ter (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise,
the transmitter holds a high level on TXD after each transmitted byte during the number of bit
periods programmed in TG in addition to the number of stop bits.
As illustrated in Figure 33-13, the behavior of TXRDY and TXEMPTY status bits is modified by
the programming o f a timeguard. TXRDY rises only when the start bit of the ne xt character is
sent, and thus remains at 0 during the timeguard transmission if a character has been written in
US_THR. TXEMPTY remain s low until the timeguard transmission is com pleted as the time-
guard is part of the current character being transmitted.
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Bad
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
US_CR
PARE
RXRDY
RSTSTA = 1
404 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 33-13. Timeguard Operations
Table 33-7 indicates the maximum length of a timeguard period that the transmitter can handle
in relation to the function of the Baud Rate.
33.6.3.8 Receiver Time-out
The Receiver Time-ou t provides sup port in han dling va riable-len gth fra mes. This feat ure de tects
an idle condition on th e RXD lin e. Wh en a time -o ut is det ect ed , th e b it TI MEO UT in th e Ch an nel
Status Register (US_CSR) r ises and can ge nerate an interrupt, thus indicating to th e driver an
end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed
in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at
0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR
remains at 0. Otherwise, the receiver loads a 1 6-bit counter with the value programmed in TO.
This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user
can either:
• Stop the counter clock until a new character is received. This is performed by writing the
Control Register (US_CR) with t he STTT O (Start Time-out) bit at 1. In this case, the idle state
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Start
Bit
TG = 4
Write
US_THR
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
TXEMPTY
TG = 4
Table 33-7. Maximum Timeguard Length Depending on Baud Rate
Baud Rate Bit time Timeguard
Bit/sec µs ms
1 200 833 212.50
9 600 104 26.56
14400 69.4 17.71
19200 52.1 13.28
28800 34.7 8.85
33400 29.9 7.63
56000 17.9 4.55
57600 17.4 4.43
115200 8.7 2.21
405
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
on RXD before a new character is received will not provide a time-out. This prevents having
to handle an interrupt before a char acte r is received and allo ws w a iting for the next idle st ate
on RXD after a frame is received.
• Obtain an interrupt while no character is received. This is performed by writing US_CR with
the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts
counting do wn immediately from the v alue T O . This enab les gener ation of a periodic interrupt
so that a user time-out can be handled, for example when no k ey is pressed on a keyboard.
If STTTO is performed, the counter clock is stopped until a first character is received. The idle
state on RXD before the start of the frame does not provide a time-out. This prevents having to
obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is
detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This
enables generation of a periodic interrupt so that a user time-out can be handled, for example
when no key is pressed on a keyboard.
Figure 33-14 shows the block diagram of the Receiver Time-out feature.
Figure 33-14. Receiver Time-out Block Diagram
Table 33-8 gives the maximum time-out period for some standard baud rates.
Table 33-8. Maximum Time-out Period
Baud Rate Bit Time Time-out
bit/sec µs ms
600 1 667 109 225
1 200 833 54 613
2 400 417 27 306
4 800 208 13 653
9 600 104 6 827
14400 69 4 551
19200 52 3 413
28800 35 2 276
33400 30 1 962
16-bit Time-out
Counter
0
TO
TIMEOUT
Baud Rate
Clock
=
Character
Received
RETTO
Load
Clock
16-bit
Value
STTTO
DQ
1
Clear
406 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.6.3.9 Framing Error
The receiver is capabl e of det ecting framing erro rs. A fra ming erro r happen s when t he stop b it of
a received character is detected at level 0. This can occur if the receiver and the transmitter are
fully desynchronized.
A framing error is reported on the FRAME bit of the Channe l Status Register (US_CSR). The
FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is
cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.
Figure 33-15. Framing Error Status
33.6.3.10 Transmit Break
The user can requ est the transmitt er to generate a break condition on the TXD line. A break con-
dition drives the TXD line low during at least one complete character. It appears the same as a
0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the
TXD line at least during one character until the user requests the brea k condition to be remo ved.
A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This
can be performed at any time, either while the transmitter is empty (no character in either the
Shift Register or in US_THR) or when a chara cter is being transmitte d. If a break is reque sted
while a character is b eing shifted out, the character is first completed before the TXD line is held
low.
Once STTBRK command is requested further STTBRK commands are igno red until the end of
the break is completed.
The break condition is remo ved by writing US_CR with the STPBRK bit at 1. If the STPBRK is
requested before the end of the minimum break duration (one character, including start, data,
parity and stop bits), the transmitter ensures that the break condition completes.
56000 18 1 170
57600 17 1 138
200000 5 328
Table 33-8. Maximum Time-out Period (Continued)
Baud Rate Bit Time Time-out
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
FRAME
RXRDY
RSTSTA = 1
407
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The transmitter con siders the break as though it is a chara cter, i.e. the STTBRK and STPBRK
commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the
break condition clears the TXRDY and TXEMPTY bits as if a character is processed.
Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable
result. All STPBRK commands requested without a previous STTBRK command are ignored. A
byte written into the Transmit Holding Register while a break is pending, but not started, is
ignored.
After the break co nd itio n, the tra ns mit te r re tu rn s th e T XD lin e to 1 fo r a minim u m of 12 bit tim e s.
Thus, the tran smitter ensures tha t the rem ote re ceiver det ects corre ctly th e end of br eak a nd the
start of the next character. If the timeguard is programmed with a value higher than 12, the TXD
line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 33-16 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK)
commands on the TXD line.
Figure 33-16. Break Transmission
33.6.3.11 Receive Break
The receiver detects a break con dition when all data, parity and stop bits are low. This corre-
sponds to detecting a framing error with data at 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR . This bit may
be cleared by writing the Contr ol Register (US_CR) with the bit RSTSTA at 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchro-
nous operating mode or one sample at high level in synchronous operating mode. The end of
break detection also asserts the RXBRK bit.
33.6.3.12 Ha rd ware Hand sh ak ing
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins
are used to connect with the remote device, as shown in Figure 33-17.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
TXRDY
TXEMPTY
STPBRK = 1
STTBRK = 1
Break Transmission End of Break
408 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 33-17. Connection with a Remote Device for Hardware Handshaking
Setting the USART to operate with hardware handshaking is performed by writing the
USART_MODE field in the Mode Register (US_MR) to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in
standard synchronous or asynchrono us mode, except that the receiver drives the RTS pin as
described below and the level on the CTS pin modifies the behavior of the transmitter as
described below. Using this m ode r equ ires using t he PDC chan ne l for r eceptio n. Th e t ransmit t er
can handle hardware handshaking in any case.
Figure 33-18 shows how the receiver operates if hardware handshaking is enabled. The RTS
pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) com-
ing from the PDC channel is high. Normally, the remote device does not start transmitting while
its CTS pin (driven by RTS) is high. As soon as the Receiver is ena bled, the RTS falls, indicating
to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the
status bit RXBUFF and, as a result, asserts the pin RTS low.
Figure 33-18. Receiver Behavior when Operating with Hardware Handshaking
Figure 33 -1 9 shows how the transmitter operates if hardware handshaking is enabled. The CTS
pin disables the transmitter. If a character is being processing, the transmitter is disabled only
after the completion of the current character and transmission of the next character happens as
soon as the pin CTS falls.
Figure 33-19. Transmitter Behavior when Operating with Hardware Handshaking
USART
TXD
CTS
Remote
Device
RXD
TXDRXD
RTS
RTS
CTS
RTS
RXBUFF
Write
US_CR
RXEN = 1
RXD RXDIS = 1
CTS
TXD
409
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.6.4 ISO 7 81 6 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing
with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link.
Both T = 0 and T = 1 protocols defined by the ISO781 6 specification are supported.
Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the
Mode Register (US_M R) t o th e value 0x4 f or prot oc ol T = 0 an d to th e valu e 0x5 for pr otocol T =
1.
33.6.4.1 ISO7816 Mod e Overview
The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is
determined by a division of the clock provided to the remo te de vice (see “Baud Rate Generator”
on page 393).
The USART connects to a smart car d as shown in Figur e 33- 20. The TXD line becomes bidirec-
tional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin
becomes bidirectional, its output remains driven by the output of the transmitter but only when
the transmitter is active while its input is directed to the input of the receiver. The USART is con-
sidered as the master of the communication as it generates the clock.
Figure 33-20. Connection of a Smart Card to the USART
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The
configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values pro-
grammed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB
or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode . Refer to
“USART Mode Register” on page 421 and “PAR: Parity Type” on page 422.
The USART cannot operate concurrently in both receiver and transmitter modes as the commu-
nication is unidirectional at a time. It has to be configured according to the required mode by
enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver
and the transmitter at the same time in ISO7816 mode may lead to unpredictable re sults.
The ISO7816 specification defines an inverse transmission format. Data bits of the character
must be transmitt ed on the I/O lin e at their nega tive value. The USART does not support t his for-
mat and the user has to perform an exclusive OR on the data before writing it in the Transmit
Holding Register (US_THR) or af ter reading it in the Receive Holding Register (US_RHR).
33.6.4.2 Protocol T = 0
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one
guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the
I/O line during the guard time.
If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter
can continue with the transmission of the next character, as shown in Figure 33-21.
Smart
Card
SCK CLK
TXD I/O
USART
410 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
If a parity error is detected by the receiver, it drives the I/O line at 0 du ring the guard time, as
shown in Figure 33-22. This error bit is also named NACK, for Non Acknowledge. In this case,
the character lasts 1 bit time more, as the guard time length is the same and is added to the
error bit time which last s 1 bit time.
When the USART is th e receiver and it detects an error, it does not load the er roneous cha racter
in the Receive Holding Regist er (US_RHR). It appropriat ely sets the PARE bit in t he Status Reg-
ister (US_SR) so that the software can handle the error.
Figure 33-21. T = 0 Protocol without Parity Error
Figure 33-22. T = 0 Protocol with Parity Error
33.6.4.3 Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of
Error (US_NER) register. The NB_ERRORS field can record up to 255 error s. Reading US_NER
automatically clears the NB_ERRORS field.
33.6.4.4 Receive NACK Inhibit
The USART can also be configured to inhibit an error. This can be achieved by setting the
INACK bit in the Mode Register (US_MR). If INACK is a t 1, no error signal is driven on the I/O
line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The
INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding
Register, as if no er ror occurred. However, the RXRDY bit does not raise.
33.6.4.5 Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can autom atically repeat the
character before moving on to the next one. Repetition is enabled by writing the
MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character
can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as
the value loaded in MAX_ITERATION.
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Next
Start
Bit
Guard
Time 2
D0 D1 D2 D3 D4 D5 D6 D7
I/O
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Start
Bit
Guard
Time 2 D0 D1
Error
Repetition
411
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
When the USART repetiti on num ber rea ches MAX_I TERATION, t he I TERATION bit is se t in the
Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the
receiver, the repetitions are stopped and the iteration counter is cleared.
The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit
at 1.
33.6.4.6 Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter.
This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum
number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as
MAX_ITERATION is reached, the char acter is cons ider ed as cor rect, an acknowledge is sent on
the line and the ITERATION bit in the Channel Status Registe r is set.
33.6.4.7 Protocol T = 1
When operating in ISO7816 protocol T = 1, the transm ission is similar to an asynchronous for-
mat with only one stop bit. The parity is generated when transmitting and checked when
receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR).
33.6.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to- point wireless communica-
tion. It embeds the modulator and demodulator which allows a glueless connection to the
infrared transceivers, as shown in Figure 33-23. The modulator and demodulator are compliant
with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to
115.2 Kb/s.
The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register
(US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator
filter. The USART transmitter an d receiver operate in a normal asynchronous mode and all
parameters are accessible. Note that the modulator and the demodulator are activated.
Figure 33-23. Connection to IrDA Transceivers
The receiver and the transmitter must be enabled or disabled according to the direction of the
transmission to be managed.
IrDA
Transceivers
RXD RX
TXD TX
USART
Demodulator
Modulator
Receiver
Transmitter
412 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.6.5.1 IrDA Modulation
For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is
represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are
shown in Table 33-9.
Figure 33-24 shows an example of character transmission.
Figure 33-24. IrDA Modulation
33.6.5.2 IrDA Baud Rate
Table 33-10 gives some examples of CD values, baud rate error and pulse duration. Note that
the requirement on the maximum acceptable error of ±1.87% must be met.
Table 33-9. IrDA Pulse Duration
Baud Rate Pulse Duration (3/16)
2.4 Kb/s 78.13 µs
9.6 Kb/s 19.53 µs
19.2 Kb/s 9.77 µs
38.4 Kb/s 4.88 µs
57.6 Kb/s 3.26 µs
115.2 Kb/s 1.63 µs
Bit Period Bit Period
3
16
Start
Bit Data Bits Stop
Bit
00
000
111 1
1
Transmitter
Output
TXD
Table 33-10. IrDA Baud Rate Error
Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time
3 686 400 115 200 2 0.00% 1.63
20 000 000 115 200 11 1.38% 1.63
32 768 000 115 200 18 1.25% 1.63
40 000 000 115 200 22 1.38% 1.63
3 686 400 57 600 4 0.00% 3.26
20 000 000 57 600 22 1.38% 3.26
32 768 000 57 600 36 1.25% 3.26
40 000 000 57 600 43 0.93% 3.26
3 686 400 38 400 6 0.00% 4.88
20 000 000 38 400 33 1.38% 4.88
413
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.6.5.3 IrDA Demodulato r
The demodulator is based on t he IrDA Receive filter comprised of an 8-bit down count er which is
loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin,
the Filter Counter starts co unting down at the Master Clock (MCK) spee d. If a rising edge is
detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is
detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
Figure 33-25 illustrates the operations of the IrDA demodulator.
Figure 33-25. IrDA Demodulator Operations
As the IrDA mode uses the same log ic as the I SO7816, note that the FI_DI _RATIO field in
US_FIDI must be set to a value higher than 0 in order to assure IrDA communicat ions operate
correctly.
32 768 000 38 400 53 0.63% 4.88
40 000 000 38 400 65 0.16% 4.88
3 686 400 19 200 12 0.00% 9.77
20 000 000 19 200 65 0.16% 9.77
32 768 000 19 200 107 0.31% 9.77
40 000 000 19 200 130 0.16% 9.77
3 686 400 9 600 24 0.00% 19.53
20 000 000 9 600 130 0.16% 19.53
32 768 000 9 600 213 0.16% 19.53
40 000 000 9 600 260 0.16% 19.53
3 686 400 2 400 96 0.00% 78.13
20 000 000 2 400 521 0.03% 78.13
32 768 000 2 400 853 0.04% 78.13
Table 33-10. IrDA Baud Rate Error (Continued)
Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time
MCK
RXD
Receiver
Input
Pulse
Rejected
65432 61
65432 0
Pulse
Accepted
Counter
Value
414 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485
mode, the USART behaves as though in asynchronous or synchronous mode and configuration
of all the parameters is possible. The difference is that the RTS pin is driven high when the
transmitter is operating. The behavio r of the RTS pin is contr olled by the TXEMPTY bit . A typical
connection of the USART to a RS485 bus is shown in Figure 33-26.
Figure 33-26. Typical Connection to a RS485 Bus
The USART is set in RS485 mode by programming the USART_MODE field in the Mode Regis-
ter (US_MR) to the value 0x1.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high
when a timeguard is pr ogrammed so that the line can re main driven aft er the last charact er com-
pletion. Figure 3 3-27 gives an example of the RTS waveform during a character transmission
when the timeguard is enabled.
Figure 33-27. Example of RTS Drive with Timeguard
USART
RTS
TXD
RXD
Differential
Bus
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
TG = 4
Write
US_THR
TXRDY
TXEMPTY
RTS
415
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal
Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Car-
rier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a
DTE (Data Terminal Equ ipment) as it drives DTR and RTS a nd can dete ct level chang e on DSR,
DCD, CTS and RI.
Setting the USART in modem mode is perfo rmed by writing t he USART_MODE field in the Mode
Register (US_MR) to the value 0x3. While operating in mod em mode the USART behaves as
though in asynchronous mode and all the paramete r configurations are available.
Table 33-11 gives the correspondence of the USART signals with modem connection standards.
The control of the DTR ou tput pin is performed by writing the Control Register (US_CR) with the
DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin
to its inactive level, i.e. high. The enable command forces the corresponding pin to its active
level, i.e. low. RTS output pin is automatically controlled in this mode
The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is
detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR)
are set respectively and can trigger an in terrupt. The status is automatically cleared when
US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is
detected at its inactive state. If a character is being transmitted when the CTS rises, the charac-
ter transmission is completed before the transmitter is actually disabled.
33.6.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback
capability allows on-board diagnostics. In the loopback mode the USART interfac e pins are dis-
connected or not and reconfigured for loopba ck internally or externally.
33.6.8.1 Normal Mode
Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD
pin.
Table 33-11. Circuit References
USART Pin V24 CCITT Direction
TXD 2 103 From terminal to modem
RT S 4 105 From terminal to modem
DTR 20 108.2 From terminal to modem
RXD 3 104 From modem to terminal
CTS 5 106 From terminal to modem
DSR 6 107 From terminal to modem
DCD 8 109 F rom terminal to modem
RI 22 125 From terminal to modem
416 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 33-28. Normal Mode Configuration
33.6.8.2 Automatic Echo Mode
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it
is sent to the TXD pin, as shown in Figu re 33-29 . Programming the transmitter has no effect on
the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains
active.
Figure 33-29. Automatic Echo Mode Configuration
33.6.8.3 Local Loopback Mode
Local loopback mode connects the output of the transmitter directly to the input of the receiver,
as shown in Figure 33-30. The TXD and RXD pins are not used. The RXD pin has no effect on
the receiver and the TXD pin is continuously driven high, as in idle state.
Figure 33-30. Local Loopback Mode Configuration
33.6.8.4 Remote Loopback Mode
Remote loopback mode directly connects the RXD p in to the TXD pin, a s shown in Figure 33 -31.
The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit
retransmission.
Receiver
Transmitter
RXD
TXD
Receiver
Transmitter
RXD
TXD
Receiver
Transmitter
RXD
TXD
1
417
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 33-31. Remote Loopback Mode Configuration
Receiver
Transmitter
RXD
TXD
1
418 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7 USART User Interface
Table 33-12. USART Memory Map
Offset Register Name Access Reset State
0x0000 Control Register US_CR Write-only –
0x0004 Mode Register US_MR Read/Write –
0x0008 Interrupt Enable Register US_IER Wr ite-only –
0x000C Interr upt Disable Register US_IDR Write-only –
0x0010 Interrupt Mask Register US_IMR Read-only 0x0
0x0014 Channel Status Register US_CSR Read-only –
0x0018 Receiver Holding Register US_RHR Read-only 0x0
0x001C Transmitter Holding Registe r US_THR Write-only –
0x0020 Baud Rate Generator Register US_BRGR Read/Write 0x0
0x0024 Receiver Time-out Register US_RTOR Read/Write 0x0
0x0028 Transmitter Timeguard Register US_TTGR Read/Write 0x0
0x2C - 0x3C Reserved – – –
0x0040 FI DI Ratio Register US_FIDI Read/Write 0x174
0x0044 Number of Errors Registe r US_NER Read-only –
0x0048 Reserved – – –
0x004C IrDA Filter Register US_IF Read/Write 0x0
0x5C - 0xFC Reserved – – –
0x100 - 0x128 Reserved for PDC Registers – – –
419
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.1 USART Control Regi st er
Name: US_CR
Access: Write-only
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Rese t Tra nsm it te r
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Dis able
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE, and RXBRK in US_CSR.
• STTBRK: Start Break
0: No effect.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RTSDISRTSENDTRDISDTREN
15 14 13 12 11 10 9 8
RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
420 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-
mitted. No effect if a break is already being transmitted.
• STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break aft er a minimum of one char acter length and transmits a high level during 12-bit periods.
No effect if no break is being transmitted.
• STTTO: Start Time-out
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
0: No effect.
1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Reset Iterations
0: No effect.
1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO: Rearm Time-out
0: No effect
1: Restart Time-out
• DTREN: Data Terminal Ready Enable
0: No effect.
1: Drives the pin DTR at 0.
• DTRDIS: Data Terminal Ready Disable
0: No effect.
1: Drives the pin DTR to 1.
• RTSEN: Request to Send Enable
0: No effect.
1: Drives the pin RTS to 0.
• RTSDIS: Request to Send Disable
0: No effect.
1: Drives the pin RTS to 1.
421
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.2 USA RT Mode Register
Name: US_MR
Access: Read/Write
• USART_MODE
• USCLKS: Clock Selection
• CHRL: Character Length.
31 30 29 28 27 26 25 24
– – – FILTER – MAX_ITERATION
23 22 21 20 19 18 17 16
– – DSNACK INACK OVER CLKO MODE9 MSBF
15 14 13 12 11 10 9 8
CHMODE NBSTOP PAR SYNC
76543210
CHRL USCLKS USART_MODE
USART_MODE Mode of the USART
0000Normal
0001RS485
0 0 1 0 Hardware Handshaking
0011Modem
0 1 0 0 IS07816 Protocol: T = 0
0101Reserved
0 1 1 0 IS07816 Protocol: T = 1
0111Reserved
1000IrDA
11xxReserved
USCLKS Selected Clock
00MCK
0 1 MCK/DIV (DIV = 8)
10Reserved
11SCK
CHRL Character Length
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
422 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• SYNC: Synchronous Mode Select
0: USART operates in Asynchronous Mode.
1: USART operates in Synchronous Mode.
• PAR: Parity Type
• NBSTOP: Number of Stop Bits
• CHMODE: Channel Mode
• MSBF: Bit Order
0: Least Significant Bit is sent/received first.
1: Most Significant Bit is sent/received first.
• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
• CLKO: Clock Output Select
0: The USART does not drive the SCK pin.
1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.
• OVER: Oversampling Mode
0: 16x Oversampling.
PAR Parity Type
0 0 0 Even parity
001Odd parity
0 1 0 Parity forced to 0 (Space)
0 1 1 Parity forced to 1 (Mark)
1 0 x No parity
1 1 x Multidrop mode
NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1)
0 0 1 stop bit 1 stop bit
0 1 1.5 stop bits Reserved
1 0 2 stop bits 2 stop bits
1 1 Reserved Reserved
CHMODE Mode Description
0 0 Normal Mode
0 1 Automatic Echo. Receiver input is connected to the TXD pin.
1 0 Local Loopback. Transmitter outp ut is connected to the Receiver Input..
1 1 Remote Loopback. RXD pin is internally connected to the TXD pin.
423
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
1: 8x Oversampling.
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generat ed.
• DSNACK: Disable Successive NACK
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-
ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag
ITERATION is asserted.
• MAX_ITERATION
Defines the maximum number of iterations in mode ISO7816, protocol T= 0.
• FILTER: Infrared Receive Line Filter
0: The USART does not filter the rece ive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
424 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.3 USA RT Interrupt Enable Register
Name: US_IER
Access: Write-only
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• RXBRK: Receiver Break Int errupt Enable
• ENDRX: End of Receiv e Transfer Interrupt Enable
• ENDTX: End of Transmit Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Enable
• PARE: Parity Error Interrupt Enable
• TIMEOUT: Time-out Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• ITERATION: Iteration Interrupt Enable
• TXBUFE: Buffer Empty Interrupt Enable
• RXBUFF: Buffer Full Interrupt Enable
• NACK: Non Acknowledge Interrupt Enable
• RIIC: Ring Indicator Input Change Enable
• DSRIC: Data Set Ready Input Change Enable
• DCDIC: Data Carrier Detect Input Change Interrupt Enable
• CTSIC: Clear to Send Input Change Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––CTSICDCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITERATION TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
425
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.4 USA RT Interrupt Disable Register
Name: US_IDR
Access: Write-only
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• ENDRX: End of Receiv e Transfer Interrupt Disable
• ENDTX: End of Transmit Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITERATION: Iteration Interrupt Disable
• TXBUFE: Buffer Empty Interrupt Disable
• RXBUFF: Buffer Full Interrupt Disable
• NACK: Non Acknowledge Interrupt Disab le
• RIIC: Ring Indicator Input Change Disable
• DSRIC: Data Set Ready Input Change Disable
• DCDIC: Data Carrier Detect Input Change Interrupt Disable
• CTSIC: Clear to Send Input Change Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––CTSICDCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITERATION TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
426 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.5 USA RT Interrupt Mask Regi st er
Name: US_IMR
Access: Read-only
• RXRDY: RXRDY Interru p t Mas k
• TXRDY: TXRDY Interrupt Mask
• RXBRK: Receiver Break Interrupt Mask
• ENDRX: End of Receive Transfer Inte rrupt Mask
• ENDTX: End of Transmit Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TIMEOUT: Time-out Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• ITERATION: Iteration Interrupt Mask
• TXBUFE: Buffer Empty Interrupt Mask
• RXBUFF: Buffer Full Interrupt Mask
• NACK: Non Acknowledge Interrupt Mask
• RIIC: Ring Indicator Input Change Mask
• DSRIC: Data Set Ready Input Change Mask
• DCDIC: Data Carrier Detect Input Change Interrupt Mask
• CTSIC: Clear to Send Input Change Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––CTSICDCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITERATION TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
427
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.6 USART Channe l Status Register
Name: US_CSR
Access: Read-only
• RXRDY: Receiver Rea dy
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be tr ansferred t o the Transmit Shif t Register, or an STTBRK comm and has been
requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• RXBRK: Break Received/E nd of Break
0: No Break received or End of Break detected since the last RSTSTA.
1: Break Received or End of Break detected since th e last RSTSTA.
• ENDRX: End of Receiver Transfer
0: The End of Transfer signal from the Receive PDC channel is inactive.
1: The End of Transfer signal from the Receive PDC channel is active.
• ENDTX: End of Transmitter Transfer
0: The End of Transf er signal from the Transmit PDC channel is inactive.
1: The End of Transf er signal from the Transmit PDC channel is active.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has bee n detected low since the last RSTSTA.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CTS DCD DSR RI CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITERATION TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
428 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• PARE: Parity Error
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
• TIMEOUT: Receiver Time-out
0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• TXEMPTY: Transmitter Empty
0: There are charact ers in either US_THR or the Transmit Shift Register, or the transmitte r is di sabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• ITERATION: Max number of Repetitions Reached
0: Maximum number of repetitions has not been reached since the last RSIT.
1: Maximum number of rep etitions has been reached since the last RSIT.
• TXBUFE: Transmission Buffer Empty
0: The signal Buffer Empty from the Transmit PDC channel is inactive.
1: The signal Buffer Empty from the Transmit PDC channel is active.
• RXBUFF: Reception Buffer Full
0: The signal Buffer Full from the Receive PDC channel is inactive.
1: The signal Buffer Full from the Receive PDC channel is active.
• NACK: Non Acknowledge
0: No Non Acknowledge has not been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
• RIIC: Ring Indicator Input Change Flag
0: No input change has been detected on the RI pin since the last read of US_CSR.
1: At least one input change has been detected on the RI pin since the last rea d of US_CSR.
• DSRIC: Data Set Ready Input Change Flag
0: No input change has been detected on the DSR pin since the last read of US_CSR.
1: At least one input change has been detected on the DSR pin since the last read of US_CSR.
• DCDIC: Data Carrier Detect Input Change Flag
0: No input change has been detected on the DCD pin since the last read of US_CSR.
1: At least one input change has been detected on the DCD pin since the last read of US_CSR.
• CTSIC: Clear to Send Input Change Flag
0: No input change has been detected on the CTS pin since the last read of US_CSR.
1: At least one input chang e has been detected on the CTS pin since the last read of US_CSR.
429
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• RI: Image of RI Input
0: RI is at 0.
1: RI is at 1.
• DSR: Image of DSR Input
0: DSR is at 0
1: DSR is at 1.
• DCD: Image of DCD Input
0: DCD is at 0.
1: DCD is at 1.
• CTS: Image of CTS Input
0: CTS is at 0.
1: CTS is at 1.
430 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.7 USA RT Receive Holding Register
Name: US_RHR
Access: Read-only
• RXCHR: Received Character
Last character received if RXRDY is set.
• RXSYNH: Received Sync
0: Last Character received is a Data.
1: Last Character received is a Command.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RXSYNH ––––––RXCHR
76543210
RXCHR
431
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.8 USART Transmit Holding Register
Name: US_THR
Access: Write-only
• TXCHR: Character to be Transmitted
Next character to be transmitted after t he current character if TXRDY is not s et.
• TXSYNH: Sync Field to be transmitted
0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
1: The next characte r sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXSYNH ––––––TXCHR
76543210
TXCHR
432 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.9 USART Baud Rate Generator Register
Name: US_BRGR
Access: Read/Write
• CD: Clock Divider
• FP: Fractional Part
0: Fractional div ide r is disa ble d .
1 - 7: Baudrate resolution, defined by FP x 1/8.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– FP
15 14 13 12 11 10 9 8
CD
76543210
CD
CD
USART_MODE ≠ ISO7816 USART_MODE =
ISO7816
SYNC = 0 SYNC = 1
OVER = 0 OVER = 1
0 Baud Rate Clock Disabled
1 to 65535 Baud Rate =
Selected Clock/16/CD Baud Rate =
Selected Clock/8/CD Baud Rate =
Selected Clock /CD Baud Rate = Selected
Clock/CD/FI_DI_RATIO
433
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.10 USART Receiver Time-out Register
Name: US_RTOR
Access: Read/Write
• TO: Time-out Value
0: The Receiver Time-out is disabled.
1 - 65535: The Receiver Time -out is enabled and the Time-out delay is TO x Bit Period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TO
76543210
TO
434 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.11 USART Transmitter Timeguard Register
Name: US_TTGR
Access: Read/Write
• TG: Timeguard Value
0: The Transmitter Timeguard is disabled.
1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TG
435
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.12 USART FI DI RATIO Register
Name: US_FIDI
Access: Read/Write
Reset Value : 0x174
• FI_DI_RATIO: FI Over DI Ratio Value
0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.
33.7.13 USART Number of Err ors Register
Name: US_NER
Access: Read-only
• NB_ERRORS: Number of Errors
Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––– FI_DI_RATIO
76543210
FI_DI_RATIO
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
NB_ERRORS
436 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
33.7.14 USART IrDA FILTER Register
Name: US_IF
Access: Read/Write
• IRDA_FILTER: IrDA Filter
Sets the filter of the IrDA demodulator.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
IRDA_FILTER
437
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34. Parallel Input Output Controller (PIO)
34.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output
lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of
an embedded peripheral. This assures effective optimization of the pins of a product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User
Interface.
Each I/O line of the PIO Controller features:
• An input change interrupt enabling level change detection on any I/O line.
• A glitch filter providing rejection of pulses lower than one-half of clock cycle.
• Multi-drive capability similar to an open drain I/O line.
• Control of the pull-up of the I/O line.
• Input visibility and output control.
The PIO Controller also featu res a synchro nous output pr oviding up to 32 bi ts of dat a output in a
single write opera tion.
438 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.2 Block Diagram
Figure 34-1. Block Diagram
Figure 34-2. Application Block Diagram
Embedded
Peripheral
Embedded
Peripheral
PIO Interrupt
PIO Controller
Up to 32 pins
PMC
Up to 32
peripheral IOs
Up to 32
peripheral IOs
PIO Clock
APB
AIC
Data, Enable
PIN 31
PIN 1
PIN 0
Data, Enable
On-Chip Peripherals
PIO Controller
On-Chip Peripheral Drivers
Control & Command
Driver
Keyboard Driver
Keyboard Driver General Purpose I/Os External Devices
439
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.3 Product Dependencies
34.3.1 Pin Multiplexing
Each pin is configurab le, according to product de finition as either a general-pur pose I/O line
only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hard-
ware-defined and thus product-dependent, the hardware designer and programmer must
carefully determine the configuration of the PIO controllers required by their application. When
an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of
the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Con-
troller can contr ol how th e pin is drive n by th e pr od u ct.
34.3.2 Exte rna l Inte rrupt Li nes
The interrupt signals FIQ and IRQ0 to IRQ n are most generally multiplexed through th e PIO
Controllers. Howeve r, it is not necessary to assign the I/O line to the interrupt function as the
PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as
inputs.
34.3.3 Power Management
The Power Management Controller controls the PIO Controller clock in order to save power.
Writing any of the registers of the user interface does not require the PIO Controller clock to be
enabled. This mea ns that the configuratio n of the I/O lines does not req uire the PIO Controlle r
clock to be enabled.
However, when the clock is disabled, not all of the features of the PIO Controller are available.
Note that the Input Change Interrupt and the read of the pin level require the clock to be
validated.
After a hardware reset, the PIO clock is disabled by default.
The user must configure the Power Management Controller before any access to the input line
information.
34.3.4 Interrupt Generation
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that
the PIO Co ntroller inter rupt lines are co nnected among t he interrup t sources 2 to 31 . Refer to the
PIO Controller peripheral id entifier in the product description to identify the interrupt sources
dedicated to the PIO Con tro lle rs.
The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.
440 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.4 Functional Description
The PIO Contro ller features u p to 32 fully-pro grammable I/O lines. Most of the control logic asso-
ciated to each I/O is represented in Figure 34-3. In this description each signal shown
represents but on e of up to 32 possible indexes.
Figure 34-3. I/O Line Control Logic
1
0
1
0
1
0
Glitch
Filter
Peripheral B
Input
Peripheral A
Input
1
0
PIO_IFDR[0]
PIO_IFSR[0]
PIO_IFER[0]
Edge
Detector
PIO_PDSR[0] PIO_ISR[0]
PIO_IDR[0]
PIO_IMR[0]
PIO_IER[0]
PIO Interrupt
(Up to 32 possible inputs)
PIO_ISR[31]
PIO_IDR[31]
PIO_IMR[31]
PIO_IER[31]
Pad
1
0
PIO_PUDR[0]
PIO_PUSR[0]
PIO_PUER[0]
PIO_MDDR[0]
PIO_MDSR[0]
PIO_MDER[0]
PIO_CODR[0]
PIO_ODSR[0]
PIO_SODR[0]
PIO_PDR[0]
PIO_PSR[0]
PIO_PER[0]
1
0
1
0
PIO_BSR[0]
PIO_ABSR[0]
PIO_ASR[0]
Peripheral B
Output Enable
Peripheral A
Output Enable
Peripheral B
Output
Peripheral A
Output
PIO_ODR[0]
PIO_OSR[0]
PIO_OER[0]
441
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.4.1 Pull- up Resistor Control
Each I/O line is design ed with a n embedd ed pull-u p resist or. The pull- up resist or can b e enabled
or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-
up Disable Resistor). Wr iting in the se register s resu lts in sett ing or clear ing the corr esponding bit
in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is dis-
abled and readin g a 0 me a ns the pu ll-u p is enab le d.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.
34.4.2 I/O Line or P eripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with
the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The regis-
ter PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates
whether the pin is co ntrolled by the cor respond ing pe ripheral or by t he PIO Con troller. A va lue of
0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO
controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral),
PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines ar e controlled by the PIO controller, i.e. PIO_PSR
resets at 1. However, in some events, it is important that PIO lines are controlled by the periph-
eral (as in the case of memory chip select lines that must be driven inactive after reset or for
address lines that must be driven low for booting out of an external memory) . Thus, the reset
value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
34.4.3 Peripheral A or B Selection
The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The
selection is performed by writing PIO_ASR (A Select Register) an d PIO_BSR (Select B Re gis-
ter). PIO_ABSR (AB Sele ct Status Re gister) in dicates which pe ripheral l ine is cu rrently sele cted.
For each pin, the corr esponding bit at level 0 means peripheral A is selected whereas the corre-
sponding bit at level 1 indicates that peripheral B is selected.
Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral
input lines are always conn ected to the pin input.
After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A.
However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line
mode.
Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the
pin. Howeve r, assignm ent of a pin to a pe ripheral fun ction req uires a write in the corr espondin g
peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR.
34.4.4 Output ControlWhen the I/0 line is assigned to a periph eral functi o n, i.e. the cor responding bit in PIO _PSR is at
0, the drive of the I/O line is co ntrolled by the peripheral. Peripheral A or B, dependin g on the
value in PIO_ABSR, determines whether the pin is driven or not.
When the I/O line is cont ro lled by th e PI O contr oller, th e p in can b e config ured t o be driven . T his
is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register).
442 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The results of these write operations are detected in PIO_OSR (Output Status Register). When
a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at
1, the corresponding I /O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data
Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set
and clear PIO_ODSR ( Output Data Stat us Register), which represents t he data driven on t he I/O
lines. Writing in PIO_OER and PIO_ODR mana ges PIO_OSR whether the pin is configured to
be controlled by the PIO controller or assigned to a peripheral function. This enables configura-
tion of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it
defines the first level driven on the I/O line.
34.4.5 Synchronous Data Output
Controlling all parallel busses using several PIOs requires two successive write operations in the
PIO_SODR and PIO_CODR registers. This may le ad to unexpected transient values. The PIO
controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output
Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are
written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable
Register) and cleared by writing to PIO_OWDR (Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at
0x0.
34.4.6 Multi Drive Control (Open Drain)
Each I/O can be independently progr ammed in Open Drain by using the Multi Drive feature. This
feature permits several drivers to be connected on the I/O line which is driven low only by each
device. An ext ernal pull-up resist or (or ena bling of the inter nal one ) is generally re quired to guar-
antee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and
PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line
is controlled by t he PIO controller or assigned t o a peripheral f unction. PIO_M DSR (Multi-drive r
Status Register) indicates the pins that are configured to support extern al drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
34.4.7 Output Line Timings
Figure 34-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by
directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is
set. Figure 34-4 also shows when the feedback in PIO_PDSR is available.
443
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 34-4. Output Line Timings
34.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO cont roller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
34.4.9 Input Glitch Filtering
Optional input glitch fil te rs are ind epende nt ly prog ra mmab le on each I /O line . When t he glit ch fil-
ter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically
rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse
durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not
be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be
visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its
duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle
latency if the pin level change occurs before a rising edge. However, this latency does not
appear if the pin level change occurs before a falling edge. This is illustrated in Figure 34-5.
The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch filter is enabled, it does not modify the b ehavior of the inputs on the peripherals.
It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The
glitch filters require that the PIO Controller clock is enabled.
2 cycles
APB Access
2 cycles
APB Access
MCK
Write PIO_SODR
Write PIO_ODSR at 1
PIO_ODSR
PIO_PDSR
Write PIO_CODR
Write PIO_ODSR at 0
444 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 34-5. Input Glitch Filter Timing
34.4.10 Input Change Interrupt
The PIO Controller ca n be program med to generat e an interrupt when it detects an input change
on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable
Register) and PIO_IDR (Int errupt Disable Register), which respective ly enable and disable the
input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask
Register). As Inp ut change de te ction is po ssible on ly by comp arin g two successive sa mplin gs of
the input of the I/O line, the PIO Contr oller clock must be enabled . The In put Chang e In terr up t is
available, rega rdless of the configuration of t he I/O line, i.e. configured as an input only, con-
trolled by the PIO Controller or assigned to a peripheral f unction.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt
Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt
line is asserted. T he interrupt signals of the thirty-two channels are ORed-wired together to gen-
erate a single interrupt signal to the Advanced Interrupt Controller.
When the software re ads PIO_ISR, all t he interrupts ar e automaticall y cleared. This signif ies that
all the interrupts that are pending when PIO_ISR is read must be handled.
Figure 34-6. Input Change Interrupt Timings
34.5 I/O Lines Programming Example
The programing example as shown in Table 34-1 below is used to define the following
configuration.
• 4-bit output po rt on I/O lines 0 to 3, (should be written in a single write operation) , open-dra in,
with pull-up resistor
MCK
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle 1 cycle 1 cycle
up to 1.5 cycles
2 cycles
up to 2.5 cycles up to 2 cycles
1 cycle
1 cycle
MCK
Pin Level
Read PIO_ISR APB Access
PIO_ISR
APB Access
445
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no
pull-up resistor
• Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up
resistors, glitch filters and input change interrupts
• F our input signals on I/O line 12 to 15 t o read an external de vice stat us (polle d, thus no inp ut
change interrupt), no pull-up resistor, no glitch filter
• I/O lines 16 to 19 assigned to periphera l A functions with pull-up resistor
• I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor
• I/O line 24 to 27 assig ned to peripheral A with Input Change Interrupt and pull-up resistor
Table 34-1. Programming Example
Register Value to be Written
PIO_PER 0x0000 FFFF
PIO_PDR 0x0FFF 0000
PIO_OER 0x0000 00FF
PIO_ODR 0x0FFF FF00
PIO_IFER 0x0000 0F00
PIO_IFDR 0x0FFF F0FF
PIO_SODR 0x0000 0000
PIO_CODR 0x0FFF FFFF
PIO_IER 0x0F00 0F00
PIO_IDR 0x00FF F0FF
PIO_MDER 0x0000 000F
PIO_MDDR 0x0FFF FFF0
PIO_PUDR 0x00F0 00F0
PIO_PUER 0x0F0F FF0F
PIO_ASR 0 x 0F0F 0000
PIO_BSR 0x00F0 0000
PIO_OWER 0x0000 000F
PIO_OWDR 0x0FFF FFF0
446 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6 PIO User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Control-
ler User Interface reg isters. Each register is 32 bits wide. If a parallel I/O line is no t defined,
writing to the corr esponding bits ha s no effect . Undefine d bits read zer o. If the I/O line is not mul-
tiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns
1 systematically.
Table 34-2. PIO Register Mapping
Offset Register Name Access Reset Value
0x0000 PIO Enable Register PIO_PER Write-only –
0x0004 PIO Disable Register PIO_PDR Write-only –
0x0008 PIO Status Register PIO_PSR Read-only (1)
0x000C Reserved
0x0010 Output Enable Register PIO_OER Write-only –
0x0014 Output Disable Register PIO_ODR Write-only –
0x0018 Output Status Register PIO_OSR Read-only 0x0000 0000
0x001C Reserved
0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only –
0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only –
0x0028 Glitch Input Filter Status Register PIO_IFSR R ead-only 0x0000 0000
0x002C Reserved
0x0030 Set Output Data Register PIO_SODR Wr ite-only –
0x0034 Clear Output Data Register PIO_CODR Write-only
0x0038 Output Data Status Register PIO_ODSR Read-only
or(2)
Read/Write –
0x003C Pin Data Status Register PIO_PDSR Read-only (3)
0x0040 Interrupt Enable Register PIO_IER Write-only –
0x0044 Interrupt Disable Register PIO_IDR Write-only –
0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000
0x004C Interrupt Status Register(4) PIO_ISR Read-only 0x00000000
0x0050 Multi-driver Enable Register PIO_MDER Write-only –
0x0054 Multi-driver Disable Register PIO_MDDR Write-only –
0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000
0x005C Reserved
0x0060 Pull-up Disable Register PIO_PUDR Write-only –
0x0064 Pull-up Enable Register PIO_PUER Write-only –
0x0068 Pad Pull-up Status Register PIO_PUSR Read-only 0x00000000
0x006C Reserved
447
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Notes: 1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disab led.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second
register.
0x0070 Peripheral A Select Register(5) PIO_ASR Write-only –
0x0074 Peripheral B Select Register(5) PIO_BSR Write-only –
0x0078 AB Status Register(5) PIO_ABSR Read-only 0x00000000
0x007C
to
0x009C Reserved
0x00A0 Output Write Enable PIO_OWER Write-only –
0x00A4 Output Write Disable PIO_OWDR Write-only –
0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000
0x00AC Reserved
Table 34-2. PIO Register Mapp ing (Continued)
Offset Register Name Access Reset Value
448 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.1 PIO Controller PIO Enable Register
Name: PIO_PER
Access: Write-only
• P0-P31: PIO Enable
0 = No effect.
1 = Enables the PIO to control the corresponding pin (disa bles peripheral control of the pin).
34.6.2 PIO Controller PIO Disable Register
Name: PIO_PDR
Access: Write-only
• P0-P31: PIO Disable
0 = No effect.
1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
449
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.3 PIO Controller PIO Status Register
Name: PIO_PSR
Access: Read-only
• P0-P31: PIO Status
0 = PIO is inactive on the corresponding I/O line (peripheral is active).
1 = PIO is active on the corresponding I/O line (peripheral is inactive).
34.6.4 PIO Controller Output Enable Register
Name: PIO_OER
Access: Write-only
• P0-P31: Output Enable
0 = No effect.
1 = Enables the output on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
450 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.5 PIO Controller Output Disable Register
Name: PIO_ODR
Access: Write-only
• P0-P31: Output Disable
0 = No effect.
1 = Disables the output on the I/O line.
34.6.6 PIO Controller Output Status Register
Name: PIO_OSR
Access: Read-only
• P0-P31: Output Status
0 = The I/O line is a pure input.
1 = The I/O line is enabled in output.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
451
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.7 PIO Controller Input Filt er Enable Register
Name: PIO_IFER
Access: Write-only
• P0-P31: Input Filter Enable
0 = No effect.
1 = Enables the input glitch filter on the I/O line.
34.6.8 PIO Controller Input Filter Disable Register
Name: PIO_IFDR
Access: Write-only
• P0-P31: Input Filter Disable
0 = No effect.
1 = Disables the input glitch filter on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
452 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.9 PIO Controller Input Filter Status Register
Name: PIO_IFSR
Access: Read-only
• P0-P31: Input Filer Status
0 = The input glitch filter is disabled on the I/O line.
1 = The input glitch filter is enabled on the I/O line.
34.6.10 PIO Controller Set Output Data Register
Name: PIO_SODR
Access: Write-only
• P0-P31: Set Output Data
0 = No effect.
1 = Sets the data to be driven on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
453
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.11 PIO Controller Clear Output Data Register
Name: PIO_CODR
Access: Write-only
• P0-P31: Set Output Data
0 = No effect.
1 = Clears the data to be driven on the I/O line.
34.6.12 PIO Controller Output Data Status Register
Name: PIO_ODSR
Access: Read-only or Read/Write
• P0-P31: Output Data Status
0 = The data to be driven on the I/O line is 0.
1 = The data to be driven on the I/O line is 1.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
454 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.13 PIO Controller Pin Data Status Register
Name: PIO_PDSR
Access: Read-only
• P0-P31: Output Data Status
0 = The I/O line is at level 0.
1 = The I/O line is at level 1.
34.6.14 PIO Controller Interrupt Enable Register
Name: PIO_IER
Access: Write-only
• P0-P31: Input Change Interrupt Enable
0 = No effect.
1 = Enables the Input Change Interrupt on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
455
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.15 PIO Controller Interrupt Disable Register
Name: PIO_IDR
Access: Write-only
• P0-P31: Input Change Interrupt Disable
0 = No effect.
1 = Disables the Input Change Interrupt on the I/O line.
34.6.16 PIO Controller Interrupt Mask Register
Name: PIO_IMR
Access: Read-only
• P0-P31: Input Change Interrupt Mask
0 = Input Change Inter rupt is disabled on the I/O line.
1 = Input Change Inter rupt is enabled on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
456 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.17 PIO Controller Interrupt Status Register
Name: PIO_ISR
Access: Read-only
• P0-P31: Input Change Interrupt Status
0 = No Input Change has been detected on the I/O line since PIO_ISR was last re ad or since reset.
1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last re ad or since reset.
34.6.18 PIO Multi-driver Enable Register
Name: PIO_MDER
Access: Write-only
• P0-P31: Multi Drive Enable.
0 = No effect.
1 = Enables Multi Drive on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
457
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.19 PIO Mu lt i-drive r Dis able Re gi st er
Name: PIO_MDDR
Access: Write-only
• P0-P31: Multi Drive Disable.
0 = No effect.
1 = Disables Multi Drive on the I/O line .
34.6.20 PIO Multi-driver Status Register
Name: PIO_MDSR
Access: Read-only
• P0-P31: Multi Drive Status.
0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level.
1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
458 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.21 PIO Pull Up Disable Register
Name: PIO_PUDR
Access: Write-only
• P0-P31: Pull Up Disable.
0 = No effect.
1 = Disables the pull up resistor on the I/O line.
34.6.22 PIO Pull Up Enable Register
Name: PIO_PUER
Access: Write-only
• P0-P31: Pull Up Enable.
0 = No effect.
1 = Enables the pull up resistor on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
459
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.23 PIO Pull Up Status Register
Name: PIO_PUSR
Access: Read-only
• P0-P31: Pull Up Status.
0 = Pull Up resistor is enabled on the I/O line.
1 = Pull Up resistor is disabled on the I/O line.
34.6.24 PIO Peripheral A Select Register
Name: PIO_ASR
Access: Write-only
• P0-P31: Peripheral A Select.
0 = No effect.
1 = Assigns the I/O line to the Peripheral A function.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
460 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.25 PIO Peripheral B Select Register
Name: PIO_BSR
Access: Write-only
• P0-P31: Peripheral B Select.
0 = No effect.
1 = Assigns the I/O line to the peripheral B function.
34.6.26 PIO Peripheral A B Status Register
Name: PIO_ABSR
Access: Read-only
• P0-P31: Peripheral A B Status.
0 = The I/O line is assigned to the Peripheral A.
1 = The I/O line is assigned to the Peripheral B.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
461
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.27 PIO Output Write Enable Register
Name: PIO_OWER
Access: Write-only
• P0-P31: Output Write Enable.
0 = No effect.
1 = Enables writing PIO_ODSR for t he I/O line.
34.6.28 PIO Output Write Disable Register
Name: PIO_OWDR
Access: Write-only
• P0-P31: Output Write Disable.
0 = No effect.
1 = Disables writing PIO_ODSR for the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
462 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.6.29 PIO Output Write Status Register
Name: PIO_OWSR
Access: Read-only
• P0-P31: Output Write Status.
0 = Writing PIO_ODSR does not affect the I/O line.
1 = Writing PIO_ODSR affects the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
463
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35. Synchronous Serial Controller (SSC)
35.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link
with external devices. It supports many serial synchronous communication protocols generally
used in audio and telecom applicat ions such as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC contains a n independent receiv er and transmitter and a common clock divider. The
receiver and the transmitter each interface with three signals: the TD/RD signal for data, the
TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be pro-
grammed to start automatically or on diff er e nt ev en ts dete cted on the Frame Sync sig na l.
The SSC’s high-level of programmability and its two dedicated PDC chan nels of up to 32 bits
permit a continuou s high bit rate data transfer without processor intervention.
Featuring connection to two PDC channels, the SSC permits interfacing with low processor
overhead to the follo wing:
• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader
464 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.2 Block Diagram
Figure 35-1. Block Diagram
35.3 Application Block Diagram
Figure 35-2. Application Block Diagram
SSC Interface PIO
PDC
APB Bridge
MCK
System
Bus
Peripheral
Bus TF
TK
TD
RF
RK
RD
Interrupt Control
SSC Interrupt
PMC
Interrupt
Management
Power
Management Test
Management
SSC
Serial AUDIO
OS or RTOS Driver
Codec Frame
Management Line Interface
Time Slot
Management
465
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.4 Pin Name List
35.5 Product Dependencies
35.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC tra nsmitter, the PIO controller must b e configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
35.5.2 Power Management
The SSC is not continuously clocked. The SSC interface may be clocked through the Power
Management Controller (PMC), therefore the programmer must first configure the PMC to
enable the SSC clock.
35.5.3 Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling interrupts requires programming the AIC before configu ring the SSC.
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each
pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt ser-
vice routine can get the interrupt origin by reading the SSC interrupt status register.
35.6 Functional Description
This chapter contains the functional description of the following: SSC Functional Block, Clock
Management, Data format, Start, Transmitter, Receiver and Frame Sync.
The receiver and tra nsmitter operate separately. However, they can work synchronously by pro-
gramming the receiver to use the tr ansmit clock and/or t o start a data transfe r when tran smission
starts. Alternatively, this can be done by programming the transmitter to use the receive clock
and/or to sta rt a data transf er when recept ion starts. The t ransmitter and t he receiver can be pro-
grammed to operate with the clock signals provided on either the TK or RK pins. This allows the
SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK
and RK pins is the master clock divided by 2.
Table 35-1. I/O Lines Description
Pin Name Pin Description Type
RF Receiver Frame Synchro Input/Output
RK Receiver Clock Input/Output
RD Receiver Data Input
TF Transmitter Frame Synchro Input/Ou tput
TK Transmitter Clock Input/Output
TD Transmitter Data Output
466 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 35-3. SSC Functional Block Diagram
35.6.1 Clock Management
The transmitter clock can be generated by:
• an external clock received on the TK I/O pad
• the receiver cloc k
• the internal clock divider
The receiver clock can be generated by:
• an external clock received on the RK I/O pad
• the tran smitter clock
• the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and th e
receiver block can generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
Interrupt Control
AIC
User
Interface
APB
MCK
Receive Clock
Controller
Start
Selector
TX Clock
RK Input
RF
TF
Clock Output
Controller
Frame Sync
Controller
Transmit Clock
Controller
Transmit Shift Register
Start
Selector
Transmit Sync
Holding Register
Transmit Holding
Register
Load Shift
RX clock
TX clock
TK Input
TF
TX PDC
RF
RD
RF
RK
Clock Output
Controller
Frame Sync
Controller
Receive Shift Register
Receive Sync
Holding Register
Receive Holding
Register
Load Shift
TD
TF
TK
RX Clock
RX PDC
Receiver
PDC
Transmitter
Clock
Divider
467
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.6.1.1 Clock Divider
Figure 35-4. Divided Clock Block Diagram
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its
maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division
by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this
field is programmed to 0, the Clock Divider is not used and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a freque ncy of Mas-
ter Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master
Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of
whether the DIV value is ev en or odd.
Figure 35-5. Divided Clock Generation
35.6.1.2 Transmitter Clock Management
The transmitter clock is generate d from the receiver clock or the divider clock or an external
clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in
SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by
the CKI bits in SSC_TCMR.
Table 35-2.
Maximum Minimum
MCK / 2 MCK / 8190
MCK
Divided Clock
Clock Divider
/ 2 12-bit Counter
SSC_CMR
Master Clock
Divided Clock
DIV = 1
Master Clock
Divided Clock
DIV = 3
Divided Clock Frequency = MCK/2
Divided Clock Frequency = MCK/6
468 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The transmitter can also drive the TK I/O pad continuously or be limited to the ac tu al da ta tra ns -
fer. The clock output is configured by the SSC_TCMR r egister. The Transmit Clock Inversio n
(CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin
(CKS field) and at the same time Cont inuous Transmit Clock (CKO field) might lead to unpredict-
able results.
Figure 35-6. Transmitter Clock Management
35.6.1.3 Receiver Clo ck Management
The receiver clock is generated from the tran smitter clock or the divider clock or an external
clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in
SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by
the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer.
The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI)
bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS
field) and at the same time Continuous Rece ive Clock (CKO field) can lead to unpredictable
results.
TK (pin)
Receiver
Clock
Divider
Clock
CKS
CKO Data Transfer
CKI CKG
Transmitter
Clock
Clock
Output
MUX Tri_state
Controller
Tri-state
Controller
INV
MUX
469
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 35-7. Receiver Clock Management
35.6.1.4 Serial Clock Ratio Considerations
The Transmitter and the Receiver can be progra mmed to operate wit h the clock signals provided
on either the TK or RK pins. This allows the SSC to support m a ny slav e-mode data tr an sf er s. In
this case, the maximum clock speed allowed on the RK pin is:
– Master Clock divided by 2 if Receiver Frame Synchro is input
– Master Clock divided by 3 if Receiver Frame Synchro is output
In addition, the maximum clock speed allowed on the TK pin is:
– Master Clock divided by 6 if Transmit Frame Synchro is input
– Master Clock divided by 2 if Transmit Frame Synchro is output
35.6.2 Transmitter Operations
A transmitted frame is trig gered by a start event an d can be followed by synchronization data
before data tran sm ission.
The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See
“Start” on pa ge 471.
The frame synchronization is configured setting the Transmit Frame Mode Register
(SSC_TFMR). See “Frame Sync” on page 473.
To transmit da ta, th e tra nsmit ter us es a sh ift re gister clocked by the transmitter clock signal and
the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR
register then tran sferred to the shift register according to the data format sele cted.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is
set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register,
the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding
register.
RK (pin)
Transmitter
Clock
Divider
Clock
CKS
CKO Data Transfer
CKI CKG
Receiver
Clock
Clock
Output
MUX Tri-state
Controller
Tri-state
Controller
INV
MUX
470 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 35-8. Transmitter Block Diagram
35.6.3 Re ce iv e r Oper at ions
A received frame is triggered by a start event and can be followed by synchronization data
before data tran sm ission.
The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See
“Start” on pa ge 471.
The frame synchronization is configured setting the Receive Frame Mode Register
(SSC_RFMR). See “Frame Sync” on page 473.
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the SSC_RCMR. The data is transferred from the shift register depending on the
data format selected.
When the receiver shift re gister is full, t he SSC tr ansfers this data in the holding register, the sta-
tus flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If
another transfer occurs before read of the RHR register, the status flag OVERUN is set in
SSC_SR and the receiver shift register is transferred in the RHR register.
Transmit Shift Register
Start
Selector
SSC_TSHRSSC_THR
Transmitter Clock
TD
SSC_TFMR.FSLENSSC_TFMR.DATLEN
SSC_CR.TXEN
SSC_CR.TXDIS
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
SSC_SR.TXEN
SSC_TFMR.DATDEF
SSC_TFMR.MSBF
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
0
1
10
RF TF
471
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 35-9. Receiver Block Diagram
35.6.4 Start The transmitter and receiver can both be programmed to start their operations when an event
occurs, resp ectively in the Transmit Start Se lection (START) field of SSC_TCMR and in the
Receive Start Selection (START) field of SSC_RCMR.
Under the following cond itions the start event is independently programmable:
• Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR
and the reception starts as soon as the Receiver is enabled.
• Synchronously with the transmitter/receiver
• On detection of a falling/rising edge on TF/RF
• On detection of a low level/high level on TF/RF
• On detection of a level change or an edge on TF/RF
A start can be programmed in the same manner on either side of the Transmit/Receive Clock
Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Re ce i ve ).
Moreover, the Receiver can start when data is detected in the bit stream with the Compare
Functions.
Detection on TF/RF in put/outp ut is done by the field FSOS of the Tr ansmit/Receive F rame Mode
Register (TFMR/RFMR).
Receive Shift Register
Start
Selector
SSC_RHRSSC_RSHR
Receiver Clock RD
SSC_RFMR.FSLEN SSC_RFMR.DATLEN
RF
SSC_CR.RXEN
SSC_CR.RXDIS
SSC_SR.RXEN
SSC_RFMR.MSBF
SSC_RCMR.STTDLY
SSC_RFMR.DATNB
TF
472 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 35-10. Transmit Start Mode
Figure 35-11. Receive Pulse/Edge Start Modes
X
TK
TF
(Input)
TD
(Output)
TD
(Output)
TD
(Output)
TD
(Output)
TD
(Output)
TD
(Output)
XBOB1
XBO B1
BO B1
BO B1
BO B1BO B1
BO B1B1
BO
X
X
X
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
Start = Falling Edge on TF
Start = Rising Edge on TF
Start = Low Level on TF
Start = High Level on TF
Start = Any Edge on TF
Start = Level Change on TF
X
RK
RF
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
XBOB1
XBO B1
BO B1
BO B1
BO B1BO B1
BO B1B1
BO
X
X
X
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
Start = Falling Edge on RF
Start = Rising Edge on RF
Start = Low Level on RF
Start = High Level on RF
Start = Any Edge on RF
Start = Level Change on RF
473
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate
different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field
in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register
(SSC_TFMR) are used to select t he required waveform.
• Programmable low or high levels during data transfer are supported.
• Programmable high levels before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and
SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed
through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.
35.6.5.1 Frame Sync Data
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
During the Frame Sync signal, the Receiver can sample the RD line and store the data in the
Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register
in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal
is programmed by the FSLEN f ield in SSC_RF MR/SSC_TFMR and has a maximum va lue of 16.
Concerning the Rece ive Frame Sync Data operatio n, if the Frame Sync Length is equ al to or
lower than the delay between the start event and the actual data reception, the data sampling
operation is perfor med in the Re ceive Sync Holding Register through the Receive Shift Register.
The Transmit Fr ame Sync Operation is performed by the transmitter only if the bit Fra me Sync
Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than
the delay bet ween the st ar t even t an d the a ctua l d ata t r ansmission, th e n ormal tr an smissio n h as
priority and the data contai ned in the Tr ansm it Sync Holding Regist er is transfe rred in the Tr ans-
mit Register, then shifted out.
35.6.5.2 Frame Sync Edge Detection
The Frame Sync Edge detection is programmed by the FSEDGE field in
SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status
Register (SSC_SR) on frame synchro edge detection (signals RF/TF).
35.6.6 Receive Compare Modes
Figure 35-12. Receive Compare Modes
CMP0 CMP3
CMP2
CMP1 Ignored B0 B2
B1
Start
RK
RD
(Input)
FSLEN
Up to 16 Bits
(4 in This Example)
STDLY DATLEN
474 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.6.6.1 Compare Functions
Length of the comparison patterns (Compare 0, Compare 1) and thus the nu mber of bits they
are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is
always done by comp aring the last bits r eceived with the comparison patte rn. Co mpare 0 can be
one start event of the Receiver. In this case, the receiver compares at ea ch new sample the last
bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R).
When this start event is sele cted , the user ca n progr am the Receiver to start a ne w data tr ansfer
either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This
selection is done with the bit (STOP) in SSC_RCMR.
35.6.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the
Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register
(SSC_RFMR). In either case, the user can independently select:
• the event that starts the data transfer (START)
• the delay in number of bit periods between the start event and the first data bit (STTDLY)
• the length of the data (DATLEN)
• the number of data to be transferred for each start event (DATNB).
• the length of synchronization transferred for each start event (FSLEN)
• the bit sense: most or lowest significant bit first (MSBF)
Additionally, the transmitter can be used to transfer synchronization and select the level driven
on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync
Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR.
475
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 35-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes
Note: 1. Example of input on falling edge of TF/RF.
Figure 35-14. Transmit Frame Format in Continuous Mode
Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData
cannot be output in continuous mode.
Table 35-3. Data Frame Registers
Transmitter Receiver Field Length Comment
SSC_TFMR SSC_RFMR DATLEN Up to 32 Size of word
SSC_TFMR SSC_RFMR DATNB Up to 16 Number of words transmitted in frame
SSC_TFMR SSC_RFMR MSBF Most significant bit first
SSC_TFMR SSC_RFMR FSLEN Up to 16 Size of Synchro data registe r
SSC_TFMR DATDEF 0 or 1 Data default value ended
SSC_TFMR FSDEN Enable send SSC_TSHR
SSC_TCMR SSC_RCMR PERIOD Up to 512 Frame size
SSC_TCMR SSC_RCMR STTDLY Up to 255 Size of transmit star t delay
Sync Data
Default
STTDLY
Sync Data Ignored
RD
Default
Data
DATLEN
Data
Data
Data
DATLEN
Data
Data Default
Default
Ignored
Sync Data
Sync Data
FSLEN
TF/RF
(1)
Start
Start
From SSC_TSHR From SSC_THR
From SSC_THR
From SSC_THR
From SSC_THR
To SSC_RHR To SSC_RHRTo SSC_RSHR
TD
(If FSDEN = 0)
TD
(If FSDEN = 1)
PERIOD
FromDATDEF FromDATDEF
From DATDEF From DATDEF
DATNB
DATLEN
Data
DATLEN
Data Default
Start
From SSC_THR From SSC_THR
TD
Start: 1. TXEMPTY set to 1
2. Write into the SSC_THR
476 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 35-15. Receive Frame Format in Continuous Mode
Note: 1. STTDLY is set to 0.
35.6.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by
setting the Loop Mode (L OOP) bit in SSC_RFMR. In this case, RD is co nnected to TD, RF is
connected to TF and RK is connected to TK.
35.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing SSC_IER (Int er rupt En able Regist er ) and SSC_I DR ( Inte rrup t Disable Re g-
ister) These reg isters enable and disable , respectively, the cor responding interrup t by setting
and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the
generation of interrupts by asserting the SSC inter rupt line connected to the AIC.
Figure 35-16. Inte rr up t Bloc k Di ag ra m
Data
DATLEN
Data
DATLEN
Start = Enable Receiver
To SSC_RHR To SSC_RHR
RD
SSC_IMR
PDC
Interrupt
Control SSC Interrupt
Set
RXRDY
OVRUN
RXSYNC
Receiver
Transmitter
TXRDY
TXEMPTY
TXSYNC
TXBUFE
ENDTX
RXBUFF
ENDRX
Clear
SSC_IER SSC_IDR
477
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.7 SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial
links. Some standard applications are shown in the following figures. All serial link applications
supported by the SSC are not listed here.
Figure 35-17. Audio Application Block Diagram
Figure 35-18. Codec App lica tio n Bloc k D iag ra m
SSC
RK
RF
RD
TD
TF
TK Clock SCK
Word Select WS
Data SD
I2S
RECEIVER
Clock SCK
Word Select WS
Data SD
Right Channel
Left Channel
MSB MSB
LSB
SSC
RK
RF
RD
TD
TF
TK Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
CODEC
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
First Time Slot
Dstart Dend
478 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 35-19. Time Slot Application Block Diagram
SSC
RK
RF
RD
TD
TF
TK SCLK
FSYNC
Data Out
Data in
CODEC
First
Time Slot
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data in
CODEC
Second
Time Slot
First Time Slot Second Time Slot
Dstart Dend
479
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8 Synchronous Serial Controller (SSC) User Interface
Table 35-4. Register Mapping
Offset Register Register Name Access Reset
0x0 Control Register SSC_CR Write –
0x4 Clock Mode Register SSC_CMR Read/Write 0x0
0x8 Reserved – – –
0xC Reserved – – –
0x10 Receive Clock Mode Register SSC_RCMR Read/Write 0x0
0x14 Receive Frame Mode Reg ist e r SSC_RFMR Read/Write 0x0
0x18 Transmit Clock Mode Register SSC_TCMR Read/Write 0x0
0x1C Transmit F rame Mode Register SSC_TFMR Read/Write 0x0
0x20 Receive Holding Register SSC_RHR Read 0x0
0x24 Transmit Holding Register SSC_THR Write –
0x28 Reserved – – –
0x2C Reserved – – –
0x30 Receive Sync. Holding Register SSC_RSHR Read 0x0
0x34 Transmit Sync. Holding Register SSC_TSHR Read/Write 0x0
0x38 Receive Compare 0 Register SSC_RC0R Read/Write 0x0
0x3C Receive Compare 1 Register SSC_RC1R Read/Write 0x0
0x40 Status Register SSC_SR Read 0x000000CC
0x44 Interrupt Enable Register SSC_IER Write –
0x48 Interrupt Disable Register SSC_IDR Write –
0x4C Interrupt Mask Register SSC_IMR Read 0x0
0x50-0xFC Reserved – – –
0x100- 0x124 Reserved for Peripheral Data Controller (PDC) – – –
480 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.1 SSC Control Register
Name: SSC_CR
Access: Write-only
• RXEN: Receive Enable
0: No effect.
1: Enables Receive if RXDIS is not set.
• RXDIS: Receiv e Dis a ble
0: No effect.
1: Disables Receive. If a char acter is currently being received, disables at end of curren t character reception.
• TXEN: Transmit Enable
0: No effect.
1: Enables Transmit if TXDIS is not set.
• TXDIS: Transmit Disable
0: No effect.
1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission.
• SWRST: Software Reset
0: No effect.
1: Performs a software reset. Has priority on any other bit in SSC_CR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
SWRST–––––TXDISTXEN
76543210
––––––RXDISRXEN
481
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.2 SSC Clock Mode Register
Name: SSC_CMR
Access: Read/Write
• DIV: Clock Divider
0: The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The
minimum bit rate is MCK/2 x 4095 = MCK/8190.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– DIV
76543210
DIV
482 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.3 SSC Re ce iv e Clo ck Mode Regist er
Name: SSC_RCMR
Access: Read/Write
• CKS: Receive Clock Selection
• CKO: Receive Clock Output Mode Selection
• CKI: Receive Clock Inversion
0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal out-
put is shifted out on Receive Clock rising edge.
1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal out-
put is shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STDDLY
15 14 13 12 11 10 9 8
– – – STOP START
76543210
CKG CKI CKO CKS
CKS Selected Receiv e Clock
0x0 Divided Clock
0x1 TK Clock signal
0x2 RK pin
0x3 Reserved
CKO Receive Clock Output Mode RK pin
0x0 None Input-only
0x1 Continuous Receive Clock Output
0x2 Receive Clock only duri ng data transfers Output
0x3-0x7 Reserved
483
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• CKG: Receive Clock Gating Selection
• START: Receive Start Selection
• STOP: Receive Stop Selection
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• PERIOD: Receive P eriod Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
CKG Receive Clock Gating
0x0 None, continuous clock
0x1 Receive Clock enabled only if RF Low
0x2 Receive Clock enabled only if RF High
0x3 Reserved
START Receive Start
0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
0x1 Transmit start
0x2 Detection of a low level on RF signal
0x3 Detection of a high level on RF signal
0x4 Detection of a falling edge on RF signal
0x5 Detection of a rising edge on RF sign al
0x6 Detection of any level change on RF signal
0x7 Detection of any edge on RF signal
0x8 Compare 0
0x9-0xF Reserved
484 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.4 SSC Receive Frame Mode Register
Name: SSC_RFMR
Access: Read/Write
• DATLEN: Data Length
0: Forbidden value (1-bit data length not supp orted).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the
PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and
15 (included), half -words are transferr ed, and for any other value, 32-bit words are transferred.
• LOOP: Loop Mode
0: Normal operating mode.
1: RD is driven by TD, RF is driven by TF and TK drives RK.
• MSBF: Most Significant Bit First
0: The lowest significant bit of the data register is sampled first in the bit st ream.
1: The most significant bit of the data register is sampled first in the bit stream.
• DATNB: Data Number per Frame
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
• FSLEN: Receive Frame Sync Length
This field d efines the nu mber of bits sample d and stor ed in the Receive Sync Data Register . When this mode is selected by
the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to
the Compare 0 or Compare 1 register.
This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal.
Pulse length is equal to FSLEN + 1 Receive Clock periods.
31 30 29 28 27 26 25 24
–––––––FSEDGE
23 22 21 20 19 18 17 16
– FSOS FSLEN
15 14 13 12 11 10 9 8
–––– DATNB
76543210
MSBF – LOOP DATLEN
485
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• FSOS: Receive Frame Sync Output Selection
• FSEDGE: Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
FSOS Selected Receive Frame Sync Signal RF Pin
0x0 None Input-only
0x1 Negative Pulse Output
0x2 Positiv e Pulse Output
0x3 Driven Low during data transfer Output
0x4 Driven High during data transfer Output
0x5 Toggling at each start of data transf er Output
0x6-0x7 Reserved Undefined
FSEDGE Frame Sync Edge Detection
0x0 Positiv e Edge Detection
0x1 Negative Edge Detection
486 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.5 SSC Transmit Clock Mode Register
Name: SSC_TCMR
Access: Read/Write
• CKS: Transmit Clock Selection
• CKO: Transmit Clock Output Mode Selection
• CKI: Transmit Clock Inversion
0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal
input is sampled on Transmit clock rising edge.
1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal
input is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
–––– START
76543210
CKG CKI CKO CKS
CKS Selected Transmit Clock
0x0 Divided Clock
0x1 RK Clock signal
0x2 TK Pin
0x3 Reserved
CKO Transmit Clo ck Output Mode TK pin
0x0 None Input-only
0x1 Continuous Transmit Clock Output
0x2 Transmit Clock only during data transfers Output
0x3-0x7 Reserved
487
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• CKG: Transmit Clock Gating Selection
• START: Transmit Start Selection
• STTDLY: Transmit Star t Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission
of data. When the Transmitter is programmed to sta rt synchronously with the Receiver, the delay is also applied.
Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emit-
ted instead of the end of TAG.
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period
signal is generate d. If not 0, a period signal is genera ted at each 2 x (PERIOD+1) Transmit Clock.
CKG Transmit Clock Gating
0x0 None, continuous clock
0x1 Transmit Clock enabled only if TF Low
0x2 Transmit Clock enabled only if TF High
0x3 Reserved
START Transmit Start
0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and
immediately after the end of transfer of the previous data.
0x1 Receive start
0x2 Detection of a low level on TF signal
0x3 Detection of a high level on TF signal
0x4 Detection of a falling edge on TF signal
0x5 Detection of a rising edge on TF signal
0x6 Detection of any level change on TF signal
0x7 Detection of any edge on TF signal
0x8 - 0xF Reserved
488 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.6 SSC Transmit Frame Mode Register
Name: SSC_TFMR
Access: Read/Write
• DATLEN: Data Length
0: Forbidden value (1-bit data length not supp orted).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the
PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data t ransfers are byte s, if DATLEN is between 8 and 15
(included), half-words are transferred, and for any other value, 32-bit words are transferre d.
• DAT DEF: Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the
PIO Controller, the pin is enabled only if the SCC TD output is 1.
• MSBF: Most Significant Bit First
0: The lowest significant bit of the data register is shifted out first in the bit stream.
1: The most significant bit of the data register is shifted out first in the bit stream.
• DATNB: Data Number per frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync
Data Register if FSDEN is 1.
This field is used with FSLEN_EXT to dete rmine the pulse length of the Transmit Fr ame Sync signal.
Pulse length is equal to FSLEN + 1 Transmit Clock periods.
31 30 29 28 27 26 25 24
––– ––––FSEDGE
23 22 21 20 19 18 17 16
FSDEN FSOS FSLEN
15 14 13 12 11 10 9 8
–––– DATNB
765 4 3210
MSBF – DATDEF DATLEN
489
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• FSOS: Transmit Frame Sync Output Selection
• FSDEN: Frame Sync Data Enable
0: The TD line is driven with the default value during the Transmit Frame Sync signal.
1: SSC_TSHR value is shifte d out during the transmissio n of the Transmit Frame Sync signal.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
FSOS Selected Transmit Frame Sync Signal TF Pin
0x0 None Input-only
0x1 Negative Pulse Output
0x2 Positive Pulse Output
0x3 Driven Low during data transfer Output
0x4 Driven High during data transfer Output
0x5 Toggling at each start of data transfer Output
0x6-0x7 Reserved Undefined
FSEDGE Frame Sync Edge Detection
0x0 Positive Edge Detection
0x1 Negative Edge Detection
490 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.7 SSC Rece ive Holding Regis ter
Name: SSC_RHR
Access: Read-only
• RDAT: Receive Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
35.8.8 SSC Transmit Holding Regist er
Name: SSC_THR
Access: Write-only
• TDAT: Transmit Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
31 30 29 28 27 26 25 24
RDAT
23 22 21 20 19 18 17 16
RDAT
15 14 13 12 11 10 9 8
RDAT
76543210
RDAT
31 30 29 28 27 26 25 24
TDAT
23 22 21 20 19 18 17 16
TDAT
15 14 13 12 11 10 9 8
TDAT
76543210
TDAT
491
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.9 SSC Receive Synchronization Holding Register
Name: SSC_RSHR
Access: Read-only
• RSDAT: Receive Synchronization Data
35.8.10 SSC Transmit Synchronization Holding Register
Name: SSC_TSHR
Access: Read/Write
• TSDAT: Transmit Synchronization Data
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RSDAT
76543210
RSDAT
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TSDAT
76543210
TSDAT
492 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.11 SSC Receive Compare 0 Register
Name: SSC_RC0R
Access: Read/Write
• CP0: Receive Comp are Data 0
35.8.12 SSC Receive Compare 1 Register
Name: SSC_RC1R
Access: Read/Write
• CP1: Receive Comp are Data 1
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CP0
76543210
CP0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CP1
76543210
CP1
493
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.13 SSC Status Register
Name: SSC_SR
Access: Read-only
• TXRDY: Transmit Ready
0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).
1: SSC_THR is empty.
• TXEMPTY: Transmit Empty
0: Data remains in SSC_THR or is curre n tly tra n sm itte d fr om TSR.
1: Last data wri tten in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
• ENDTX: End of Transmission
0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.
1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.
• TXBUFE: Transmit Buffer Empty
0: SSC_TCR or SSC_TNCR have a value other than 0.
1: Both SSC_TCR and SSC_TNCR have a value of 0.
• RXRDY: Receiv e Re ady
0: SSC_RHR is empty.
1: Data has been received and loaded in SSC_RHR.
• OVRUN: Receive Overrun
0: No data has been loaded in SSC_RHR wh ile pr evious data has not been read since the last read of the St at us Registe r.
1: Data has bee n loaded in SSC_RHR while pr evious dat a has not yet been read sin ce the last read o f the St atus Regi ster.
• ENDRX: End of Reception
0: Data is written on the Receive Counter Register or Receive Next Counter Register.
1: End of PDC transfe r when Receive Counter Register has arrived at zero .
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––RXENTXEN
15 14 13 12 11 10 9 8
––––RXSYNTXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
494 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• RXBUFF: Receive Buffer Full
0: SSC_RCR or SSC_RNCR have a value other than 0.
1: Both SSC_RCR and SSC_RNCR have a value of 0.
•CP0: Compare 0
0: A compare 0 has not occurr ed since the last read of the Status Register.
1: A compare 0 has occurred since the last read of the Status Register.
•CP1: Compare 1
0: A compare 1 has not occurr ed since the last read of the Status Register.
1: A compare 1 has occurred since the last read of the Status Register.
• TXSYN: Transmit Sync
0: A Tx Sync has not occurred since the last read of the Status Register.
1: A Tx Sync has occurred since the last read of the Status Register.
• RXSYN: Receive Sync
0: An Rx Sync has not occurred since the last read of the Status Registe r.
1: An Rx Sync has occurred since the last read of the Status Register.
• TXEN: Transmit Enable
0: Transmit is disabled.
1: Transmit is enabled.
• RXEN: Receive Enable
0: Receive is disabled.
1: Receive is enabled.
495
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.14 SSC Interrupt Enable Register
Name: SSC_IER
Access: Write-only
• TXRDY: Transmit Ready Interrupt Enable
0: No effect.
1: Enables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Enable
0: No effect.
1: Enables the Transmit Empty Interrupt.
• ENDTX: End of Transmission Interrupt Enable
0: No effect.
1: Enables the End of Transmission Interrupt.
• TXBUFE: Transmit Buffer Empt y Interrupt Enable
0: No effect.
1: Enables the Transmit Buffer Empty Interrupt
• RXRDY: Receiv e Re ady Interru p t Enable
0: No effect.
1: Enables the Receive Ready Int errupt.
• OVRUN: Receive Overrun Interrupt Enable
0: No effect.
1: Enables the Receive Overrun Interrupt.
• ENDRX: End of Reception Interrupt Enable
0: No effect.
1: Enables the End of Reception Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––RXSYNTXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
496 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• RXBUFF: Receive Buffer Full Interrupt Enable
0: No effect.
1: Enables the Receive Buffer Full Interrupt.
• CP0: Compare 0 Interrupt Enable
0: No effect.
1: Enables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Enable
0: No effect.
1: Enables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable
0: No effect.
1: Enables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0: No effect.
1: Enables the Rx Sync Interrupt.
497
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.15 SSC Interrupt Disable Register
Name: SSC_IDR
Access: Write-only
• TXRDY: Transmit Ready Interrupt Disable
0: No effect.
1: Disables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Disable
0: No effect.
1: Disables the Transmit Empty Interrupt.
• ENDTX: End of Transmission Interrupt Disable
0: No effect.
1: Disables the End of Transmission Interrupt.
• TXBUFE: Transmit Buffer Empty Interrupt Disable
0: No effect.
1: Disables the Transmit Buffer Empty Interrupt.
• RXRDY: Receiv e Re ady Interru p t Dis able
0: No effect.
1: Disables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Disable
0: No effect.
1: Disables the Receive Overrun Interrupt.
• ENDRX: End of Reception Interrupt Disable
0: No effect.
1: Disables the End of Reception Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––RXSYNTXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
498 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• RXBUFF: Receive Buffer Full Interrupt Disable
0: No effect.
1: Disables the Receive Buffer Full Interrupt.
• CP0: Compare 0 Interrupt Disable
0: No effect.
1: Disables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Disable
0: No effect.
1: Disables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable
0: No effect.
1: Disables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0: No effect.
1: Disables the Rx Sync Interrupt.
499
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
35.8.16 SSC Interrupt Mask Regi st er
Name: SSC_IMR
Access: Read-only
• TXRDY: Transmit Ready Interrupt Mask
0: The Transmit Ready Interrupt is disabled.
1: The Transmit Ready Interrupt is enabled.
• TXEMPTY: Transmit Empty Interrupt Mask
0: The Transmit Empty Interrupt is disabled.
1: The Transmit Empty Interrupt is enabled.
• ENDTX: End of Transmission Interrupt Mask
0: The End of Transmission Interrupt is disabled.
1: The End of Transmission Interrupt is enabled.
• TXBUFE: Transmit Buffer Empty Interrupt Mask
0: The Transmit Buffer Empty Interrupt is disabled.
1: The Transmit Buffer Empty Interrupt is enabled.
• RXRDY: Receiv e Re ady Interru p t Ma s k
0: The Receive Ready Interrupt is disabled.
1: The Receive Ready Interrupt is enabled.
• OVRUN: Receive Overrun Interrupt Mask
0: The Receive Overrun Interrupt is disabled.
1: The Receive Overrun Interrupt is enabled.
• ENDRX: End of Reception Interrupt Mask
0: The End of Reception Interrupt is disabled.
1: The End of Reception Interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––RXSYNTXSYN CP1 CP0
76543210
RXBUF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
500 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• RXBUFF: Receive Buffer Full Interrupt Mask
0: The Receive Buffer Full Interrupt is disabled.
1: The Receive Buffer Full Interrupt is enabled.
• CP0: Compare 0 Interrupt Mask
0: The Compare 0 Interrupt is disabled.
1: The Compare 0 Interrupt is enabled.
• CP1: Compare 1 Interrupt Mask
0: The Compare 1 Interrupt is disabled.
1: The Compare 1 Interrupt is enabled.
• TXSYN: Tx Sync Interrupt Mask
0: The Tx Sync Interrupt is disabled.
1: The Tx Sync Interr upt is enabled.
• RXSYN: Rx Sync Interrupt Mask
0: The Rx Sync Interrupt is disabled.
1: The Rx Sync Interrupt is enabled.
501
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36. Timer/Counter (TC)
36.1 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels.
Each channel ca n be independe n tly pr og ra m m ed to p e rfo rm a wide r an g e of fu nc tio ns in clud in g
frequency measurement, event counting, interval measurement, pulse generation, delay timing
and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose
input/output signals which can be configured by the user. Each channel drives an internal inter-
rupt signal which can be programmed to generate processor interrupts.
The Timer Counter block has two global registers which act upon all three TC channels.
The Block Control Regist er allows the three ch annels to be star ted simultaneously with the same
instruction.
The Block Mode Register defines the external clock inputs for each channel, allowing them to be
chained.
Table gives t he assignm ent of th e device Tim er Counter clock inputs common to Timer Counter
0 to 2.
Timer Counter Clock Assignment
Name Definition
TIMER_CLOCK1 MCK/2
TIMER_CLOCK2 MCK/8
TIMER_CLOCK3 MCK/32
TIMER_CLOCK4 MCK/128
TIMER_CLOCK5 MCK/1024
502 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.2 Block Diagram
Figure 36-1. Timer/Counte r Blo ck D iag ra m
Table 36-1. Signal Name Description
Block/Channel Signal Name Description
Channel Signal
XC0, XC1, XC2 External Clock Inputs
TIOA Capture Mode: Timer/Counter Input
Waveform Mode: Timer/Counter Output
TIOB Capture Mode: Timer/Counter Inp ut
Waveform Mode: Time r/Counter Input/output
INT Interrupt Signal Output
SYNC Synchronization Input Signal
Timer/Counter
Channel 0
Timer/Counter
Channel 1
Timer/Counter
Channel 2
SYNC
Parallel I/O
Controller
TC1XC1S
TC0XC0S
TC2XC2S
INT0
INT1
INT2
TIOA0
TIOA1
TIOA2
TIOB0
TIOB1
TIOB2
XC0
XC1
XC2
XC0
XC1
XC2
XC0
XC1
XC2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TIOA0
TIOA2
TIOA0
TIOA1
Advanced
Interrupt
Controller
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer Counter
TIOA
TIOB
TIOA
TIOB
TIOA
TIOB
SYNC
SYNC
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
TIMER_CLOCK1
503
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.3 Pin Name List
36.4 Product Dependencies
36.4.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the TC pins to their peripheral
functions.
36.4.2 Power Management
The TC is clocked t hrough t he Power Mana gement Controller (PMC), th us the prog rammer must
first configure the PMC to enable the Timer/Counter clock.
36.4.3 Interrupt The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the
TC interrupt re qu ire s pr og ra m m i ng the AIC bef or e co nfig u rin g th e TC.
Table 36-2. TC pin list
Pin Name Description Type
TCLK0-TCLK2 External Clock Input Input
TIOA0-TIOA2 I/O Line A I/O
TIOB0-TIOB2 I/O Line B I/O
504 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.5 Functional Description
36.5.1 TC DescriptionThe three channels of the Timer/Counter are independent and identical in operation. The regis-
ters for channel programming are listed in Table 36-4 on pa ge 517.
36.5.1.1 16-bit Counter
Each channel is organized around a 16-bit counter. The valu e of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
The current value of the counter is accessible in real time by reading the Counter Value Regis-
ter, TC_CV. The counter can be re set by a trigger. In this case, the counter value passes to
0x0000 on the next valid edge of the selected clock.
36.5.1.2 Clock Selection
At block level, input clock signals of each channel can either be connected to the externa l inputs
TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or
TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 36-2 on page 505.
Each channel can independe ntly select an internal or external clock source for its counter:
• Internal clock signals: TIM ER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3,
TIMER_CLOCK4, TIMER_CLOCK5
• External clock signals: XC0, XC1 or XC2
This selection is made by the TCCLKS bits in the TC Channel Mode Register.
The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the
opposite edges of the clock.
The burst fun ction allows the clock to be validat ed when an external signal is high. The BURST
parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 36-3 on
page 505.
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the
master clock period. The external clock frequency must be at least 2.5 times lower than the mas-
ter clock.
505
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 36-2. Clock Chaining Selection
Figure 36-3. Clock Selection
Timer/Counter
Channel 0
SYNC
TC0XC0S
TIOA0
TIOB0
XC0
XC1 = TCLK1
XC2 = TCLK2
TCLK0 TIOA1
TIOA2
Timer/Counter
Channel 1
SYNC
TC1XC1S
TIOA1
TIOB1
XC0 = TCLK2
XC1
XC2 = TCLK2
TCLK1 TIOA0
TIOA2
Timer/Counter
Channel 2
SYNC
TC2XC2S
TIOA2
TIOB2
XC0 = TCLK0
XC1 = TCLK1
XC2
TCLK2 TIOA0
TIOA1
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
TCCLKS
CLKI
BURST
1
Selected
Clock
506 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.5.1.3 Clock Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See Figure 36-4.
• The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
commands in the Control Register. In Capture M ode it can be disabl ed b y an RB load e v ent if
LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare
e v ent if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no
effect: only a CLKEN command in the Control Register can re-enable the clock. When the
clock is en abled, the CLKSTA bit is set in the Status Register.
• The clock can also be started or stopped: a trigger (software, synchro, external or compare)
always starts the clock. The clock can be stopped by an RB load event in Capture Mode
(LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in
TC_CMR). The start and the stop commands have effect only if the clock is enabled.
Figure 36-4. Clock Control
36.5.1.4 TC Operating Modes
Each channel can independently operate in two different modes:
• Capture Mode provides measurement on signals.
• Waveform Mode provides wave generati on.
The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register.
In Capture Mode, TIOA and TIOB are configured as input s.
In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not
selected to be the external trigger.
36.5.1.5 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to
both modes, and a f ourth external trigger is available to each mode.
The following trigge rs are common to both modes:
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
Stop
Event Disable
Event
Counter
Clock
Selected
Clock Trigger
507
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• Software Trigger: Each channel has a software trigger, available by setting SWTRG in
TC_CCR.
• SYNC: Each channel has a synchro nization signal SYNC . When asserted, this signal has the
same effect as a software trigger. The SYNC signals of all channels are asserted
simultaneously by writing TC_BCR (Block Control) with SYNC set.
• Compare RC Trigger: RC is implemented in each channel and can pro vide a trigger when the
counter value matches the RC value if CPCTRG is set in TC_CMR.
The channel can also be configured to have an external trigger. In Capture Mode, the external
trigger signa l can be selected betwee n TIOA and TIOB. In Wav eform Mode, an ext ernal event
can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external
event can then be programmed to perform a trigger by setting ENETRG in TC_CMR.
If an external trigger is used, the duration of the pulses must be longer than the master clock
period in order to be detected.
Regardless of the trigger used, it will be taken into account at the following active edge of the
selected clock. This means that the counter value can be read differently from zero just after a
trigger, especially when a low frequency signal is selected as the clock.
36.5.2 Capture Operating Mode
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register).
Capture Mode allows the TC channel to perform measurements such as pulse timing, fre-
quency, period, duty cycle and phase on TIOA and TIOB signals which are considered as
inputs.
Figure 36-5 shows the configuration of the TC channel when programmed in Capture Mode.
36.5.2.1 Capture Registe rs A and B
Registers A and B (RA and RB) ar e used as capture registers. This mean s that they can be
loaded with the counter value when a programmable event occurs on the signal TIOA.
The LDRA parameter in T C_CMR defines the TIOA edge for the loading of register A, and th e
LDRB parameter defines the TIOA edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since
the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before th e re ad of th e last value loade d sets th e Over ru n Erro r Flag (LO VRS)
in TC_SR (Status Register). In this case, the old value is overwritten.
36.5.2.2 Trigger Conditions
In addition t o the SYNC signa l, the soft ware tr igger and the RC co mpare t rigger, an ext ernal tr ig-
ger can be defined.
The ABETRG bit in TC_CMR selects TIOA or TIOB input signa l as an external trigger. The
ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external
trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
508 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 36-5. Capture Mod e
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
BURST
TIOB
Register C
Capture
Register A Capture
Register B Compare RC =
16-bit Counter
ABETRG
SWTRG
ETRGEDG CPCTRG
TC1_IMR
Trig
LDRBS
LDRAS
ETRGS
TC1_SR
LOVRS
COVFS
SYNC
1
MTIOB
TIOA
MTIOA
LDRA
LDBSTOP
If RA is not loaded
or RB is Loaded If RA is Loaded
LDBDIS
CPCS
INT
Edge
Detector
Edge
Detector
LDRB
Edge
Detector
CLK OVF
RESET
Timer/Counter Channel
509
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.5.3 Waveform Operating Mode
Waveform oper ating mode is entered by setting the WAVE p arameter in TC_CMR (Channel
Mode Register).
In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same fre-
quency and independently programmable duty cycles, or generates different types of one-shot
or repetitive pulses.
In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used
as an external event (EEVT parameter in TC_CMR).
Figure 36-6 shows the configuration of the TC channel when programmed in Waveform Operat-
ing Mode.
36.5.3.1 Waveform Selection
Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of
TC_CV varies.
With any selection, RA, RB and RC can all be used as compare registers.
RA Compare is used to co ntro l th e T IOA outpu t, RB Comp ar e is used to cont r ol the TIO B ou tp ut
(if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.
510 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 36-6. Waveform Mode
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
CPCDIS
BURST
TIOB
Register A Register B Register C
Compare RA = Compare RB = Compare RC =
CPCSTOP
16-bit Counter
EEVT
EEVTEDG
SYNC
SWTRG
ENETRG
WAVSEL
TC1_IMR
Trig
ACPC
ACPA
AEEVT
ASWTRG
BCPC
BCPB
BEEVT
BSWTRG
TIOA
MTIOA
TIOB
MTIOB
CPAS
COVFS
ETRGS
TC1_SR
CPCS
CPBS
CLK OVF
RESET
Output Controller
Output Controller
INT
1
Edge
Detector
Timer/Counter Channel
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
WAVSEL
511
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.5.3.2 WAVSEL = 00
When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has
been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle
continues. See Figure 36-7.
An external event trigger or a software trigger can reset the value of TC_CV. It is important to
note that the trigger may occur at any time. See Figure 36-8.
RC Compare canno t be programmed to gene rate a trigger in this co nfiguration. At the same
time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the
counter clock (CPCDIS = 1 in TC_CMR).
Figure 36-7. WAVSEL= 00 without trigger
Time
Counter V alue
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
512 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 36-8. WAVSEL= 00 with trigger
36.5.3.3 WAVSEL = 10
When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then auto-
matically reset on a RC Compare. Once the value of TC_CV has been reset, it is then
incremented and so on. See Figure 36-9.
It is important to note that TC_CV can be reset at any time by an external event or a software
trigger if both are programmed correctly. See Figure 36-10.
In addition, RC Compa re can sto p the cou nter clo ck (CPCSTOP = 1 in TC_CMR) an d/ or di sable
the counter clock (CPCDIS = 1 in TC_CMR).
Time
Counter V alue
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter cleared by trigger
513
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 36-9. WAVSEL = 10 Without Trigger
Figure 36-10. WAVSEL = 10 With Trigger
36.5.3.4 WAVSEL = 01
When WAVSEL = 01, the value o f TC_CV is incremented from 0 to 0xFFFF. Once 0 xFFFF is
reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on.
See Figure 36-11.
A trigger such as an exter nal even t or a softwar e trigg er can modify TC_CV at any time. If a trig-
ger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while
TC_CV is decrementing, TC_CV then increments. See Figure 36-12.
Time
Counter V alue
R
C
R
B
R
A
TIOB
TIOA
Counter cleared by compare match with RC
0xFFFF
Waveform Examples
Time
Counter V alue
R
C
R
B
R
A
TIOB
TIOA
Counter cleared by compare match with RC
0xFFFF
Waveform Examples
Counter cleared by trigger
514 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
RC Compare cannot be pr ogrammed to generate a trigger in this configuration.
At the same time, RC Compare can stop the coun ter clock (CPCSTOP = 1) and/or disable the
counter clock (CPCDIS = 1).
Figure 36-11. WAVSEL = 01 Without Trigger
Figure 36-12. WAVSEL = 01 With Trigger
36.5.3.5 WAVSEL = 11
When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the
value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 36-13.
Time
Counter V alue
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter V alue
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
515
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
A trigger such as an exter nal even t or a softwar e trigg er can modify TC_CV at any time. If a trig-
ger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while
TC_CV is decrementing, TC_CV then increments. See Figure 36-14.
RC Compare can sto p the count er clock (CPCSTOP = 1) and/or d isable t he counte r clock (CPC-
DIS = 1).
Figure 36-13. WAVSEL = 11 Without Trigger
Figure 36-14. WAVSEL = 11 With Trigger
36.5.3.6 External Event/Trigger Conditions
An external event can be programmed to be detected on one of the clo ck sources (XC0, XC1,
XC2) or TIOB. The external event selected can then be used as a trigger.
Time
Counter V alue
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with RC
0xFFFF
Waveform Examples
Time
Counter V alue
TIOB
TIOA
Counter decremented by compare match with RC
0xFFFF
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
516 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines
the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is
cleared (none), no external event is defined.
If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output
and the compare register B is not used to generate waveforms and subsequently no IRQs. In
this case the TC channel can only generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by setting bit ENETRG in
TC_CMR.
As in Capture Mode, the SYNC signal and the sof tware t rigge r ar e also ava ilable as tri gge rs. RC
Compare can also be used as a trigger depending on the parameter WAVSEL.
36.5.3.7 Output Controller
The output contr oller defines the output level ch anges on TIOA and TIOB followin g an event.
TIOB control is used only if TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB: software trigger, external event and RC compare.
RA compare controls TIOA and RB compare controls TIOB. Each of these events can be pro-
grammed to set, clear or toggle the output as defined in the corresponding parameter in
TC_CMR.
517
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6 Timer/Counter (TC) User Interface
36.6.1 Global Register Mapping
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC
block. TC channels are controlled b y the registers listed in Table 36-4. The offset of each of the
channel registers in Table 36-4 is in relation to the off set of the corresponding cha nnel as men-
tioned in Tabl e 36 -4 .
36.6.2 Channel Memory Mapping
Note: 1. Read-only if WAVE = 0
Table 36-3. Timer/Coun te r (T C) Glob al Re gis ter Ma p
Offset Channel/Register Name Access Reset Value
0x00 TC Channel 0 See Table 36-4
0x40 TC Channel 1 See Table 36-4
0x80 TC Channel 2 See Table 36-4
0xC0 TC Block Control Register TC_BCR Write-only –
0xC4 TC Block Mode Register TC_BMR Read/Write 0
Table 36-4. TC Channel Memory Map
Offset Register Name Access Reset Value
0x00 Channel Control Register TC_CCR Write-only –
0x04 Channel Mode Register TC_CMR Read/W rite 0
0x08 Reserved –
0x0C Reserved –
0x10 Counter Value TC_CV Read-only 0
0x14 Register A TC_RA Read/Write(1) 0
0x18 Register B TC_RB Read/Write(1) 0
0x1C Register C TC_RC Read/Write 0
0x20 Status Register TC_SR Read-only 0
0x24 Interrupt Enable Register TC_IER Write-only –
0x28 Interrupt Disable Register TC_IDR Write-only –
0x2C Interrupt Mask Register TC_IMR Read-only 0
0xFC Reserved – – –
518 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.3 TC Block Control Register
Name: TC_BCR
Access: Write-only
• SYNC: Synchro Command
0 = No effect.
1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SYNC
519
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.4 TC Block Mode Regist er
Name: TC_BMR
Access: Read/Write
• TC0XC0S: External Clock Signal 0 Selection
• TC1XC1S: External Clock Signal 1 Selection
• TC2XC2S: External Clock Signal 2 Selection
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TC2XC2S TCXC1S TC0XC0S
TC0XC0S Signal Connected to XC0
00TCLK0
0 1 none
10TIOA1
11TIOA2
TC1XC1S Signal Connected to XC1
00TCLK1
0 1 none
10TIOA0
11TIOA2
TC2XC2S Signal Connected to XC2
00TCLK2
0 1 none
10TIOA0
11TIOA1
520 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.5 TC Channel Control Register
Name: TC_CCR
Access: Write-only
• CLKEN: Counter Clock Enable Command
0 = No effect.
1 = Enables the clock if CLKDIS is not 1.
• CLKDIS: Counter Clock Disable Command
0 = No effect.
1 = Disables the clock.
• SWTRG: Software Trigger Command
0 = No effect.
1 = A software trigger is performed: the counter is reset and the clock is started.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––SWTRGCLKDISCLKEN
521
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.6 TC Channel Mode Register: Capture Mode
Name: TC_CMR
Access: Read/Write
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
• LDBDIS: Counter Clock Disable with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – LDRB LDRA
15 14 13 12 11 10 9 8
WAVE = 0 CPCTRG – – – ABETRG ETRGEDG
76543210
LDBDIS LDBSTOP BURST C LKI TCCLKS
TCCLKS Clock Selected
000TIMER_CLOCK1
001TIMER_CLOCK2
010TIMER_CLOCK3
011TIMER_CLOCK4
100TIMER_CLOCK5
101XC0
110XC1
111XC2
BURST
0 0 The clock is not gated by an external signal.
0 1 XC0 is ANDed with the selected clock.
1 0 XC1 is ANDed with the selected clock.
1 1 XC2 is ANDed with the selected clock.
522 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• ETRGEDG: External Trigger Edge Selection
• ABETRG: TIOA or TIOB External Trigger Selection
0 = TIOB is used as an external trigg er.
1 = TIOA is used as an external trigg er.
• CPCTRG: RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and start s the counter clock.
•WAVE
0 = Capture Mode is enabled.
1 = Capture Mode is disabled (Waveform Mode is enabled).
• LDRA: RA Loading Selection
• LDRB: RB Loading Selection
ETRGEDG Edge
0 0 none
0 1 rising edge
1 0 falling edge
1 1 each edge
LDRA Edge
0 0 none
0 1 rising edge of TIOA
1 0 falling edge of TIOA
1 1 each edge of TIOA
LDRB Edge
0 0 none
0 1 rising edge of TIOA
1 0 falling edge of TIOA
1 1 each edge of TIOA
523
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.7 TC Channel Mode Register: Waveform Mode
Name: TC_CMR
Access: Read/Write
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• CPCSTOP: Counter Clo ck Stopped with RC Compare
0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.
• CPCDIS: Counter Clock Disable with RC Compare
0 = Counter clock is not disabled when counter reaches RC.
1 = Counter clock is disabled when counter reaches RC.
31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE = 1 WAVSEL ENETRG EEVT EEVTEDG
76543210
CPCDIS CPCSTOP BURST CLKI TCCLKS
TCCLKS Clock Selected
0 0 0 TIMER_CLOCK1
0 0 1 TIMER_CLOCK2
0 1 0 TIMER_CLOCK3
0 1 1 TIMER_CLOCK4
1 0 0 TIMER_CLOCK5
101XC0
110XC1
111XC2
BURST
0 0 The clock is not gated by an external signal.
0 1 XC0 is ANDed with the selected clock.
1 0 XC1 is ANDed with the selected clock.
1 1 XC2 is ANDed with the selected clock.
524 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• EEVTEDG: External Event Edge Selection
• EEVT: External Event Selection
Note: 1. If TIOB is chosen a s the e xtern al ev ent signal , it is co nfigured as an input and no longer generates wa veforms and sub-
sequently no IRQs.
• ENETRG: External Event Trigger Enable
0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the
TIOA output.
1 = The external event resets the counter and starts the counter clock.
• WAVSEL: W aveform Selection
• WAVE = 1
0 = Waveform Mode is disabled (Capture Mode is enabled).
1 = Waveform Mode is enabled.
• ACPA: RA Compare Effect on TIOA
EEVTEDG Edge
0 0 none
0 1 rising edge
1 0 falling edge
1 1 each edge
EEVT Signal selected as external event TIOB Direction
0 0 TIOB input(1)
01XC0 output
10XC1 output
11XC2 output
WAVSEL Effect
0 0 UP mode without automatic trigger on RC Compare
1 0 UP mode with automatic tr igger on RC Compare
0 1 UPDOWN mode without automatic trigger on RC Compare
1 1 UP DOWN mode with automatic trigger on RC Compare
ACPA Effect
0 0 none
0 1 set
1 0 clear
1 1 toggle
525
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• ACPC: RC Compare Effect on TIOA
• AEEVT: External Event Effect on TIOA
• ASWTRG: Software Trigger Effect on TIOA
• BCPB: RB Compare Effect on TIOB
• BCPC: RC Compare Effect on TIOB
ACPC Effect
0 0 none
0 1 set
1 0 clear
1 1 toggle
AEEVT Effect
0 0 none
0 1 set
1 0 clear
1 1 toggle
ASWTRG Effect
0 0 none
0 1 set
1 0 clear
1 1 toggle
BCPB Effect
0 0 none
0 1 set
1 0 clear
1 1 toggle
BCPC Effect
0 0 none
0 1 set
1 0 clear
1 1 toggle
526 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• BEEVT: External Event Effect on TIOB
• BSWTRG: Software Trigger Effect on TIOB
BEEVT Effect
0 0 none
0 1 set
1 0 clear
1 1 toggle
BSWTRG Effect
0 0 none
0 1 set
1 0 clear
1 1 toggle
527
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.8 TC Counter Value Register
Name: TC_CV
Access: Read-only
• CV: Counter Value
CV contains the counter value in real time.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CV
76543210
CV
528 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.9 TC Register A
Name: TC_RA
Access: Read-only if WAVE = 0, Read/Write if WAVE = 1
• RA: Register A
RA contains the Register A value in real time.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RA
76543210
RA
529
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.10 TC Register B
Name: TC_RB
Access: Read-only if WAVE = 0, Read/Write if WAVE = 1
• RB: Register B
RB contains the Register B value in real time.
36.6.11 TC Register C
Name: TC_RC
Access: Read/Write
• RC: Register C
RC contains the Register C value in real time.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RB
76543210
RB
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RC
76543210
RC
530 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.12 TC Status Register
Name: TC_SR
Access: Read-only
• COVFS: Counter Overflow Status
0 = No counter overflow ha s occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
• LOVRS: Load Overrun Status
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any rea d of th e corresponding register since the last read o f the Sta-
tus Register, if WAVE = 0.
• CPAS: RA Compare Status
0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
• CPBS: RB Compare Status
0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
• CPCS: RC Compare Status
0 = RC Compare has not occurred since the last read of the Status Register.
1 = RC Compare has occurred since the last read of the Status Register.
• LDRAS: RA Loading Status
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
• LDRBS: RB Loading Status
0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
• ETRGS: External Trigger Status
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––MTIOBMTIOACLKSTA
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
531
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• CLKSTA: Clock Enabling Statu s
0 = Clock is disabled.
1 = Clock is enabled.
• MTIOA: TIOA Mirror
0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.
• MTIOB: TIOB Mirror
0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.
532 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.13 TC Interrupt Enable Register
Name: TC_IER
Access: Write-only
• COVFS: Counter Overflow
0 = No effect.
1 = Enables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0 = No effect.
1 = Enables the Load Overrun Interrupt.
• CPAS: RA Compare
0 = No effect.
1 = Enables the RA Compare Interrupt.
• CPBS: RB Compare
0 = No effect.
1 = Enables the RB Compare Interrupt.
• CPCS: RC Compare
0 = No effect.
1 = Enables the RC Compare Interrupt.
• LDRAS: RA Loading
0 = No effect.
1 = Enables the RA Load Interrupt.
• LDRBS: RB Loading
0 = No effect.
1 = Enables the RB Load Interrupt.
• ETRGS: External Trigger
0 = No effect.
1 = Enables the External Trigger Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
533
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.14 TC Interrupt Disable Register
Name: TC_IDR
Access: Write-only
• COVFS: Counter Overflow
0 = No effect.
1 = Disables the Coun ter Overflow Interrupt.
• LOVRS: Load Overrun
0 = No effect.
1 = Disables the Load Overrun Interrupt (if WAVE = 0).
• CPAS: RA Compare
0 = No effect.
1 = Disables the RA Compare Interrupt (if WAVE = 1).
• CPBS: RB Compare
0 = No effect.
1 = Disables the RB Compare Interrupt (if WAVE = 1).
• CPCS: RC Compare
0 = No effect.
1 = Disables the RC Compar e Interrupt.
• LDRAS: RA Loading
0 = No effect.
1 = Disables the RA Load Interrupt (if WAVE = 0).
• LDRBS: RB Loading
0 = No effect.
1 = Disables the RB Load Interrupt (if WAVE = 0).
• ETRGS: External Trigger
0 = No effect.
1 = Disables the External Trigger Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
534 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
36.6.15 TC Interrupt Mask Register
Name: TC_IMR
Access: Read-only
• COVFS: Counter Overflow
0 = The Counter Overflow Interrupt is disabled.
1 = The Counter Overflow Interrupt is enabled.
• LOVRS: Load Overrun
0 = The Load Overrun Interrupt is disabled.
1 = The Load Overrun Interrupt is enabled.
• CPAS: RA Compare
0 = The RA Compare Interrupt is disabled.
1 = The RA Compare Interrupt is enabled.
• CPBS: RB Compare
0 = The RB Compare Interrupt is disabled.
1 = The RB Compare Interrupt is enabled.
• CPCS: RC Compare
0 = The RC Compare Interrupt is disabled.
1 = The RC Compare Interrupt is enabled.
• LDRAS: RA Loading
0 = The Load RA Interrupt is disable d.
1 = The Load RA Interrupt is enabled.
• LDRBS: RB Loading
0 = The Load RB Interrupt is disable d.
1 = The Load RB Interrupt is enabled.
• ETRGS: External Trigger
0 = The External Trigger Interrupt is disabled.
1 = The External Trigger Inter rupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
535
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37. Pulse WIdth Modulation Controller (PWM)
37.1 Overview The PWM macrocell controls several channels independently. Each channel controls one
square output waveform. Characteristics of the output waveform such as period, duty-cycle and
polarity are configurable through the user interface. Each channel selects and uses one of the
clocks provided by the clock generator. The clock generator provides sever al clocks resulting
from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through APB mapped registers.
Channels can be synchro nized, to gene rate n on over lapped wavef orms. All cha nnels inte grate a
double buffering system in order to prevent an unexpected output waveform while modifying the
period or the duty-cycle.
37.2 Block Diagram
Figure 37-1. Pulse Width Modulation Controller Block Diagram
PWM
Controller
APB
PWMx
PWMx
PWMx
Channel
Update
Duty Cycle
Counter
PWM0
Channel
PIO
AIC
PMC MCK Clock Generator APB Interface Interrupt Generator
Clock
Selector
Period
Comparator
Update
Duty Cycle
Counter
Clock
Selector
Period
Comparator
PWM0
PWM0
536 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.3 I/O Lines Description
Each channel outputs one waveform on one external I/O line.
37.4 Product Dependencies
37.4.1 I/O Lines The pins used for interfacing the PWM may be multiple xed with PIO lines. The programmer must
first progra m the PIO controlle r to assign the d esired PWM pins to their pe ripher al fu nction. I f I/O
lines of the PWM are not used by the application, they can be used for other purposes by the
PIO controller.
All of the PWM outpu ts may or may not be enab led. If a n application r equires onl y four channels,
then only four PIO lines will be assigned to PWM outputs.
37.4.2 Power Management
The PWM is not continuously clocked. The programmer must first enable the PWM clock in the
Power Management Controlle r (PMC) before using the PWM. However, if the application does
not require PWM operations, the PWM clock can be stopped when not needed and be restarted
later. In this case, the PWM will resume its operations where it left off.
Configuring the PWM does not req uire the PWM clock to be enabled.
37.4.3 Interrupt Sources
The PWM interrupt line is connected on one of the internal sources of the Advanced Interrupt
Controller. Using the PWM interrupt requires the AIC to be programmed first. Note that it is not
recommended to use the PWM interrupt line in edge sensitive mode.
Table 37-1. I/O Line Descripti on
Name Description Type
PWMx PWM Waveform Output for channel x Output
537
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.5 Functional Description
The PWM macrocell is primarily composed of a clock generator module and 4 channels.
– Clocked by the system clock, MCK, the clo ck generator module provides 13 clocks.
– Each channel can independently choose one of the clock generator outputs.
– Each channel generates an output waveform with attributes tha t can be defined
independently for each channel through the user interface registers.
37.5.1 PWM Clock Generator
Figure 37-2. Functional View of the Clock Generator Block Diagram
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in
the Power Management Controller (PMC).
The PWM macrocell master clock, MCK, is divided in the clock generator module to provide dif-
ferent clocks available for all channels. Each channel can independently select one of the
divided clocks.
The clock generator is divided in three blocks:
– a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8,
FMCK/16, FMCK/32, FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024
modulo n counter
MCK
MCK/2
MCK/4
MCK/16
MCK/32
MCK/64
MCK/8
Divider A clkA
DIVA
PWM_MR
MCK
MCK/128
MCK/256
MCK/512
MCK/1024
PREA
Divider B clkB
DIVB
PWM_MR
PREB
538 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA
(DIVB) field value in the PWM Mode register (PWM_MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register
are set to 0. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provide d by the m odulo n co un ter ar e turn ed of f e xcept clock “c lk” . Th is situa-
tion is also true when the PWM master clock is turned off through the Power Management
Controller.
37.5.2 PWM Channel
37.5.2.1 Block Diagram
Figure 37-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of three blocks:
• A cloc k selecto r which selects one of t he cloc ks pr ov ided by the cloc k gener ator d escribed in
Section 37.5.1 “PWM Clock Generator” on page 537.
• An internal counter clocked by the output of the clock selector. This internal counter is
incremented or decremen ted according to the channel configur ation and comparators e vent s.
The size of the internal counter is 16 bits.
• A comparator used to generate events according to the internal counter value. It also
computes the PWMx output waveform according to the configuration.
37.5.2.2 Waveform Properties
The different properties of output waveforms are:
• the internal clock selection. The internal channel counter is clock ed by one of the clocks
provided by the clock genera tor de scribed in th e pr evious se ction. Th is channe l p ar a met er is
defined in the CPRE field of th e PW M _CM R x reg iste r. This field is reset at 0.
• the waveform period. This channel parameter is defined in the CPRD field of the
PWM_CPRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X giv en prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula
Comparator PWMx
output waveform
Internal
Counter
Clock
Selector
inputs
from clock
generator
inputs from
APB bus
Channel
539
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X giv en prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
• the wavef or m alignment. The output wa vef o rm can be left or center aligned. Center alig ned
wav eforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
XCPRD×()
MCK
--------------------------------
CRPD DIVA×()
MCK
-------------------------------------------
CRPD DIVAB×()
MCK
-----------------------------------------------
2XCPRD××()
MCK
-------------------------------------------
2CPRD DIVA××()
MCK
------------------------------------------------------
2CPRD×DIVB×()
MCK
------------------------------------------------------
duty cycle period 1 fchannel_x_clock CDTY×⁄–()
period
------------------------------------------------------------------------------------------------------------=
duty cycle period 2⁄()1 fchannel_x_clock CDTY×⁄–())
period 2⁄()
------------------------------------------------------------------------------------------------------------------------------=
540 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 37-4. Non Overlapped Center Aligned Waveforms
Note: 1. See Figure 37-5 on page 541 for a detailed description of center aligned waveforms.
When center aligned, the internal channel counter increa ses up to CPRD and.decreases down
to 0. This ends the period.
When left aligned, the internal channel counter increases up to CPRD and is reset. This ends
the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a
left aligned channel.
Waveforms are fixe d at 0 when:
• CDTY = CPRD and CPOL = 0
• CDTY = 0 and CPOL = 1
Waveforms are fixe d at 1 (once the channel is enable d ) whe n :
• CDTY = 0 and CPOL = 0
• CDTY = CPRD and CPOL = 1
The waveform polarity must be set before enabling the channel. This immediately affects the
channel output level. Changes on channel polarity are not taken into account while the channel
is enabled.
PWM0
PWM1
Period
No overlap
541
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 37-5. Waveform Properties
PWM_MCKx
CHIDx(PWM_SR)
Center Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output W av ef orm PWMx
CPOL(PWM_CMRx) = 0
Output W av ef orm PWMx
CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
Left Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output W av ef orm PWMx
CPOL(PWM_CMRx) = 0
Output Waveform PWMx
CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
CALG(PWM_CMRx) = 0
CALG(PWM_CMRx) = 1
Period
Period
CHIDx(PWM_ENA)
CHIDx(PWM_DIS)
542 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.5.3 PWM Controller Operations
37.5.3.1 Initialization Before enabling the output channel, this channel must have been configured by the software
application:
• Configuration of the clock generator if DIVA and DIVB are required
• Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
• Configuration of the wave form alignment for each channel (CALG field in the PWM_CMRx
register)
• Configuratio n of the period f o r each channel (CPRD in the PWM_CPRDx register). Writing in
PWM_CPRDx Register is possible while the channel is disabled. After validation of the
channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained
below.
• Configuration of the duty cycle fo r each channel (CDTY in the PWM_CDTYx register).
Writing in PWM_CDTYx Register is possible while the channel is disab led. Afte r v alidation of
the channel, the user m ust use PWM_CUPDx Register to update PWM_CDTYx as ex plained
below.
• Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx
register)
• Enable Interrupts (Writing CHIDx in the PWM_IER register)
• Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
It is possible to synchronize different channels by enabling them at the same time by means of
writing simultaneously several CHIDx bits in the PWM_ENA register.
• In such a situation, all channels may have the same clock selector configuration and the
same period specified.
37.5.3.2 Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relatio nship between the
value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can
help the user in choosi ng. The event num ber written in the Period Register giv es the PWM accu-
racy. The Duty Cycle quantum ca nnot be lo wer th an 1/PWM_CPRDx value. The higher the value
of PWM_CPRDx, the gr eater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value
between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle qua ntum cannot be lo w er
than 1/15 of the PWM period.
37.5.3.3 Changing the Duty Cycle or the Period
It is possible to modulate the output waveform duty cycle or period.
To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx)
to change waveform parameters while the channel is still enabled. The user can write a new
period value or duty cycle value in the update register (PWM_CUPDx). This register holds the
new value until the en d of th e cu rr en t cycle and upda tes the valu e fo r th e n ex t cycle . De pe nd in g
on the CPD field in the PWM_CMRx register, PWM_CUPDx either updates PWM_CPRDx or
PWM_CDTYx. Note that even if the update register is used, the period must not be smaller than
the duty cycle.
543
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 37-6. Synchronized Period or Duty Cycle Update
To prevent over wr iting t h e PWM_CUPDx b y so ft ware, the user can use status e vent s in o rder to
synchronize his software. Two methods are possible. In both, the user must enable the dedi-
cated interrupt in PWM_IER at PWM Controller level.
The first method (polling method) consists of reading the relevant status bit in PWM_ISR Regis-
ter according to the enabled channel(s). See Figure 37-7.
The second met hod uses an Interrupt Service Routine associated with the PWM channel.
Note: Reading the PWM_ISR register automatica lly clears CHIDx flags.
Figure 37-7. Polling Method
Note: Polarity and alignment can be modified only when the channel is disabled.
PWM_CUPDx Value
PWM_CPRDx PWM_CDTYx
End of Cycle
PWM_CMRx. CPD
User's Writing
10
Writing in PWM_CUPDx
The last write has been taken into account
CHIDx = 1
Writing in CPD field
Update of the Period or Duty Cycle
PWM_ISR Read
Acknowledgement and clear previous register state
YES
544 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.5.3.4 Interrupts Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end
of the corresponding channel period. The interrupt remains active until a read operation in the
PWM_ISR register occurs.
A channel interrupt is en abled by setting the cor responding bit in the PWM_IER re gister. A chan-
nel interrupt is disable d by setting the corresponding bit in the PWM_IDR register .
545
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6 Pulse Width Modulation (PWM) Controller User Interface
Table 37-2. PWM Controller Registers
Offset Register Name Access Peripheral
Reset Value
0x00 PWM Mode Register PWM_MR Read/Write 0
0x04 PWM Enable Register PWM_ENA Write-only -
0x08 PWM Disable Register PWM_DIS Write-only -
0x0C PWM Status Register PWM_SR Read-only 0
0x10 PWM Interrupt Enable Register PWM_IER Write-only -
0x14 PWM Interrupt Disable Register PWM_IDR Write-only -
0x18 PWM Interrupt Mask Register PWM_IMR Read-only 0
0x1C PWM Interrupt Status Register PWM_ISR Read-only 0
0x4C - 0xFC Reserved – – –
0x100 - 0x1FC Reserved
0x200 Channel 0 Mode Register PWM_CMR0 Read/Write 0x0
0x204 Channel 0 Duty Cycle Register PWM_CDTY0 Read/Write 0x0
0x208 Channel 0 Period Register PWM_CPRD0 Read/Write 0x0
0x20C Channel 0 Counter Register PWM_CCNT0 Read-only 0x0
0x210 Channel 0 Update Register PWM_CUPD0 Write-only -
... Reserved
0x220 Channel 1 Mode Register PWM_CMR1 Read/Write 0x0
0x224 Channel 1 Duty Cycle Register PWM_CDTY1 Read/Write 0x0
0x228 Channel 1 Period Register PWM_CPRD1 Read/Write 0x0
0x22C Channel 1 Counter Register PWM_CCNT1 Read-only 0x0
0x230 Channel 1 Update Register PWM_CUPD1 Write-only -
... ... ... ... ...
546 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6.1 PWM Mode Register
Name: PWM_MR
Access: Read/Write
• DIVA, DIVB: CLKA, CLKB Divide Factor
• PREA, PREB
31 30 29 28 27 26 25 24
–––– PREB
23 22 21 20 19 18 17 16
DIVB
15 14 13 12 11 10 9 8
–––– PREA
76543210
DIVA
DIVA, DIVB CLKA, CLKB
0 CLKA, CLKB clock is turned off
1 CLKA, CLKB clock is clock selected by PREA, PREB
2-255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
PREA, PREB Divider Input Clock
0000MCK.
0001MCK/2
0010MCK/4
0011MCK/8
0100MCK/16
0101MCK/32
0110MCK/64
0111MCK/128
1000MCK/256
1001MCK/512
1010MCK/1024
Other Reserved
547
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6.2 PWM Enable Register
Name: PWM_ENA
Access: Write-only
• CHIDx: Channel ID
0 = No effect.
1 = Enable PWM output for channel x.
37.6.3 PWM Disable Register
Name: PWM_DIS
Access: Write-only
• CHIDx: Channel ID
0 = No effect.
1 = Disable PWM output for channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
548 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6.4 PWM Status Register
Name: PWM_SR
Access: Read-only
• CHIDx: Channel ID
0 = PWM output for channel x is disabled.
1 = PWM output for channel x is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
549
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6.5 PWM Interrupt Enable Register
Name: PWM_IER
Access: Write-only
• CHIDx: Channel ID.
0 = No effect.
1 = Enable interrupt for PWM channel x.
37.6.6 PWM Int e rru pt Dis able Re gi st er
Name: PWM_IDR
Access: Write-only
• CHIDx: Channel ID.
0 = No effect.
1 = Disable interrupt for PWM channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
550 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6.7 PWM Interrupt Mask Register
Name: PWM_IMR
Access: Read-only
• CHIDx: Channel ID.
0 = Interrupt f or PWM channel x is disabled.
1 = Interrupt f or PWM channel x is enabled.
37.6.8 PWM Interrupt Status Register
Name: PWM_ISR
Access: Read-only
• CHIDx: Channel ID
0 = No new channel period has been achieved since the last read of the PWM_ISR register.
1 = At least one new ch annel period has been achi eved since the last read of the PWM_ISR register.
Note: Reading PWM_ISR automatically clears CHIDx flags.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
551
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6.9 PWM Channel Mode Register
Name: PWM_CMRx
Access: Read/Write
• CPRE: Channel Pre-scaler
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The output waveform starts at a low level.
1 = The output waveform starts at a high level.
• CPD: Channel Update Period
0 = Writing to the PWM_CUPDx will modify the duty cyc le at the next period start event.
1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––CPDCPOLCALG
76543210
–––– CPRE
CPRE Channel Pre-scaler
0000MCK
0001MCK/2
0010MCK/4
0011MCK/8
0100MCK/16
0101MCK/32
0110MCK/64
0111MCK/128
1000MCK/256
1001MCK/512
1010MCK/1024
1011CLKA
1100CLKB
Other Reserved
552 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6.10 PWM Channel Duty Cycle Register
Name: PWM_CDTYx
Access: Read/Write
Only the first 16 bits (int er na l ch annel counter size) are significant.
• CDTY: Channel Duty Cycle
Defines the waveform duty cycle. This value must be defined betwee n 0 and CPRD (PWM_CPRx).
31 30 29 28 27 26 25 24
CDTY
23 22 21 20 19 18 17 16
CDTY
15 14 13 12 11 10 9 8
CDTY
76543210
CDTY
553
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6.11 PWM Channel Period Register
Name: PWM_CPRDx
Access: Read/Write
Only the first 16 bits (int er na l ch annel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Cloc k (MCK) divided b y an X giv en prescaler v alue (with X bein g 1, 2, 4, 8, 16, 32, 64, 12 8,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
If the waveform is center-aligned, then the output waveform period depend s on the counter source clock and can be
calculated:
– By using the Master Cloc k (MCK) divided b y an X giv en prescaler v alue (with X bein g 1, 2, 4, 8, 16, 32, 64, 12 8,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
31 30 29 28 27 26 25 24
CPRD
23 22 21 20 19 18 17 16
CPRD
15 14 13 12 11 10 9 8
CPRD
76543210
CPRD
XCPRD×()
MCK
--------------------------------
CRPD DIVA×()
MCK
-------------------------------------------
CRPD DIVAB×()
MCK
-----------------------------------------------
2XCPRD××()
MCK
-------------------------------------------
2CPRD DIVA××()
MCK
------------------------------------------------------
2CPRD×DIVB×()
MCK
------------------------------------------------------
554 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
37.6.12 PWM Channel Counter Register
Name: PWM_CCNTx
Access: Read-only
• CNT: Channel Counter Register
Internal counter value. This register is reset when:
the channel is enabled (writing CHIDx in the PWM_ENA register).
the counter reaches CPRD value def ine d in the PWM _C PRDx register if the waveform is left aligned.
37.6.13 PWM Channel Update Register
Name: PWM_CUPDx
Access: Write-only
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modify-
ing the waveform period or duty-cycle.
Only the first 16 bits (int er na l ch annel counter size) are significant.
31 30 29 28 27 26 25 24
CNT
23 22 21 20 19 18 17 16
CNT
15 14 13 12 11 10 9 8
CNT
76543210
CNT
31 30 29 28 27 26 25 24
CUPD
23 22 21 20 19 18 17 16
CUPD
15 14 13 12 11 10 9 8
CUPD
76543210
CUPD
CPD (PWM_CMRx Register)
0The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the
beginning of the next period.
1The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning
of the next period.
555
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38. USB Device Port (UDP)
38.1 Overview The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed
device specification.
Each endpoint can be config ure d in one of several USB tra nsfe r types. It can be asso ciat ed with
one or two banks of a dual-port RAM used to store the current data payload. If two banks are
used, one DPR bank is read or written by the processor, while the other is read or written by the
USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device
maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of
DPR.
Note: 1. The Dual-Bank function provides two banks for an endpoint. This feature is used for ping-pong mode.
Suspend and resume are automatically detected by the USB device, which notifies the proces-
sor by raising an interrupt. Depending on the product, an external signal can be used to send a
wake up to the USB host contro ller .
Table 38-1. USB Endpoint Description
Endpoint Number Mnemonic Dual-Bank(1) Max. Endpoint Size En dpoint Type
0 EP0 No 8 Control/Bulk/Interrupt
1 EP1 Yes 64 Bulk/Iso/Interrupt
2 EP2 Yes 64 Bulk/Iso/Interrupt
3 EP3 No 64 Control/Bulk/Interrupt
4 EP4 Yes 64 Bulk/Iso/Interrupt
5 EP5 Yes 64 Bulk/Iso/Interrupt
6 EP6 Yes 64 Bulk/Iso/Interrupt
7 EP7 Yes 64 Bulk/Iso/Interrupt
556 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.2 Block Diagram
Figure 38-1. Block Diagram
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by
reading and writing 8-bit values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain
(MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system
mode. The host is then notified that the device asks for a resume. This optional feature must
also be negotiated with the host during the enumeration.
38.2.1 Signal Description
Atmel Bridge
12 MHz
Suspend/Resume Logic
W
r
a
p
p
e
r
W
r
a
p
p
e
r
U
s
e
r
I
n
t
e
r
f
a
c
e
Serial
Interface
Engine
SIE
MCK
Master Clock
Domain
Dual
Port
RAM
FIFO
UDPCK
Recovered 12 MHz
Domain
udp_int
USB Device
Embedded
USB
Transceiver
DDP
DDM
APB
to
MCU
Bus
txoen
eopn
txd
rxdm
rxd
rxdp
Table 38-2. Signal Names
Signal Name Description Type
UDPCK 48 MHz clock input
MCK Master clock input
udp_int Interr upt line connected to the Advanced Interrupt
Controller (AIC) input
DDP USB D+ line I/O
DDM USB D- line I/O
557
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.3 Product Dependencies
For further d etails on the USB De vice hardware im plementation, see the specific Pr oduct Prop-
erties document.
The USB physical transceiver is integrated into the product. The bidirectional differential signals
DDP and DDM are available from the product boundary.
38.3.1 I/O Lines DDP and DDM are not controlled by any PIO controllers. The e mbedded USB physical trans -
ceiver is controlled by the USB device peripheral.
To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to
assign this I/O in input PIO mode .
38.3.2 Power Management
The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL
with an accuracy of ± 0.25%.
Thus, the USB device receives two clocks from the Power Management Controller (PMC): the
master clock, MCK, used to d rive the peripheral user int erface, and the UDPCK, used to inter -
face with the bus USB signals (recovered 12 MHz domain).
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be
enabled before any read/write operations to the UDP registers including the UDP_TXVC
register.
38.3.3 Interrupt The USB device interface has an interrupt line connected to the Interrupt Controller.
Handling the USB device interrupt requires programming the Interrupt Controller before config-
uring the UDP.
558 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.4 Typical Connection
Figure 38-2. Board Schematic to Interface Device Peripheral
38.4.1 USB Device Transceiver
The USB device transceiver is embedded in the product. A few discrete components are
required as follows:
• the application detects all device states as defined in chapter 9 of the USB specification;
–VBUS monitoring
• to reduce power consumption the ho st is disconnected
• for line termination.
38.4.2 VBUS Monitoring
VBUS monitoring is required to detect host connection. VBUS monitoring is done using a stan-
dard PIO with intern al p ullup d i sable d. W hen th e host is s witche d o ff, it sh ou ld be con side r ed as
a disconnect, the pullup must be disa ble d in ord er to pr even t powerin g th e ho st th ro ugh the pull-
up resistor.
When the host is disc onnected and the tran sceiver is en abled, the n DDP and DDM ar e floating.
This may lead to over consumption. A solu tion is to connect 330 KΩ pulldowns on DDP and
DDM. These pulldowns do not alter DDP and DDM signal integrity.
A termination serial resistor must be connected to DDP and DDM. The resistor value is defined
in the electrical specification of the product (REXT).
R
EXT
R
EXT
DDM
DDP
PIO 27 K
47 K
330 K
Type B
Connector
12
34
5V Bus Monitoring
330 K
559
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.5 Functional Description
38.5.1 USB V2.0 Full-speed Introduction
The USB V2.0 full-speed provides commun ication services between host and attached USB
devices. Each device is offered with a collection of communication flows (pipes) associated with
each endpoint. Software on the host communicates with a USB device through a set of commu-
nication flows.
Figure 38-3. Example of USB V2.0 Full-speed Communicat ion Control
The Control Transfer endpoint EP0 is always used when a USB device is first conf igured (USB v. 2.0 specifications).
38.5.1.1 USB V2.0 Full-speed Transfer Types
A communication flow is carried over one of four transfer types defined by the USB device.
EP0
USB Host V2.0
Software Client 1 Software Client 2
Data Flow: Bulk Out Transfer
Data Flow: Bulk In Transfer
Data Flow: Control Transfer
Data Flow: Control Transfer
EP1
EP2
USB Device 2.0
Block 1
USB Device 2.0
Block 2
EP5
EP4
EP0
Data Flow: Isochronous In Transfer
Data Flow: Isochronous Out Transfer
USB Device endpoint configuration requires that
in the first instance Control Transfer must be EP0.
Table 38-3. USB Communication Flow
Transfer Direction Bandwidth Supported Endpoint Size Error Detection Retr ying
Control Bidirectional Not guaranteed 8, 16, 32, 64 Yes Automatic
Isochronous Unidirectional Guaranteed 64 Yes No
Interrupt Unidirectional Not guaranteed ≤ 64 Yes Yes
Bulk Unidirectional Not guaranteed 8, 16, 32, 64 Yes Yes
560 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.5.1.2 USB Bus Transaction s
Each transfer results in one or more transactions over the USB bus. There are three kinds of
transactions flowing across the bus in packets:
1. Setup Transaction
2. Data IN Transaction
3. Data OUT Transaction
38.5.1.3 USB Transfer Event Definition s
As indicated below, transfers are sequential events carried out on the USB bus.
Notes: 1. Control transfer must use endpoints with no ping-pong attributes.
2. Isochronous transfers must use endpoints with ping-pong attributes.
3. Control transfers can be aborted using a stall handshake.
A status transaction is a special type of host-to- device transaction used only in a contr ol transfer.
The control transfer must be performed using endpoints with no ping-pong attributes. According
to the control se quence (read or write), the USB device sends or receives a status transaction.
Table 38-4. USB Transfer Events
Control Transfers(1) (3)
• Setup transaction > Data IN transactions > Status
OUT transaction
• Setup transacti on > Data OUT t ran sactions > Status
IN transaction
• Setup transaction > Status IN transaction
Interrupt IN Transfer
(device toward host) • Data IN transaction > Data IN transaction
Interrupt OUT Transfer
(host toward device) • Data OUT transaction > Data OUT transaction
Isochronous IN Transfer(2)
(device toward host) • Data IN transaction > Data IN transaction
Isochronous OUT Transfer(2)
(host toward device) • Data OUT transaction > Data OUT transaction
Bulk IN Transfer
(device toward host) • Data IN transaction > Data IN transaction
Bulk OUT Transfer
(host toward device) • Data OUT transaction > Data OUT transaction
561
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 38-4. Control Read and Write Sequences
Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using
D ATA1 PID. Refer to Chapter 8 of the Univ ersal Serial Bus Specification, Rev. 2.0, f or more information on the protocol la y er.
2. During the Status OUT stage, the host emits a zero length p acket to the device (Data OUT transaction with no data).
38.5.2 Handling Transactions with USB V2.0 Device Peripheral
38.5.2.1 Setup Transaction
Setup is a special type of host-t o-device t ransactio n used during control t ransf ers. Co nt rol tr ans-
fers must be performed using en dpoints with no ping-pong attribut es. A setup transaction needs
to be handled as soon as possible by the firmware. It is used to transmit requests from the host
to the device. These requests are then handled by the USB device and may require more argu-
ments. The arguments are sent to the device by a Data OUT transaction which follows the setup
transaction. These requests may also return data. The data is carried out to the host by the next
Data IN transaction which follows the setup tran saction. A status transaction ends the control
transfer.
When a setup transfer is received by the USB endpoint:
• The USB device automatically acknowledges the setup packet
• RXSETUP is set in the UDP_CSRx register
• An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is
carried out to the microcontroller if interrupts are enabled for this endpoint.
Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read
the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the
setup packet has been rea d in t he FIF O. Ot herwise, the USB d evice wou ld a ccept the n ext Da ta
OUT transfer and overwrite the setup packet in the FIFO.
Control Read Setup TX Data OUT TX Data OUT TX
Data Stage
Control Write
Setup Stage
Setup Stage
Setup TX
Setup TX
No Data
Control
Data IN TX Data IN TX
Status Stage
Status Stage
Status IN TX
Status OUT TX
Status IN TX
Data Stage
Setup Stage Status Stage
562 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 38-5. Setup Transaction Followed by a Data OUT Transaction
38.5.2.2 Data IN Transaction
Data IN transactions are used in control, iso chronous, bulk and interrupt transfers and conduct
the transfer of data from the device to the host. Data IN transactions in isochronous tra nsfer
must be done using endpoints with ping-pong att ributes.
38.5.2.3 Using Endpoints Without Ping-pong Attributes
To perform a Data IN transaction using a non ping-pong endpoint:
1. The application chec ks if it is possible to write in the FIFO by polling TXPKTRDY in the
endpoint’s UDP_CSRx register (TXPKTRDY must be cleared).
2. The application writes the first pack et of data to be sent in the endpoint’s FIFO, writing
zero o r more byte values in the endpoint’s UDP_FDRx register,
3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in
the endpoint’s UDP_CSRx register.
4. The application is notified that the endpoint’s FIFO has been released by the USB
device when TXCOMP in the endpoint’s UDP_CSRx register has been set. Then an
interrupt for the corresponding endpoint is pending while TXCOMP is set.
5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO,
writing zero or more byte values in the endpoint’s UDP_FDRx register,
6. The microcontroller notifies the USB peripheral it has finished by setting the TXPK-
TRDY in the endpoint’s UDP_CSRx regist er.
7. The application clears the TXCOMP in the endpoint’s UDP_CSRx.
After the last packet has been sent, the application must clear TXCOMP once this has been set.
TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN
packet. An interrupt is pending while TXCOMP is set.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the
Data IN protocol layer.
RX_Data_BKO
(UDP_CSRx)
ACK
PID
Data OUT
Data OUT
PID
NAK
PID
ACK
PID
Data Setup
Setup
PID
USB
Bus Packets
RXSETUP Flag
Set by USB Device Cleared by Firmware Set by USB
Device Peripheral
FIFO (DPR)
Content Data Setup Data
XX XX OUT
Interrupt Pending
Setup Received Setup Handled by Firmware Data Out Received
Data OUT
Data OUT
PID
563
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 38-6. Data IN Transfer for Non Ping-pong Endpoint
38.5.2.4 Using Endpoints With Ping-pong Attribute
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This
also allows handling t h e maximum band wid th d efined in the USB specificat ion durin g bulk tr an s-
fer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must
prepare the next data payload to be sent while the current one is being sent by the USB device.
Thus two banks of memory are used. While one is available for the microcontroller, the other
one is locked by the USB device.
Figure 38-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints
When using a ping-pong endp oint, the following procedures are required to perform Data IN
transactions:
USB Bus Packets Data IN 2
Data IN NAK
ACK
Data IN 1
FIFO (DPR)
Content Data IN 2Load In ProgressData IN 1
Cleared by Firmware
DPR access by the firmware
Payload in FIFO
TXCOMP Flag
(UDP_CSRx)
TXPKTRDY Flag
(UDP_CSRx)
PID
Data IN Data IN
PIDPID PIDPID ACK
PID
Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus
Interrupt
Pending
Interrupt Pending
Set by the firmware Set by the firmware
Cleared by
Firmware
Cleared by Hw
Cleared by Hw
DPR access by the hardware
USB Device USB Bus
Read
Write
Read and Write at the Same Time
1st Data Payload
2nd Data Payload
3rd Data Payload
3rd Data Payload
2nd Data Payload
1st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
Microcontroller
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 1
564 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
1. The microcontroller chec ks if it is possib le to write in the FIFO by polling TXPKTRDY to
be cleared in the endpoint’s UDP_CSRx register.
2. The microcontroller writes the first data pa yload to be sent in the FIFO (Bank 0) , writing
zero o r more byte values in the endpoint’s UDP_FDRx register.
3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the
FIFO b y setting the TXPKTRDY in the endpoint’s UDP_CSRx register.
4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second
data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the
endpoint’s UDP_FDRx register.
5. The microcontroller is notified that the first Bank has been released by the USB device
when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending
while TXCOMP is being set.
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB
device that it has prepared the second Bank to be sent, raising TXPKTRDY in the end-
point’s UDP_CSRx register.
7. At this step, Bank 0 is available and the microcontroller can prepare a third data pay-
load to be sent.
Figure 38-8. Data IN Transfer for Ping-pong Endpoint
Warning: There is software critical path due to the fact that once the second bank is filled, the
driver has t o wait for TX_C OMP to set TX _PKTRDY. If t he delay betw een receivin g TX_COMP
is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the
bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Data INData IN
Read by USB Device
Read by USB Device
Bank 1
Bank 0
FIFO (DPR)
TXCOMP Flag
(UDP_CSRx) Interrupt Cleared by Firmware
Set by USB
Device
TXPKTRDY Flag
(UDP_MCSRx)
ACK
PID Data IN
PID ACK
PID
Set by Firmware,
Data Payload Written in FIFO Bank 1
Cleared by USB Device,
Data Payload Fully Transmitted
Data IN
PID
USB Bus
Packets
Set by USB Device
Set by Firmware,
Data Payload Written in FIFO Bank 0
Written by
FIFO (DPR) Microcontroller
Written by
Microcontroller
Written by
Microcontroller
Microcontroller
Load Data IN Bank 0 Microcontroller Load Data IN Bank 1
USB Device Send Bank 0 Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
Interrupt Pending
565
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.5.2.5 Data OUT Transaction
Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and con-
duct the transfer of data from the host to the device. Data OUT transactions in isochronous
transfers must be done using endpoints with ping-pong attributes.
38.5.2.6 Data OUT Transaction Without Ping-pong Attributes
To perform a Data OUT transaction, using a non ping-pong endpoint:
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. While the FIFO associated to this
endpoint is being used by the microcontr oller, a NAK PID is returned to the host. Once
the FIFO is a v ailab le, data is written to the FIFO b y the USB de vice and an ACK is auto-
matically carried out to the host.
3. The microcontroller is notified that the USB device has received a data payload polling
RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this
endpoint while RX_DATA_BK0 is set.
4. The number of bytes available in the FIFO is made available by reading RXBYTECNT
in the endpoint’s UDP_CSRx register.
5. The microcontroller carries out data received from the endpoint’s memory to its mem-
ory. Data received is availabl e by reading the endpoint’s UDP_FDRx register.
6. The microcontroller notifies the USB device that it has finished the transfer by clearing
RX_DATA_BK0 in the endpoint’s UDP_CSRx register.
7. A new Data OUT packet can be accepted by the USB device.
Figure 38-9. Data OUT Transfer for Non Ping-pong Endpoints
An interrupt is pending while the flag RX_DATA_B K0 is set. Memory tran sfer between th e USB
device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been
cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the
current Data OUT pa cket in the FIFO.
ACK
PID
Data OUTNAK PIDPIDPIDPIDPID Data OUT2ACKData OUT Data OUT 1
USB Bus
Packets
RX_DATA_BK0
Set by USB Device Cleared by Firmware,
Data Payload Written in FIFO
FIFO (DPR)
Content Written by USB Device Microcontroller Read
Data OUT 1 Data OUT 1 Data OUT 2
Host Resends the Next Data Payload
Microcontroller Transfers Data
Host Sends Data Payload
Data OUT2 Data OUT2
Host Sends the Next Data Payload
Written by USB Device
(UDP_CSRx) Interrupt Pending
566 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.5.2.7 Using Endpoints With Ping-pong Attributes
During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be
able to guarantee a constant bandwidth, the microcontroller must read the previous data pay-
load sent by the host, while the current data payload is received by the USB device. Thus two
banks of memory are used. While one is availabl e for the microco ntroller, the o ther one is locked
by the USB device.
Figure 38-10. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints
When using a ping-pong endpoint, the following p rocedures are required to perform Data OUT
transactions:
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint . It is written in the endpoint’s FIFO
Bank 0.
3. The USB device sends an ACK PID pac ket to the host . The host can immedi ately send
a second Data OUT packet . It is accepted by the device and copied to FIFO Bank 1.
4. The microcontroller is notifi ed that the USB device has received a data payload, polling
RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this
endpoint while RX_DATA_BK0 is set.
5. The number of bytes available in the FIFO is made available by reading RXBYTECNT
in the endpoint’s UDP_CSRx register.
6. The microcontroller transfers out data received from the endpoint’s memory to the
microcontroller’s memory. Data received is made available by reading the endpoint’s
UDP_FDRx register.
7. The microcontroller notifies the USB peripheral device that it has finished the transfer
by clea ring RX_DATA_BK0 in the endpoint’s UDP_CSRx register.
8. A third Data OUT packet can be accepted by the USB peripheral device and copied in
the FIFO Bank 0.
9. If a second Data OUT packet has been received, the microcontroller is notified b y the
flag RX_DATA_BK1 set in the endpoint’s UDP_CSRx register. An interrupt is pending
for this endpoint while RX_DATA_BK1 is set.
USB Device USB Bus
Read
Write
Write and Read at the Same Time
1st Data Payload
2nd Data Payload
3rd Data Payload
3rd Data Payload
2nd Data Payload
1st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
Microcontroller
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 1
567
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
10. The microcontroller transfers out data received from the endpoint’s memory to the
microcontroller’s memory. Data received is available by reading the endpoint’s
UDP_FDRx register.
11. The microcontroller notifies the USB device it has finished the transfer by clearing
RX_DATA_BK1 in the endpoint’s UDP_CSRx register.
12. A f ourth Data OUT packet can be accepted by the USB device and copied in t he FIFO
Bank 0.
Figure 38-11. Data OUT Transfer for Ping-pong Endpo int
Note: An interrupt is pen ding while the RX_DATA_BK0 or RX_DATA_BK1 flag is set.
Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine
which one to clear first. Thu s the software must keep an intern al counter to be sure to cle ar alter-
natively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software
application is busy el sewhere and t he two banks are f illed by the USB host. Once th e application
comes back to the USB driver, the two flags are set.
38.5.2.8 Stall Handshake
A stall handshake can be used in on e of two distinct occasions. (For more inform ation on the
stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)
• A functional stall is used when the halt feature associated with the endpoint is set. ( Refer to
Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt
feature.)
• To abort the current request, a protocol stall is use d, but uniquely with control transfer.
The following procedure generates a stall packet:
A
P
Data OUT PID
ACK Data OUT 3
Data OUT
Data OUT 2
Data OUT
Data OUT 1
PID
Data OUT 3Data OUT 1Data OUT1
Data OUT 2 Data OUT 2
PID PID PID
ACK
Cleared by Firmware
USB Bus
Packets
RX_DATA_BK0 Flag
RX_DATA_BK1 Flag
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 1
FIFO (DPR)
Bank 0
Bank 1
Write by USB Device Write In Progress
Read By Microcontroller
Read By Microcontroller
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 0
Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0,
Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1,
Host Sends Third Data Payload
Cleared by Firmware
Write by USB Device
FIFO (DPR)
(UDP_CSRx)
(UDP_CSRx)
Interrupt Pending
Interrupt Pending
568 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register.
2. The host receives the stall packet.
3. The microcontroller is notified that the device has sent the stall by polling the
STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The
microcontroller must clear STALLSENT to clear the interrupt.
When a setup transaction is received after a stall handshake, STALLSENT must be cleared in
order to prevent interrupts due to STALLSENT being set.
Figure 38-12. Stall Handshake (Data IN Transfer)
Figure 38-13. Stall Handshake (Data OUT Transfe r)
Data IN Stall PIDPID
USB Bus
Packets
Cleared by Firmware
Set by Firmware
FORCESTALL
STALLSENT Set by
USB Device
Cleared by Firmware
Interrupt Pending
Data OUT PID Stall PID
Data OUT
USB Bus
Packets
Cleared by Firmware
Set by Firmware
FORCESTALL
STALLSENT
Set by USB Device
Interrupt Pending
569
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.5.2.9 Transmit Data Cancellation
Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure
to cancel transmission data held in these banks is described below.
To see the organization of dual-bank availability refer to Table 38-1 ”USB Endpoint Descript ion” .
38.5.2.10 Endpoints Without Dual-Banks
There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In
the other instance, TXPKTRDY is not set.
• TXPKTRDY is not set:
– Reset the endpo int to clear the FIFO (pointers). (See Section 38.6.9 ”UDP Reset
Endpoint Register”.)
• TXPKTRDY has already been set:
– Clear TXPKTRDY so that no packet is ready to be sent
– Reset the endpo int to clear the FIFO (pointers). (See Section 38.6.9 ”UDP Reset
Endpoint Register”.)
38.5.2.11 Endpoints With Dual-Banks
There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In
the other instance, TXPKTRDY is not set.
• TXPKTRDY is not set:
– Reset the endpo int to clear the FIFO (pointers). (See Section 38.6.9 ”UDP Reset
Endpoint Register”.)
• TXPKTRDY has already been set:
– Clear TXPKTRDY and read it back until actually read at 0.
– Set TXPKTRDY and read it back until actually read at 1.
– Clear TXPKTRDY so that no packet is ready to be sent.
– Reset the endpo int to clear the FIFO (pointers). (See Section 38.6.9 ”UDP Reset
Endpoint Register”.)
570 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.5.3 Controlling Device States
A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Speci-
fication, Rev 2.0.
Figure 38-14. USB Device State Diagram
Movement from one state to another depends on the USB bus state or on standard requests
sent through co ntrol transactions via the default endpoint (endpoint 0).
After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Sus-
pend/Resume requ ests from the USB host is mandatory. Constraints in Suspend Mode are very
strict for bus-powered applications; devices may not consume more than 500 µA on the USB
bus.
While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activ-
ity) or a USB device may send a wake up request to the host, e.g., waking up a PC by moving a
USB mouse.
The wake up feature is not mandatory for all devices and must be negotiated with the host.
Attached
Suspended
Suspended
Suspended
Suspended
Hub Reset
or
Deconfigured
Hub
Configured
Bus Inactive
Bus Activity
Bus Inactive
Bus Activity
Bus Inactive
Bus Activity
Bus Inactive
Bus Activity
Reset
Reset
Address
Assigned
Device
Deconfigured Device
Configured
Powered
Default
Address
Configured
Power
Interruption
571
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.5.3.1 Not Powered State
Self powered devices can detect 5V VBUS using a PIO as described in the typical connection
section. When the device is not con nect ed to a ho st , device powe r consum pt ion can be reduced
by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM
lines are pulled down by 330 K Ω resistors.
38.5.3.2 Entering Attached State
When no device is connected, the USB DDP and DDM signals are tied to GND by 15 KΩ pull-
down resistors integrated in the hub downstream ports. When a device is attached to a hub
downstream port , the device connects a 1.5 KΩ pull-up resistor on DDP. The USB bus line go es
into IDLE state, DDP is pulled up by the device 1.5 KΩ resistor to 3.3V and DDM is pulled down
by the 15 KΩ resistor of the host.
To enable integrated pull-up, the PUON bit in the UDP_TXVC register must be set.
Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is
done in the Power Management Controller.
After pullup connecti on, t he de vice ent er s the po were d sta te. I n this stat e, the UDPCK and MCK
must be enabled in the Power Management Controller. The transceiver ca n remain disabled.
38.5.3.3 From Powered State to Default State
After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmask-
able flag ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered.
Once the ENDBUSRES interrupt ha s been triggered, the device enters Default State. In this
state, the UDP software must:
• Enable the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and,
optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The
enumeration then begins b y a control transfer.
• Configure the interrupt mask register which has been reset by the USB reset detection
• Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register.
In this state UDPCK and MCK must be enabled.
Warning: Each time an ENDBUSRES interru pt is triggered, the Interrupt Mask Reg ister and
UDP_CSR registers have been reset.
38.5.3.4 From Default State to Address State
After a set address standard device request, the USB host peripheral enters the address state.
Warning: Before the device enters in address state, it must achieve the Status IN transaction of
the control tran sfer, i.e., the UDP device sets its new address once th e TXCOMP flag in the
UDP_CSR[0] register has been received and cleared.
To move to ad dress state, the driv er software sets the FADDEN flag in the UD P_GLB_STAT
register, sets its new address, and sets the FEN bit in the UDP_FADDR register.
38.5.3.5 From Address State to Configured State
Once a valid Set Configuration standard request has been received and acknowledged, the
device enables endpoints corresponding to the current configuration. This is done by setting the
EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding
interrupts in the UDP_IER register.
572 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.5.3.6 Entering in Suspend State
When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the
UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in th e UDP_IMR
register.This flag is clear ed by writin g to t he UDP_I CR re gist er. T hen t he de vice en ters Su sp end
Mode.
In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an exam-
ple, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes
into Idle Mode. It may also switch off other devices on the board.
The USB device peripheral clocks can be switched off. Resume event is asynchronously
detected. MCK and UDPCK can be switched off in the Power Management contro ller and the
USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register.
Warning: Read, wr ite oper ation s to t he UDP r egister s are a llowed only if MCK is en abled for the
UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations
after writing to the UDP_TXVC and acknowledging the RXSUSP.
38.5.3.7 Receiving a Host Resume
In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver
and clocks are disabled (however the pullup shall not be removed).
Once the resume is detected on the bus, the W AKEUP signal in the UDP_ISR is set. It may gen-
erate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be
used to wake up the core, enable PLL and main oscillators and configure clocks.
Warning: Read, wr ite oper ation s to t he UDP r egister s are a llowed only if MCK is en abled for the
UDP peripheral. MCK for the UDP must be enabled before clearing the WAKEUP bit in the
UDP_ICR register and clea ring T XVDIS in th e UDP_ TXVC re gist er .
38.5.3.8 Sending a Device Remote Wakeup
In Suspend state it is possible to wake up the host sending an external resume.
• The de vice m ust wait at lea st 5 ms after bein g entered in susp end bef ore sending an e xternal
resume.
• The device has 10 ms from the moment it starts to drain current an d it forces a K state to
resume the host.
• The device must force a K state from 1 to 15 ms to resume the host
Before sending a K state to the host, MCK, UDPCK and the transceiver must be enabled. Then
to enable the r emote wakeup feature, the RMWUPE bit in the UDP_GLB _STAT register must be
enabled. To fo rce the K st ate on t he line, a t ransiti on of the ESR bit fro m 0 to 1 has t o be do ne in
the UDP_GLB_STAT register. This transition must be accomplished by first writing a 0 in the
ESR bit and then writing a 1.
The K state is automatically ge nerated and released according to the USB 2.0 specification.
573
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6 USB Device Port (UDP) User Interface
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write
operations to th e UDP registers, including the UDP_TXVC register.
Notes: 1. Re set values are not defined for UDP_ISR.
2. See Warning above the ”Register Mapping” on this page.
Table 38-5. Register Mapping
Offset Register Name Access Reset
0x000 Frame Number Register UDP_FRM_NUM Read-only 0x0000_0000
0x004 Global State Register UDP_GLB_STAT Re ad-write 0x0000_0010
0x008 Function Address Register UDP_FADDR Read-write 0x0000_0100
0x00C Reserved – – –
0x010 Interrupt Enable Register UDP_IER Write-only
0x014 Interrupt Disable Register UDP_IDR Write-only
0x018 Interrupt Mask Register UDP_IMR Read-only 0x0000_1200
0x01C Interr upt Status Register UDP_ISR Read-only –(1)
0x020 Interrupt Clear Register UDP_IC R Write-only
0x024 Reserved – – –
0x028 Reset Endpoint Register UDP_RST_EP Read-write 0x00 00_0000
0x02C Reserved – – –
0x030 + 0x4 * (ept_num - 1) Endpoint Control and Status Register UDP_CSR Read-write 0x0000_0000
0x050 + 0x4 * (ept_num - 1) Endpoint FIFO Data Register UDP_FDR Read-write 0x0000_0000
0x070 Reserved – – –
0x074 Transceiver Control Register UDP_TXVC(2) Read-write 0x0000_0100
0x078 - 0xFC Reserved – – –
574 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.1 UDP Frame Number Registe r
Name: UDP_FRM_NUM
Access: Read-only
• FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats
This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
Value Updated at the SOF_EOP (Start of Frame End of Packet).
• FRM_ERR: Frame Error
This bit is set at SOF_EO P when the SOF packet is received containing an error.
This bit is reset upon re ceipt of SOF_PID.
• FRM_OK: Frame OK
This bit is set at SOF_EOP when the SOF packet is received without any error.
This bit is reset upon receipt of SOF_PID (Packet Identification).
In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for
EOP.
Note: In th e 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L.
31 30 29 28 27 26 25 24
--- --- --- --- --- --- --- ---
23 22 21 20 19 18 17 16
––––––FRM_OKFRM_ERR
15 14 13 12 11 10 9 8
––––– FRM_NUM
76543210
FRM_NUM
575
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.2 UDP Global State Register
Name: UDP_GLB_STAT
Access: Read-write
This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0.
• FADDEN: Function Address Enable
Read:
0 = Device is not in address state.
1 = Device is in address state.
Write:
0 = No effect, only a reset can bring back a device to the default state.
1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_FADDR regis-
ter must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting
FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.
• CONFG: Configured
Read:
0 = Device is not in configured st ate.
1 = Device is in configure d state.
Write:
0 = Sets device in a non configured state
1 = Sets device in configured state.
The device is set in configured state when it is in address state and receives a successf ul Set Configuration request. Refer
to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.
• ESR: Enable Send Resume
0 = Mandatory value prior to starting any Remote Wake Up procedure.
1 = Starts the Remote Wake Up procedure if this bit value was 0 and if RMWUPE is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – RMWUPE RSMINPR ESR CONFG FADDEN
576 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• RMWUPE: Remote Wake Up Enable
0 = The Remote Wake Up feature of the device is disabled.
1 = The Remote Wake Up feature of the device is enabled.
577
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.3 UDP Function Address Register
Name: UDP_FADDR
Access: Read-write
• FADD[6:0]: F unction Address Value
The Function Ad dress Value must be prog rammed by firmware on ce the device receives a set add ress request from the
host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification,
Rev. 2.0 for more information. After power up or reset, the function address value is set to 0.
• FEN: Function Enable
Read:
0 = Function endpoint disabled.
1 = Function endpoint enabled.
Write:
0 = Disables function endpo int.
1 = Default value.
The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller
sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data
packets from and to the host.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––FEN
76543210
–FADD
578 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.4 UDP Interrupt Enable Register
Name: UDP_IER
Access: Write-only
• EP0INT: Enable Endpoint 0 Interrupt
• EP1INT: Enable Endpoint 1 Interrupt
• EP2INT: Enable Endpoint 2Interrupt
• EP3INT: Enable Endpoint 3 Interrupt
• EP4INT: Enable Endpoint 4 Interrupt
• EP5INT: Enable Endpoint 5 Interrupt
• EP6INT: Enable Endpoint 6 Interrupt
• EP7INT: Enable Endpoint 7 Interrupt
0 = No effect.
1 = Enables corresponding Endpoint Interrupt.
• RXSUSP: Enable UDP Suspend Interrupt
0 = No effect.
1 = Enables UDP Suspend Interrupt.
• RXRSM: Enable UDP Resume Interrupt
0 = No effect.
1 = Enables UDP Resume Interrupt.
• SOFINT: Enable Start Of Frame Interrupt
0 = No effect.
1 = Enables Start Of Frame Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP – SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
579
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• WAKEUP: Enable UDP bus Wakeup Interrupt
0 = No effect.
1 = Enables USB bus Interrupt.
580 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.5 UDP Interrupt Disable Register
Name: UDP_IDR
Access: Write-only
• EP0INT: Disable Endpoint 0 Interrupt
• EP1INT: Disable Endpoint 1 Interrupt
• EP2INT: Disable Endpoint 2 Interrupt
• EP3INT: Disable Endpoint 3 Interrupt
• EP4INT: Disable Endpoint 4 Interrupt
• EP5INT: Disable Endpoint 5 Interrupt
• EP6INT: Disable Endpoint 6 Interrupt
• EP7INT: Disable Endpoint 7 Interrupt
0 = No effect.
1 = Disables corresponding Endpoint Interrupt.
• RXSUSP: Disable UDP Suspend Interrupt
0 = No effect.
1 = Disables UDP Suspend Interrupt.
• RXRSM: Disable UDP Resume Interrupt
0 = No effect.
1 = Disables UDP Resume Interrupt.
• SOFINT: Disable Start Of Frame Interrupt
0 = No effect.
1 = Disables Start Of Frame Interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP – SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
581
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• WAKEUP: Disable USB Bus Interrupt
0 = No effect.
1 = Disables USB Bus Wakeup Interrupt .
582 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.6 UDP Interrupt Mask Register
Name: UDP_IMR
Access: Read-only
• EP0INT: Mask Endpoint 0 Interrupt
• EP1INT: Mask Endpoint 1 Interrupt
• EP2INT: Mask Endpoint 2 Interrupt
• EP3INT: Mask Endpoint 3 Interrupt
• EP4INT: Mask Endpoint 4 Interrupt
• EP5INT: Mask Endpoint 5 Interrupt
• EP6INT: Mask Endpoint 6 Interrupt
• EP7INT: Mask Endpoint 7 Interrupt
0 = Corresponding Endpoint Interrupt is disabled.
1 = Corresponding Endpoint Interrupt is enabled.
• RXSUSP: Mask UDP Suspend Interrupt
0 = UDP Suspend Interrupt is disabled.
1 = UDP Suspend Interr upt is enabled.
• RXRSM: Mask UDP Resume Interrupt.
0 = UDP Resume Interrupt is disabled.
1 = UDP Resume Interrupt is enabled.
• SOFINT: Mask Start Of Frame Interrupt
0 = Start of Frame Interrupt is disabled.
1 = Start of Frame Interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP BIT12 SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
583
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• BIT12: UDP_IMR Bit 12
Bit 12 of UDP_IMR cannot be masked and is always read at 1.
• WAKEUP: USB Bus WAKEUP Interrupt
0 = USB Bus Wakeup Interrupt is disabled.
1 = USB Bus Wakeup Interrupt is enabled.
Note: When the USB block is in suspend mode, the application ma y power down the USB logic. In this case, any USB HOST resume
request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is
enabled.
584 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.7 UDP Interrupt Status Register
Name: UDP_ISR
Access: Read-only
• EP0INT: Endpoint 0 Interrupt Status
• EP1INT: Endpoint 1 Interrupt Status
• EP2INT: Endpoint 2 Interrupt Status
• EP3INT: Endpoint 3 Interrupt Status
• EP4INT: Endpoint 4 Interrupt Status
• EP5INT: Endpoint 5 Interrupt Status
• EP6INT: Endpoint 6 Interrupt Status
• EP7INT: Endpoint 7Interrupt Status
0 = No Endpoint0 Interrupt pending.
1 = Endpoint0 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit.
• RXSUSP: UDP Suspend Interrupt Status
0 = No UDP Suspend Interrupt pending.
1 = UDP Suspend Interrupt has been raised.
The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP ENDBUSRES SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
585
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• RXRSM: UDP Resume Interrupt Status
0 = No UDP Resume Interrupt pending.
1 =UDP Resume Interrupt has been raised.
The USB device sets this bit when a UDP resume signal is detected at its port.
After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR
register.
• SOFINT: Start of Frame Interrupt Status
0 = No Start of Frame Interrupt pending.
1 = Start of Frame Interrupt has been raised.
This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using
isochronous endpoints.
• ENDBUSRES: End of BUS Reset Interrupt Status
0 = No End of Bus Reset Interrupt pending.
1 = End of Bus Reset Interrupt has been raised.
This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the end-
point 0. The host sta rts the enumeration, then performs the configuration.
• WAKEUP: UDP Resume Interrupt Status
0 = No Wakeup Interrupt pending.
1 = A Wakeup Interrupt ( USB Host Sent a RESUME or RESET) occurred since the last clear.
After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ICR
register.
586 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.8 UDP Interrupt Clear Register
Name: UDP_ICR
Access: Write-only
• RXSUSP: Clear UDP Suspend Interrupt
0 = No effect.
1 = Clears UDP Suspend Interrupt.
• RXRSM: Clear UDP Resume Interrupt
0 = No effect.
1 = Clears UDP Resume Interrupt.
• SOFINT: Clear Start Of Frame Interrupt
0 = No effect.
1 = Clears Start Of Frame Interrupt.
• ENDBUSRES: Clear End of Bus Reset Interrupt
0 = No effect.
1 = Clears End of Bus Reset Interrupt.
• WAKEUP: Clear Wakeup Interrupt
0 = No effect.
1 = Clears Wakeup Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP ENDBUSRES SOFINT EXTRSM RXRSM RXSUSP
76543210
––––––––
587
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.9 UDP Reset Endpoint Register
Name: UDP_RST_EP
Access: Read-write
• EP0: Reset Endpoint 0
• EP1: Reset Endpoint 1
• EP2: Reset Endpoint 2
• EP3: Reset Endpoint 3
• EP4: Reset Endpoint 4
• EP5: Reset Endpoint 5
• EP6: Reset Endpoint 6
• EP7: Reset Endpoint 7
This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It
also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter
5.8.5 in the USB Serial Bus Specification, Rev.2.0.
Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags.
0 = No reset.
1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx register.
Resetting the endpoint is a two-step operation:
1. Set the corresponding EPx field.
2. Clear the corresponding EPx field.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
588 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.10 UDP Endpoint Control and Status Register
Name: UDP_CSRx [x = 0..Y]
Access: Read-write
WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write
operation before executing another write by polling the bits which must be set/cleared.
/// Bitmap for all status bits in CSR that are not effected by a value 1.
#define REG_NO_EFFECT_1_ALL AT91C_UDP_RX_DATA_BK0\
| AT91C_UDP_RX_DATA_BK1\
| AT91C_UDP_STALLSENT\
| AT91C_UDP_RXSETUP\
| AT91C_UDP_TXCOMP
/// Sets the specified bit(s) in the UDP_CSR register.
/// \param endpoint The endpoint number of the CSR to process.
/// \param flags The bitmap to set to 1.
#define SET_CSR(endpoint, flags) \
{ \
volatile unsigned int reg; \
reg = AT91C_BASE_UDP->UDP_CSR[endpoint] ; \
reg |= REG_NO_EFFECT_1_ALL; \
reg |= (flags); \
AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \
while ( (AT91C_BASE_UDP->UDP_CSR[endpoint] & (flags)) != (flags)); \
}
/// Clears the specified bit(s) in the UDP_CSR register.
/// \param endpoint The endpoint number of the CSR to process.
/// \param flags The bitmap to clear to 0.
#define CLEAR_CSR(endpoint, flags) \
{ \
volatile unsigned int reg; \
reg = AT91C_BASE_UDP->UDP_CSR[endpoint]; \
reg |= REG_NO_EFFECT_1_ALL; \
31 30 29 28 27 26 25 24
––––– RXBYTECNT
23 22 21 20 19 18 17 16
RXBYTECNT
15 14 13 12 11 10 9 8
EPEDS – – – DTGLE EPTYPE
76543210
DIR RX_DATA_
BK1 FORCE
STALL TXPKTRDY STALLSENT
ISOERROR RXSETUP RX_DATA_
BK0 TXCOMP
589
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
reg &= ~(flags); \
AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \
while ( (AT91C_BASE_UDP->UDP_CSR[endpoint] & (flags)) == (flags)); \
}
Note: In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and 1peripheral clock cycle. How-
e ver, RX_DATA_BK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK clock cycles and 5 peripheral clock cycles
before accessing DPR.
• TXCOMP: Generates an IN P acket with Data Previously Written in the DPR
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Clear the flag, clear t he interrupt.
1 = No effect.
Read (Set by the USB peripheral):
0 = Data IN transaction has not been acknowledged by the Host.
1 = Data IN transaction is achieved, acknowled ged by the Host.
After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the
host has acknowledged t he transaction.
• RX_DATA_BK0: Receive Data Bank 0
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Notify USB peripheral de vice that data have been read in the FIFO's Bank 0.
1 = To leave the read value unchanged.
Read (Set by the USB peripheral):
0 = No data packet has been received in the FIFO's Bank 0.
1 = A data packet has been received, it has been stored in the FIFO's Bank 0.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to
the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read
through the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral
device by clearing RX_DATA_BK0.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
• RXSETUP: Received Setup
This flag generates an interrupt while it is set to one.
Read:
0 = No setup packet available.
1 = A setup data packet has been sent by the host and is available in the FIFO.
590 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Write:
0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO.
1 = No effect.
This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and success-
fully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the
UDP_FDRx register to the microcontroller memory . Once a transfer has been do ne, RXSETUP must be cleared by th e
device firmware.
Ensuing Data OUT transaction is not accepted while RXSETUP is set.
• STALLSENT: Sta ll Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints)
This flag generates an interrupt while it is set to one.
STALLSENT: This ends a STALL handshake.
Read:
0 = The host has not acknowledged a STALL.
1 = Host has acknowledged the stall.
Write:
0 = Resets the STALLSENT f lag, clears the interrupt.
1 = No effect.
This is mandatory for the device firmware to clear this flag . Otherwise the interrupt remains.
Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL
handshake.
ISOERROR: A CRC error has been detected in an isochronous transfer.
Read:
0 = No error in the previous isochronous transfer.
1 = CRC error has been detect ed, data available in the FIFO are corrupted.
Write:
0 = Resets the ISOERROR flag, clears the interrupt.
1 = No effect.
• TXPKTRDY: Transmit Packet Ready
This flag is cleared by t he USB device.
This flag is set by the USB device firmware.
Read:
0 = There is no data to send.
1 = The data is waiting to be sent upon reception of token IN.
591
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Write:
0 = Can be used in the procedure to cancel transmission data. (See, Section 38.5.2.9 “Transmit Data Cancellation” on
page 569)
1 = A new data payload has been written in the FIFO by the firmware and is ready to be sent.
This flag is used to gene rate a Data IN transa ction (d evice to host ). Device f irmwa re checks that it can write a data payload
in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx register. Once
the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB
bus transactions can start. TXCOMP is set once the data payload has been received by the host.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
• FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints)
Read:
0 = Normal state.
1 = Stall state.
Write:
0 = Return to normal state.
1 = Send STALL to the host.
Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL
handshake.
Control endpoin ts: During the data stage and sta tus stage, this bit indicates that the microcontroller cannot comp lete the
request.
Bulk and interrupt endpoints: This bit notifies the host that the en dpoint is halted.
The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.
• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Notifies USB device tha t data have been read in the FIFO’s Bank 1.
1 = To leave the read value unchanged.
Read (Set by the USB peripheral):
0 = No data packet has been received in the FIFO's Bank 1.
1 = A data packet has been received, it has been stored in FIFO's Bank 1.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to
microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read
through UDP_FDRx regist er. Once a transfer is do ne, the d evice fir mware must rele ase Bank 1 to the USB device by clear-
ing RX_DATA_BK1.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
592 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• DIR: Transfer Direction (only available for control endpoints)
Read-write
0 = Allows Data OUT transactions in the control data stage.
1 = Enables Data IN transactions in the control data stage.
Refer to Chapte r 8. 5.3 of th e Universal Serial Bus Specification, Rev. 2. 0 for more information on th e control data stage.
This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in
the setup data packet, the data stage is either a devic e to host (DIR = 1) or ho st to device (DIR = 0) data transfer. It is not
necessary to check this bit to reverse direction for the status stage.
• EPTYPE[2:0]: Endpoint Type
Read-Write
• DTGLE: Data Toggle
Read-only
0 = Identifies DATA0 packet.
1 = Identifies DATA1 packet.
Refer to Chapter 8 of the Un iversal Serial Bus Specification, Rev. 2.0 for more inform ation on DATA0, DATA1 packet
definitions.
• EPEDS: Endpoint Enable Disable
Read:
0 = Endpoint disabled.
1 = Endpoint enabled.
Write:
0 = Disables endpoint .
1 = Enables endpoint.
Control endpoints are always enabled. Reading or writing this field has no effect on control endpo ints.
Note: After reset, all endpoints are configured as control endpoint s (zero).
Value Name Description
000 CTRL Control
001 ISO_OUT Isochronous OUT
101 ISO_IN Isochronous IN
010 BULK_OUT Bulk OUT
110 BULK_IN Bulk IN
011 INT_OUT Interrupt OUT
111 INT_IN Interrupt IN
593
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• RXBYTECNT[10:0] : Number of Bytes Available in the FIFO
Read-only
When the host sends a data packet to the device, the USB device stores the d ata in the FIFO and notifies the microcon-
troller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register.
594 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.11 UDP FIFO Data Register
Name: UDP_FDRx [x = 0..Y]
Access: Read-write
• FIFO_DATA[7:0]: FIFO Data Value
The microcontroller can push or pop values in the FIFO through this register.
RXBYTECNT in the correspo nding UDP_CSRx re giste r is the number of bytes to be read from t he FIFO (sent by th e host).
The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be
more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0
for more inform a tio n.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
FIFO_DATA
595
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
38.6.12 UDP Transceiver Control Register
Name: UDP_TXVC
Access: Read-write
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write
operations to the UDP registers including the UDP_TXVC register.
• TXVDIS: Transceiver Disable
When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can
be done by setting TXVDIS field.
To enable the transceiver, TXVDIS must be cleared.
• PUON: Pullup On
0: The 1.5KΩ integrated pullup on DDP is disconnected.
1: The 1.5 KΩ integrated pullup on DDP is connected.
NOTE: If the USB p ullup is not connected on DDP, the user should not wr ite in any UDP register other than th e UDP_TXVC
register. This is be cause if DDP and DDM are floating at 0, or pulled down, then SE0 is rece ived by the device with the con-
sequence of a USB Reset .
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––
PUON TXVDIS
76543210
––––––––
596 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
597
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39. Analog-to-Digital Converter (ADC)
39.1 Overview The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Con-
verter (ADC). It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-
digital conversions of 8 analog lines. The conversions extend from 0V to ADVREF.
The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a
common register for all channels, as well as in a channel-dedicated register. Software trigger,
external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter out-
put(s) are configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC
channel. These features reduce both power consumption and processor intervention.
Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time.
39.2 Block Diagram
Figure 39-1. Analog-to-Digital Converter Block Diagram
ADC Interrupt
ADC
ADTRG
VDDANA
ADVREF
GND
Trigger
Selection Control
Logic
Successive
Approximation
Register
Analog-to-Digital
Converter
Timer
Counter
Channels
User
Interface
AIC
Peripheral Bridge
APB
PDC
ASB
Dedicated
Analog
Inputs
Analog Inputs
Multiplexed
with I/O lines
AD-
AD-
AD-
PIO
AD-
AD-
AD-
598 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.3 Signal Description
39.4 Product Dependencies
39.4.1 Power Management
The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the
ADC clock is automatica lly st opped a fter e ach conversion. As the lo gic is small an d the ADC cell
can be put into Sleep Mode, the Power Management Controller has no effect on the ADC
behavior.
39.4.2 Interrupt Sources
The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt
Controller. Using the ADC interrupt requires the AIC to be programmed first.
39.4.3 Analog Inputs The analog input pins can be multip lexed with PIO lin es. In this case, the assignment o f the ADC
input is automatically done as soon as the corresponding channel is enabled by writing the reg-
ister ADC_CHER. By default, after reset, the PIO line is configured as input with its pull-up
enabled and the ADC inp ut is connected to the GND.
39.4.4 I/O Lines The p in ADTRG may be shared with other periph eral functions through the PIO Cont roller. In
this case, the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC
function.
39.4.5 Timer TriggersTimer Counters may or may not be used as hardware triggers depending on user requirements.
Thus, some or all of the timer counters may be non-connected.
39.4.6 Conversion Performances
For performance and electrical characteristics of the ADC, see the DC Characteristics section.
Table 39-1. ADC Pin Description
Pin Name Description
VDDANA Analog power supply
ADVREF Reference voltage
AD0 - AD7Analog input channels
ADTRG External trigger
599
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.5 Functional Description
39.5.1 Analog-to-digital Conversion
The ADC uses the ADC Clock to perfor m conversi ons. Conver ting a si ngle anal og value to a 10-
bit digital data requ ire s Sample and Hold Clock cycles a s defi ned in t h e field SHTI M o f the “ADC
Mode Register” on page 606 an d 10 ADC Clo ck cycles. The ADC Clo ck fr eq uency is select ed in
the PRESCAL field of the Mode Register (ADC_MR).
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to
63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency accord-
ing to the parameters given in the Product definition section.
39.5.2 Conversion Reference
The conversion is perfo rme d on a full r ang e be twee n 0V and th e re ference voltage pin ADVREF.
Analog inputs betwe e n th ese volt ag es con ver t to va lue s ba se d on a linear co nversion.
39.5.3 Conversion Resolution
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit
LOWRES in the ADC Mode Register (ADC_MR). By default, afte r a reset, the resolution is the
highest and the DATA field in the data registers is fully used. By setting the b it LOWRES, the
ADC switches in th e lowe st resolu tio n and t h e conve rsion re su lts can be re ad in the eight lowest
significant bits of the data registers. The two highest b its of the DATA field in th e correspo nding
ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer
request sizes to 16-bit. Set ti ng the b it LO WRES aut om at ically switches to 8-bit data transfers. In
this case, the destination buffers are optimized.
600 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.5.4 Conversion Results
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data
Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register
(ADC_LCDR).
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of
a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either
EOC and DRDY can trigger an inter rupt.
Reading one of the ADC_ CDR registers clears the cor responding EOC bit. Read ing ADC_LCDR
clears the DRDY bit and the EOC bit corresponding to the last converted channel.
Figure 39-2. EOCx and DRDY Flag Behav ior
If the ADC_CDR is not read before further incoming data is converted, the corresponding Over-
run Error (OVRE) flag is set in the Status Register (ADC_SR).
In the same way, ne w dat a convert ed wh en DRDY is high sets the bit GOVRE (Gen eral Ov errun
Error) in ADC_SR.
The OVRE and GOVRE flags ar e automatically cleared when ADC_SR is read.
Conv ersion Time
Read the ADC_CDRx
EOCx
DRDY
Read the ADC_LCDR
CHx
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
Write the ADC_CR
with START = 1
Conv ersion Time
Write the ADC_CR
with START = 1
601
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 39-3. GOVRE and OVREx Flag Behavior
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and
then reenabled during a conversion, its associated data and its corresponding EOC and OVRE
flags in ADC_SR are unpredictable.
EOC0
GOVRE
CH0
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
ADTRG
EOC1
CH1
(ADC_CHSR)
(ADC_SR)
OVRE0
(ADC_SR)
Undefined Data Data A Data B
ADC_LCDR
Undefined Data Data A
ADC_CDR0
Undefined Data Data B
ADC_CDR1
Data C
Data C
Conversion
Conversion
Read ADC_SR
DRDY
(ADC_SR)
Read ADC_CDR1
Read ADC_CDR0
Conversion
602 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.5.5 Conversion Triggers
Conversions of the active analog channels are started with a software or a hardware trigger. The
software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1.
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the
external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRG-
SEL in the Mode Register (ADC_MR). The selected hardware trigger is enabled with the bit
TRGEN in the Mode Register (ADC_MR).
If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the
selected signal. I f one of the TIOA ou tputs is sele cted, th e correspo nding Timer Counter cha nnel
must be programmed in Waveform Mode.
Only one start comman d is necessar y to initiat e a conversion seq uence on all the ch ann els. The
ADC hardware logic automatically performs the conversions on the active channels, then waits
for a new req uest. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Reg-
isters enable the analog channels to be enabled or disabled independently.
If the ADC is used with a PDC, only the transfers of converted data from enabled channels are
performed and the resulting data buffers shou ld be interpreted accordingly.
Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if
a hardware trigger is selected, the start of a con version can be initiated eith er by the hardware or
the software trigger.
39.5.6 Sleep Mode and Conversion Sequencer
The ADC Sleep Mode ma ximi zes powe r savin g by automatically deactivating the ADC when it is
not being used for conversions. Sleep Mode is selected by setting the bit SLEEP in the Mode
Register ADC_MR.
The SLEEP mode is a utomatically managed by a conversion sequencer, which can automati-
cally process the conversions of all channels at lowest power consumption.
When a start conversion request occurs, the ADC is automatically activated. As the analog cell
requires a start-up t ime, the lo gic waits during this ti me and starts the conversion on the enabled
channels. When all conversio ns are complet e, the ADC is d eactivated u ntil the n ext trigge r. Trig-
gers occurring during the sequence are not taken into account.
The conversion sequencer allows automatic processing with minimum processor intervention
and optimized power consumption. Conversion sequences can be performed periodically using
a Timer/Counter output. The periodic acquisition of several samples can be processed automat-
ically without any intervention of the processor thanks to the PDC.
Note: The reference voltage pins always remain connected in normal mode as in sleep mode.
603
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.5.7 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in
the Mode Register ADC_MR.
In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the
best conver ted final value between two channels selection. This time has to be programmed
through the SHTIM bitfield in the Mode Register ADC_MR.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be
taken into consideration to program a precise value in the SHTIM field. See the section ADC
Characteris tics in th e pr od uct datasheet.
604 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6 Analog-to-digital Converter (ADC) User Interface
Table 39-2. ADC Register Mapping
Offset Register Name Access Reset State
0x00 Control Register ADC_CR Write-onl y –
0x04 Mode Regi ster ADC_MR Read/Write 0x00000000
0x08 Reserved – – –
0x0C Reserved – – –
0x10 Channel Enable Register ADC_CHER Write-onl y –
0x14 Channel Disable Register ADC_CHDR Write-only –
0x18 Channel Status Register ADC_CHSR Read-only 0x00000000
0x1C Status Register ADC_SR Read-only 0x000C0000
0x20 Last Converted Data Register ADC_LCDR Read-only 0x00000000
0x24 Interrupt Enable Register ADC_IER Write-only –
0x28 Interrupt Disable Register ADC_IDR Wr ite-only –
0x2C Interrupt Mask Regi ster ADC_IMR Re ad-only 0x00000000
0x30 Channel Data Register 0 ADC_CDR0 Read-only 0x00000000
0x34 Channel Data Register 1 ADC_CDR1 Read-only 0x00000000
... ... ... ... ...
0x4C Channel Data Registe r 7 ADC_CDR7 Read-only 0x00000000
0x50 - 0xFC Reserved – – –
605
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6.1 ADC Control Register
Name: ADC_CR
Access: Write-only
• SWRST: Software Reset
0 = No effect.
1 = Resets the ADC simulating a hardware reset.
• START: Start Conversion
0 = No effect.
1 = Begins analog-to-digital conversion.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––
START SWRST
606 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6.2 ADC Mode Register
Name: ADC_MR
Access: Read/Write
• TRGEN: Trigger Enable
• TRGSEL: Trigger Selection
• LOWRES: Resolution
• SLEEP: Sleep Mode
31 30 29 28 27 26 25 24
–––– SHTIM
23 22 21 20 19 18 17 16
– – – STARTUP
15 14 13 12 11 10 9 8
–– PRESCAL
76543210
– – SLEEP LOWRES TRGSEL TRGEN
TRGEN Selected TRGEN
0 Hardware triggers are disabled. Starting a conversion is only possible by software.
1 Hardware trigger selected by TRGSEL field is enabled.
TRGSEL Selected TRGSEL
0 0 0 TIOA Ouput of the Timer Counter Channel 0
0 0 1 TIOA Ouput of the Timer Counter Channel 1
0 1 0 TIOA Ouput of the Timer Counter Channel 2
011Reserved
100Reserved
101Reserved
1 1 0 External trigger
111Reserved
LOWRES Selected Resolution
0 10-bit resolution
1 8-bit resolution
SLEEP Selected Mode
0 Normal Mode
1 Sleep Mode
607
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
• PRESCAL: Prescaler Rate Selection
ADCClock = MCK / ( (PRESCAL+1) * 2 )
• STARTUP: Start Up Time
Startup Time = (STARTUP+1) * 8 / ADCClock
• SHTIM: Sample & Hold Time
Sample & Hold Time = SHTIM / ADCClock
608 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6.3 ADC Channel Enable Register
Name: ADC_CHER
Access: Write-only
• CHx: Channel x Enable
0 = No effect.
1 = Enables the corr esponding channel.
39.6.4 ADC Channel Dis able Regi st er
Name: ADC_CHDR
Access: Write-only
• CHx: Channel x Disable
0 = No effect.
1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver-
sion, its associated data an d its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
609
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6.5 ADC Channel Status Register
Name: ADC_CHSR
Access: Read-only
• CHx: Channel x Status
0 = Corresponding channel is disabled.
1 = Corresponding channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
610 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6.6 ADC Status Register
Name: ADC_SR
Access: Read-only
• EOCx: End of Conversion x
0 = Corresponding analog channel is disabled, or the conversion is not finished.
1 = Corresponding analog channel is enabled and conversion is complete.
• OVREx: Overrun Error x
0 = No overrun error on the corresponding channel since the last read of ADC_SR.
1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR.
• DRDY: Data Ready
0 = No data has been converted since the last read of ADC_LCDR.
1 = At least one data has been converted and is available in ADC_LCDR.
• GOVRE: General Overrun Error
0 = No General Overrun Error occurred since the last rea d of ADC_SR.
1 = At least one General Overrun Error has occurred since the last read of ADC_SR.
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR.
• RXBUFF: RX Buffer Full
0 = ADC_RCR or ADC_RNCR have a value other than 0.
1 = Both ADC_RCR and ADC_RNCR have a value of 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RXBUFFENDRXGOVREDRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
611
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6.7 ADC Last Converted Data Register
Name: ADC_LCDR
Access: Read-only
• LDATA: Last Data Converted
The analog-to- digital conve rsion dat a is pl aced into this register at the end of a conversion and remains until a new conver-
sion is completed.
39.6.8 ADC Interrupt Enable Register
Name: ADC_IER
Access: Write-only
• EOCx: End of Conver sion Interrupt Enable x
• OVREx: Overrun Error Interrupt Enable x
• DRDY: Data Ready Interrupt Enable
• GOVRE: General Overrun Error Interrupt Enable
• ENDRX: End of Rece ive Buffer In terrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––– LDATA
76543210
LDATA
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RXBUFFENDRXGOVREDRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
612 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6.9 ADC Interrupt Disable Register
Name: ADC_IDR
Access: Write-only
• EOCx: End of Conversion Interrupt Disable x
• OVREx: Overrun Error Interrupt Disable x
• DRDY: Data Ready Interrupt Disable
• GOVRE: General Overrun Error Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RXBUFFENDRXGOVREDRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
613
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6.10 ADC Interrupt Mask Register
Name: ADC_IMR
Access: Read-only
• EOCx: End of Conversion Interrupt Mask x
• OVREx: Overrun Error Interrupt Mask x
• DRDY: Data Ready Interrupt Mask
• GOVRE: General Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RXBUFFENDRXGOVREDRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
614 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39.6.11 ADC Channel Data Register
Name: ADC_CDRx
Access: Read-only
• DATA: Converted Data
The analog-to- digital conve rsion dat a is pl aced into this register at the end of a conversion and remains until a new conver-
sion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––– DATA
76543210
DATA
615
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40. SAM7SE512/256/32 Electrical Characteristics
40.1 Absolute Maximu m Ratings
Table 40-1. Absolute Maximum Ratings*
Operating Temperature (Industrial).........-40⋅C to + 85⋅C*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device at these or other con-
ditions beyond those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for
extended periods may affect device reliabil ity.
Storage Temperature............................-60°C to + 150°C
Voltage on Input Pins
with Respect to Ground............................-0.3V to + 5.5V
Maximum Operating Voltage
(VDDCORE, and VDDPLL).......................................2.0V
Maximum Operating Voltage
(VDDIO, VDDIN and VDDFLASH).............................4. 0V
Total DC Output Current on all I/O lines
128-lead LQFP/144-ball LFBGA...........................200 mA
616 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.2 DC Characteristics
The following characteristics are applicable to the operating tem perature range: TA = -40°C to 85°C, unless otherwise
specified.
Table 40-2. DC Characteristics
Symbol Parameter Conditions Min Typ Max Units
VVDDCORE DC Supply Core 1.65 1.95 V
VVDDPLL DC Supply PLL 1.65 1.95 V
VVDDIO DC Supply I/Os 3.3V domain 3.0 3.6 V
VVDDIO DC Supply I/Os 1.8V domain 1.65 1.95
VVDDFLASH DC Supply Flash 3.0 3.6 V
VIL Input Low-level Voltage VVDDIO from 3.0V to 3.6V -0.3 0.8 V
VVDDIO from 1.65V to 1.95V -0.3 0.3 x
VVDDIO V
VIH Input High-level Voltage VVDDIO from 3.0V to 3.6V 2.0 VVDDIO
+0.3V V
VVDDIO from 1.65V to 1.95V 0. 7 x
VVDDIO
VVDDIO
+0.3V V
VHys Hysteresis Voltage VVDDIO from 3.0V to 3.6V 0.4 0.7 V
VVDDIO from 1.65V to 1.95V 0.3 0.6 V
VOL Output Low-level Voltage IO max, VVDDIO from 3.0V to 3.6V 0.4 V
IO max, VVDDIO from 1.65V to 1.95V 0.25 x
VVDDIO
VOH Output High-level Voltage IO max, VVDDIO from 3.0V to 3.6V VVDDIO -0.4 V
IO max, VVDDIO from 1.65V to 1.95V 0.75 x
VVDDIO
ILEAK Input Leakage Current
PA0-PA3, Pull-up resistors disabled
(Typ: TA = 25°C, Max: TA = 85°C) 40 400 nA
Other PIOs, Pull-up resistors disabled
(Typ: TA = 25°C, Max: TA = 85°C) 20 200 nA
RPULLUP Pull-up Resistor
PA0-PA31, PB0-PB31,PC0-PC23,
VVDDIO from 3.0V to 3.6V 70 130 190 kΩ
PA0-PA31, PB0-PB31,PC0-PC23,
VVDDIO from 1.65V to 1.95V 95 147 320 kΩ
RPULLDOWN Pull-down Resistor,
(TST, ERASE, JTAGSEL) VVDDIO from 3.0V to 3.6V,
Pins connected to VVDDIO 81528kΩ
CIN Input Capacitance 14 pF
617
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
ISC Static Current
(SAM7SE512/256)
On VVDDCORE = 1.85V,
MCK = 500Hz TA = 25°C 12 60
µA
All inputs driven at 1
(including TMS, TDI, TCK,
NRST)
Flash in standby mode
All peripherals off
TA = 85°C 40 300
ISC Static Current
(SAM7SE32)
On VVDDCORE = 1.85V,
MCK = 500Hz TA = 25°C 10 40
µA
All inputs driven at 1
(including TMS, TDI, TCK,
NRST)
Flash in standby mode
All peripherals off
TA = 85°C 20 150
IOOutput Current
PA0-PA3, VVDDIO from 3.0V to 3.6V 16 mA
PA0-PA3, VVDDIO from 1.65V to 1.95V 8 mA
PA4-PA31, PB0-PB31, PC0-PC23 and
NRST, VVDDIO from 3.0V to 3.6V 8mA
PA4-PA31, PB0-PB31, PC0-PC23 and
NRST, VVDDIO from 1.65V to 1.95V 4mA
Table 40-2. DC Characteristics (Continued)
Symbol Parameter Conditions Min Typ Max Units
Table 40-3. 1.8V Voltage Regulator Characteristics
Symbol Parameter Conditions Min Typ Max Units
VVDDIN Supply Voltage 3.0 3.3 3.6 V
VVDDOUT Output Voltage IO = 20 mA 1.81 1.85 1.89 V
IVDDIN Current consumption After startup, no load 90 µA
After startup, Idle mode, no load 10 25 µA
TSTART Startup Time Cload = 2.2 µF, after VDDIN > 2.7V 150 µS
IOMaximum DC Output Current VDDIN = 3.3V 100 mA
IOMaximum DC Output Current VDDIN = 3.3V, in Idle Mode 1 mA
Table 40-4. Brownout Detector Characteristics
Symbol Parameter Conditions Min Typ Max Units
VBOT18- VDDCORE Threshold Level 1.65 1.68 1.71 V
VHYST18 VDDCORE Hysteresis VHYST18 = VBOT18+ - VBOT18- 50 65 mV
VBOT33- VDDFLASH Threshold Level 2.70 2.80 2.90 V
VHYST33 VDDFLASH Hysteresis VHYST33 = VBOT33+ - VBOT33- 70 120 mV
618 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
IDD Current Consumption BOD on (GPNVM0 bit activ e) 24 30 µA
BOD off (GPNVM0 bit inactiv e ) 1 µA
TSTART Startup Time 100 200 µs
Table 40-4. Brownout Detector Characteristics
Symbol Parameter Conditions Min Typ Max Units
Table 40-5. DC Flash Characteristics SAM7SE32
Symbol Parameter Conditions Min Max Units
ISB Standby current
@25°C
onto VDDCORE = 1.8V
onto VDDFLASH = 3.3V 3
25 µA
µA
@85°C
onto VDDCORE = 1.8V
onto VDDFLASH = 3.3V 5
125 µA
µA
ICC Active current
Random Read @ 30MHz
onto VDDCORE = 1.8V
onto VDDFLASH = 3.3V 3.4
0.4 mA
mA
Write
onto VDDCORE = 1.8V
onto VDDFLASH = 3.3V 400
2.2 µA
mA
Table 40-6. DC Flash Characteristics SAM7SE512/ 256
Symbol Parameter Conditions Min Max Units
ISB Standby current
@25°C
onto VDDCORE = 1.8V
onto VDDFLASH = 3.3V 10
40 µA
µA
@85°C
onto VDDCORE = 1.8V
onto VDDFLASH = 3.3V 20
120 µA
µA
ICC Active current
Random Read @ 30MHz (on e
bank for SAM7SE512)
onto VDDCORE = 1.8V
onto VDDFLASH = 3.3V 4.5
0.8 mA
mA
Write (one bank for
SAM7SE512)
onto VDDCORE = 1.8V
onto VDDFLASH = 3.3V
400
5.5 µA
mA
619
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.3 Po wer Consumption
• Typical power consumption of PLLs, Slow Clock and Main Oscillator.
• Power consumption of power supply in two different modes: Active and ultra Low-power.
• Power consumption by peripheral: calculated as the difference in current measurement after
having enabled then disabled the corresponding clock.
40.3.1 Power Consumption Versus Modes
The values in Table 40-7and Table 40-8 on page 620 are measured values of the power con-
sumption with operating conditions as follows:
•V
DDIO = VDDIN = VDDFLASH= 3.3V
•V
DDCORE = VDDPLL = 1.85V
•T
A = 25°C
• There is no consumption on the I/Os of the device
Figure 40-1. Measure Schematics:
1.8V
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDPLL
3.3V
VDDIO
VDDFLASH
AMP1
AMP2
620 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The figures shown below in Table 40-7 represent the power consumption typically measured on
the power supplies..
Notes: 1. “Flash is in standby mode”, means the Flash is not accessed at all.
2. Low power consumption figures stated abov e cannot be guaranteed when accessing the Flash
in Ultra Low Power mode. In order to meet given low power consumption figures, it is recom-
mended to either stop the processor or jump to SRAM.
40.3.2 Peripheral Power Consumption in Active Mode
Table 40-7. Power Consumption for Different Modes
Mode Conditions Consumption Unit
Active
(SAM7SE512/256/32)
Voltage regulator is on.
Brown Out Detector is activated.
Flash is read.
ARM Core clock is 48 MHz.
Analog-to-Digital Converter activated.
All peripheral clocks activated.
USB transceiver enabled.
onto AMP1
onto AMP2 31
29 mA
Ultra Low Power(2)
(SAM7SE512/256/32)
Voltage regulator is in Low-power mode.
Brown Out Detector is de-activated.
Flash is in standby mode.(1)
ARM Core in idle mode.
MCK @ 500 Hz.
Analog-to-Digital Converter de-activated.
All peripheral clocks de-activated.
USB transceiver disabled.
DDM and DDP pins must be left floating.
onto AMP1
onto AMP2 26
12 µA
Table 40-8. Power Consumption on VDDCORE(1)
Peripheral Consumptio n (Typ) Unit
PIO Controller 12
µA/MHz
USART 30
UDP 24
PWM 15
TWI 6
SPI 18
SSC 35
Timer Counter Channels 7
ARM7TDMI 170
System Peripherals (SAM7SE512/256/32) 265
621
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Note: 1. Note: VDDCORE = 1. 85V, TA = 25°C
40.4 Crystal Oscillators Characteristics
40.4.1 RC Osc ill at or Chara ct erist ics
Table 40-9. RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
1/(tCPRC) RC Oscillator Frequency VDDPLL = 1.65V 22 32 42 kHz
Duty Cycle 45 50 55 %
tST Startup Time VDDPLL = 1.65V 75 µs
IOSC Current Consumption After Startup Time 1.9 µA
622 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.4.2 Mai n Osc illa t or Chara cteris ti cs
Notes: 1. CS is the shunt capacitance.
2. RS = 100-200 Ω; CSHUNT = 2.0 - 2.5 pF; CM = 2 – 1.5 fF (typ, worst case) using 1 K ohm serial resistor on xout.
3. RS = 50-100 Ω; CSHUNT = 2.0 - 2.5 pF; CM = 4 - 3 fF (typ, worst case).
4. RS = 25-50 Ω; CSHUNT = 2.5 - 3.0 pF; CM = 7 -5 fF (typ, worst case).
5. RS = 20-50 Ω; CSHUNT = 3.2 - 4.0 pF; CM = 10 - 8 fF (typ, worst case).
6. CL and CLEXT ∅
Table 40-10. Main Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
1/(tCPMAIN) Crystal Oscillator Frequency 3 16 20 MHz
CL1, CL2 SAM7SE512/256
Internal Load Capacitance (CL1 = CL2)Integrated Load Capacitance
((XIN or XOUT)) 34 40 46 pF
CL1, CL2 SAM7SE32
Internal Load Capacitance (CL1 = CL2)Integrated Load Capacitance
(XIN or XOUT) 18 22 26 pF
CL (6) SAM7SE512/256
Equivalent Load Capacitance Integrated Load Capacitance
(XIN and XOUT in series) 17 20 23 pF
CL (6) SAM7SE32
Equivalent Load Capacitance Integrated Load Capacitance
(XIN and XOUT in series) 91113pF
Duty Cycle 30 50 70 %
tST Startup Time
VDDPLL = 1.2 to 2V
CS = 3 pF(1) 1/(tCPMAIN) = 3 MHz
CS = 7 pF(1) 1/(tCPMAIN) = 16 MHz
CS = 7 pF(1) 1/(tCPMAIN) = 20 MHz
14.5
1.4
1
ms
IDDST Standby Current Consumption Standby mode 1 µA
PON Drive le vel
@3 MHz
@8 MHz
@16 MHz
@20 MHz
15
30
50
50
µW
IDD ON Current dissipation
@3 MHz (2)
@8 MHz (3)
@16 MHz (4)
@20 MHz (5)
150
150
300
400
250
250
450
550
µA
CLEXT (6) Maximum external capa citor
on XIN and XOUT 10 pF
XIN XOUT
CLEXT
CL
CLEXT
AT91SAM7SE
623
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.4.3 Crystal Characteri st ic s
40.4.4 XIN Clock Characteristics
Note: 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1
in the CKGR_MOR register, see the Clock Generator Main Oscillator Register.
Figure 40-2. XIN Clock Timing
Table 40-11. Crystal Characteristics
Symbol Parameter Conditions Min Typ Max Unit
ESR Equivalent Series Resistor Rs
Fundamental @3 MHz
Fundamental @8 MHz
Fundamental @16 MHz
Fundamental @20 MHz
200
100
80
50
Ω
CMMotional capacitance 8fF
CSHUNT Shunt capacitance 7pF
Table 40-12. XIN Clock Electrical Characteristics
Symbol Parameter Conditions Min Max Units
1/(tCPXIN) XIN Clock F requency (1) 50.0 MHz
tCPXIN XIN Clock Period (1) 20.0 ns
tCHXIN XIN Clock High Half-period (1) 8.0 ns
tCLXIN XIN Clock Low Half-period (1) 8.0 ns
tCLCH Rise Time (1) 400 ns
tCHCL Fall Time (1) 400 ns
CIN XIN Input Capacitance (SAM7SE512/256) (1) 46 pF
CIN XIN Input Capacitance (SAM7SE32) (1) 26 pF
RIN XIN Pull-down Resistor (1) 500 kΩ
VXIN_IL VXIN Input Low-le vel Voltage (1) -0.3 0.3 x VDDPLL V
VXIN_IH VXIN Input High-level Voltage (1) 0.7 x VDDPLL 1.95 V
IDDBP Bypass Current Consumption (1) 15 µW/MHz
tCPXIN
tCPXIN
tCPXIN tCHXIN
tCLCH tCHCL
VXIN_IL
VXIN_IH
624 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.5 PLL Characteristics
Note: Startup time depends on PLL RC filter. A calculation tool is provided by Atmel.
Table 40-13. Phase Lock Loo p Chara ct er istic s
Symbol Parameter Conditions Min Typ Max Unit
FOUT Output Frequency Field OUT of CKGR_PLL is: 00 80 160 MHz
10 150 220 MHz
FIN Input Frequency 1 32 MHz
IPLL Current Consumption Active mode 4 mA
Standby mode 1 µA
625
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.6 USB Transceiver Characteristics
40.6.1 Electrical Characteristics
40.6.2 Switching Characteristics
Table 40-14. Electrical Parameters
Symbol Parameter Conditions Min Typ Max Unit
Input Levels
VIL Low Level 0.8 V
VIH High Level 2.0 V
VDI Diff e rential Input Sensitivity |(D+) - (D-)| 0.2 V
VCM Differential Input Commo n Mode
Range 0.8 2.5 V
CIN Transceiver capacitance Capacitance to ground on each line 9.18 pF
I Hi-Z State Data Line Leakage 0V < VIN < 3.3V -10 +10 µA
REXT Recommended Externa l USB
Series Resi stor In series with each USB pin with ±5% 27 Ω
Output Levels
VOL Low Level Output Measured with RL of 1.425 kOhm tied
to 3.6V 0.0 0.3 V
VOH High Level Output Measured with RL of 14.25 kOhm tied
to GND 2.8 3.6 V
VCRS Output Signal Crossover Voltage Measure conditions described in
Figure 40-3 1.3 2.0 V
Consumption
IVDDIO Current Consumption Transceiver enabled in input mode
DDP=1 and DDM=0 105 200 µA
IVDDCORE Current Consumption 80 150 µA
Pull-up Resistor
RPUI Bus Pull-up Resistor on
Upstream Port (idle bus) 0.900 1.575 kΩ
RPUA
Bus Pull-up Resisto r on
Upstream Port (upstream port
receiving) 1.425 3.090 kΩ
Table 40-15. In Full Speed
Symbol Parameter Conditions Min Typ Max Unit
tFR Transition Rise Time CLOAD = 50 pF 4 20 ns
tFE Transition Fall Time CLOAD = 50 pF 4 20 ns
tFRFM Rise/Fall time Matching 90 111.11 %
626 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 40-3. USB Data Signal Rise and Fall Times
10% 10%
90%
VCRS
tRtF
Differential
Data Lines
Rise Time Fall Time
Fosc = 6MHz/750kHz REXT=27 ohms
Cload
Buffer
(b)
(a)
627
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.7 ADC Characteristics
Notes: 1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles f or tr ack and hold acquisition time and 10 clock cycles for
conversion.
2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for
conversion.
The user can drive ADC input with impedance up to:
•Z
OUT ≤ (SHTIM -470) x 10 in 8-bit resolution mode
•Z
OUT ≤ (SHTIM -589) x 7.69 in 10-bit resolution mode
with SHTIM (Sample and Hold Time register) expressed in ns and ZOUT expressed in ohms.
Table 40-16. Channel Conversion Time and ADC Clock
Parameter Conditions Min Typ Max Units
ADC Clock Frequency 10-bit resolution mode 5 MHz
8-bit resolution mode 8
Startup Time Return from Idle Mode 20 µs
Track and Hold Acquisition Time 600 ns
Conversion Time ADC Cl ock = 5 MHz 2 µs
ADC Clock = 8 MHz 1.25
Throughput Rate ADC Clock = 5 MHz 384(1) kSPS
ADC Clock = 8 MHz 533(2)
Table 40-17. External Voltage Reference Input
Parameter Conditions Min Typ Max Units
ADVREF Input Voltage Range 2.6 VDDIN V
8-bit resolution mode 2.5
ADVREF Average Current On 13 samples with ADC Clock = 5 MHz 200 250 µA
Current Consumption on VDDIN 0.55 1 mA
Table 40-18. Analog Inputs
Parameter Min Typ Max Units
Input Voltage Range 0V
ADVREF
Input Leakage Current 1µA
Input Capacitance 12 14 pF
Table 40-19. Transfer Ch aracteristics
Parameter Conditions Min Typ Max Units
Resolution 10 Bit
Integral Non-linearity ±2 LSB
Differential Non- linearity No missing code ±1 LSB
Offset Error ±2 LSB
Gain Error ±2 LSB
Absolute Accuracy ±4 LSB
628 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
For more information on data converter terminology, please refer to the application note: Data
Converter Terminology, Atmel lit° 6022.
40.8 AC Characteristics
40.8.1 Master Clock Characteristics
40.8.2 I/O Characteristics
Criteria used to define the maximum frequency of the I/Os:
• output duty cycle (30%-7 0%)
• minimum output swing : 100mV to VDDIO - 100mV
• Addition of rising and falling time inferior to 75% of the per iod
Notes: 1. Pin Group 1 = SDCK
2. Pin Group 2 = PA4 to PA31, PB0 to PB31 and PC0-PC23
Table 40-20. Master Clock Waveform Parameters
Symbol Parameter Conditions Min Max Units
1/(tCPMCK) Master Clock Frequency VDDCORE = 1.8V 55 MHz
1/(tCPMCK) Master Clock Frequency VDDCORE = 1.65V 48 MHz
Table 40-21. I/O Characteristics
Symbol Parameter Conditions Min Max Units
FreqMaxI01 Pin Group 1 (1) frequency Load: 30 pF(4) 48.2 MHz
Load: 30 pF(5) 25 MHz
PulseminHI01 Pin Group 1 (1) High Level Pulse Width Load: 30 pF(4) 20 ns
Load: 30 pF(5) 40
PulseminLI01 Pin Group 1 (1) Low Level Pulse Width Load: 30 pF(4) 20 ns
Load: 30 pF(5) 40
FreqMaxI02 Pin Group 2 (2) frequency Load: 40 pF(4) 25 MHz
Load: 40 pF(5) 16 MHz
PulseminHI02 Pin Group 2 (2) High Level Pulse Width Load: 40 pF(4) 20 ns
Load: 40 pF(5) 31 ns
PulseminLI02 Pin Group 2 (2) Low Level Pulse Width Load: 40 pF(4) 20 ns
Load: 40 pF(5) 31 ns
FreqMaxI03 Pin Group 3 (3)frequency Load: 40 pF(4) 30 MHz
Load: 40 pF(5) 20 MHz
PulseminHI03 Pin Group 3 (3) High Level Pulse Width Load: 40 pF(4) 16.6 ns
Load: 40 pF(5) 31 ns
PulseminLI03 Pin Group 3 (3) Low Level Pulse Width Load: 40 pF(4) 16.6 ns
Load: 40 pF(5) 31 ns
629
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
3. Pin Group 3 = PA0 to PA3
4. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF
5. VVDDIO from 1.65V to 1.95V, maximum external capacitor = 40 pF
40.8.3 SPI Chara ct e ri st ic s
Figure 40-4. SPI Master Mode with (CPOL= NCPHA = 0) or (CPOL= NCPHA= 1)
Figure 40-5. SPI Master Mode with (CPOL = 0 and NCPHA=1) or (CPOL=1 and NCPHA= 0)
Figure 40-6. SPI Slave Mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)
SPCK
MISO
MOSI
SPI2
SPI0SPI1
SPCK
MISO
MOSI
SPI5
SPI3SPI4
SPCK
MISO
MOSI
SPI6
SPI7SPI8
630 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 40-7. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
Notes: 1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF.
2. 1.8V domain: VVDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF.
3. tCPMCK: Master Clock period in ns.
SPCK
MISO
MOSI
SPI9
SPI10 SPI11
Table 40-22. SAM7SE512/256 SPI Timings
Symbol Parameter Conditions Min Max Units
SPI0MISO Setup time before SPCK rises (master) 3.3V domain(1) 26 + (tCPMCK)/2(3) ns
1.8V domain(2) 34 + (tCPMCK)/2(3) ns
SPI1MISO Hold time after SPCK rises (master) 3.3V domain(1) 0ns
1.8V domain(2) 0ns
SPI2SPCK rising to MOSI Delay (master) 3.3V domain(1) 7ns
1.8V domain(2) 10 ns
SPI3MISO Setup time before SPCK falls (master) 3.3V domain(1) 26 + (tCPMCK)/2(3) ns
1.8V domain(2) 34 + (tCPMCK)/2(3) ns
SPI4MISO Hold time after SPCK falls (master) 3.3V domain(1) 0ns
1.8V domain(2) 0ns
SPI5SPCK falling to MOSI Delay (master) 3.3V domain(1) 7ns
1.8V domain(2) 10 ns
SPI6SPCK falling to MISO Delay (slave) 3.3V doma in(1) 22.5 ns
1.8V domain(2) 30.5 ns
SPI7MOSI Setup time before SPCK rises (slave) 3.3V domain(1) 1ns
1.8V domain(2) 2.5 ns
SPI8MOSI Hold time after SPCK rises (slave) 3.3V domain(1) 2ns
1.8V domain(2) 2ns
SPI9SPCK rising to MISO Delay (slave) 3.3V domain(1) 23 ns
1.8V domain(2) 28 ns
SPI10 MOSI Setup time before SPCK falls (slave) 3.3V domain(1) 1ns
1.8V domain(2) 1
SPI11 MOSI Hold time after SPCK falls (slave) 3.3V doma in(1) 2ns
1.8V domain(2) 2ns
631
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Notes: 1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF.
2. 1.8V domain: VVDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF.
3. tCPMCK: Master Clock period in ns.
Note that in SPI master mode the ATSAM7SE512/256/32 does not sample the data (MISO) on
the opposite edge where data clocks out (MOSI) but the same edge is used as shown in Figure
40-4 and Figure 40-5.
SAM7SE32 SPI Timings
Symbol Parameter Conditions Min Max Units
SPI0MISO Setup time before SPCK rises (master) 3.3V domain(1) 26 + (tCPMCK)/2(3) ns
1.8V domain(2) 45 + (tCPMCK)/2(3) ns
SPI1MISO Hold time after SPCK rises (master) 3.3V domain(1) 0ns
1.8V domain(2) 0ns
SPI2SPCK rising to MOSI Delay (master) 3.3V domain(1) 4ns
1.8V domain(2) 12 ns
SPI3MISO Setup time before SPCK falls (master) 3.3V domain(1) 26 + (tCPMCK)/2(3) ns
1.8V domain(2) 34 + (tCPMCK)/2(3) ns
SPI4MISO Hold time after SPCK falls (master) 3.3V domain(1) 0ns
1.8V domain(2) 0ns
SPI5SPCK falling to MOSI Delay (master) 3.3V domain(1) 4ns
1.8V domain(2) 6ns
SPI6SPCK falling to MISO Delay (slave) 3.3V doma in(1) 23.7 ns
1.8V domain(2) 42 ns
SPI7MOSI Setup time before SPCK rises (slave) 3.3V domain(1) 1ns
1.8V domain(2) 1ns
SPI8MOSI Hold time after SPCK rises (slave) 3.3V domain(1) 3ns
1.8V domain(2) 3ns
SPI9SPCK rising to MISO Delay (slave) 3.3V domain(1) 24 ns
1.8V domain(2) 40 ns
SPI10 MOSI Setup time before SPCK falls (slave) 3.3V domain(1) 1ns
1.8V domain(2) 1
SPI11 MOSI Hold time after SPCK falls (slave) 3.3V doma in(1) 3ns
1.8V domain(2) 3ns
632 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.8.4 SMC Signals These timings are given for a maximum 10 pF load on SDCK and a maximum 50 pF load on the
databus.
Note: 1. n = Number of standard Wait States inserted.
Note: 1. n = Number of standard Wait States inserted.
.
Table 40-23. SAM7SE512/256 General-purpose SMC Signals
Symbol Parameter Conditions Min Max Units
SMC7NCS Minimum Pulse Width
(Address to Chip Select Setup) 3.3V domain (n + 1) x tCPMCK - 2.5 (1) ns
1.8V domain (n + 1) x tCPMCK - 3.0 (1) ns
SMC8NWAIT Minimum Pulse Width tCPMCK ns
Table 40-24. SAM7SE32 General-purpose SMC Signals
Symbol Parameter Conditions Min Max Units
SMC7NCS Minimum Pulse Width
(Address to Chip Select Setup) 3.3V domain (n + 1) x tCPMCK - 2.5 (1) ns
1.8V domain (n + 1) x tCPMCK - 5.0 (1) ns
SMC8NWAIT Minimum Pulse Width tCPMCK ns
Table 40-25. SAM7SE512/256 SMC Write Signals
Symbol Parameter Conditions Min Max Units
SMC15 NWR High to NUB Change (3) 3.3V domain 7.0 ns
1.8V domain 9.5 ns
SMC16 NWR High to NLB/A0 Change (3) 3.3V domain 7.5 ns
1.8V domain 10 ns
SMC17 NWR High to A1 - A22 Change(3) 3.3V domain 8 ns
1.8V domain 8.5 ns
SMC18 NWR High to Chip Select Inactive (3) 3.3V domain 7.0 ns
1.8V domain 9.0 ns
SMC19 Data Out Valid before NWR High
(No W a it States) (3) 3.3V domain 0.5 * tCPMCK - 0.5 ns
1.8V domain 0.5 * tCPMCK - 1 ns
SMC20 Data Out Valid before NWR High
(Wait States) (3) 3.3V domain n x tCPMCK - 0.5(1) ns
1.8V domain n x tCPMCK - 1(1) ns
SMC21 Data Out Valid after NWR High
(No W a it States)(3)) 3.3V domain 0.5 * tCPMCK - 5.7 ns
1.8V domain 0.5 * tCPMCK - 8 ns
SMC22 Data Out Valid after NWR High
(Wait States without Hold Cycles) (3) 3.3V domain 0.5 * tCPMCK - 5.2 ns
1.8V domain 0.5 * tCPMCK - 8 ns
SMC23 Data Out Valid after NWR High
(Wait States with Hold Cycles) (3) 3.3V domain h x tCPMCK - 5.7 (2) ns
1.8V domain h x tCPMCK - 8.0 (2) ns
633
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Notes: 1. n = Number of standard Wait States inserted.
2. h = Number of Hold Cycles inserted.
3. Not applicable when Address to Chip Select Setup Cycles are inserted.
.
Notes: 1. n = Number of standard Wait States inserted.
2. h = Number of Hold Cycles inserted.
3. Not applicable when Address to Chip Select Setup Cycles are inserted.
SMC26 NWR Minimum Pulse Width
(No W a it States) (3) 3.3V domain 0.5 * tCPMCK - 1 ns
1.8V domain 0.5 * tCPMCK - 1.5 ns
SMC27 NWR Minimum Pulse Width
(Wait States) (3) 3.3V domain n x tCPMCK - 1.5(1) ns
1.8V domain n x tCPMCK - 1.5(1) ns
Table 40-25. SAM7SE512/256 SMC Write Signals (Continued)
Symbol Parameter Conditions Min Max Units
Table 40-26. SAM7SE32 SMC Write Signals
Symbol Parameter Conditions Min Max Units
SMC15 NWR High to NUB Change (3) 3.3V domain 6.0 ns
1.8V domain 9.0 ns
SMC16 NWR High to NLB/A0 Change (3) 3.3V domain 6.0 ns
1.8V domain 9.0 ns
SMC17 NWR High to A1 - A22 Change(3) 3.3V domain 6.0 ns
1.8V domain 9.0 ns
SMC18 NWR High to Chip Select Inactive (3) 3.3V domain 5.5 ns
1.8V domain 9.0 ns
SMC19 Data Out Valid before NWR High
(No W a it States) (3) 3.3V domain 0.5 * tCPMCK - 3.5 ns
1.8V domain 0.5 * tCPMCK - 6.0 ns
SMC20 Data Out Valid before NWR High
(Wait States) (3) 3.3V domain n x tCPMCK - 3.5(1) ns
1.8V domain n x tCPMCK - 6.0(1) ns
SMC21 Data Out Valid after NWR High
(No W a it States)(3)) 3.3V domain 0.5 * tCPMCK - 5.5 ns
1.8V domain 0.5 * tCPMCK - 12 ns
SMC22 Data Out Valid after NWR High
(Wait States without Hold Cycles) (3) 3.3V domain 0.5 * tCPMCK - 5.2 ns
1.8V domain 0.5 * tCPMCK - 8 ns
SMC23 Data Out Valid after NWR High
(Wait States with Hold Cycles) (3) 3.3V domain h x tCPMCK - 6.0(2) ns
1.8V domain h x tCPMCK - 12(2) ns
SMC26 NWR Minimum Pulse Width
(No W a it States) (3) 3.3V domain 0.5 * tCPMCK - 2.0 ns
1.8V domain 0.5 * tCPMCK - 6.5 ns
SMC27 NWR Minimum Pulse Width
(Wait States) (3) 3.3V domain n x tCPMCK - 2.5(1) ns
1.8V domain n x tCPMCK - 7.0(1) ns
634 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
3. n = Number of standard Wait States inserted.
4. h = Number of Hold Cycles inserted.
5. Not applicable when Address to Chip Select Setup Cycles are inserted.
Table 40-27. SAM7SE512/256 SMC Read Signals
Symbol Parameter Conditions Min Max Units
SMC35 NRD High to NUB Change 3.3V domain (h x tCPMCK) - 2(4) (h x tCPMCK)+ 1 (4) ns
1.8V domain (h x tCPMCK) - 2(4) (h x tCPMCK)+ 1 (4) ns
SMC36 NRD High to NLB/A0 Change 3.3V domain (h x tCPMCK) - 1.5(4) (h x tCPMCK)+ 1.5 (4) ns
1.8V domain (h x tCPMCK) - 1.5(4) (h x tCPMCK)+ 1 (4) ns
SMC37 NRD High to A1-A22 Change 3.3V domain (h x tCPMCK) - 2(4) (h x tCPMCK)+ 2 (4) ns
1.8V domain (h x tCPMCK) - 2(4) (h x tCPMCK)+ 3.5 (4) ns
SMC38 NRD High to Chip Select Inactive 3.3V domain (h x tCPMCK) - 3 (4) (h x tCPMCK)+ 1(4) ns
1.8V domain (h x tCPMCK) - 3.5 (4) (h x tCPMCK)+ 2(4) ns
SMC40 Data Setup before NRD High 3.3V domain 22.2 ns
1.8V domain 35 ns
SMC41 Data Hold after NRD High 3.3V domain 0 ns
1.8V domain 0 ns
SMC42 Data Setup before NCS High 3.3V domain 23.2 ns
1.8V domain 37 ns
SMC43 Data Hold after NCS High 3.3V domai n 0 ns
1.8V domain 0 ns
SMC44 NRD Minimum Pulse Width (1) (5) 3.3V domain (n +1) x tCPMCK - 1 (3) ns
1.8V domain (n +1) x tCPMCK - 1.5 (3) ns
SMC45 NRD Minimum Pulse Width (2) (5) 3.3V domain (2 x n +1) x 0.5 x tCPMCK -
1(3) ns
1.8V domain (2 x n +1) x 0.5 x tCPMCK -
1(3) ns
Table 40-28. SAM7SE32 SMC Read Signals
Symbol Parameter Conditions Min Max Units
SMC35 NRD High to NUB Change 3.3V domain (h x tCPMCK) - 2(4) (h x tCPMCK)+ 1.5(4) ns
1.8V domain (h x tCPMCK) - 2(4) (h x tCPMCK)+ 7(4) ns
SMC36 NRD High to NLB/A0 Change 3.3V domain (h x tCPMCK) - 2(4) (h x tCPMCK)+ 1.5(4) ns
1.8V domain (h x tCPMCK) - 1.5(4) (h x tCPMCK)+ 6.5(4) ns
SMC37 NRD High to A1-A22 Change 3.3V domain (h x tCPMCK) - 3(4) (h x tCPMCK)+ 3(4) ns
1.8V domain (h x tCPMCK) - 3(4) (h x tCPMCK)+ 8(4) ns
SMC38 NRD High to Chip Select
Inactive 3.3V domain (h x tCPMCK) - 2.5(4) (h x tCPMCK)+ 2(4) ns
1.8V domain (h x tCPMCK) - 3(4) (h x tCPMCK)+ 2(4) ns
635
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
3. n = Number of standard Wait States inserted.
4. h = Number of Hold Cycles inserted.
5. Not applicable when Address to Chip Select Setup Cycles are inserted.
SMC40 Data Setup before NRD High 3.3V domain 23.2 ns
1.8V domain 37 ns
SMC41 Data Hold after NRD High 3.3V domain -0 ns
1.8V domain -0 ns
SMC42 Data Setup before NCS High 3.3V domain 25.2 ns
1.8V domain 39 ns
SMC43 Data Hold after NCS High 3.3V domain 0 ns
1.8V domain 0 ns
SMC44 NRD Minimum Pulse Width (1) (5) 3.3V domain (n +1) x tCPMCK - 2 (3) ns
1.8V domain (n +1) x tCPMCK - 6 (3) ns
SMC45 NRD Minimum Pulse Width (2) (5) 3.3V domain (2 x n +1) x 0.5 x tCPMCK - 2(3) ns
1.8V domain (2 x n +1) x 0.5 x tCPMCK -
6.5(3) ns
Table 40-28. SAM7SE32 SMC Read Signals (Continued)
Symbol Parameter Conditions Min Max Units
636 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 40-8. SMC Signals in Memor y Interface Mode
Notes: 1. Early Read Protocol
2. Standard Read Protocol with or without Setup and Hold Cycles.
NRD(1)
NRD(2)
NCS
NWAIT
A1 - A22
D0 - D15
Read
NWR
D0 - D15
to Write
NUB/NLB/A0
SMC40 SMC41
SMC44
SMC45
SMC19 SMC21
SMC
18
SMC
17
SMC
15
SMC
16
SMC26
SMC
38
SMC
37
SMC
35
SMC
36
SMC8
SMC35
SMC36
SMC37
SMC38
SMC40 SMC41 SMC41
SMC44
SMC45
SMC27
SMC22
SMC20
SMC35
SMC36
SMC37
SMC38
SMC40
SMC45
SMC20 SMC23
SMC27
637
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 40-9. SM Signals in LCD Interface Mode
Notes: 1. Standard Read Protocol only.
2. With Standard Wait States insert ed only.
NRD(1)
NCS
NWAIT
A1 - A22
D0 - D15
Read
NWR(2)
D0 - D15
to Write
NUB/NLB/A0
SMC8
SMC7SMC7
SMC
35
SMC
36
SMC
37
SMC39
SMC42 SMC43
SMC46
SMC24 SMC25
SMC28
638 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.8.5 SDRAMC Signals
These timings are given for a maximum 30 pF load on SDCK and a maximum 50 pF load on the databus.
Table 40-29. SDRAMC Clock Signal
Symbol Parameter
Min Max
Units1.8V Supply 3.3V Supply 1.8V
Supply 3.3V Supply
1/(tCPSDCK) SDRAM Controller Clock Frequency 24 48.2 MHz
tCPSDCK SDRAM Controller Clock Period 41.7 20.7 ns
Table 40-30. SAM7SE512/256 SDRAMC Signals
Symbol Parameter
Min Max
Units1.8V Supply 3.3V Supply 1.8V Supply 3.3V Supply
SDRAMC1SDCKE High before SDCK Rising Edge 17.5 12 ns
SDRAMC2SDCKE Low after SDCK Rising Edge 22 9.5 ns
SDRAMC3SDCKE Low before SDCK Rising Edge 11 10 ns
SDRAMC4SDCKE High after SDCK Rising Edge 20.5 8 ns
SDRAMC5SDCS Low before SDCK Rising Edge 11 10.5 ns
SDRAMC6SDCS High after SDCK Rising Edge 20.5 7.5 ns
SDRAMC7RAS Low before SDCK Rising Edge 10.5 10 ns
SDRAMC8RAS High after SDCK Rising Edge 20.5 8 ns
SDRAMC9SDA10 Change before SDCK Rising Edge 10.5 10 ns
SDRAMC10 SDA10 Change after SDCK Rising Edge 20.5 8 ns
SDRAMC11 Address Change before SDCK Rising Edge 8.5 7.5 ns
SDRAMC12 Address Change after SDCK Rising Edge 20 9 ns
SDRAMC13 Bank Change before SDCK Rising Edge 9 8 ns
SDRAMC14 Bank Change after SDCK Rising Edge 20.5 9 ns
SDRAMC15 CAS Low before SDCK Rising Edge 10.5 10 ns
SDRAMC16 CAS High after SDCK Rising Edge 20.5 8 ns
SDRAMC17 DQM Change before SDCK Rising Edge 10 9.5 ns
SDRAMC18 DQM Change after SDCK Rising Edge 20.5 9 ns
SDRAMC19 D0-D15 in Setup before SDCK Rising Edge 16 12.5 ns
SDRAMC20 D0-D15 in Hold after SDCK Rising Edge 3 2 ns
SDRAMC21 D16-D31 in Setup before SDCK Rising Edge 16 12.5 ns
SDRAMC22 D16-D31 in Hold after SDCK Rising Edge 3 2 ns
SDRAMC23 SDWE Low before SDCK Rising Edge 10.5 10 n s
SDRAMC24 SDWE High after SDCK Rising Edge 20.5 8 ns
SDRAMC25 D0-D15 Out Valid before SDCK Rising Edge 6.5 5.5 ns
SDRAMC26 D0-D15 Out Valid after SDCK Rising Edge 17 4.5 ns
SDRAMC27 D16-D31 Out Valid before SDCK Rising Edge 6.5 5.5 ns
SDRAMC28 D16-D31 Out Valid after SDCK Rising Edge 17 4.5 ns
639
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Table 40-31. SAM7SE32 SDRAMC Signals
Symbol Parameter
Min Max
Units1.8V Supply 3.3V Supply 1.8V Supply 3.3V Supply
SDRAMC1SDCKE High before SDCK Rising Edge 11.5 6.5 ns
SDRAMC2SDCKE Low after SDCK Rising Edge 23.5 11.5 ns
SDRAMC3SDCKE Lo w be fore SDCK Rising Edge 10.5 5.5 ns
SDRAMC4SDCKE High after SDCK Rising Edge 22.5 11 ns
SDRAMC5SDCS Low before SDCK Rising Edge 11.5 7.5 n s
SDRAMC6SDCS High after SDCK Rising Edge 22 10.5 ns
SDRAMC7RAS Low before SDCK Rising Edge 12.5 8 ns
SDRAMC8RAS High after SDCK Rising Edge 22 10 ns
SDRAMC9SDA10 Change before SDCK Rising Edge 12.5 8 ns
SDRAMC10 SDA10 Change after SDCK Rising Edge 22 10 ns
SDRAMC11 Address Change before SDCK Rising Edge 10 5 ns
SDRAMC12 Address Change after SDCK Rising Edge 22 10.5 ns
SDRAMC13 Bank Change before SDCK Rising Edge 9.5 4.5 ns
SDRAMC14 Bank Change after SDCK Rising Edge 22.5 10.5 ns
SDRAMC15 CAS Low before SDCK Rising Edge 12 7 ns
SDRAMC16 CAS High after SDCK Rising Edge 22 10.5 ns
SDRAMC17 DQM Change before SDCK Rising Edge 8.5 4.5 ns
SDRAMC18 DQM Change after SDCK Rising Edge 22 10.5 ns
SDRAMC19 D0-D15 in Setup before SDCK Rising Edge 8.5 8 .5 ns
SDRAMC20 D0-D15 in Hold after SDCK Rising Edge 2 1 ns
SDRAMC21 D16-D31 in Setup before SDCK Rising
Edge 8.5 8.5 ns
SDRAMC22 D16-D31 in Hold after SDCK Rising Edge 2 1 ns
SDRAMC23 SDWE Low before SDCK Rising Edge 12 7.5 ns
SDRAMC24 SDWE High after SDCK Rising Edge 22 10.5 ns
SDRAMC25 D0-D15 Out Valid bef ore SDCK Rising Edge 6.5 2 ns
SDRAMC26 D0-D15 Out Valid after SDCK Rising Edge 20 9 ns
SDRAMC27 D16-D31 Out Va lid before SDCK Rising
Edge 6.5 2 ns
SDRAMC28 D16-D31 Out Valid after SDCK Rising Edge 20 9 ns
640 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 40-10. SDRAMC Signals
RAS
A0 - A9,
A11 - A13
D0 - D15
Read
SDCK
SDA10
D0 - D15
to Write
SDRAMC1
SDCKE
SDRAMC2SDRAMC3SDRAMC4
SDCS
SDRAMC5SDRAMC6SDRAMC5SDRAMC6SDRAMC5SDRAMC6
SDRAMC7SDRAMC8
CAS
SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16
SDWE
SDRAMC23 SDRAMC24
SDRAMC9SDRAMC10
SDRAMC9SDRAMC10
SDRAMC9SDRAMC10
SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12
SDRAMC11 SDRAMC12
BA0/BA1
SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14
SDRAMC17 SDRAMC18
SDRAMC17 SDRAMC18
DQM0 -
DQM3
SDRAMC19 SDRAMC20
D16 - D31
Read
SDRAMC21 SDRAMC22
SDRAMC25 SDRAMC26
D16 - D31
to Write
SDRAMC27 SDRAMC28
641
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.8.6 Embedded Flash Characteristics
The maximum operating frequency is given in Table 40-32 and Table 40-33 but is limited by the Embedded Flash access
time when the processor is fetch ing code out of it. Table 40-32 an d Table 40-33 give the device max imum operating fre-
quency depending on the FWS field of the MC_FMR register. This field defines the number of wait states required to
access the Embedded Flash Memory.
Notes: 1. FWS = Fl ash Wait States
2. It is not necessary to use 3 wait states because the Flash can operate at maximum frequency with only 2 wait states.
Notes: 1. FWS = Fl ash Wait States
2. It is not necessary to use 2 or 3 wait states because the Flash can operate at maximum frequency with on ly 1 wait state.
Table 40-32. Embedded Flash Wait States (VDDCORE = 1.65V)
FWS(1) Read Operations Maximum Operating Frequency (MHz)
0 1 cycle 25
1 2 cycles 44
2 3 cycles 48.2
3(2) 4 cycles 48.2
Table 40-33. Embedded Flash Wait States (VDDCORE = 1.8V)
FWS(1) Read Operations Maximum Operating Frequency (MHz)
0 1 cycle 30
1 2 cycles 55
2(2) 3 cycles 55
3(2) 4 cycles 55
Table 40-34. AC Flash Characteristics
Parameter Conditions Min Max Units
Program Cycle Time per page including auto-erase 6 ms
per page without auto-erase 3 m s
Full Chip Erase 15 ms
642 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.8.7 JTAG/ICE Timings
40.8.7.1 ICE Interface Signals
Note: 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF.
Figure 40-11. ICE Interface Signals
Table 40-35. ICE Interface Timing Specification
Symbol Parameter Conditions Min Max Units
ICE0TCK Low Half-period (1) 51 ns
ICE1TCK High Half-period (1) 51 ns
ICE2TCK Period (1) 102 ns
ICE3TDI, TMS, Setup before TCK High (1) 0ns
ICE4TDI, TMS, Hold after TCK High (1) 3ns
ICE5TDO Hold Time (1) 13 ns
ICE6TCK Low to TDO Valid (1) 20 ns
TCK
ICE
3
ICE
4
ICE
6
TMS/TDI
TDO
ICE
5
ICE
1
ICE
2
ICE
0
643
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
40.8.7.2 JTAG Interface Signals
Note: 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF.
Table 40-36. JTAG Interface Timing specification
Symbol Parameter Conditions Min Max Units
JTAG0TCK Low Half-period (1) 6.5 ns
JTAG1TCK High Half-period (1) 5.5 ns
JTAG2TCK Period (1) 12 ns
JTAG3TDI, TMS Setup before TCK High (1) 2ns
JTAG4TDI, TMS Hold after TCK High (1) 3ns
JTAG5TDO Hold Time (1) 4ns
JTAG6TCK Low to TDO Valid (1) 16 ns
JTAG7Device Inputs Setup Time (1) 0ns
JTAG8Device Inputs Hold Time (1) 3ns
JTAG9Device Outputs Hold Time (1) 6ns
JTAG10 TCK to Device Outputs Valid (1) 18 ns
644 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 40-12. JTAG Interface Signals
TCK
JTAG9
TMS/TDI
TDO
Device
Outputs
JTAG5
JTAG4
JTAG3
JTAG0JTAG1
JTAG2
JTAG10
Device
Inputs
JTAG8
JTAG7
JTAG6
645
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
41. SAM7SE512/256/32 Mechanical Characteristics
41.1 Package Drawings
Figure 41-1. LQFP128 Package Drawing
This package respects the recommendations of the NEMI User Group.
Table 41-1. Device and LQFP Package Maximum Weight
SAM7SE512/256/32 800 mg
Table 41-2. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification e3
Table 41-3. LQFP Package Characteristics
Moisture Sensitivity Level 3
646 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Figure 41-2. 144-ball LFBGA Package Drawing
This package respects the recommendations of the NEMI User Group.
All dimensions are in mm
Table 41-4. Device and LFBGA Package Maximum Weight
SAM7SE512/256/32 mg
Table 41-5. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification e1
Table 41-6. LFBGA Package Characteristics
Moisture Sensitivity Level 3
647
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
41.2 Soldering Pr ofile
Table 41-7 gives the recommended soldering profile from J-STD-020C.
Note: The package is certified to be backward compatible with Pb/Sn soldering profile.
A maximum of three reflow passes is allowed per component.
41.3 Marking All devices are marked with the Atmel logo and the ordering code.
Additional marking has the following format:
where
•“YY”: manufactory year
• “WW”: manufactory week
• “V”: revision
• “XXXXXXXXX”: lot number
Table 41-7. Soldering Profile
Profile Feature Green Package
Average Ramp-up Rate (217°C to Peak) 3⋅C/sec. max.
Preheat Temperature 175°C ±25°C 180 sec. max.
Temperature Maintain ed Above 217°C 60 sec. to 150 sec.
Time within 5⋅C of Actual P eak Temperature 20 sec. to 40 sec.
Peak Temperature Range 260⋅C
Ramp-down Rate 6⋅C/sec. max.
Time 25⋅C to Peak Te mperature 8 min. max.
YYWW V
XXXXXXXXX ARM
648 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
42. SAM7SE512/256/32 Ordering Information
Table 42-1. Ordering Information
Ordering Code MRL Package Package Type Temperature
Operating Range
AT91SAM7SE512B-AU B LQFP128 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE256B-AU B LQFP128 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE32B-AU B LQFP128 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE512B-CU B LFBGA144 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE256B-CU B LFBGA144 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE32B-CU B LFBGA144 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE512-AU A LQFP128 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE256-AU A LQFP128 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE32-AU A LQFP128 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE512-CU A LFBGA144 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE256-CU A LFBGA144 Green Industrial
(-40⋅C to 85⋅C)
AT91SAM7SE32-CU A LFBGA144 Green Industrial
(-40⋅C to 85⋅C)
649
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43. SAM7SE512/256/32 Errata
43.1 Errata Summary by Product and Revision or Manufacturing Number
Table 43-1. Errata Summary Ta ble
Part
AT91SAM7SE
Product Revision
or Manufacturing Number
Errata
SAM7SE512/256/32 rev A
SAM7SE512/256 rev B
SAM7SE32 rev B
ADC DRDY Bit Cleared XXX
ADC DRDY not Cleared on Disable X
ADC DRDY Possibly Skipped due to CDR Read X
ADC Possible Skip on DRDY when Disabling a Channel X
ADC GOVRE Bit is not Updated XXX
ADC GOVRE Bit is Not Set when Reading CDR X
ADC GOVRE Bit is Not Set when Disabling a Channel X
ADC OVRE Flag Behavior XXX
ADC EOC Set although Channel Disabled X
ADC Spurious Clear of EOC Flag X
ADC Sleep Mode XXX
EFC Embedded Flash Access Time X
FLASH Power consumption with data read access with multiple load of two
words XXX
PWM Update when PWM_CCNTx = 0 or 1 XXX
PWM Update when PWM_CPRDx = 0 XXX
PWM Counter Start Value XXX
PWM Behavior of CHIDx Status Bits in the PWM_SR Register X
RTT Possible Event Loss when Reading RTT_SR X
SDRAMC PDC buffer in 16-bit SDRAM while the Core Accesses SDRAM X
SPI Software Reset Must be Written Twice X
SPI Baudrate Set to 1 X
SPI Bad Serial Clock Generation on 2nd Chip Select XXX
SSC Periodic Transmission Limitations in Master Mode X
SSC Transmitter Limitations in Slave Mode XXX
SSC Transmitter Limitations in Slave Mode X
SSC Last RK Clock Cycle when RK Outputs a Clock during Data Transfer XXX
650 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
SSC First RK Clock Cycle when RK Outputs a Clock during Data Transfer XXX
TWI Switching from Slave to Master Mode X
USART CTS in Hardware Handshaking X
USART Two Characters Sent with Hardware Handshaking X
USART RXBRK Flag Error in Asynchronous Mode X
USART DCD is Active High instead of Low X
Table 43-1. Errata Summary Table (Continued)
Part
AT91SAM7SE
Product Revision
or Manufacturing Number
Errata
SAM7SE512/256/32 rev A
SAM7SE512/256 rev B
SAM7SE32 rev B
651
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.2 SAM7SE512/256/32 Errata - Rev. A Parts
Refer to Section 41.3 ”Ma rk ing ” .
Notes: 1. AT91SAM7SE512 Revision A chip ID is 0x272A 0A40.
2. AT91SAM7SE256 Revision A chip ID is 0x272A 0940.
3. AT91SAM7SE32 Revision A chip ID is 0x2728 0340.
43.2.1 Analog-to-Digital Converter (ADC)
43.2.1.1 ADC: DRDY Bit Cleared
The DRDY Flag sh ould b e clea red on ly af t er a r ead o f ADC_LCDR (Last Conver ted Da ta Regis-
ter). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY
flag.
Problem Fix/Workaround
None.
43.2.1.2 ADC: DRDY not Cleared on Disable
When reading LCDR at the same instant as an end of conversion, with DRDY already active,
DRDY is kept active regardless of the enable status of the current channel. This sets DRDY,
whereas new data is not sto re d.
Problem Fix/Workaround
None.
43.2.1.3 ADC: DRDY Possibly Skipped due to CDR Read
Reading CDR for channel "y" at the same instant as an end of conversion on channel "x" with
EOC[x] already active, leads to skipping to set the DRDY flag if channel "x" is en abled.
Problem Fix/Workaround
Use of DRDY functionality with access to CDR registers should be avoided.
43.2.1.4 ADC: Possible Skip on DRDY when Disabling a Channel
DRDY does not rise when disabling channel "y" at the same time as an end of "x" channel con-
version, although data is stored into CDRx and LCDR.
Problem Fix/Workaround
None.
43.2.1.5 ADC: GOVRE Bit is Not Updated
Read of the St atus Register at the same instant as an end of conve rsion leads to skip ping the
update of the GOVRE (general overrun) flag. GOVRE is neither reset nor set.
For example, if reading the status while an end of conversion is occurring and:
1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun
condition but the GOVRE flag is not reset.
2. GOVRE is inactive but DRDY is active, does correspond to a new general overrun con-
dition but the GOVRE flag is not set.
Problem Fix/Workaround
None.
652 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.2.1.6 ADC: GOVRE Bit is not Set when Reading CDR
When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on
channel "x" with the following conditions:
• EOC[x] already active,
• DRDY already active,
• GOVRE inactive,
• previous data stored in LCDR being neithe r data from ch an nel "y", nor dat a fro m channel "x".
GOVRE should be set but is not.
Problem Fix/Workaround
None.
43.2.1.7 ADC: GOVRE Bit is not Set when Disabling a Channel
When disabling channel "y" at the same instant as an end of conversion on channel "x", EOC[x]
and DRDY being already active, GOVRE does not rise.
Note: OVRE[x] rises as expected.
Problem Fix/Workaround
None.
43.2.1.8 ADC: OVRE Flag Behavior
When the OVRE flag (on channel i) has been set but the related EOC status (of channel i) has
been cleared (by a r ead of CDRi o r LCDR), read ing th e Status re gister at th e same insta nt as an
end of conversion (causing the set of EOC status on channel i), does not lead to a reset of the
OVRE flag (on channel i) as exp ected.
Problem Fix/Workaround
None.
43.2.1.9 ADC: EOC Set although Channel Disabled
If a channel is disabled while a conversion is running and if a read of CDR is performed at the
same time as an end of conversion of any channel, the EOC of the channel with the conversion
running may ri se (whereas it has been disabled).
Problem Fix/Workaround
Do not take into account the EOC of a disabled channel
43.2.1.10 ADC: Spurious Clear of EOC Flag
If "x" and "y" are two successively converted channels and "z" is yet another enabled channel
("z" being neither "x" nor "y"), reading CDR on channel "z" at the same instant as an end of con-
version on channel "y" automatically clears EOC[x] instead of EOC[z].
Problem Fix/Workaround
None.
43.2.1.11 ADC: Sleep Mode
If Sleep mode is activated while there is no activity (no co nversion is being performed), it will
take effect only after a conversion occurs.
653
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Problem Fix/Workaround
To activate sleep mode as soon as possible, it is recommended to write successively, ADC
Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digi-
tal conversion, put ADC into slee p mode at the end of this conversion.
43.2.2 Flash Memory
43.2.2.1 Flash: Power Consumption with data read access with multiple load of two word s
When no Wait State (FWS = 0) is programmed and when data read access is performed with a
multiple load of two words, the internal Flash may stay in read mode.
It implies a potential increase of power consumption on VDDCORE (around 2 mA). Note that it
does not concern the program execution; thus, no issue is present when the program is fetching
out of Flash.
Problem Fix/Workaround
2 workaroun ds are po ssible:
• Add one Wait State when performing these data read accesses (FWS =1)
• After the m ultiple load, perform a single read data access to an address different from the
previous address accesses .
654 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.2.3 Pulse Width Modulation Controller (PWM)
43.2.3.1 PWM: Update when PWM_CCNTx = 0 or 1
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Problem Fix/Workaround
Check the Channel Cou nter Register before writing the Channel Update Register.
43.2.3.2 PWM: Update when PWM_CPRDx = 0
When the Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround
Do not write 0 in the Channel Period Register.
43.2.3.3 PWM: Counter Start Value
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter
starts at 1.
Problem Fix/Workaround
None.
43.2.3.4 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
There is an erratic behavior o f the CHIDx status bit in the PWM_SR Regist er. When a chan nel is
disabled by writing in the PWM_DIS Register just after enabling it (before completion of a Clock
Period of the clock selected for the channel), the PWM line is internally disabled but the CHIDx
status bit in the PWM_SR stays at 1.
Problem Fix/Workaround
Do not disable a channel bef ore completion of one period of the selected clock.
43.2.4 Real-Time Timer (RTT)
43.2.4.1 RTT: Possible Event Loss when Reading RTT_SR
If an event (RTTINC or ALMS) occurs within the same slow clock cycle when RTT_SR is read,
the corresponding bit might be cleared. This might lead to the loss of this event.
Problem Fix/Workaround
The software must handle RTT event as interrupt and should not poll RTT_SR.
43.2.5 SDRAM Controller (SDRAMC)
43.2.5.1 SDRAMC: PDC Buffer in 16-bit SDRAM while the Core Accesses SDRAM
When the SAM7SE interfaces with 16-bit SDRAM memory and the processor accesses the
SDRAM, either for instruction fetch or da ta read/write, the data transferred by the PDC fro m
SDRAM buffers to the peripherals might be corrupted. Transfers from peripherals to SDRAM
buffers are no t affected.
Problem Fix/Workaround
Map the transmit PDC buffers in internal SRAM or Flash.
655
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.2.6 Serial Peripheral Interface (SPI)
43.2.6.1 SPI: Baudrate Set to 1
When the Baudrate is set to 1 (so , the serial clock frequ ency equals th e master clock), a nd when
the BITS field (number of bits to be transmitted) in SPI_CSRx equals an odd value (in this case
9, 11, 13 or 15), an additional pulse will be generated on SPCK.
It does not occur when the BITS field is equal to 8, 10, 12, 14 or 16 and the Baudrate is equal
to 1.
Problem Fix/Workaround
None.
43.2.6.2 SPI: Bad Serial Clock Generation on 2nd Chip Select
There is a bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and
NCPHA = 0.
This occurs using SPI with the following conditions:
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
serial clock frequency equals the system clock f requency); the o ther tr a nsfers set with SCBR
are not equal to 1.
• Transmitting with the slowest chip select and then with the fastest one, then an additional
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
43.2.6.3 SPI: Software Reset Must Be Written Twice
If a software reset (SWRST in th e SPI control regi ster) is perfo rmed, the SPI may not work prop-
erly (the clock is enabled before the chip select).
Problem Fix/Workaround
The SPI Control Registe r field SWRST (Softwar e Reset) needs to be written twice to be correctly
set.
43.2.7 Synchronous Serial Controller (SSC)
43.2.7.1 SSC: Periodic Transmission Limitations in Master Mode
If the Least Signific ant Bit is sent firs t (MSBF = 0), the first TAG during the fra me synchro is no t
sent.
Problem Fix/Workaround
None.
43.2.7.2 SSC: Transmitter Limitations in Slave Mode
If TK is progr ammed as an output a nd TF is programmed as an input, it is impossib le to emit
data when the starting edge (rising or falling) of synchro has a Start Delay equal to zero.
656 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Problem Fix/Workaround
None.
43.2.7.3 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as an input and TF is programmed as an output and re quested to be set to
low/high during data emission, the Frame Synchro signal is generated one bit clock period after
the data start and one data bit is lost. This problem does not exist when generating a periodic
synchro.
Problem Fix/Workaround
The data need to be del ayed for one bit clock p eriod with an exter nal assemb ly. In the following
schematic, TD, TK and NRST are SAM7SE signals, TXD is the delayed da ta to connect to the
device.
43.2.7.4 SSC: Last RK Cloc k Cycle when RK Outputs a Cloc k During Data Transfer
When the SSC receiver is used with the following conditions:
• the internal clock divider is used (CKS = 0 and DIV differ ent from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
At the end of the data, the RK pin is set in high impedance which might be seen as an unex-
pected clock cycle.
Problem Fix/Workaround
Enable the pull-up on RK pin.
43.2.7.5 SSC: First RK Clock Cycle when RK Outputs a Clock During Data Transfer
When the SSC receiver is used with the following conditions:
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
657
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
Problem Fix/Workaround
None.
43.2.8 Two Wire Interface (TWI)
43.2.8.1 TWI: Switching from Slave to Master Mode
When the TWI is set in slave mode and if a master write access is performed, the start event is
correctly generated but the SCL line is stuck at 1, so no transfer is possible.
Problem Fix/Workaround
Two software wo rka r ou nd s ar e po ssib l e :
1. Perform a software reset before going to master mode (TWI must be reconfigured).
2. P erform a slave read access before switching to master mode.
43.2.9 Universal Synchronous Asynchronous Receiver Transmitter (USART)
43.2.9.1 USART: CTS in Hardware Handshaking
When Hardware Handshaking is used and if CTS goes high near the end of the starting bit, a
character can be lost.
CTS must not go high during a time slot occurring between 2 Master Clock periods before the
starting bit and 16 Master Clock periods after the rising edge of the starting bit.
Problem Fix/Workaround
None.
43.2.9.2 USART: Two Characters Sent with Hardware Handshaking
When Hardware Handshaking is used and if CTS goes high during the TX of a character and if
the holding register (US_THR) is not empty, the content of the US_THR will also be transmitted.
Problem Fix/Workaround
Do not use the PDC in transmit mode and do not fill US_THR before TXRDY is set to 1.
43.2.9.3 USART: DCD is Active High Instead of Low
DCD signal is active at “High” level in USART block (Modem Mode).
DCD should be active at “Low” level.
Problem Fix/Workaround
Add an inverter.
43.2.9.4 USART: RXBRK Flag Error in Asynchronous Mode
In Receiver mode, when 2 characters are consecutive (without a timeguar d in between), the
RXBRK is not taken into account. As a result, the RXBRK flag is not enabled correctly, and the
frame error flag is set.
Problem Fix/Workaround
Constraints on the Transmitter device connected to the AT91 USART Receiver:
658 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
The Transmitter may use the timeguard feature, or send 2 STOP conditions. Only 1 STOP con-
dition is taken into account by the Receiver state machine; afte r this STOP condition, as ther e is
no valid data, the Receiver state machine will go in idle mode and will enable the RXBRK
condition.
659
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.3 SAM7SE512/256 Errata - Rev. B Parts
Refer to Section 41.3 ”Ma rk ing ” .
Notes: 1. AT91SAM7SE512 Revision B chip ID is 0x272A 0A41.
2. AT91SAM7SE256 Revision B chip ID is 0x272A 0941.
43.3.1 Analog-to-Digital Converter (ADC)
43.3.1.1 ADC: DRDY Bit Cleared
The DRDY Flag sh ould b e clea red on ly af t er a r ead o f ADC_LCDR (Last Conver ted Da ta Regis-
ter). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY
flag.
Problem Fix/Workaround
None.
43.3.1.2 ADC: GOVRE Bit is Not Updated
Read of the St atus Register at the same instant as an end of conve rsion leads to skip ping the
update of the GOVRE (general overrun) flag. GOVRE is neither reset nor set.
For example, if reading the status while an end of conversion is occurring and:
1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun
condition but the GOVRE flag is not reset.
2. GOVRE is inactive but DRDY is active, does correspond to a new general overrun con-
dition but the GOVRE flag is not set.
Problem Fix/Workaround
None.
43.3.1.3 ADC: OVRE Flag Behavior
When the OVRE flag (on channel i) has been set but the related EOC status (of channel i) has
been cleared (by a r ead of CDRi o r LCDR), read ing th e Status re gister at th e same insta nt as an
end of conversion (causing the set of EOC status on channel i), does not lead to a reset of the
OVRE flag (on channel i) as exp ected.
Problem Fix/Workaround
None.
43.3.1.4 ADC: Sleep Mode
If Sleep mode is activated while there is no activity (no co nversion is being performed), it will
take effect only after a conversion occurs.
Problem Fix/Workaround
To activate sleep mode as soon as possible, it is recommended to write successively, ADC
Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digi-
tal conversion, put ADC into sleep mode at the end of this conversion.
660 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.3.2 Flash Controller
43.3.2.1 EFC : Embedded Flash Access Time
The embedded Flash maximum access time is lower than expected. The tables below show the
frequencies:
Notes: 1. FWS = Flash Wait States
2. It is not necessary to use 3 wait states because the Flash can operate at maximum with only 2
wait states.
Notes: 1. FWS = Flash Wait States
2. It is not necessary to use 3 wait states because the Flash can operate at maximum with only 2
wait states.
Problem Fix/Workaround
Set the number of Wait states (FWS) according to the frequency requirements described in the
errata.
43.3.3 Flash Memory
43.3.3.1 Flash: Power Consumption with data read access with multiple load of two word s
When no Wait State (FWS = 0) is programmed and when data read access is performed with a
multiple load of two words, the internal Flash may stay in read mode.
It implies a potential increase of power consumption on VDDCORE (around 2 mA). Note that it
does not concern the program execution; thus, no issue is present when the program is fetching
out of Flash.
Problem Fix/Workaround
2 workaroun ds are po ssible:
• Add one Wait State when performing these data read accesses (FWS =1)
• After the m ultiple load, perform a single read data access to an address different from the
previous address accesses .
Table 43-2. Embedded Flash Wait State VDDCORE set at 1.65V
FWS(1) Read Operations Maximum Operating Frequency (MHz)
0 1 cycle 20
1 2 cycles 40
2 3 cycles 48.2
3(2) 4 cycles 48.2
Table 43-3. Embedded Flash Wait State VDDCORE set at 1.80V
FWS(1) Read Operations Maximum Operating Frequency (MHz)
0 1 cycle 21.5
1 2 cycles 43
2 3 cycles 55
3(2) 4 cycles 55
661
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.3.4 Pulse Width Modulation Controller (PWM)
43.3.4.1 PWM: Update when PWM_CCNTx = 0 or 1
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Problem Fix/Workaround
Check the Channel Cou nter Register before writing the Channel Update Register.
43.3.4.2 PWM: Update when PWM_CPRDx = 0
When the Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround
Do not write 0 in the Channel Period Register.
43.3.4.3 PWM: Counter Start Value
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter
starts at 1.
Problem Fix/Workaround
None.
43.3.5 Serial Peripheral Interface (SPI)
43.3.5.1 SPI: Bad Serial Clock Generation on 2nd Chip Select
There is a bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and
NCPHA = 0.
This occurs using SPI with the following conditions:
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
serial clock frequency equals the system clock f requency); the o ther t r ansfers set with SCBR
are not equal to 1.
• Transmitting with the slowest chip select and then with the fastest one, then an additional
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
43.3.6 Synchronous Serial Controller (SSC)
43.3.6.1 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when the starting edge (rising or falling) of synchro has a Start Delay equal to zero.
Problem Fix/Workaround
None.
662 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.3.6.2 SSC: Last RK Cloc k Cycle when RK Outputs a Cloc k During Data Transfer
When the SSC receiver is used with the following conditions:
• the internal clock divider is used (CKS = 0 and DIV differ ent from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
At the end of the data, the RK pin is set in high impedance which might be seen as an unex-
pected clock cycle.
Problem Fix/Workaround
Enable the pull-up on RK pin.
43.3.6.3 SSC: First RK Clock Cycle when Rk Outputs a Clock During Data Transfer
When the SSC receiver is used with the following conditions:
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
Problem Fix/Workaround
None.
663
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.4 SAM7SE32 Errata - Rev. B Parts
Refer to Section 41.3 ”Ma rk ing ” .
Notes: 1. AT91SAM7SE32 Revision B chip ID is 0x2728 0341.
43.4.1 Analog-to-Digital Converter (ADC)
43.4.1.1 ADC: DRDY Bit Cleared
The DRDY Flag sh ould b e clea red on ly af t er a r ead o f ADC_LCDR (Last Conver ted Da ta Regis-
ter). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY
flag.
Problem Fix/Workaround
None.
43.4.1.2 ADC: GOVRE Bit is Not Updated
Read of the St atus Register at the same instant as an end of conve rsion leads to skip ping the
update of the GOVRE (general overrun) flag. GOVRE is neither reset nor set.
For example, if reading the status while an end of conversion is occurring and:
1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun
condition but the GOVRE flag is not reset.
2. GOVRE is inactive but DRDY is active, does correspond to a new general overrun con-
dition but the GOVRE flag is not set.
Problem Fix/Workaround
None.
43.4.1.3 ADC: OVRE Flag Behavior
When the OVRE flag (on channel i) has been set but the related EOC status (of channel i) has
been cleared (by a r ead of CDRi o r LCDR), read ing th e Status re gister at th e same insta nt as an
end of conversion (causing the set of EOC status on channel i), does not lead to a reset of the
OVRE flag (on channel i) as exp ected.
Problem Fix/Workaround
None.
43.4.1.4 ADC: Sleep Mode
If Sleep mode is activated while there is no activity (no co nversion is being performed), it will
take effect only after a conversion occurs.
Problem Fix/Workaround
To activate sleep mode as soon as possible, it is recommended to write successively, ADC
Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digi-
tal conversion, put ADC into slee p mode at the end of this conversion.
43.4.2 Flash Memory
43.4.2.1 Flash: Power Consumption with data read access with multiple load of two word s
When no Wait State (FWS = 0) is programmed and when data read access is performed with a
multiple load of two words, the internal Flash may stay in read mode.
664 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
It implies a potential increase of power consumption on VDDCORE (around 2 mA). Note that it
does not concern the program execution; thus, no issue is present when the program is fetching
out of Flash.
Problem Fix/Workaround
2 workaroun ds are po ssible:
• Add one Wait State when performing these data read accesses (FWS =1)
• After the m ultiple load, perform a single read data access to an address different from the
previous address accesses .
43.4.3 Pulse Width Modulation Controller (PWM)
43.4.3.1 PWM: Update when PWM_CCNTx = 0 or 1
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Problem Fix/Workaround
Check the Channel Cou nter Register before writing the Channel Update Register.
43.4.3.2 PWM: Update when PWM_CPRDx = 0
When the Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround
Do not write 0 in the Channel Period Register.
43.4.3.3 PWM: Counter Start Value
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter
starts at 1.
Problem Fix/Workaround
None.
43.4.4 Serial Peripheral Interface (SPI)
43.4.4.1 SPI: Bad Serial Clock Generation on 2nd Chip Select
There is a bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and
NCPHA = 0.
This occurs using SPI with the following conditions:
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
serial clock frequency equals the system clock f requency); the o ther t r ansfers set with SCBR
are not equal to 1.
• Transmitting with the slowest chip select and then with the fastest one, then an additional
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
665
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
43.4.5 Synchronous Serial Controller (SSC)
43.4.5.1 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when the starting edge (rising or falling) of synchro has a Start Delay equal to zero.
Problem Fix/Workaround
None.
43.4.5.2 SSC: Last RK Cloc k Cycle when RK Outputs a Cloc k During Data Transfer
When the SSC receiver is used with the following conditions:
• the internal clock divider is used (CKS = 0 and DIV differ ent from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
At the end of the data, the RK pin is set in high impedance which might be seen as an unex-
pected clock cycle.
Problem Fix/Workaround
Enable the pull-up on RK pin.
43.4.5.3 SSC: First RK Clock Cycle when Rk Outputs a Clock During Data Transfer
When the SSC receiver is used with the following conditions:
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
Problem Fix/Workaround
None.
666 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
667
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
44. Revision History
In the tables that follow, the most recent version of the document appears fi rst.
Note: “rfo” indicates changes requested during document review and approval loop.
Version
6222H Comments
Change
Request
Ref.
Electrical Characteristics:
Section 40.2 ”DC Characteristics”: Table 40.2, “DC Characteristics”, changed values for ‘R pull-up Resistor ’ 8124
Errata:
Section 43.3 ”SAM7SE512/256 Errata - Rev. B Parts”: “Flash Controller”: “EFC : Embedded Flash Access
Time”, added
Section 43.1 ”Errata Summary by Product and Revision or Manufacturin g Number”, added column named
“SAM7SE32 Rev B”
Section 43.4 ”SAM7SE32 Errata - Rev. B Parts”, added
8124
8156
Version
6222G Comments
Change
Request
Ref.
‘Preliminary’ removed from 1st page, and from all headers and footers. rfo
ADC:
Section 39.6.2 ”ADC Mode Register”, formula updated in SHTIM bitfi eld description. 7890
Errata:
Table 43-1, “Errata Summary Table” added.
Notes added on top of Section 43.2 ”SAM7SE512/256/3 2 Errata - Rev. A Parts” .
Section 43.5 ”SAM7SE512/256/32 Errata - Rev. B Parts” added
Typos fixed within Section 43.2 ”SAM7SE512/256/32 Errata - Rev. A Parts”.
7749
rfo
SAM7SE512/256/32 Ordering Information:
MRL B Ordering Codes added to Table 42-1, “Ordering Information” 7749
Version
6222F Comments
Change
Request
Ref.
Boot ROM:
SAM7SE32 user area addresses updated in Section 25.5 ”Hardware and Software Constraints”.
Variables - only used in this section - changed into text (Yy, Yy_prod, Yz, Yz_prod, DRXD_PIO, DTXD_PIO).
7312
rfo
SAM7SE512/256/32 Errata - Rev. A Parts:
Section 43.2.2 ”Flash Memory” added. 7541
‘AT91SAM’ product prefix chang ed to ‘SAM’ (except for Chip ID and ordering codes). rfo
668 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Version
6222E Comments
Change
Request
Ref.
Features:
“Mode for General Purpose Two-wire UART Serial Communica tion” added to “Debug Unit (DBGU)”.
Signal Description:
Table 3-1, “Signal Description List”, AD 0-AD3 and AD4-AD7 comments reversed.
System Controller:
Figure 9-1 ”System Controller Block Diagram”, ‘periph_nreset’ changed into ‘power_on_reset’ for RT T.
5846
5271
5222
AT91SAM7SE512/256/3 2 Electrical Characteristics:
Section 40.7 ”ADC Characteristics”, Table 40-17 and Table 40-18 edited. 6774
AT91SAM7SE512/256/32 Errata - Rev. A Parts:
Section 43.2.9.4 ”USART: RXBRK Flag Error in Asynchronous Mode” description edited.
Section 43.2.6.3 ”SPI: Software Reset Must Be Written Twice” added.
USART: XOFF Character Bad Behavior remove d from Section 43.2.9
6626
5785
5337
Embedded Flash Controller (EFC):
Section 19.2.4.4 ”General-purpose NVM Bits”, bit values edited in last paragraph.
Text added below Figure 19-6 ”Example of Partial Page Programming:” 6236
6774
External Bus Interface (EBI):
Note (8) added to row NWR0/NWE/CFWE in Table 21-3.
Note (1) added to Figure 21-6.6774
Memory Controller (MC):
Section 18.5.2 ”MC Abort Status Register”, MST0, MST1, SVMST0, SVMST1 edited. 5687
Reset Controller (RSTC):
Section 13.2.4.4 ”Software Reset”, text added at the end of PERRST description. 5436
USB Transceiver Characteristics:
Latest Programmer Datasheet used (UDP_6083S instead of UDP_6083M). 6774
669
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Version
6222D Comments
Change
Request
Ref.
“Two Wire Interface (TWI)” Erroneous text ref erences to PDC functionality removed from the TWI section of
the datasheet: page 353, page 355.
(32.7.7 “Using The Peripheral DMA Controller (PDC)” removed from page 357), su bsequent chapter
numbering effected.
(32.9.45 “PDC” removed from page 368), subsequent chapter numbering effected.
Table 32-4, “Register Mapping”, reserved offset for PDC removed
Section 32.10.6 ”TWI Status Register”, TXBUFE, RXBUFF, ENDTX, ENDRX bit fields and descriptions
removed.
Section 32.10.7 ”TWI Interrupt Enable Register” , TXBUFE, RXBUFF, ENDTX, ENDRX bit fields and
descriptions removed.
Section 32.10.8 ”TWI Interrupt Disable Register”,TXBUFE, RXBUFF, ENDTX, ENDRX bit fields and
descriptions removed.
Section 32.10.9 ”TWI Interrupt Mask Register”,TXBUFE, RXBUFF, ENDTX, ENDRX bit fields and
descriptions removed.
5187
Version
6222C Comments
Change
Request
Ref.
Overview:
Figure 8-1 ”SAM7SE Memory Mapping”, Compact Flash not shown w/EBI Chip Select 5. Compact Flash is
shown with EBI Chip Select 2
Section 8.1.2.1 ”Flash Overview”, updated AT91SAM7SE32 ...”reads as 8192 32-bit words.”
Section 6. ”I/O Lines Considerations”, “JTAG Port Pins”,“Test Pin”,“Reset Pin”,“ERASE Pin”; descriptions
updated.
4804
4512
5062
PMC
Section 29.9.10 ”PMC Master Clock Register”, MDIV removed from bit fields 9 and 8. 4766
TWI
Important changes to this datasheet include a clarification of Atmel TWI compatibility with I2C Standard. (See
Section 32.1 ”Overview” and Table 32-1)
Section 32.7 ”Master Mode”, re written. New Master Read-write flowcharts, ne w Read-write transf er wav ef orms,
bit field description modification etc.
Figure 32-2 ”Application Block Diagram”, updated
Figure 32-5 ”Master Mode Typical Application Block Diagram”, updated
New sections; Section 32.7.4 ”Master Transmitter Mode” and Section 32.7.5 ”Master Receiver Mode” replace
“Transmitting Data”. See also: Figure 32-6, Figure 32-7, Figure 32-8, Figure 32-9 and Figure 32-10
Section 32.7.6 ”Internal Address” added and includes, Section 32.7.6.1 ”7-bit Slave Addressing” and Section
32.7.6.2 ”10-bit Slave Addressing” See also: Figure 32-11, Figure 32-12 and Figure 32-13
Section 32.9.6 ”Read Write Flowcharts”, updated and new flowcharts added.
4373
Fixed typo in ARBLST bit fields; “TWI Interrupt Enable Register”, “TWI Interrupt Disable Registe r ” and “TWI
Interrupt Mask Register”
Inserted EOSACC bit field description in “TWI Interrupt Enable Register”
4584
4586
670 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Section 40. ”SAM7SE512/256/32 Electrical Characteristics”
Table 40-12, “XIN Clock Electrical Characteristics” VXIN_IL, VXIN_IH updated
Table 40-2, “DC Characteristics”, juncti on temperature removed and
VDDIO DC supplies 3.3V and 1.8V defined
Table 40-7, “Power Consumption for Different Modes”: Footnote assigned to Flash In standby mode. Footnote
assigned to Ultra Low Power mode .
Table 40-5, “DC Flash Characteristics SAM7SE32”, Max standby current updated.
5007
rfo
4657
4598
rfo
Section 41. ”SAM7SE512/256/32 Mechanical Characteristics”
LQFP-package, JESD97 Classification is e3.
Ther mal Considerations removed. 4971/5007
4657
Section 43. ”SAM7SE512/256/32 Errata”
Section 43.2.1 ”Analog-to-Digital Converter (ADC)”, added to errata.
Section 43.2.5 ”SDRAM Controller (SDRAMC)”, added to errata.
Section 43.2.6.1 ”SPI: Baudrate Set to 1”, Problem Fix/Workaround = None.
Section 43.2.6.2 ”SPI: Bad Serial Clock Generation on 2nd Chip Select”, added to errata.
Section 43.2.7.4 ”SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer”, added to errata.
Section 43.2.7.5 ”SSC: First RK Clock Cycle when RK Outputs a Clock During Data Transfer”, added to errata.
Section 43.2.9.3 ”USART: DCD is Active High Instead of Low”, added to errata.
Section 43.2.9.4 ”USART: RXBRK Flag Error in Asynchronous Mode”, added to errata.
5007/4751
/4642
Version
6222C Comments
Change
Request
Ref.
Version
6222B Comments
Change
Request
Ref.
Overview, Section 6.1 ”JTAG Port Pins”, Section 6.3 ”Reset Pin”, Section 6.5 ”SDCK Pin”, remov ed statement:
“not 5V tolerant”. Section 7.6 ”SDRAM Controller” Mobile SDRAM controller added to SDRAMC descrip tion
INL and DNL updated in Section 10.14 “Analog-to-Digital Converter” on page 42
3826
4005
“Features” on page 2, Fully Static Operation: added up to 55 MHz at 1.8V and 85°C worst case conditions
Section 7.1 ”ARM7TDMI Processor”, Runs at up to 55 MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V)
Section 7.8 ”Peripheral DMA Controller” PDC priority list added.
Section 7.5 ”Stati c Me mor y Controller” Multiple device adaptability: compliant w/PSRAM in synchronous
operations
3924
3833
review
Clock Generator, Removed information on capacitor load value in Section 28.3.1 ”Main Oscillator
Connections” Figure 28-2 ”Typical Crystal Connection” on page 272, upd ated, CL1 and CL2 labels removed. 3282
3861
DBGU, Deb u g Un i t Ch i p ID Re gister, “SRAMSIZ: Internal SRAM Size” on page 320 updated w/AT91SAM7L
internal RAM size and “ARCH: Architecture Identifier” on page 321 updated bin values for 0x60 and 0xF0, and
added descriptions for CAP7, AT91SAM7AQxx series and CAP11
3828
3369
3807
EBI, Table 21-3, “EBI Pins and External Static Device Connections,” on page 138, I/O[8:15 ] bits added in
NAND Flash column, added notes to table for SDRAM, NAND FLash and references to app notes.
Figure 21-1 ”Organization of the External Bus Interface” SDCK is not multiplexed with PIO
Section 21.7.6.1 ”Hardware Configuration” A25 removed from CFRNW in CompactFlash
Section 21.7.7.1 ”Hardware Configuration” A25 removed from CFRNW in CompactFlash True IDE
3742/3743
/
3852
3924
4044/3836
671
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Electri cal Characteristics,
Section 40.4.3 ”Crystal Characteristic s” TCHXIN and TCHLXIN updated, TCLCH and TCHCL added to
Table 40-12, “XIN Clock Electrical Characteristics” and Figure 40-2 ”XIN Clock Timing” has been added.
3966
Section 40.7 ”ADC Characteristics” INL and DNL updated and Absolute accuracy added to Table 40-19,
“Transfer Characteristics”. Reference to Data Converter Terminology added below table.
INL and DNL updated in Section 10.14 “Analog-to-Digital Converter” on page 42
4005
Section 40.8.4 ”SMC Signals”,A25 Address line changed to A22. Table 40-25 on page 632 thru Table 40-28 on
page 634 and in the following two figures.
Figure 40-8 ”SMC Signals in Memory Interface Mode” and Figure 40-9 ”SM Signals in LCD Interface Mode”
SMC timings updated to be concordant with signals listed in Tab le 40-25 thru Tabl e 40-28.
4044/3836
Section 40.8.6 ”Embedded Flash Characteristics” updated. Note added t oTable 40-32, “Embedded Flash Wait
States (VDDCORE = 1.65V)” and added Tab le 40-33, “Embedded Flash Wait States (VDDCORE = 1.8V)”
Table 40-20, “Master Clock Waveform Parameters”, updated w/VDDCORE = 1.8V, Max = 55 MHz
3924
Table 40-10, “Main Oscillator Characteristics” add ed schematic in footnote to CL and CLEXT symbols
Table 40-7, “Power Consumption for Different Modes” DDM and DDP pins must be left floating.
Table 40-32, “Embedded Flash Wait States (VDDCORE = 1.65V)” footnote (2) added.
3868
3829
review
ECCC, Section 24.3 ”Fun ctional Description” and Section 24.3.1 ”Write Acce ss” and Se ction 24.3.2 “Read
Access” on page 220 updated. Section 24.4.4 ”ECC Parity Register” and Section 24.4.5 “ECC NParity
Register” on page 228 instruction updated. 3970
ERRATA, Section 43.2.9.1 ”USART: CTS in Hardware Handshaking”, updated.....”if CTS goes high near the
end of the starting bit, a character can be lost”........... 3955
MC, Section 18.4.5 ”Memory Protection Unit”, initializati on guidelines updated at end of section. 4045
PIO, Section 34.4.5 ”Synchronous Data Output”, PIO_OWSR typo corrected.
User Interface, Table 34-2, “PIO Register Mapping,” on page 446, footnotes updated on PIO_PSR,
PIO_ODSR, PIO_PDSR table cells.
3289
3974
SDRAMC, Secti on 23 .1 “Overview” on page 199, Mobile SDRAM controller added to SDRAMC description
Figure 23-1 on page 199 , SDCK signal in the Block Diagram up dated. 3826
review
SMC, Figure 22-9, Figure 22-10, Figure 22-11, Figure 22-12, Figure 22-13 and Figure 22-25 replaced
32-bit bus removed from bit field descriptio n “BAT: Byte Access Type” on page 196
“SMC Chip Select Registers” on page 196, section restructured with table mo v ed from the end of the section to
appear in the bit field description: “NWS: Number of Wait States” on page 196. “Don’t Care” and “Number of
Wait States” column added to this table and NRD Pulse Length is defined in Standard Read and Early Read
Protocols.
Note 1 assigned to table describing bit fields “RWSETUP: Read and Write Signal Setup Time”and “RWHOLD:
Read and Write Signal Hold Time” on page 197.
GLOBAL All references to A25 address line changed to be A22 (23-bit address bus)
Note specific to ECC Controller adde d to “RWHOLD: Read and Write Signal Hold Time”bit field description.
“Overview” on page 161, Address space is 64 Mbytes and the address bus is 23 bits.
“External Memory Mapping” on page 163, external address bus is 23 bits.
Figure 22-3 on page 164 , maximum address space per device is 8 Mbytes.
Figure 22-32 on page 183,change in values on [D15:0] line.
Figure 22-45, Figure 22-46 and Figure 22-47 on page 198 replaced.
3846
3847
3848/4182
3863/3864
3886
review
Version
6222B Comments
Change
Request
Ref.
672 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
SSC, Section 35.6.6.1 “Compare Functions” on page 474, updated review
UDP, Table 38-2, “USB Communication Flow” , Supported end point size updated for transfer interrupt
Control endpoints are not effected by the “EPEDS: Endpoint Enable Disable”bit field in the USB_CSR register.
write 1 updated in “RX_ DATA_BK0: Receive Data Bank 0”bit field in USB_CSR register.
write 0 updated in “TXPKTRDY: Transmit Packet Ready”bit field in USB_CSR register.
3476
4063
4099
USART, In the US_MR register, typo fixed in bit field description “CLKO: Clo ck Output Select” on page 422
and DIV value given in bit fi eld description “USCLKS: Clock Selection” on page 421
Section 33.5.1 “I/O Lines” on page 392, 3rd paragraph updated.
In the US_CSR register the bit field description “TXEMPTY: TXEMPTY Interrupt Enable” on page 424 has
been updated
3306
3763
3851
3895
Version
6222A Comments
Change
Request
Ref.
First issue: Preliminary
Version
6222B Comments
Change
Request
Ref.
1
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Features....................................................................................................1
1 Description ...............................................................................................3
1.1Configuration Summary of the SAM7SE512, SAM7SE256 and SAM7SE32 ............3
2 Block Diagram ..........................................................................................4
3 Signal Description ....................................................................................5
4 Package .....................................................................................................9
4.1128-lead LQFP Package Outline ...............................................................................9
4.2128-lead LQFP Pinout .............................................................................................10
4.3144-ball LFBGA Package Outline ............................................................................11
4.4144-ball LFBGA Pinout ............................................................................................12
5 Power Considerations ...........................................................................13
5.1Power Supplies ........................................................................................................13
5.2Power Consumption ................................................................................................13
5.3Voltag e Re gu lat or ............................. ... .... ... ... ................ ... .... ... ... ................ ... .... ... ...1 3
5.4Typical Powering Schematics ..................................................................................14
6 I/O Lines Considerations .......................................................................15
6.1JTAG Port Pins .............. ... ... ... ................. ... ... ... ... .... ................ ... ... .... ... ... ................1 5
6.2Test Pin ......... ... ... ... ... ................. ... ... ... ................ .... ... ... ... ................. ... ... ... ... ..........15
6.3Reset Pin .................................................................................................................15
6.4ERASE Pin ..............................................................................................................15
6.5SDCK Pin ......... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ................ ... ... ... .... ... ...16
6.6PIO Controller lines .................................................................................................16
6.7I/O Lines Current Drawing .......................................................................................16
7 Processor and Architecture ..................................................................17
7.1ARM7TDM I Pro ce sso r ... ... ... ... .... ... ... ................ ... .... ... ... ... ................. ... ... ... ... .... ......17
7.2Debu g an d Te st Featu re s ........................... ... ... ... .... ................ ... ... .... ................ ... ...1 7
7.3Memory Controller ...................................................................................................17
7.4External Bus Interface .............................................................................................18
7.5Static Memory Controller .........................................................................................18
7.6SDRAM Controller ...................................................................................................19
7.7Error Corrected Code Controller ..............................................................................19
7.8Peripheral DMA Controller .......................................................................................20
8 Memories ................................................................................................21
2 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
8.1Embedded Memories ..............................................................................................23
8.2External Memories ...................................................................................................27
9 System Controller ..................................................................................28
9.1Reset Controller .......................................................................................................30
9.2Clock Generator ......................................................................................................30
9.3Power Management Controller ................................................................................31
9.4Adv an ce d In ter rup t C on tr oller ..... ... ... ... .... ................ ... ... ... .... ................ ... ... ... .... ......32
9.5Debu g Unit ........................ ... ... .... ... ................ ... ... .... ... ... ................ .... ... ... ... .............33
9.6Periodic Interval Timer .............................................................................................33
9.7Watch do g Time r ............... ... ... .... ... ................ ... ... .... ... ................ ... .... ... ... ................3 3
9.8Real-time Timer .......................................................................................................33
9.9PIO Controllers ........................................................................................................33
9.10Voltage Regulator Controller .................................................................................34
10 Peripherals ..............................................................................................35
10.1User Interface ........................................................................................................35
10.2Peripher al Ide n tifie rs .................... ... ... .... ... ... ... ................ .... ... ... ... .... ................ ... ...3 5
10.3Peripher al Mu ltip lex ing on PIO Line s ................ .... ... ................ ... .... ... ... ... ... ..........36
10.4PIO Controller A Multiplexing ................................................................................37
10.5PIO Controller B Multiplexing ................................................................................38
10.6PIO Controller C Multiplexing ................................................................................39
10.7Serial Peripheral Interface .....................................................................................39
10.8Two Wire Interface ................................................................................................40
10.9USART ..................................................................................................................40
10.10Serial Synchronous Controller .............................................................................40
10.11Time r Co un te r .. ... ... .... ... ................ ... .... ... ................ ... ... .... ................ ... ... ... .... ......41
10.12PWM Controller ...................................................................................................41
10.13USB Device Port ................. .... ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... ...4 2
10.14Analog-to-Digital Converter .................................................................................42
11 ARM7TDMI Processor Overview ...........................................................43
11.1Overvie w ............... ................ ................. ................ ............. ................ ................ ...43
11.2ARM7TDMI Processor ...........................................................................................44
12 Debug and Test Features ......................................................................49
12.1Overvie w ............... ................ ................. ................ ............. ................ ................ ...49
12.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ ...4 9
12.3Application Examples ............................................................................................50
3
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
12.4Debug and Test Pin Description ............................................................................51
12.5Functional Description ...........................................................................................52
13 Reset Controller (RSTC) ........................................................................55
13.1Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ ...5 5
13.2Functional Description ...........................................................................................56
13.3Reset Contr olle r (RSTC) User Interfa ce ...... ... ... .... ... ... ................ .... ... ... ... ... ..........63
14 Real-time Timer (RTT) ............................................................................67
14.1Overvie w ............... ................ ................. ................ ............. ................ ................ ...67
14.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ ...6 7
14.3Functional Description ...........................................................................................67
14.4Real-time Timer (RTT) User Interface ...................................................................69
15 Watchdog Timer (WDT) .........................................................................73
15.1Overvie w ............... ................ ................. ................ ............. ................ ................ ...73
15.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ ...7 3
15.3Functional Description ...........................................................................................74
15.4Watchdog Timer (WDT) User Interface .................................................................76
16 Periodic Interval Timer (PIT) .................................................................79
16.1Overvie w ............... ................ ................. ................ ............. ................ ................ ...79
16.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ ...7 9
16.3Functional Description ...........................................................................................80
16.4Periodic Interval Timer (PIT) User Interface ..........................................................82
17 Voltage Regulator Mode Controller (VREG) ........................................85
17.1Overvie w ............... ................ ................. ................ ............. ................ ................ ...85
17.2Voltage Regulator Power Controller (VREG) User Interface .................................86
18 Memory Controller (MC) ........................................................................87
18.1Overvie w ............... ................ ................. ................ ............. ................ ................ ...87
18.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ ...8 7
18.3Functional Description ...........................................................................................88
18.4External Memory Areas .........................................................................................89
18.5Memory Controller (MC) User Interface ................................................................93
19 Embedded Flash Controller (EFC) ......................................................101
19.1Overview ........... ............. ................ ................ ................ ................. ................ ....101
19.2Functional Description .........................................................................................101
19.3Embedded Flash Controller (EFC ) User Interface ..............................................110
4 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
20 Fast Flash Programming Interface (FFPI) ..........................................117
20.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 1 17
20.2Parallel Fast Flas h Pro g ramm i ng ............. ... ................ ... .... ... ... ... ................ .... ... .11 8
20.3Serial Fast Flash Programming ...........................................................................128
21 External Bus Interface (EBI) ................................................................135
21.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 1 35
21.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .13 6
21.3I/O Lines Desc rip tio n ................ ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... .13 7
21.4Application Example ............................................................................................138
21.5Product Dependencies ........................................................................................141
21.6Functional Description .........................................................................................141
21.7Implementation Examples ...................................................................................148
21.8External Bus Interface (EBI) User Interface ........................................................157
22 Static Memory Controller (SMC) .........................................................161
22.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 1 61
22.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .16 1
22.3I/O Lines Desc rip tio n ................ ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... .16 2
22.4Multiplexed Signals ..............................................................................................162
22.5Product Dependencies ........................................................................................163
22.6Functional Description .........................................................................................163
22.7Static Memory Controller (SMC) User Interface ..................................................195
23 SDRAM Controller (SDRAMC) .............................................................199
23.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 1 99
23.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .19 9
23.3I/O Lines Desc rip tio n ................ ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... .20 0
23.4Application Example ............................................................................................200
23.5Product Dependencies ........................................................................................202
23.6Functional Description .........................................................................................204
23.7SDRAM Controller (SDRAMC) User Interface ....................................................210
24 Error Corrected Code Controller (ECC) .............................................219
24.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 2 19
24.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .21 9
24.3Functional Description .........................................................................................220
24.4ECC User Interface .............................................................................................224
5
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
25 AT91SAM Boot Program .....................................................................229
25.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 2 29
25.2Flow Diagram ......................................................................................................229
25.3Device Initialization ..............................................................................................229
25.4SAM-BA Boot ......................................................................................................230
25.5Hardware and Software Constraints ....................................................................233
26 Peripheral DMA Controller (PDC) .......................................................235
26.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 2 35
26.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .23 5
26.3Functional Description .........................................................................................236
26.4Peripheral DMA Controller (PDC) User Interface ...............................................238
27 Advanced Interrupt Controller (AIC) ..................................................245
27.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 2 45
27.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .24 5
27.3Application Block Diagram ...................................................................................246
27.4AIC Detailed Block Diagram ................................................................................246
27.5I/O Line Descr ipt i on ............................... ... ... ... ... .... ................ ... ... .... ... ... ... ...........246
27.6Product Dependencies ........................................................................................247
27.7Functional Description .........................................................................................248
27.8Advanced Interrupt Controller (AIC) User Interface .............................................260
28 Clock Generator ...................................................................................271
28.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 2 71
28.2Slow Clock RC Oscillator .....................................................................................271
28.3Main Oscillator .....................................................................................................271
28.4Divider and PLL Block .........................................................................................273
29 Power Management Controller (PMC) ................................................275
29.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 2 75
29.2Master Clock Controller .......................................................................................275
29.3Processor Clock Controller ..................................................................................276
29.4USB Clock Controller ...........................................................................................276
29.5Peripher al Cloc k Con tr olle r ... .... ................ ... ... ... .... ... ... ........................................276
29.6Programmable Clock Output Controller ...............................................................277
29.7Programming Sequence ......................................................................................277
29.8Clock Switching Details .......................................................................................281
29.9Power Man ag em e nt Cont ro ller (PM C ) Use r Inter fa c e ....... ... ... ... .... ................ ... .28 4
6 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
30 Debug Unit ( DBGU) .............................................................................. 299
30.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 2 99
30.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .30 0
30.3Product Dependencies ........................................................................................301
30.4UART Operations ................................................................................................301
30.5Debug Unit Use r In ter fa ce ................ .... ... ... ... ... .... ................ ... ... .... ... ... ..............308
31 Serial Peripheral Interface (SPI) ..........................................................323
31.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 3 23
31.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .32 4
31.3Application Block Diagram ...................................................................................324
31.4Signal Description ...............................................................................................325
31.5Product Dependencies ........................................................................................325
31.6Functional Description .........................................................................................326
31.7Serial Peripheral Interface (SPI) User Interface ..................................................335
32 Two Wire Interface (TWI) .....................................................................349
32.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 3 49
32.2List of Abbr ev iatio n s ................. ................ ... ... ... .... ................ ... ... .... ... ... ..............34 9
32.3Block Diagram ................ ... ................ .... ... ... ... ... .... ................ ... ... .... ... ... ... ... ........350
32.4Application Block Diagram ...................................................................................350
32.5Product Dependencies ........................................................................................351
32.6Functional Description .........................................................................................352
32.7Master Mode ........................................................................................................353
32.8Multi-ma ste r Mo d e ....................... ... ... .... ... ................ ... ... .... ... ................ ... ... .... ... .36 4
32.9Slave Mode ..........................................................................................................367
32.10Two-wir e Int er fa ce (TW I) Use r Int erfa c e ................ ... ... .... ................ ... ... ... .... ... .37 5
33 Universal Synchronous Asynchronous Receiver Transceiver (USART) 389
33.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 3 89
33.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .39 0
33.3Application Block Diagram ...................................................................................391
33.4I/O Lines Description ..........................................................................................391
33.5Product Dependencies ........................................................................................392
33.6Functional Description .........................................................................................393
33.7USART User Interface ........................................................................................418
34 Parallel Input Output Controller (PIO) ................................................437
34.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 4 37
7
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
34.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .43 8
34.3Product Dependencies ........................................................................................439
34.4Functional Description .........................................................................................440
34.5I/O Lines Programming Example .........................................................................444
34.6PIO User Interface ...............................................................................................446
35 Synchronous Serial Controller (SSC) ................................................ 463
35.1Descrip tion ............... ............. ................. ................ ................ ................ ..............46 3
35.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .46 4
35.3Application Block Diagram ...................................................................................464
35.4Pin Name List ......................................................................................................465
35.5Product Dependencies ........................................................................................465
35.6Functional Description .........................................................................................465
35.7SSC Application Examples ..................................................................................477
35.8Synchr onou s Ser i al Co ntr o ller (SSC) Use r In te rfa ce ............... ... .... ....................479
36 Timer/Counter (TC) ..............................................................................501
36.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 5 01
36.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .50 2
36.3Pin Name List ......................................................................................................503
36.4Product Dependencies ........................................................................................503
36.5Functional Description .........................................................................................504
36.6Timer/Counter (TC) User Interface ......................................................................517
37 Pulse WIdth Modulation Controller (PWM) ........................................535
37.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 5 35
37.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .53 5
37.3I/O Lines Desc rip tio n ................ ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... .53 6
37.4Product Dependencies ........................................................................................536
37.5Functional Description .........................................................................................537
37.6Pulse Width Modulation (PWM) Controller User Interface .................................545
38 USB Device Port (UDP) ........................................................................555
38.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 5 55
38.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .55 6
38.3Product Dependencies ........................................................................................557
38.4Typical Connection ..............................................................................................558
38.5Functional Description .........................................................................................559
38.6USB Device Port (UDP) User Interface ...............................................................573
8 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
39 Analog-to-Digital Converter (ADC) .....................................................597
39.1Overvie w ............... ................ ................. ................ ............. ................ ................ . 5 97
39.2Block Diagram ................ ... ................ .... ... ... ... ... ................. ... ... ... .... ... ................ .59 7
39.3Signal Description ................................................................................................598
39.4Product Dependencies ........................................................................................598
39.5Functional Description .........................................................................................599
39.6Analog-to-digital Converter (ADC) User Interface ...............................................604
40 SAM7SE512/256/32 Electrical Characteristics ..................................615
40.1Absolute Ma xim u m Ra ting s ...................... ... ... ... .... ... ................ ... .... ... ... ... ...........615
40.2DC Characteristics ...............................................................................................616
40.3Power Consu m ption ....................... ... .... ... ... ... ................ .... ... ... ... .... ... ................ .61 9
40.4Crystal Oscillators Characteristics ......................... ... ... ... .... ... ... ... .... ... ... ..............621
40.5PLL Characteristics ........ ................ ... .... ... ... ... ................ .... ... ... ... .... ................ ... .62 4
40.6USB Transceiver Characteristics .........................................................................625
40.7ADC Characteristics ...........................................................................................627
40.8AC Charac te rist ics .......... ... ................ .... ... ... ... ... ................. ... ... ... .... ... ... ..............62 8
41 SAM7SE512/256/32 Mechanical Characteristics ...............................645
41.1Package Dra win gs ... .... ... ... ... .... ................ ... ... ... .... ... ................ ... .... ... ... ... ... ........645
41.2Soldering Profile ..................................................................................................647
41.3Marking ................................................................................................................ 647
42 SAM7SE512/256/32 Ordering Information .........................................648
43 SAM7SE512/256/32 Errata ...................................................................649
43.1Errata Summary by Product and Revision or Manufacturing Number .................649
43.2SAM7SE512 /2 56 /3 2 Err at a - Rev . A Parts ............ ................ ... ... .... ... ... ... ... ........651
43.3SAM7SE512/256 Errata - Rev. B Parts ...............................................................659
43.4SAM7SE32 Errata - Rev. B Parts ........................................................................663
44 Revision History ...................................................................................667
Headquarters International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: (+1) (408) 441-0311
Fax: (+1) (408) 487-2600
Atmel Asia Limited
Unit 01-5 & 16, 19F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
HONG KONG
Tel: (+852) 2245-6100
Fax: (+852) 2722-1369
Atmel Munich GmbH
Business Campus
Parkring 4
D-85748 Garching b. Munich
GERMANY
Tel: (+49) 89-31970-0
Fax: (+49) 89-3194621
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
JAPAN
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Product Contact
Web Site
www.atmel.com
www.atmel.com/AT91SAM
Technical Support
AT91SAM Support
Atmel technical support
Sales Contacts
www.atmel.com/contacts/
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or co mpl etene ss o f the c ontents of this document and rese rves the right to ma ke changes to specifications
and product descr iptions at any time without notice. Atmel does not make any commitment to update the infor mation contained herein. Unless specifi cally provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applicatio ns intended to suppor t or sustain life.
© 2011 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, SAMBA®, DataFlash®and others are registered
trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM®, ARMPowered®logo, Cortex®, Thumb®-2 and others are registered
trademarks or trademarks of ARM Ltd. Windows® and others are registered trademarks or trademarks of Microsoft Corporation in the US and/or
other countries. Other terms and product names may be trademar ks of others.
6222H–ATARM–25-Jan-12
2 6222H–ATARM–25-Jan-12
SAM7SE512/256/32
