671
6222H–ATARM–25-Jan-12
SAM7SE512/256/32
Electri cal Characteristics,
Section 40.4.3 ”Crystal Characteristic s” TCHXIN and TCHLXIN updated, TCLCH and TCHCL added to
Table 40-12, “XIN Clock Electrical Characteristics” and Figure 40-2 ”XIN Clock Timing” has been added.
3966
Section 40.7 ”ADC Characteristics” INL and DNL updated and Absolute accuracy added to Table 40-19,
“Transfer Characteristics”. Reference to Data Converter Terminology added below table.
INL and DNL updated in Section 10.14 “Analog-to-Digital Converter” on page 42
4005
Section 40.8.4 ”SMC Signals”,A25 Address line changed to A22. Table 40-25 on page 632 thru Table 40-28 on
page 634 and in the following two figures.
Figure 40-8 ”SMC Signals in Memory Interface Mode” and Figure 40-9 ”SM Signals in LCD Interface Mode”
SMC timings updated to be concordant with signals listed in Tab le 40-25 thru Tabl e 40-28.
4044/3836
Section 40.8.6 ”Embedded Flash Characteristics” updated. Note added t oTable 40-32, “Embedded Flash Wait
States (VDDCORE = 1.65V)” and added Tab le 40-33, “Embedded Flash Wait States (VDDCORE = 1.8V)”
Table 40-20, “Master Clock Waveform Parameters”, updated w/VDDCORE = 1.8V, Max = 55 MHz
3924
Table 40-10, “Main Oscillator Characteristics” add ed schematic in footnote to CL and CLEXT symbols
Table 40-7, “Power Consumption for Different Modes” DDM and DDP pins must be left floating.
Table 40-32, “Embedded Flash Wait States (VDDCORE = 1.65V)” footnote (2) added.
3868
3829
review
ECCC, Section 24.3 ”Fun ctional Description” and Section 24.3.1 ”Write Acce ss” and Se ction 24.3.2 “Read
Access” on page 220 updated. Section 24.4.4 ”ECC Parity Register” and Section 24.4.5 “ECC NParity
Register” on page 228 instruction updated. 3970
ERRATA, Section 43.2.9.1 ”USART: CTS in Hardware Handshaking”, updated.....”if CTS goes high near the
end of the starting bit, a character can be lost”........... 3955
MC, Section 18.4.5 ”Memory Protection Unit”, initializati on guidelines updated at end of section. 4045
PIO, Section 34.4.5 ”Synchronous Data Output”, PIO_OWSR typo corrected.
User Interface, Table 34-2, “PIO Register Mapping,” on page 446, footnotes updated on PIO_PSR,
PIO_ODSR, PIO_PDSR table cells.
3289
3974
SDRAMC, Secti on 23 .1 “Overview” on page 199, Mobile SDRAM controller added to SDRAMC description
Figure 23-1 on page 199 , SDCK signal in the Block Diagram up dated. 3826
review
SMC, Figure 22-9, Figure 22-10, Figure 22-11, Figure 22-12, Figure 22-13 and Figure 22-25 replaced
32-bit bus removed from bit field descriptio n “BAT: Byte Access Type” on page 196
“SMC Chip Select Registers” on page 196, section restructured with table mo v ed from the end of the section to
appear in the bit field description: “NWS: Number of Wait States” on page 196. “Don’t Care” and “Number of
Wait States” column added to this table and NRD Pulse Length is defined in Standard Read and Early Read
Protocols.
Note 1 assigned to table describing bit fields “RWSETUP: Read and Write Signal Setup Time”and “RWHOLD:
Read and Write Signal Hold Time” on page 197.
GLOBAL All references to A25 address line changed to be A22 (23-bit address bus)
Note specific to ECC Controller adde d to “RWHOLD: Read and Write Signal Hold Time”bit field description.
“Overview” on page 161, Address space is 64 Mbytes and the address bus is 23 bits.
“External Memory Mapping” on page 163, external address bus is 23 bits.
Figure 22-3 on page 164 , maximum address space per device is 8 Mbytes.
Figure 22-32 on page 183,change in values on [D15:0] line.
Figure 22-45, Figure 22-46 and Figure 22-47 on page 198 replaced.
3846
3847
3848/4182
3863/3864
3886
review
Version
6222B Comments
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