S29WS064N0LBFW110 - Spansion, Inc.

Publication Number S29WS-N_00 Revision GAmendment 0Issue Date January 25, 2005

ADVANCE

INFORMATION

S29WS-N MirrorBit™ Flash Family

S29WS256N, S29WS128N, S29WS064N

256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only

Simultaneous Read/Write, Burst Mode Flash Memory

Data Sheet

Notice to Readers: The Advance Information status indicates that this

document contains information on one or more products under development

at Spansion LLC. The information is intended to help you evaluate this product.

Do not design in this product without contacting the factory. Spansion LLC

reserves the right to change or discontinue work on this proposed product

without notice.

This page intentionally left blank.

Publication Number S29WS-N_00 Revision G Amendment 0 Issue Date January 25, 2005

General Description

The Spansion S29WS256/128/064N are MirrorbitTM Flash products fabricated on 110 nm process technology . These burst

mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate

banks using separate data and address pins. These products can operate up to 80 MHz and use a single VCC of

1.7 V to 1.95 V that makes them ideal for today’s demanding wireless applications requiring hi gher density, better per-

formance and lowered power consumption.

Distinctive Characteristics

Single 1.8 V read/program/erase (1.70–1.95 V)

110 nm MirrorBit™ Technology

Simultaneous Read/Write operation with zero

latency

32-word Write Buffer

Sixteen-bank architecture consisting of 16/8/4

Mwords for WS256N/128N/064N, respectively

Four 16 Kword sectors at both top and bottom of

memory array

254/126/62 64 Kword sectors (WS256N/128N/

064N)

Programmable burst read modes

— Linear for 32, 16 or 8 words linear read with or

without wrap-a round

— Continuous sequ ential read mode

SecSi™ (Secured Silicon) Sector region consisting

of 128 words each for factory and customer

20-year data retention (typical)

Cycling Endurance: 100,000 cycles per sector

(typical)

RDY output indicates data available to system

Command set compatible with JEDEC (42.4)

standard

Hardware (WP#) protection of top and bottom

sectors

Dual boot sector configuration (top and bottom)

Offered Packages

— WS064N: 80-ball FBGA (7 mm x 9 mm)

— WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)

Low VCC write inhibit

Persistent and Password methods of Advanced

Sector Protection

Write operation status bits indicate program and

erase operation completion

Suspend and Resume commands for Program and

Erase operations

Unlock Bypass program command to reduce

programming time

Synchronous or Asynchronous program operation,

independent of burst control register settings

ACC input pin to reduce factory programming time

Support for Common Flash Interface (CFI)

Industrial Temperature range (contact factory)

Performance Characteristics

S29WS-N MirrorBit™ Flash Family

S29WS256N, S29WS128N, S29WS064N

256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only

Simultaneous Read/Write, Burst Mode Flash Memory

Data Sheet ADVANCE

INFORMATION

Read Access Times

Speed Option (MHz) 80 66 54

Max. Synch. Latency, ns (tIACC)808080

Max. Synch. Burst Access, ns (tBACC) 9 11.2 13.5

Max. Asynch. Access Time, ns (tACC)808080

Max CE# Access Time, ns (tCE)808080

Max OE# Access Time, ns (tOE) 13.5 13.5 13.5

Current Consumption (typical values)

Continuous Burst Read @ 66 MHz 35 mA

Simultaneous Operation (asynchronous) 50 mA

Program (asynchronous) 19 mA

Erase (as ynchronous) 19 mA

Standby Mode (asynchronous) 20 µA

Typical Program & Eras e Ti mes

Single Word Programming 40 µs

Effective Write Buffer Programming (VCC) Per Word 9.4 µs

Effective Write Buffer Programming (VACC) Per Word 6 µs

Sector Erase (16 Kword Sector) 150 ms

Sector Erase (64 Kword Sector) 600 ms

S29WS-N MirrorBit™ Flash Family S29WS-N_00_G0    January 25, 2005  
Advance Information
Contents
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Physical Dimensions/Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1 Related Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Special Handling Instructions for FBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 VBH084—84-ball Fine-Pitch Ball Grid Array, 8 x 11.6 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 TLC080—80-ball Fine-Pitch Ball Grid Array, 7 x 9 mm  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 MCP Look-ahead Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device Operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Synchronous (Burst) Read Mode & 
 
Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.3 Continuous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
3.4 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 8-, 16-, 32-Word Linear Burst without Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1. Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2 Write Buffer Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37
5.5 Erase Suspend/Erase Resume Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37
5.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.7 Accelerated Program/Chip Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39
5.8 Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.9 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
8 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
9 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  53
4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5 Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  54
6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57
7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57
7.1. WP# Method  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57
7.2 ACC Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57
7.3 Low V
CC
 Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57
7.4 Write Pulse “Glitch Protection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.5 Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1 Standby Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  59
2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  59

  January 25, 2005  S29WS-N_00_G0 S29WS-N MirrorBit™ Flash Family 3
Advance Information
3 Hardware RESET# Input Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  59
4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
1 Factory Secured Silicon
 
Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3 Secured Silicon Sector Entry and Secured Silicon Sector Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . .61
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
1 Absolute Maximum Ratings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  63
2 Operating Ranges  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  64
3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  64
4 Key to Switching Waveforms   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  65
5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6 V
CC
 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  66
7 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  67
8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.1. CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.2 Synchronous/Burst Read  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.4 AC Characteristics—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  72
8.5 Hardware Reset (RESET#)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  74
8.6 Erase/Program Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  75
8.7 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  85
8.8 BGA Ball Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Commonly Used Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Revisions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4 S29WS-N MirrorBit™ Flash Family S29WS-N_00_G0   Januar y 25, 2005  
Advance Information
Figures
Figure 3.1. S29WS- N Blo ck Diagram..................................................................................................................... 8
Figure 4.1. 84-ball Fine-Pitch Ball Grid Array (S29WS25 6N, S29WS128N).................................................................10
Figure 4.2. VBH084—84-ball F ine -Pitch Ball G rid Array (FBG A) 8 x 11.6 mm MCP Compatible Pack age .........................11
Figure 4.3. 80-ball Fine -Pitch Ball Grid Array (S29WS064N)........................................... .........................................12
Figure 4.4. TLC080—80-ball Fine-Pitch  Ball Grid Array (FBGA)  7 x 9 mm MCP Compatible Pa c k age...............................13
Figure 4.5. MCP Look- ahe ad Diagr am ..................................................................................................................15
Figure 7.1. Synchron ous/A syn ch ron ou s State  Diagram...........................................................................................21
Figure 7.2. Synchron ous Re ad ................................................................................... ................. ........................23
Figure 7.3. Single Wor d Pro gram................................................................................................. ........................29
Figure 7.4. Write Buffer Prog ramming Operation ...................................................................................................33
Figure 7.5. Sector Erase O peration......................................................................................................................36
Figure 7.6. Write Operation S tatus Flow char t........................................................................................................43
Figure 8.1. Advanced Secto r Protection/Unprotection.............................................................................................50
Figure 8.2. PPB Progr am /Er ase  Algorithm......................................................................................... ....................53
Figure 8.3. Lock Regis ter Pr ogra m  Algorithm.........................................................................................................56
Figure 11.1. Maximum Neg a tive  Overshoot Waveform ................................................................................ .............64
Figure 11.2. Maximum Positive  Overshoot Waveform...............................................................................................64
Figure 11.3. Test Setup ................................................................. ........................................ ..............................64
Figure 11.4. Input Waveforms and Measure ment Levels...........................................................................................66
Figure 11.5. V
CC
 Power-up  Diagram ............................................................................. .........................................66
Figure 11.6. CLK Characterization ................................................................................ ............... ..........................68
Figure 11.7. CLK Syn c hronous B urst Mode Read......................................................................................................70
Figure 11.8. 8-word L inear Burst w ith  Wrap Around.................................................................................................71
Figure 11.9. 8-word Linear Burst w ithou t Wrap  Around ............................................................................................71
Figure 11.10. Linear Burst with RD Y Set On e Cycle Befor e Data..................................................................................72
Figure 11.11. Asynchrono us M od e Read...................................................................................................................73
Figure 11.12. Reset Timing s..................................................................................................... ..............................74
Figure 11.13. Chip/Secto r Erase Op eratio n Tim ings............................. .................................................. ....................76
Figure 11.14. Asynchr onous Program Operation Timings............................................................................................77
Figure 11.15. Synchron ous Pro gr am  Ope ration Tim ings .............................................................................................78
Figure 11.16. Accelera ted Un lock  Byp ass Pr ogr am m ing  Tim ing ...................................................................................79
Figure 11.17. Data# Polling  Timin gs (D uring  E m bed de d Algorith m).............................................................................79
Figure 11.18. Toggle  Bit Timings  (D uring E mbedd ed Algorithm )..................................................................................80
Figure 11.19. Synchron ous Da ta Polling T iming s/To gg le Bit Tim ing s ............................................................... .............80
Figure 11.20. DQ2 vs. DQ6....................................................................................................... .............................81
Figure 11.21. Latency with Boundary Cross ing when Frequency >  66 MHz....................................................................81
Figure 11.22. Latency with Boundary Cross ing into Prog ram/Erase  Bank......................................................................82
Figure 11.23. Example of W ait States Ins ertion ........................................................................................................83
Figure 11.24. Back-to-Back  Read /W rite Cycle Tim in gs............................................................................. ..................84

  January 25, 2005  S29WS-N_00_G0 S29WS-N MirrorBit™ Flash Family 5
Advance Information
Ta b l e s
Table 2.1. Input/Output D escriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . .7
Table 6.1. S29WS256N Sector & Memo ry Address Map . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . .  .17
Table 6.2. S29WS128N Sector & Memo ry Address Map . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . .  .18
Table 6.3. S29WS064N Sector & Memo ry Address Map . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . .  .19
Table 7.1. Device Ope rations  . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . .20
Table 7.2. Address Latency (S29WS256N)   . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.3. Address Latency (S29WS128N/S29WS 064N)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 7.4. Address/Boun dary Crossin g Latency (S29WS256N @ 80/66 MH z) . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .22
Table 7.5. Address/Boundary Crossing Laten cy (S29WS256N @  54M Hz) . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .22
Table 7.6. Address/Boun dary Crossin g Latency (S29WS128N/S29WS064N)  . . . . . . . . . . . . . .  . . . . . . . . . . .  . . . . . . . .23
Table 7.7. Burst Address Groups  . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7.8. Co nfiguration R egister  . . . . . . . . . . . . .  . . . . . . . . . . .  . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . .25
Table 7.9. Au toselect Addresses . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . .  . . . . . . . .26
Table 7.10. A utoselect Entry  . . . . . . . . . . .  . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . .26
Table 7.11. A utoselect Exit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .26
Table 7.12. S ingle Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 7.13. Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 7.14. S ec t or Erase . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .35
Table 7.15. Chip  Erase  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .37
Table 7.16. Erase Suspend  . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .38
Table 7.17. Erase Resu me . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 7.18. Program S uspend  . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 7.19. Pr ogram R es ume . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .39
Table 7.20. Unlock Bypass Entry  . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . .40
Table 7.21. Unlock Bypas s  Program   . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .40
Table 7.22. Unlock Bypas s  Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . .41
Table 7.23. DQ6 and D Q 2 Indicatio ns  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .45
Table 7.24. W rite Operation Status . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .46
Table 7.25. Re set . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 8.1. Lo ck Registe r  . . . . . . . . .  . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 8.2. Se ctor Protection Sch emes . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .57
Table 10.1.  Secured Silicon Sec tor Addre sses . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .60
Table 10.2. Secured Silicon S ec t or Entry . . . . . . . . . . . . .  . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 10.3. Secured Silicon S ec t or Program   . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 10.4. Secured Silicon S ec t or Exit . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .62
Table 11.1. Te st Specifications . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 12.1.  M emory Array Commands  . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . .88
Table 12.2. S ec t or Protection  Commands  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 12.3. CFI Query Identification String   . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .90
Table 12.4. S y stem Interface String . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . .90
Table 12.5. Device Geometry Definition  . . . . . . . .  . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . .91
Table 12.6. Pr imary Vend or-Specific Ex tended Query  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . .92

6 S29WS-N MirrorBit™ Flash Family S29WS-N_00_G0 January 25, 2005

Advance Information

1 Ordering Information

The ordering part number is formed by a valid combination of the following:

S29WS 256 N 0S BA W 01 0

PACKING TYPE

0 = Tray (standard; see note 1)

2 = 7-inch Tape and Reel

3 = 13-inch Tape and Reel

MODEL NUMBER (Note 3)

(Package Ball Count, Package Dimensions, DYB Protect/Unprotect After

Power-up)

01 = 84-ball, 8 x 11.6 mm, DYB Unprotect

11 = 80-ball, 7 x 9 mm, DYB Protect

TEMPERATURE RANGE (Note 3)

W = Wireless (–25

C to +85

I = Industrial (–40

C to +85

C, contact factory for availability)

PACKAGE TYPE AND MATERIAL

BA = Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package

BF = Very Thin Fine-Pitch BGA, Lead (Pb)-free Package

SPEED OPTION (BURST FREQUENCY)

0S = 80 MHz (contact factory for availability)

0P = 66 MHz

0L = 54 MHz

PROCESS TECHNOLOGY

N = 110 nm MirrorBit™ Technology

FLASH DENSIT Y

256 = 256 Mb

128 = 128 Mb

064 = 64 Mb

DEVICE FAMILY

S29WS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

S29WS-N Valid Combinations (Notes 1, 2, 3)

VIO Range DY B Powe r

Up State

Package Type

(Note 2)

Base Ordering

Part Number

Product

Status

Speed

Option

Package Type,

Material, &

Temperature Range

Model

Number

Packing

Ty p e

S29WS256N Preliminary

0S, 0P, 0L BAW (

Lead (Pb)-free

Compliant),

BFW (

Lead (Pb)-free)

0, 2, 3

(Note 1) 1.70–1.95 V

Unprotect 8 mm x 11.6 mm

84-ball

MCP-Compatible

11 Protect

S29WS128N Advance 01 Unprotect

11 Protect

S29WS064N Advance 01 Unprotect 7 mm x 9 mm

80-ball

MCP-Compatible

11 Protect

Notes:

1. Type 0 is standard. Specify other options as required.

2. BGA package marking omits leading “S29” and packing type

designator from ordering part number.

3. For 1.5 VIO option, oth er boo t options, or ind ustrial te mperature

range, contact your local sales office.

lid

Com

nat

ons

V alid Combinations list configurations planned to be supported in vol-

ume for this device. Consult your local sales office to confirm avail-

ability of specific valid combinations and to check on newly released

combinations.

January 25, 2005 S29WS-N_00_G0 S29WS-N MirrorBit™ Flash Family 7

Advance Information

2 Input/Output Descriptions & Logic Symbol

Table identifies the input and output package connections provided on the device.

Table 2.1. Input/Output Descriptions

Symbol Type Description

A23–A0 Input Address lines for WS256N (A22-A0 for WS128 and A21-A0 for WS064N).

DQ15–DQ0 I/O Data input/output.

CE# Input Chip Enable. Asynchronous relativ e to CLK.

OE# Input Output Enable. Asy nc hronous relative to CLK.

WE# Input Write Enable.

VCC Supply Device Powe r Supply.

VIO Input Versatile IO In pu t. Should be tied to V CC.

VSS I/O Ground.

NC No Connect Not connected internally.

RDY Output Ready. Indicates when valid burst data is ready to be read.

CLK Input Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK

increment the internal address counter. Should be at VIL or VIH while in asynchronous

mode.

AVD# Input

Address V alid. I ndicates to device that the valid address is present on the address inputs.

When low during asynchronous mode, indi cates valid address; when low during burst

mode, causes starting address to be latched at the next active clock edge.

When high, device ignores address inputs.

RESET# Input Hardware Reset. Low = device resets and returns to reading array data.

WP# Input Write Protect. At VIL, disables progra m and er ase func tions in the four outermost sectors.

Should be at VIH for all other conditions.

ACC Input Acceleration In pu t. A t V HH, accelerates programming; automatically places device in

unlock bypass mode. At V IL, disables all program and er ase functions. Should be at VIH for

all other conditions.

RFU Reserved Reserved for future use (see MCP look-ahead pinout for us e with MCP).

8 S29WS-N MirrorBit™ Flash Family S29WS-N_00_G0 January 25, 2005

Advance Information

3 Block Diagram

Figure 3.1. S29WS-N Block Diagram

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

Detector

State

Control

Command

WE#

RESET#

WP#

ACC

CE#

OE#

DQ15–DQ0

Data

Latch

Y-Gating

Cell Matrix

Address Latch

max

–A0*

RDY

Buffer RDY

Burst

State

Control

Burst

Address

Counter

AVD#

CLK

* WS256N: A23-A0

WS128N: A22-A0

WS064N: A21-A0

January 25, 2005 S29WS-N_00_G0 S29WS-N MirrorBit™ Flash Family 9

Advance Information

4 Physical Dimensions/Connection Diagrams

This section shows the I/O designations and package specifications for the S29WS-N.

4.1 Related Documents

The following documents contain information relating t o the S 29WS -N devices. Cli ck on th e title

or go to www.amd.com/flash (click on Technical Documentation) or www.fujitsu.com to download

the PDF file, or request a copy from your sales office.

Migration to the S29WS256N Family Application Note

Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits

4.2 Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth-

ods. The package and/or data integrity may be compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of time.

10 S29WS-N MirrorBit™ Flash Family S29WS-N_00_G0 January 25, 2005

Advance Information

Figure 4.1. 84-ball Fine-Pitch Ball Grid Array (S29WS256N, S29WS128N)

DQ8 DQ14

RFU

RFU ACC WE# A8 A11

C3 C4 C5 C6 C7 C8

A6 RFU RESET# RFU A19 A12 A15

D2 D3 D4 D5 D6 D7 D8 D9

A5 A18 RDY A20 A9 A13 A21

E2 E3 E4 E5 E6 E7 E8 E9

A1 A4 A17 A10 A14 A22

F2 F3 F4 F7 F8 F9

DQ1A0 DQ6 RFU A16

G3 G4G2 G7 G8 G9

CE#f1

DQ0

OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU

H2 H3 H4 H5 H6 H7 H8 H9

DQ10 V

RFU DQ12 DQ7 V

J2 J3 J4 J5 J6 J7 J8 J9

DQ2 DQ11 RFU DQ5

K3 K8

K4 K5 K6 K7

RFU A23

RFU RFU

RFU CLK RFU RFU RFU RFU

B3 B4 B5 B6 B7 B8

RFU RFU V

RFU RFU RFU

L3 L4 L5 L6 L7 L8

B2 B9

K2 K9

L9L2

AVD# RFU

RFU

WP#

RFU

A1 A10

M1 M10

Ball F6 is RFU on

128 Mb device.

84-Ball Fine-Pitch Ball Grid Array, 256 & 128 Mb

(Top View, Balls Facing Down,

MCP Compatible)

January 25, 2005 S29WS-N_00_G0 S29WS-N MirrorBit™ Flash Family 11

Advance Information

4.2.1 VBH084—84-ball Fine-Pitch Ball Grid Array, 8 x 11.6 mm

Note: BSC is an ANSI standard for Basic Space Centering

Figure 4.2. VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package

3339 \ 16-038.25b

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

PACKAGE VBH 084

JEDEC N/A

11.60 mm x 8.00 mm NOM

PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.00 OVERALL THICKNESS

A1 0.18 --- --- BALL HEIGHT

A2 0.62 --- 0.76 BODY THICKNESS

D 11.60 BSC. BODY SIZE

E 8.00 BSC. BODY SIZE

D1 8.80 BSC. BALL FOOTPRINT

E1 7.20 BSC. BALL FOOTPRINT

MD 12 ROW MATRIX SIZE D DIRECTION

ME 10 ROW MATRIX SIZE E DIRECTION

N 84 TOTAL BALL COUNT

φb 0.33 --- 0.43 BALL DIAMETER

e 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

(A2-A9, B10-L10, DEPOPULATED SOLDER BALLS

M2-M9, B1-L1)

BOTTOM VIEW

TOP VIEW

SIDE VIEW

A1 CORNER

ML JK

C0.05

(2X)

C0.05

BACEDFHG

BCA

φ 0.15

φ 0.08 M

0.10 C

C0.08

NXφb

SEATING PLANE

A1 CORNER

INDEX MARK

12 S29WS-N MirrorBit™ Flash Family S29WS-N_00_G0 January 25, 2005

Advance Information

Figure 4.3. 80-ball Fine-Pitch Ball Grid Array (S29WS064N)

DQ8 DQ14

RFU

RFU ACC WE# A8 A11

B2 B3 B4 B5 B6 B7

A6 RFU RESET# RFU A19 A12 A15

C1 C2 C3 C4 C5 C6 C7 C8

A5 A18 RDY A20 A9 A13 A21

D1 D2 D3 D4 D5 D6 D7 D8

A1 A4 A17 A10 A14 RFU

E1 E2 E3 E6 E7 E8

DQ1A0 DQ6 RFU A16

F2 F3F1 F6 F7 F8

CE#f1

DQ0

OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU

G1 G2 G3 G4 G5 G6 G7 G8

DQ10 V

RFU DQ12 DQ7 V

H1 H2 H3 H4 H5 H6 H7 H8

DQ2 DQ11 RFU DQ5

J2 J7

J3 J4 J5 J6

RFU RFU

RFU CLK RFU RFU RFU RFU

A2 A3 A4 A5 A6 A7

RFU RFU V

RFU RFU RFU

K2 K3 K4 K5 K6 K7

A1 A8

J1 J8

K8K1

AVD# RFU

RFU

WP#

RFU

80-ball Fine-Pitch Ball Grid Array, 64 Mb

(Top View, Balls Facing Down,

MCP Compatible)

January 25, 2005 S29WS-N_00_G0 S29WS-N MirrorBit™ Flash Family 13

Advance Information

4.2.2 TLC080—80-ball Fine-Pitch Ball Grid Array, 7 x 9 mm

Note: BSC is an ANSI standard for Basic Space Centering

Figure 4.4. TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm MCP Compatible Package

3430 \ 16-038.22 \ 10.15.04

PACKAGE TLC 080

JEDEC N/A

D x E 9.00 mm x 7.00 mm

PACKAGE

SYMBOL MIN NOM MAX NOTE

A --- --- 1.20 PROFILE

A1 0.17 --- --- BALL HEIGHT

A2 0.81 --- 0.97 BODY THICKNESS

D 9.00 BSC. BODY SIZE

E 7.00 BSC. BODY SIZE

D1 7.20 BSC. MATRIX FOOTPRINT

E1 5.60 BSC. MATRIX FOOTPRINT

MD 10 MATRIX SIZE D DIRECTION

ME 8 MATRIX SIZE E DIRECTION

n 80 BALL COUNT

φb 0.35 0.40 0.45 BALL DIAMETER

eE 0.80 BSC. BALL PITCH

eD 0.80 BSC BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

NOTES:

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

"E" DIRECTION.

n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE

OUTER ROW SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

0.08

0.20 C

0.15

(2X)

0.15

(2X)

INDEX MARK

TOP VIEW

SIDE VIEW

CORNER

80X

0.15 M C

0.08

PIN A1

DCEFGH

PIN A1

CORNER

BOTTOM VIEW

14 S29WS-N MirrorBit™ Flash Family S29WS-N_00_G0 Januar y 25, 2005

Advance Information

4.3 MCP Look-ahead Connection Diagram

Figure 4.5 shows a migration path from the S29WS-N to higher densities and the option to include

additional die within a single package. Spansion LLC provides this standard look -ahead connection

diagram that supports

NOR Flash and SRAM densities up to 4 Gigabits

NOR Flash and pSRAM densities up to 4 Gigabits

NOR Flash and pSRAM and data storage densities up to 4 Gigabits

The following multi-chip package (MCP) data sheet(s) are based on the S29WS-N. Refer to these

documents for input/output descriptions for each product:

Publication Number S71WS256_512NC0.

The physical package outline may v ary between connection diagr ams and densities. The connec -

tion diagram for any MCP, however, is a subset of the pinout in Figure 4.5.

In some cases, outrigger balls may exist in locations outside the grid shown. These outrigger balls

are reserved; do not connect them to any other signal.

For further information about the MCP look-ahead pinout, refer to the Design-In Scalable Wireless

Solutions with Spansion Products application note, available on the web or through an AMD or

Fujitsu sales office.

January 25, 2005 S29WS-N_00_G0 S29WS-N MirrorBit™ Flash Family 15

Advance Information

Figure 4.5. MCP Look-ahead Diagram

J4 J5 J6 J7 J8 J2

H7 H8 H9

G7 G8 G9

F7 F8 F9

E7 E8 E9

K2 K3

D6 D7

CE#f1

OE#

CE1#s1 DQ0

D2 D3

C2 C3

AVD# VSSds

WP# A7 A8WE#WP/ACCLB#s

C4 C5

C6 C7

D8 D9

CE1#dsA11

C8 C9

RY/BY#dsCLKdsRESET#dsVCCdsCE#f2CLK

A15A12A19

A21A13A9

A22A14A10

A16 A24DQ6

CE2s1

A20

A23

CE2s2

H4 H5

G4 G5

F4 F5

RESET#fUB#s

RDYA18

CE1#s2A17

VCCs2DQ1

CREsDQ15DQ13DQ4DQ3DQ9

K4 K5

K7 K8 K9

DQ7VCCs1VCCfDQ10

H2 H3

G2 G3

F2 F3

E2 E3

A6A3

A5A2

A4A1

VSSA0

L4 L5 L6 L7 L8 L9

M2 M3

VCCnds DQ8

A27 A26

VSSDQ12

LOCK

or WP#/ACCds

DQ14DQ5A25DQ11DQ2

M5 M6 M7 M8 M9

or VCCQds

VCCQs1CE2#dsVCCfVSSnds DNU

N10

Legend:

Data-storage Only

Shared

or NC (not connected)

Flash Shared Only

1st Flash Only

2nd Flash Only

K5 K6

B10

A10

P10

1st RAM Only

2nd RAM Only

RAM Shared Only

DoC Only

NC or ds

96-ball Fine-Pitch Ball Grid Array

(Top View, Balls Facing Down)

J4 J5 J6 J7 J8 J2

H7 H8 H9

G7 G8 G9

F7 F8 F9

E7 E8 E9

K2 K3

D6 D7

CE#f1

OE#

CE1#s1 DQ0

D2 D3

C2 C3

AVD# VSSds

WP# A7 A8WE#WP/ACCLB#s

C4 C5

C6 C7

D8 D9

CE1#dsA11

C8 C9

RY/BY#dsCLKdsRESET#dsVCCdsCE#f2CLK

A15A12A19

A21A13A9

A22A14A10

A16 A24DQ6

CE2s1

A20

A23

CE2s2

H4 H5

G4 G5

F4 F5

RESET#fUB#s

RDYA18

CE1#s2A17

VCCs2DQ1

CREsDQ15DQ13DQ4DQ3DQ9

K4 K5

K7 K8 K9

DQ7VCCs1VCCfDQ10

H2 H3

G2 G3

F2 F3

E2 E3

A6A3

A5A2

A4A1

VSSA0

L4 L5 L6 L7 L8 L9

M2 M3

VCCnds DQ8

A27 A26

VSSDQ12

LOCK

or WP#/ACCds

DQ14DQ5A25DQ11DQ2

M5 M6 M7 M8 M9

or VCCQds

VCCQs1CE2#dsVCCfVSSnds DNU

N10

Legend:

Data-storage Only

Shared

or NC (not connected)

Flash Shared Only

1st Flash Only

2nd Flash Only

K5 K6

B10

A10

P10

1st RAM Only

2nd RAM Only

RAM Shared Only

DoC Only

NC or ds

16 S29WS-N_00_G0  January 25, 2005
Advance Information
5 Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Understanding Burst Mode Flash Memory Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Spansion Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers
Enhanced Flash drivers
Flash file system
CAD Modeling Support
VHDL and Verilog
IBIS
ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical support:
Email 
US and Canada: HW.support@amd.com 
Asia Pacific: asia.support@amd.com 
Europe, Middle East, and Africa 
Japan: http://edevice.fujitsu.com/jp/support/tech/#b7
Frequently Asked Questions (FAQ) 
http://ask.amd.com/ 
http://edevice.fujitsu.com/jp/support/tech/#b7
Phone 
US: (408) 749-5 703 
Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453 
Sunnyva le , CA 94088 -3 453 , USA  
Telephone: 408-962-2500 or 
1-866-SPANSION 
Spansion Japan Limited 
4-33-4 Nishi Shinjuku, Shinjuku-ku 
Tokyo, 160-0023 
Telephone: +81-3-5302-2200 
Facsimile: +81-3-5302-2674
http://www.spansion.com

January 25, 2005 S29WS-N_00_G0 17

Advance Information

6 Product Overview

The S29WS-N family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/write

burst mode Flash device optimized for today’s wireless designs that demand a large storage array,

rich functionality, and low power consumption.

These devices are organized in 16, 8 or 4 Mwords of 16 bit s each and are capa ble of continuous,

synchronous (bu rst) read or li near read (8-, 16 -, or 32-wo rd aligned grou p) with or with out wrap

around. These products also offer single word progra mming or a 32-word b uffer for progr amming

with program/erase and suspend functionality. Additional features include:

Advanced Sector Protection methods for protecting sectors as required

256 words of Secured Silicon area for storing customer and factory secured information.

The Secured Silicon Sector is One Time Programmable.

6.1 Memory Map

The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables 6.1–6.3.

Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their

address ranges that are not explicitly listed (such as SA005–SA017) have sector starting and ending addresses that form the same

pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.

Table 6.1. S29WS256N Sector & Memory Address Map

Bank

Size

Sector

Count

Sector Size

(KB) Bank

Sector/

Sector Range Address Range Notes

2 MB 432 0

SA000 000000h–003FFFh

Contains four smaller sectors at

bottom of addressable memory.

SA001 004000h–007FFFh

SA002 008000h–00BFFFh

SA003 00C000h–00FFFFh

15 128 SA004 to SA018 010000h–01FFFFh to 0F0000h–0FFFFFh

All 128 KB sectors.

Pattern for sector address r ange

is xx0000h–xxFFFFh.

(see note)

2 MB 16 128 1 SA019 to SA034 100000h–10FFFFh to 1F0000h–1FFFFFh

2 MB 16 128 2 SA035 to SA050 200000h–20FFFFh to 2F0000h–2FFFFFh

2 MB 16 128 3 SA051 to SA066 300000h–30FFFFh to 3F0000h–3FFFFFh

2 MB 16 128 4 SA067 to SA082 400000h–40FFFFh to 4F0000h–4FFFFFh

2 MB 16 128 5 SA083 to SA098 500000h–50FFFFh to 5F0000h–5FFFFFh

2 MB 16 128 6 SA099 to SA114 600000h–60FFFFh to 6F0000h–6FFFFFh

2 MB 16 128 7 SA115 to SA130 700000h–70FFFFh to 7F0000h–7FFFFFh

2 MB 16 128 8 SA131 to SA146 800000h–80FFFFh to 8F0000h–8FFFFFh

2 MB 16 128 9 SA147 to SA162 900000h–90FFFFh to 9F0000h–9FFFFFh

2 MB 16 128 10 SA163 to SA178 A00000h–A0FFFFh to AF0000h–AFFFFFh

2 MB 16 128 11 SA179 to SA194 B00000h–B0FFFFh to BF0000h–BFFFFFh

2 MB 16 128 12 SA195 to SA210 C00000h–C0FFFFh to CF0000h–CFFFFFh

2 MB 16 128 13 SA211 to SA226 D00000h–D0FFFFh to DF0000h–DFFFFFh

2 MB 16 128 14 SA227 to SA242 E00000h–E0FFFFh to EF0000h–EFFFFFh

2 MB

15 128

SA243 to SA257 F00000h–F0FFFFh to FE0000h–FEFFFFh

432

SA258 FF0000h–FF3FFFh

Contains four smaller sectors at

top of addres sa ble me mor y.

SA259 FF4000h–FF7FFFh

SA260 FF8000h–FFBFFFh

SA261 FFC000h–FFFFFFh

18 S29WS-N_00_G0 January 25, 2005

Advance Information

Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their

address ranges that are not explicitly listed (such as SA005–SA009) have sector starting and ending addresses that form the same

pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.

Table 6.2. S29WS128N Sector & Memory Address Map

Bank Size

Sector

Count

Sector Size

(KB) Bank

Sector/

Sector Range Address Range Notes

1 MB 4

SA000 000000h–003FFFh

Contains four smaller sectors at

bottom of addressable memory.

32 SA001 004000h–007FFFh

32 SA002 008000h–00BFFFh

32 SA003 00C000h–00FFFFh

7128 SA004 to SA010 010000h–01FFFFh to 070000h–07FFFFh

All 128 KB sectors.

Pattern for sector address range

is xx0000h–xxFFFFh.

(see note)

1 MB 8128 1 SA011 to SA018 080000h–08FFFFh to 0F0000h–0FFFFFh

1 MB 8128 2 SA019 to SA026 100000h–10FFFFh to 170000h–17FFFFh

1 MB 8128 3 SA027 to SA034 180000h–18FFFFh to 1F0000h–1FFFFFh

1 MB 8128 4 SA035 to SA042 200000h–20FFFFh to 270000h–27FFFFh

1 MB 8128 5 SA043 to SA050 280000h–28FFFFh to 2F0000h–2FFFFFh

1 MB 8128 6 SA051 to SA058 300000h–30FFFFh to 370000h–37FFFFh

1 MB 8128 7 SA059 to SA066 380000h–38FFFFh to 3F0000h–3FFFFFh

1 MB 8128 8 SA067 to SA074 400000h–40FFFFh to 470000h–47FFFFh

1 MB 8128 9 SA075 to SA082 480000h–48FFFFh to 4F0000h–4FFFFFh

1 MB 8128 10 SA083 to SA090 500000h–50FFFFh to 570000h–57FFFFh

1 MB 8128 11 SA091 to SA098 580000h–58FFFFh to 5F0000h–5FFFFFh

1 MB 8128 12 SA099 to SA106 600000h–60FFFFh to 670000h–67FFFFh

1 MB 8128 13 SA107 to SA114 680000h–68FFFFh to 6F0000h–6FFFFFh

1 MB 8128 14 SA115 to SA122 700000h–70FFFFh to 770000h–77FFFFh

1 MB

7128

SA123 to SA129 780000h–78FFFFh to 7E0000h–7EFFFFh

32 SA130 7F0000h–7F3FFFh

Contains four smaller sectors at

top of addressable memory.

32 SA131 7F4000h–7F7FFFh

32 SA132 7F8000h–7FBFFFh

32 SA133 7FC000h–7FFFFFh

January 25, 2005 S29WS-N_00_G0 19

Advance Information

Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their

address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same

pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.

Table 6.3. S29WS064N Sector & Memory Address Map

Bank Size

Sector

Count

Sector Size

(KB) Bank

Sector/

Sector Range Address Range Notes

0.5 MB

432

SA000 000000h–003FFFh

Contains four smaller sectors at

bottom of addressable memory.

SA001 004000h–007FFFh

SA002 008000h–00BFFFh

SA003 00C000h–00FFFFh

128

SA004 010000h–01FFFFh

All 128 KB sectors.

Patter n for sector a ddress r ang e is

xx0000h–xxFFFFh.

(see note)

SA005 020000h–02FFFFh

SA006 030000h–03FFFFh

0.5 MB 4128 1 SA007–SA010 040000h–04FFFFh to 070000h–07FFFFh

0.5 MB 4128 2 SA011–SA014 080000h–08FFFFh to 0B0000h–0BFFFFh

0.5 MB 4128 3 SA015–SA018 0C0000h–0CFFFFh to 0F0000h–0FFFFFh

0.5 MB 4128 4 SA019–SA022 100000h–10FFFFh to 130000h–13FFFFh

0.5 MB 4128 5 SA023–SA026 140000h–14FFFFh to 170000h–17FFFFh

0.5 MB 4128 6 SA027–SA030 180000h–18FFFFh to 1B0000h–1BFFFFh

0.5 MB 4128 7 SA031–SA034 1C0000h–1CFFFFh to 1F0000h–1FFFFFh

0.5 MB 4128 8 SA035–SA038 200000h–20FFFFh to 230000h–23FFFFh

0.5 MB 4128 9 SA039–SA042 240000h–24FFFFh to 270000h–27FFFFh

0.5 MB 4128 10 SA043–SA046 280000h–28FFFFh to 2B0000h–2BFFFFh

0.5 MB 4128 11 SA047–SA050 2C0000h–2CFFFFh to 2F0000h–2FFFFFh

0.5 MB 4128 12 SA051–SA054 300000h–30FFFFh to 330000h–33FFFFh

0.5 MB 4128 13 SA055–SA058 340000h–34FFFFh to 370000h–37FFFFh

0.5 MB 4128 14 SA059–SA062 380000h–38FFFFh to 3B0000h–3BFFFFh

0.5 MB

3128

SA063 3C0000h–3CFFFFh

SA064 3D0000h–3DFFFFh

SA065 3E0000h–3EFFFFh

432

SA066 3F0000h–3F3FFFh

Contains four smaller sectors at top

of addressable memory.

SA067 3F4000h–3F7FFFh

SA068 3F8000h–3FBFFFh

SA069 3FC000h–3FFFFFh

20 S29WS-N_00_G0 January 25, 2005

Advance Information

7 Device Operations

This section describes the read, program, erase, simultaneous read/write oper ations, handshak-

ing, and reset features of the Flash devices.

Operations are initiated by writing specific commands or a sequence with specific address and

data patterns into the command registers (see Tables 12.1 and 12.2). The command register itself

does not occupy any addressable memory location; rather, it is composed of latches that store

the commands, along with the address and data information needed to execute the command.

The contents of the register serve as input to the internal state machine and the state machine

outputs dictate the function of the device. Writing incorrect address and data values or writing

them in an improper sequence may place the devi ce in an unknown state, in which case the sys-

tem must write the reset command to return the device to the reading array data mode.

7.1 Device Operation Table

The device must be setup appropriately for each operation. Table 7.1 describes the required state

of each control pin for any particular operation.

Table 7.1. Device Operations

Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.

7.2 Asynchronous Read

All memories require access time to output array data. In an asynchronous read operation, data

is read from one memory location at a time. Addresses are presented to the device in random

order, and the propagation delay through the device causes the data on its outputs to arrive asyn-

chronously with the address on its inputs.

The device defaults t o reading array data asynchronously after device power-up or hardware re-

set. Asynchronous read requires that the CLK signal remain at VIL during the entire memory read

operation. To read data from the memory array, the system must first assert a valid address on

Amax– A0, while driving A VD# and CE# to VIL. WE# must remain at VIH. The rising edge of A VD#

latches the address. The OE# signal must be driven to VIL, once AV D# has been driven to VIH.

Operation

CE# OE# WE# Addresses DQ15–0 RESET# CLK AVD#

Asynchrono us Read - Addresses Latc he d L L H Addr I n Data Out H X

Asynchrono us Read - Addresses St eady State L L H Addr In D ata Out H X L

Asynchronous Write L H L Addr In I/O H X L

Synchr onous Write L H L Addr In I/O H

Standby (C E#) H X X X HIGH Z H X X

Hardwa re R e set X X X X HIGH Z L X X

Burst Read Operations (Synchronous)

Load Starting Burst Address L X H Addr In X H

Advance Burst to next addre ss with appropriate

Data presente d on the Data Bus LLH X Burst

Data Out HH

Terminate current Burst read cycle H X H X HIGH Z H X

Terminate current Burst read cycle via RESET# X X H X HIGH Z L X X

Terminate current Burst read cycle and start new

Burst read cycle LXHAddr In I/O H

January 25, 2005 S29WS-N_00_G0 21

Advance Information

Data is output on A/DQ15-A/DQ0 pins after the access time (tOE) has elapsed from the falling

edge of OE#.

7.3 Synchronous (Burst) Read Mode &

Configuration Register

When a series of adjacent addresses needs to be read from the device (in order from lowest to

highest address), the synchronous (or burst read) mode can be used to significantly reduce the

overall time needed for the d evice to output a rray data. After an initial acce ss time required for

the data from the first address location, subsequent data is output synchronized to a clock input

provided by the system.

The device offers both continuous and linear methods of burst read operation, which are dis-

cussed in subsections 7.3.3 and 7.3.4, and 7.3.5.

Since the device defaults to asynchronous read mode after power-up or a hardware reset, the

configuration register must be set to enable the burst read mode . Other Configuration Register

settings include the number of wait states to insert before the initial word (tIACC) of each burst

access, the burst mode in which to operate, and when RDY indicates data is ready to be read.

Prior to entering the burst mode, the system should first determine the configuration register set-

tings (and read the current register settings if desired via the Read Configuration Register

command sequence), and then write the configuration register command sequence. See Section

7.3.6, Configuration R egister, and Table 12.1, Memory Array Comma nds for further details.

Figure 7.1. Synchronous/Asynchronous State Diagram

The device outputs the initial word subject to the following operational conditions:

tIACC specification: the time from the ris ing edge of the first clock cycle after addresses

are latched to valid data on the device outputs.

configuration register setting CR13–CR11: the total number of clock cycles (wait states)

that occur before valid data appears on the device outputs. The effect is that tIACC is

lengthened.

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Synchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(CR15 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(CR15 = 1)

22 S29WS-N_00_G0 January 25, 2005

Advance Information

The device outputs subsequent words tBACC after the active edge of each successive clock cycle,

which also increments the internal address counter. The device outputs burst data at this rate sub-

ject to the following operational conditions:

starting address: whether the address is divisible by four (where A[1:0] is 00). A divisi-

ble-by-four address incurs the least number of additional wait states that occur after the

initial word. The number of additional wait states required increases for burst operations

in which the starting address is one, two, or three locations above the divisible-by-four

address (i.e., where A[1:0] is 01, 10, or 11).

boundary crossing: There is a boundary at every 128 words due to the internal architec-

ture of the device. One additional wait state must be inserted when crossing this boundary

if the memory bus is operating at a high clock frequency. Please refer to the tables below .

clock frequency: the speed at which the device is expected to burst data. Higher speeds

require additional wait states after the initial word for proper operation.

In all cases, with or without latency, the RDY output indicates when the next data is available to

be read.

Tables 7.2-7.6 reflect wait states required for S29WS256/128/064N devices. Refer to the “Con-

figuration Register” table (CR11 - CR14) and timing diagrams for more details.

Ta b l e 7 . 2 . Address Latency (S29WS256N)

Ta b l e 7 . 3 . Address Latency (S29WS128N/S29WS064N)

Ta b l e 7 . 4 . Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz)

Ta b l e 7 . 5 . Address/Boundary Crossing Latency (S29WS256N @ 54MHz)

Word Wait States Cycle

0 x ws D0 D1 D2 D3 D4 D5 D6 D7 D8

1 x ws D1 D2 D3 1 ws D4 D5 D6 D7 D8

2 x ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8

3 x ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8

Word Wait States Cycle

0 5, 6, 7 ws D0 D1 D2 D3 D4 D5 D6 D7 D8

1 5, 6, 7 ws D1 D2 D3 1 ws D4 D5 D6 D7 D8

2 5, 6, 7 ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8

3 5, 6, 7 ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8

Word Wait States Cycle

0 7, 6 ws D0 D1 D2 D3 1 ws D4 D5 D6 D7

1 7, 6 ws D1 D2 D3 1 ws 1 ws D4 D5 D6 D7

2 7, 6 ws D2 D3 1 ws 1 ws 1 ws D4 D5 D6 D7

3 7, 6 ws D3 1 ws 1 ws 1 ws 1 ws D4 D5 D6 D7

Word Wait States Cycle

0 5 ws D0 D1 D2 D3 D4 D5 D6 D7 D8

1 5 ws D1 D2 D3 1 ws D4 D5 D6 D7 D8

2 5 ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8

3 5 ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8

January 25, 2005 S29WS-N_00_G0 23

Advance Information

Ta b l e 7 . 6 . Address/Boundary Crossing Latency (S29WS128N/S29WS064N)

Figure 7.2. Synchronous Read

7.3.3 Continuous Burst Read Mode

In the continuous burst read mode, the device outputs sequential burst data from the starting

address given and then wrap around to address 000000h when it reaches the highest addressable

memory location. The burst read mode continues until the system drives CE# high, or RESET=

Word Wait States Cycle

0 5, 6, 7 ws D0 D1 D2 D3 1 ws D4 D5 D6 D7

1 5, 6, 7 ws D1 D2 D3 1 ws 1 ws D4 D5 D6 D7

2 5, 6, 7 ws D2 D3 1 ws 1 ws 1 ws D4 D5 D6 D7

3 5, 6, 7 ws D3 1 ws 1 ws 1 ws 1 ws D4 D5 D6 D7

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Write Set Configuration Register

Command and Settings:

Address 555h, Data D0h

Address X00h, Data CR

Load Initial Address

Address = RA

Read Initial Data

RD = DQ[15:0]

Read Next Data

RD = DQ[15:0]

Wait X Clocks:

Additional Latency Due to Starting

Address, Clock Frequency, and

Boundary Crossing

End of Data?

Yes

Crossing

Boundary? No

Yes

Completed

Delay X Clocks

Unlock Cycle 1

Unlock Cycle 2

RA = Read Address

RD = Read Data

Command Cycle

CR = Configuration Register Bits CR15-CR0

Note: Setup Configuration Register parameters

Refer to the Latency tables.

24 S29WS-N_00_G0 January 25, 2005

Advance Information

VIL. Continuous burst mode can also be aborted by a sserting AVD# low and providing a new ad-

dress to the device.

If the address being read crosses a 128-word line boundary (as mentioned above) and the sub-

sequent word line is not being programmed or erased, additional latency cycles are required as

reflected by the configuration register table (Table 7.8).

If the address crosses a bank boundary while the subsequent bank is programming or erasing,

the device provides read status information and the clock is ignored. Upon completion of status

read or program or erase operation, the host can restart a burst read operation using a new ad-

dress and AVD# pulse.

7.3.4 8-, 16-, 32-Word Linear Burst Read with Wrap Around

In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con-

secutive addresses that are determined by the group within which the starting address falls. The

groups are sized according to the number of words read in a single burst sequence for a given

mode (see Table 7.7).

For example, if the starting address in the 8-word mode is 3Ch, the address range to be read

would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device

outputs all words in that burst address group until all word are read, regardless of where the start-

ing address occurs in the address group, and then terminates the burst read.

In a similar fashion, the 16-word and 32-word Linear W r ap modes begin t heir burst sequence on

the starting address provided to the device, the n wrap back to the first address in the selected

address group.

Note that in this mode the address pointer does not cross the boundary that occurs every 128

words; thus, no additional wait states are inserted due to boundary crossing.

Ta b l e 7 . 7 . Burst Address Groups

7.3.5 8-, 16-, 32-Word Linear Burst without Wrap Around

If wrap around is not enabled f or li near bu rst r ead operations, the 8-word, 16-word, or 32 -word

burst executes up to the maximum memory addre ss of the selected number of words. The burst

stops after 8, 16, or 32 addresses and does not wrap around to th e first address of the selected

group.

For example, if the starting address in the 8- word mode is 3Ch, the address range to be read

would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around

is not enabled. The next address to be read requires a new address and AVD# pulse. Note that

in this burst read mode, the address pointer may cross the boundary that occurs every 128 words,

which will incur the additional boundary crossing wait state.

7.3.6 Configuration Register

The configuration register sets v arious operational p arameters associated with burst mod e. Upon

power-up or hardware reset, the device defaults to the asynchronous read mode, and the config-

uration register settings are in their default state. The host system should determine the proper

settings for the entire configuration register, and then execute the Set Configuration Register

command sequence, before attempting burst operations. The configuration register is not reset

after deasserting CE#. The Configuration Register can also be read using a command sequence

(see Table 12.1). The following list describes the register settings.

Mode Group Size

Group Address Ranges

8-word 8 words 0-7h, 8-Fh, 10-17h,...

16-word 16 words 0-Fh, 10-1Fh, 20-2Fh,...

32-word 32 words 00-1Fh, 20-3Fh, 40-5Fh,...

January 25, 2005 S29WS-N_00_G0 25

Advance Information

Ta b l e 7 . 8 . Configuration Register

Reading the Configuration Table. The configuration register can be read with a four-cycle com-

mand sequence. See Table 12.1 for sequence details. Once the data has been read from the

configuration register, a software reset command is required to set the device into the correct

state.

7.4 Autoselect

The Autoselect is used for manufacturer ID, Device identification, and sector protection informa-

tion. This mode is primarily intended for programming equipment to automatically match a device

with its corresponding programming algorithm. The Autoselect codes can also be accessed in-sys-

tem. When verifying sector protection, the sector address must appear on the appropriate highest

order address bits (see Table 7.9). The remaining address bits are don't care. The most significant

four bits of the address during the third write cycle selects the bank from which the Autoselect

codes are read by the host. All other banks can be accessed normally for data read without exiting

the Autoselect mode.

To access the Autoselect codes, the host system must issue the Autoselect command.

CR Bit Function Settings (Binary)

CR15 Set Device Read

Mode 0 = Synchronous Read (Burst Mode) Enabled

1 = Asynchronous Read Mode (default) Enabled

CR14 Boundary Crossing

54 MHz 66 Mhz 80 MHz

S29WS064N

S29WS128N N/A N/A N/A Default value is "0"

S29WS256N 0 1 1 0 = No extra boundary crossing latency

1 = With extra boundary crossing latency (default)

Must be set to “1” greater than 54 MHz.

CR13

Programmable

Wait State

S29WS064N

S29WS128N 011

011 = Data valid on 5th active CLK edge after addresses

latched

100 = Data valid on 6th active CLK edge after addresses

latched

101 = Data valid on 7th active CLK edge after addresses

latched (default)

110 = Reserved

111 = Reserved

Inserts wait states before initial data is available. Setting

greater number of wait state s before initial data reduces

latency after initial data.

(Notes 1, 2)

S29WS256N

CR12 S29WS064N

S29WS128N 100

S29WS256N

CR11 S29WS064N

S29WS128N 101

S29WS256N

CR10 RDY Polarity 0 = RDY signal active low

1 = RDY signal active high (default)

CR9 Reserved 1 = default

CR8 RDY 0 = RDY active one clock cycle bef ore data

1 = RDY active with data (default)

When CR13-CR11 are set to 000, RDY is active with data

regardless of CR8 setting.

CR7 Reserved 1 = default

CR6 Reserved 1 = default

CR5 Reserved 0 = default

CR4 Reserved 0 = default

CR3 Burst Wrap Around 0 = No Wrap Around Burst

1 = Wrap Around Burst (default)

CR2

CR1

CR0 Burst Length

000 = Continuous (default)

010 = 8-Word Linear Burst

011 = 16-Word Linear Burst

100 = 32-Word Linear Burst

(All other bit settings are reserved)

Notes:

1. Refer to Tables 7.2 - 7.6 for wait states requir ements.

2. Refer to Synchronous Burst Read timing diagrams

3. Configuration Register is in the default state upon power-up or hardware reset.

26 S29WS-N_00_G0 January 25, 2005

Advance Information

The Autoselect command sequence may be written to an address within a bank that is

either in the read or erase-suspend-read mode.

The Autoselect command may not be written while the device is actively progr amming or

erasing. Autoselect does not support simultaneous operations or burst mode.

The system must write the reset command to return to the read mode (or erase-suspend-

read mode if the bank was previously in Erase Suspend).

See Table 12.1 for command sequence details.

Ta b l e 7 . 9 . Autoselect Addresses

Notes:

1. Any offset within the device works.

2. BA = Bank Address. The bank address is required.

3. base = base address.

Description Address Read Data

Manufacturer ID (BA) + 00h 0001h

Device ID, Word 1 (BA) + 01h 227Eh

Device ID, Word 2 (BA) + 0Eh 2230 (WS256N)

2231 (WS128N)

2232 (WS064N)

Device ID, Word 3 (BA) + 0Fh 2200

Indicator Bi ts

(See Note) (BA) + 03h

DQ15 - DQ8 = Reserved

DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Lock ed

DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Lock ed

DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake

DQ4, DQ3 (WP# Protectio n Boot Code): 00 = WP# Protects b oth Top Boot and

Bottom Boot Sectors . 01, 10, 11 = Reserved

DQ2 = Reserved

DQ1 (D YB Power up State [Lock Regist er DQ4]): 1 = U nlocked (user option ),

0 = Locked (default)

DQ0 (PPB Eraseabili ty [Lock Register DQ3]): 1 = Erase allow e d,

0 = Erase disabled

Sector Block Lock/

Unlock (SA) + 02h 0001h = Locked, 0000h = Unlocked

Note: For WS128N and WS064, DQ1 and DQ0 are reserved.

Software Functions and Sample Code

Table 7.10. Autoselect Entry

(LLD Function = lld_AutoselectEntryCmd)

Cycle Operation Byte Address Word Address Data

Unlock Cycle 1 W rite BAxAAAh BAx555h 0x00AAh

Unlock Cycle 2 Write BAx555h BAx2AAh 0x0055h

Autoselect Command Write BAxAAAh BAx555h 0x0090h

Table 7.11. Autoselect Exit

(LLD Function = lld_AutoselectExitCmd)

Cycle Operation Byte Address Word Address Data

Unlock Cy cle 1 Write base + XXXh base + XXXh 0x00F0h

January 25, 2005 S29WS-N_00_G0 27

Advance Information

The following is a C source code example of using the autoselect function to read the manu-

facturer ID . Refer to the Spansion Low Level Driver User’s Guide (av ailable on www.amd.com

and www.fujitsu.com) for general information on Spansion Flash memory software develop-

ment guidelines.

/* Here is an example of Autoselect mode (getting manufacturer ID) */

/* Define UINT16 example: typedef unsigned short UINT16; */

UINT16 manuf_id;

/* Auto Select Entry */

*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */

/* multiple reads can be performed after entry */

manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */

/* Autoselect exit */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autosele ct (wri te reset command) */

28 S29WS-N_00_G0 January 25, 2005

Advance Information

7.5 Program/Erase Operations

These devices are capable of several modes of programming and or erase operations which are

described in detail in the following sections. However, prior to an y programming and or er ase op-

eration, devices must be setup appropriately as outlined in the configuration register (Table 7.8).

For any program and or erase operations, including writing command sequences, the system

must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and

drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data.

Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st

rising edge of WE# or CE#.

Note the following:

When the Embedded Program algorithm is complete, the device returns to the read

mode.

The system can determine the status of the program operation by using DQ7 or DQ6.

Refer to the Write Operation Status section for information on these status bits.

A “0” cannot be programmed back to a “1.” Attempting to do so causes the device to set

DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding

read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.”

Any commands written to the device during the Embedded Program Algorithm are ig-

nored except the Program Suspend command.

Secured Silicon Sector, Autoselect, and CFI functions are una vailable when a program op-

eration is in progress.

A hardware rese t immediat ely termina tes t he prog ram operation and the prog ram com-

mand sequence should be reinitiated once the device has returned to the rea d m ode, to

ensure data integrity.

Programming is allowed in any sequence and across sector boundaries for single word

programming operation.

7.5.1. Single Word Programming

Single word progr amming mode is the simplest method o f programming. In this mode, f our Flash

command write cycles are used to program an individual Flash address. The data for this pro-

gramming operation could be 8-, 16- or 32-bits wide. While this method is supported by all

Spansion devices, in general it is not recommended for devices that support Write Buffer Pro-

gramming. See Table 12.1 for the required bus cycles and Figure 7.3 for the flowchart.

When the Embedded Program algorithm is complete, the device then returns to the read mode

and addresses are no longer latched. The system can determine the status of the program oper-

ation by using DQ7 or DQ6. Refer to the Write Oper ation Status section for information on these

status bits.

During programming, any command (except the Suspend Program command) is ignored.

The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program

operation is in progress.

January 25, 2005 S29WS-N_00_G0 29

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A hardware reset immediately terminates the program operation. The program command

sequence should be reinitiated once the device has returned to the read mode, to ensure

data integrity.

Figure 7.3. Single Word Program

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Write Program Command:

Address 555h, Data A0h

Program Data to Address:

PA, PD

Unlock Cycle 1

Unlock Cycle 2

Setup Command

Program Address (PA),

Program Data (PD)

FAIL. Issue reset command

to return to read array mode.

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Polling Status

= Busy?

Polling Status

= Done? Error condition

(Exceeded Timing Limits)

PASS. Device is in

read mode.

30 S29WS-N_00_G0 January 25, 2005

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Note: Base = Base Address.

The following is a C source code example of using t he single word program funct ion. R efer to

the Spansion Low Level Driver User’s Guide (available on www.amd.com and

www.fujitsu.com) for general information on Spansion Flash m emory software development

guidelines.

/* Example: Program Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)base_addr + 0x555 ) = 0x00A0; /* write program setup command */

*( (UINT16 *)pa ) = data; /* write data to be programmed */

/* Poll for program completion */

7.5.2 Write Buffer Programming

Write Buffer Programming allows the system to write a maximum of 32 words in one program-

ming operation. This results in a faster effective word programming time than the standard

“word” programming algorithms. The Write Buffer Programming command sequence is initiated

by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer

Load command written at the Sector Address in which programming occurs. At this point, the sys-

tem writes the number of “word locations minus 1” that are loaded into the page buffer at the

Sector Address in which programming occurs. This tells the device how many write buffer ad-

dresses are loaded with data and therefore when to expect the “Progr am Buffer to Flash” confirm

command. The number of locations to program cannot exceed the size of the write buffer or the

operation aborts. (Number loaded = the number of locations to program minus 1. For example,

if the system programs 6 address locations, then 05h shou ld be wr itten to the device.)

The system then writes the starting address/data combination. This starting address is the first

address/data pair to be programmed, and selects the “write-buffer-page” address. All subsequent

address/data pairs must fall within the elected-write-buffer-page.

The “write-buffer-page” is selected by using the addresses AMAX - A5.

The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the

write buffer. (This means Write Buffer P rogr amming cannot be performed across multiple “write-

buffer-pages.” This also means that Write Buffer Programming cannot be performed across mul-

tiple sectors. If the system attempts to load programming data outside of the selected “write-

buffer-page”, the operation ABORTs.)

After writing the Starting Address/Data pair, the system then writes the remaining address/data

pairs into the write buffer.

Note that if a Write Buffer address location is loaded multiple times, the “address/data pair”

counter is decremented for ev ery data load op eration. Also, the last data loaded at a location b e-

fore the “Program Buffer to Flash” confirm command is programmed into the device. It is the

software's responsibility to comprehend ramifications of loading a write-buffer location more than

Software Functions and Sample Code

Table 7.12. Single Word Program

(LLD Function = lld_ProgramCmd)

Cycle Operation Byte Address Word Address Data

Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh

Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h

Program Setup Write Base + AAAh Base + 555h 00A0h

Program W rite Wo rd Address Word Address Data W ord

January 25, 2005 S29WS-N_00_G0 31

Advance Information

once. The counter decrements for each data load operation, NOT for each unique write-bu ffer-

address location. Once the specified number of write buffer locations have been loaded, the sys-

tem must then write the “Program Buffer to Flash” command at the Sector Address. Any other

address/data write combinations abort the Writ e Buffer Programming oper ation. The device goes

“busy.” The Data Bar polling techniques should be used while monitoring the last address location

loaded into the write buffer. This eliminates the need to store an address in memory because the

system can load the last address location, issue the program confi rm command at the last loaded

address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1

should be monitored to determine the device status during Write Buffer Programming.

The write-buffer “embedded” programming operation can be suspended using the standard sus-

pend/resume commands. Upon successful completion of the Write Buffer Programming operation,

the device returns to READ mode.

The Write Buffer Programming Sequence is ABORTED under any of the following conditions:

Load a value that is greater than the page buffer size during the “Number of Locations to

Program” step.

Write to an address in a sector different than th e one specified during the Write-Buffer-

Load command.

W rite an Address/Data pair to a different write-buffer-page than the one selected by the

“Starting Address” during the “write buffer data loading” stage of the operation.

Write data other than the “Confirm Command” after the specified number of “data load”

cycles.

The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location

loaded”), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation

was ABORTED. A “Write-to-Buffer-Abort reset” command sequence is required when using the

write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector,

autoselect, and CFI functions are unavailable when a program operation is i n prog ress.

Write buffer programming is allowed in any sequence of memory (or address) locations. These

flash devices are capable of handling multiple write buffer programming operations on the same

write buffer address rang e without interv ening erases.

Use of the write buffer is strongly recommended for programming when multiple words are to be

programmed. Write buffer programming is approximately eight times faster than programming

one word at a time.

32 S29WS-N_00_G0 January 25, 2005

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Notes:

1. Base = Base Address.

2. Last = Last cycle of write buffer program operation; depending on number of

words written, the total number of cycles may be from 6 to 37.

3. For maximum efficiency, it is recommended that the write buffer be loaded with

the highest number of words (N words) possible.

The following is a C source code example of using the write buffer pr ogram fu nction. R efer to

the Spansion Low Level Driver User’s Guide (available on www.amd.com and

www.fujitsu.com) for general information on Spansion Flash m emory software development

guidelines.

/* Example: Write Buffer Programming Command */

/* NOTES: Write buffer programming limited to 16 words. */

/* All addresses to be written to the flash in */

/* one operation must be within the same flash */

/* page. A flash page begins at addresses */

/* evenly divisible by 0x20. */

UINT16 *src = source_of_data; /* address of source data */

UINT16 *dst = destination_of_data; /* flash destination address */

UINT16 wc = words_to_program -1; /* word count (minus 1) */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)sector_address ) = 0x0025; /* write write buffer load command */

*( (UINT16 *)sector_address ) = wc; /* write word count (minus 1) */

loop:

*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */

dst++; /* increment destination pointer */

src++; /* increment source pointer */

if (wc == 0) goto confirm /* done when word count equals zero */

wc--; /* decrement word count */

goto loop; /* do it again */

confirm:

*( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */

/* poll for completion */

/* Example: Write Buffer Abort Reset */

*( (UINT16 *)addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)addr + 0x555 ) = 0x00F0; /* write buffer abort reset */

Software Functions and Sample Code

Table 7.13. Write Buffer Program

(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)

Cycle Description Operation Byte Address Word Address Data

1 Unlock Write Base + AAAh Base + 555h 00AAh

2 Unlock W rite Base + 554h Base + 2AAh 0055h

3 Write Buffer Load Command Write Program Address 0025h

4 Write Word Coun t Write Progr a m Addre ss Word Count (N– 1 )h

Number of words (N) loaded into the write buffer can be from 1 to 32 words.

5 to 36 Load Buffer Word N Write Program Address, Word N Word N

Last Write Buffer to Flash Write Sector Address 0029h

January 25, 2005 S29WS-N_00_G0 33

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Figure 7.4. Write Buffer Programming Operation

7.5.3 Sector Erase

The sector erase function erases one or more sectors in the memory array. (See Table 12.1,

Memory Arr ay Command s; and Figure 7.5, S ector Erase Oper ation.) The device does not require

the system to preprogram prior to er ase. The Embedded Erase algorithm automatically programs

and verifies the entire memory for an all zero data pattern prior to electrical erase. After a suc-

cessful sector erase, all locations within the erased sector contain FFFFh. The system is not

required to provide any controls or timings during these oper at ions.

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Issue

Write Buffer Load Command:

Address 555h, Data 25h

Load Word Count to Program

Program Data to Address:

SA = wc

Unlock Cycle 1

Unlock Cycle 2

wc = number of words – 1

Yes

wc = 0?

Write Buffer

Abort Desired?

Write Buffer

Abort?

Polling Status

= Done?

Error?

FAIL. Issue reset command

to return to read array mode.

Write to a Different

Sector Address to Cause

Write Buffer Abort

PASS. Device is in

read mode.

Confirm command:

SA 29h

Wait 4 µs

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Write Next Word,

Decrement wc:

PA data , wc = wc – 1

RESET. Issue Write Buffer

Abort Reset Command

34 S29WS-N_00_G0 January 25, 2005

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After the command sequence is written, a sector erase time-out of no less than tSEA occurs. Dur-

ing the time-out period, additional sector addresses and sector er ase commands may be written.

Loading the sector erase buffer ma y be done in any sequence, and the number of sectors may be

from one sector to all sectors. The time between these additional cycles must be less than tSEA.

Any sector erase address and command following the exceeded time-out (tSEA) may or may not

be accepted. An y command other than Sector Er ase or Erase Suspend during the time-out period

resets that bank to the read mode. The system can monitor DQ3 to determine if t he sector er ase

timer has timed out (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the

rising edge of the final WE# pulse in the command sequence.

When the Embedded Er ase algorithm is complete, the bank returns t o reading array da ta and ad-

dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the

system can read data from the non-erasing banks. The system can determine the status of the

erase oper ation by read ing DQ7 or DQ6 /DQ2 in the erasing bank. R efer to “Write Operation Sta-

tus” for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other

commands are ignored. However, note that a hardware reset immediately terminates the erase

operation. If that occurs, the sector erase command sequence should be reinitiated once that

bank has returned to reading array data, to ensure data integrity.

Figure 7.5 illustrates the algorithm for the erase operation. Refer to the “Erase/Pro gram Opera-

tions” section for parameters and timing diagrams.

January 25, 2005 S29WS-N_00_G0 35

Advance Information

The following is a C source code example of using the sector erase function. Refer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Sector Erase Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write additional unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write additional unlock cycle 2 */

*( (UINT16 *)sector_address ) = 0x0030; /* write sector erase command */

Software Functions and Sample Code

Ta b l e 7 . 1 4 . S e c t o r E r a s e

(LLD Function = lld_SectorEraseCmd)

Cycle Description Operation Byte Address Word Address Data

1 Unlock Write Base + AAAh Base + 555h 00AAh

2 Unlock Write Base + 554h Base + 2AAh 0055h

3 Setup Command W rite Base + AAAh Base + 555h 0080h

4 Unlock Write Base + AAAh Base + 555h 00AAh

5 Unlock Write Base + 554h Base + 2AAh 0055h

6 Sector Erase Command Write Sector Address Sector Address 0030h

Unlimited additional sectors may be selected for erase; command(s) must be written within t

SEA

36 S29WS-N_00_G0 January 25, 2005

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Figure 7.5. Sector Erase Operation

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Write Sector Erase Cycles:

Address 555h, Data 80h

Address 555h, Data AAh

Address 2AAh, Data 55h

Sector Address, Data 30h

Write Additional

Sector Addresses

FAIL. Write reset command

to return to reading array.

PASS. Device returns

to reading array.

Wait 4 µs

Perform Write Operation

Status Algorithm

Select

Additional

Sectors?

Unlock Cycle 1

Unlock Cycle 2

Yes

Last Sector

Selected?

Done?

DQ5 = 1?

Command Cycle 1

Command Cycle 2

Command Cycle 3

Specify first sector for erasure

Error condition (Exceeded Timing Limits)

Status may be obtained by reading DQ7, DQ6 and/or DQ2.

Poll DQ3.

DQ3 = 1?

• Each additional cycle must be written within tSEA timeout

• Timeout resets after each additional cycle is written

• The host system may monitor DQ3 or wait tSEA to ensure

acceptance of erase commands

• No limit on number of sectors

• Commands other than Erase Suspend or selecting

additional sectors for erasure during timeout reset device

to reading array data

Notes:

1. See Table 12.1 for erase command sequence.

2. See the section on DQ3 for information o n the sector erase timeout.

(see Figure 7.6)

January 25, 2005 S29WS-N_00_G0 37

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7.5.4 Chip Erase Command Sequence

Chip erase is a six-bus cycle operation as indicated by Table 12.1. Thes e comma nds invoke th e

Embedded Er ase algorithm, which does not require the system to prep rogram prior to er ase. The

Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all

zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip

contain FFFFh. The system is not required to provide any controls or ti ming s during these oper -

ations. The “Command Definition” section in the appendix shows the address and data

requirements for the chip er ase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-

dresses are no longer latched. The system can determine the status of the erase operation by

using DQ7 or DQ6/ DQ 2. Refer to “Writ e Op eratio n St atus” fo r info r mat i on on the se stat us bi ts .

Any commands written during the chip erase operation are ignored. However, note that a hard-

ware reset immediately terminates the erase operation. If that occurs, the chip erase command

sequence should be reinitiated once that bank has returned to reading array data, to ensure data

integrity.

The following is a C source code example of using the chip erase function. R efer to the Span-

sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for

general information on Spansion Flash memory software dev elopment guid elines.

/* Example: Chip Erase Command */

/* Note: Cannot be suspended */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write additional unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write additional unlock cycle 2 */

*( (UINT16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */

7.5.5 Erase Suspend/Erase Resume Commands

When the Erase Susp end command is written during the sector erase time-out, the device imme -

diately terminates the time-out period and suspends the erase operation. The Erase Suspend

command allows the system to interrupt a sector erase operation and then read data from, or

program data to, any sector not selected for erasure. The bank address is required when writing

this command. This command is valid only during the sector erase operation, including the min-

imum tSEA time-out period during the sector erase command sequence. The Erase Suspend

command is ignored if written during the chip erase operation.

When the Erase Suspend comm and is written after the tSEA time-out period has expired and dur-

ing the sector erase oper ation, the device requires a maximum of tESL (er ase suspend latency) to

suspend the erase operation.

Software Functions and Sample Code

Table 7.15. Chip Erase

(LLD Function = lld_ChipEraseCmd)

Cycle Description Operation Byte Address Word Address Data

1 Unlock Write Base + AAAh Base + 555h 00AAh

2 Unlock Write Base + 554h Base + 2AAh 0055h

3 Setup Command W rite Base + AAAh Base + 555h 0080h

4 Unlock Write Base + AAAh Base + 555h 00AAh

5 Unlock Write Base + 554h Base + 2AAh 0055h

6 Chip Erase Command Write Base + AAAh Base + 555h 0010h

38 S29WS-N_00_G0 January 25, 2005

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After the erase operation has been suspended, the bank ente rs the erase-suspend-read mode.

The system can read data from or program data to an y sector not selected for er asure . (The de-

vice “erase suspends” all sectors selected for erasure.) Reading at any address within erase-

suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6,

and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table

7.24 for information on these status bits.

After an erase-suspended program operation is complete, the bank returns to the erase-suspend-

read mode. The system can determine the status of the progr am operation using the DQ7 or DQ6

status bits, just as in the standard program operation.

In the erase-suspend-read mode, the system can also issue the Autoselect command sequence.

Refer to the “Write Buffer Programming Operation” section and the “Autoselect Command Se-

quence” section for details.

To resume the sector erase operation, the system must write the Erase Resume command. The

bank address of the erase-suspended bank is required when writing this command. Further writes

of the Resume command are ignored. Another Er ase Suspend command can be writte n after the

chip has resumed erasing.

The following is a C source code example of using the erase suspend function. Refer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Erase suspend command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */

The following is a C source code example of using the erase resume function. Refer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Erase resume command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */

/* The flash needs adequate time in the resume state */

7.5.6 Program Suspend/Program Resume Commands

The Program Suspend command allows the system to interrupt an embedd ed programmi ng op-

eration or a “Write to Buffer” programming operation so that data can read from any non-

suspended sector. When the Program Suspend command is written during a programmin g pro-

cess, the device halts the programming operation within tPSL (program suspend latency) and

updates the status bits. Addresses are “don't-cares” when writing the Program Suspend

command.

Software Functions and Sample Code

Table 7.16. Erase Suspend

(LLD Function = lld_EraseSuspendCmd)

Cycle Operation Byte Address Word Address Data

1 Write Bank Address Bank Address 00B0h

Table 7.17. Erase Resume

(LLD Function = lld_EraseResumeCmd)

Cycle Operation Byte Address Word Address Data

1 Write Bank Address Bank Address 0030h

January 25, 2005 S29WS-N_00_G0 39

Advance Information

After the progr amming operation has been suspende d, the system can read arr a y data from any

non-suspended sector. The Program Suspend command may also be issued during a program-

ming operation while an erase is suspended. In this case, data may be read from any addresses

not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector

area, then user must use the proper command sequences to enter and exit this region.

The system may also write the Autoselect command sequence when the device is in Program Sus-

pend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes

are not stored in the memory array. When the device exits the Autoselect mode, the device re-

verts to Program Suspend mode, and is ready for another valid operation. See “Autoselect

Command Sequence” for more information.

After the Program Resume command is written, the device reverts to programming. The system

can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in

the standard program operation. See “Write Operati on Sta tu s” fo r mo re in for mat i on .

The system must write the Program Resume command (address bits are “don't care”) to exit the

Program Suspend mode and continue the progr amming oper ation. Furth er writes of the Prog ram

Resume comm and are ignored. Another Progr am Suspend command can be written after the de-

vice has resumed programming.

The following is a C source code example of using the program suspend function. R efer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Program suspend command */

*( (UINT16 *)base_addr + 0x000 ) = 0x00B0; /* write suspend command */

The following is a C source code example of using the program resume function. Refer to the

Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)

for general information on Spansion Flash memory software development guidelines.

/* Example: Program resume command */

*( (UINT16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */

7.5.7 Accelerated Program/Chip Erase

Accelerated single word programming, write buffer programming, sector erase, and chip erase

operations are enabled through the ACC function. This method is faster than the standard chip

program and erase command sequences.

The accelerated chip program and erase functions must not be used more than 10 times

per sector. In addition, accelerated chip program and erase should be performed at room tem-

perature (25°C ±10°C).

Software Functions and Sample Code

Ta b l e 7 . 1 8 . P r o g r a m S u s p e n d

(LLD Function = lld_ProgramSuspendCmd)

Cycle Operation Byte Address Word Address Data

1 Write Bank Address Bank Address 00B0h

Ta b l e 7 . 1 9 . P r o g r a m R e s u m e

(LLD Function = lld_ProgramResumeCmd)

Cycle Operation Byte Address Word Address Data

1 Write Bank Address Bank Address 0030h

40 S29WS-N_00_G0 January 25, 2005

Advance Information

If the system asserts VHH on this input, the device automatically enters the aforementioned Un-

lock Bypass mode and uses the higher voltage on the input to reduce the time required for

program and erase operations. The system can then use the Write Buffer Load command se-

quence provided by the Unlock Bypass mode. Note that if a “Write-to-Buffer-Abort Reset” is

required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used

to reset the device. Removing VHH from the ACC input, upon completion of the embedded pro-

gram or er ase op eration, returns the device to normal operation.

Sectors must be unlocked prior to raising ACC to VHH.

The ACC pin must not be at VHH for operations other than accelerated programming and

accelerated chip erase, or device damage may result.

The ACC pin must not be left floating or unconnected; inconsistent beha vior of the device

may result.

ACC locks all sector if set to VIL; ACC should be set to VIH for all other conditions.

7.5.8 Unlock Bypass

The device features an Unlock Bypass mode to facilitate faster word programming. Once the d e-

vice enters the Unlock Bypass mode, only two write cycles are required to program data, instead

of the normal four cycles.

This mode dispenses with the initial two unlock cycles required in the standard program command

sequence, resulting in faster total programming ti me . Th e “Co m ma nd De fi niti on S um ma ry ” sec-

tion shows the requirements for the unlock bypass command sequences.

During the unlock bypass mode, only the Read, Unlock Bypass Progr am and Unlock Bypass R eset

commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock

bypass reset command sequence. The first cycle must contain the bank address and the data 90h.

The second cycle need only contain the data 00h. The bank then returns to the read mode.

The following are C source code examples of using the unlock bypass entry, program, and exit

functions. R efer to the Spansion Low Level Driver User’s Guide (avai lable soon on www . amd.com

and www.fujitsu.com) for general information on Spansion Flash memory software development

guidelines.

/* Example: Unlock Bypass Entry Command */

*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */

/* At this point, programming only takes two write cycles. */

/* Once you enter Unlock Bypass Mode, do a series of like */

/* operations (programming or sector erase) and then exit */

/* Unlock Bypass Mode before beginning a different type of */

/* operations. */

Software Functions and Sample Code

Table 7.20. Unlock Bypass Entry

(LLD Function = lld_UnlockBypassEntryCmd)

Cycle Description Operation Byte Address Word Address Data

1 Unlock Write Base + AAAh Base + 555h 00AAh

2 Unlock Write Base + 554h Base + 2AAh 0055h

3 Entry Command Write Base + AAAh Base + 555h 0020h

Table 7.21. Unlock Bypass Program

(LLD Function = lld_UnlockBypassProgramCmd)

Cycle Description Operation Byte Address Word Address Data

1 Progr am Setup Comm and Write Base + xxxh Base +xxxh 00A0h

January 25, 2005 S29WS-N_00_G0 41

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/* Example: Unlock Bypass Program Command */

/* Do while in Unlock Bypass Entry Mode! */

*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0; /* write program setup command */

*( (UINT16 *)pa ) = data; /* write data to be programmed */

/* Poll until done or error. */

/* If done and more to program, */

/* do above two cycles again. */

/* Example: Unlock Bypass Exit Command */

*( (UINT16 *)base_addr + 0x000 ) = 0x0090;

*( (UINT16 *)base_addr + 0x000 ) = 0x0000;

7.5.9 Write Operation Status

The device provides several bits to determine the status of a program or erase operation. The

following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.

DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-

bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase

Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the comman d se-

quence. Note that the Data# P olling is valid only for the last word being programmed in the write-

buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other

than the last word to be programmed in the write-buffer-page returns false status information.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the

datum programmed to DQ7. This DQ7 status also applies to programming during Er ase Suspend.

When the Embedded Progr am algorithm is complete, the device outp uts the datum progr a mmed

to DQ7. The system must provide the program address to read valid status information on DQ7.

If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi-

mately tPSP, then that bank returns to the read mode.

During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embed-

ded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling

produces a “1” on DQ7. The system must provide an address within any of the sectors selected

for erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected,

Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode.

If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7

at an address within a protected sector, the status may not be valid.

Just prior to the comple tion of an Embedded Program or Erase oper ation, DQ7 may change asyn-

chronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may

change from providing status informatio n to valid data on DQ7. Depending on when the system

samples the DQ7 output, it may read the status or valid data. Even if the device has completed

2 Program Command Write Program Address Program Address Program Data

Table 7.22. Unlock Bypass Reset

(LLD Function = lld_UnlockBypassResetCmd)

Cycle Description Operation Byte Address Word Address Data

1 Reset Cycle 1 Write Base + xxxh Base +xxxh 0090h

2 Reset Cycle 2 Write Base + xxxh Base +xxxh 0000h

Table 7.21. Unlock Bypass Program

(LLD Function = lld_UnlockBypassProgramCmd)

Cycle Description Operation Byte Address Word Address Data

42 S29WS-N_00_G0 January 25, 2005

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the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be

still invalid. Valid data on DQ7-D00 appears on successive read cycles.

See the following for more information: Table 7.24, Write Operation Status, shows the outputs

for Data# Polling on DQ7. Figure 7.6, Write Operation S tatus Flowchart, shows the Data# P olling

algorithm; and Figure 11.17, Data# Polling Timings (During Embedded Algorithm), shows the

Data# Polling timing diagram.

January 25, 2005 S29WS-N_00_G0 43

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Figure 7.6. Write Operation Status Flowchart

START

DQ7=valid

data?

YES

DQ5=1?

YES

Write Buffer

Programming?

YES

Device BUSY,

Re-Poll

DQ1=1?

YES

DQ1=1

AND DQ7 ≠

Valid Data?

YES

(Note 4)

Write Buffer

Operation

Failed

DQ6

toggling?

YES

TIMEOUT

(Note 1) (Note 3)

Programming

Operation?

DQ6

toggling?

YES

DQ2

toggling?

YES

Erase

Operation

Complete

Device in

Erase/Suspend

Mode

Program

Operation

Failed

DEVICE

ERROR

Erase

Operation

Complete

Read3=

valid data?

YES

Notes:

1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.

2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.

3) May be due to an attempt to program a 0 to 1. Use the RESET

command to exit operation.

4) Write buffer error if DQ1 of last read =1.

5) Invalid state, use RESET command to exit operation.

6) Valid data is the data that is intended to be programmed or all 1's for

an erase operation.

7) Data polling algorithm valid for all operations except advanced sector

protection.

Device BUSY,

Re-Poll

Device BUSY,

Re-Poll

Device BUSY,

Re-Poll

(Note 1)

(Note 2)

(Note 6)

(Note 5)

44 S29WS-N_00_G0  January 25, 2005
Advance Information
DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether  a n Embedd ed Program or Erase algo-
rithm is in progress or complete, or whether the device has entered the Erase Suspend mode. 
Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of 
the final WE# pulse in the command sequence (prior to the program or erase operation), and dur-
ing the sector erase time-out. 
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. 
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 
toggles for approximately tASP [all sectors protected toggle time], then returns to  reading a rray 
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected. 
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or 
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm 
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to deter mi ne which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). 
If a program a ddress falls within a prot ected  sector, DQ6 toggles for approximat ely t PAP after the 
program command sequence is written, then returns to reading array data. 
DQ6 also toggles during the erase-suspend-progr am mode , an d stops toggling once the Embe d -
ded Program Algorith m is  complete. 
See the following for additional information: Figure 7.6, W rite Operation Status Flowchart ; Figure 
11.18, Toggle Bit Timings (During Embedded Algorithm), and Tables 7.23 and 7.24. 
Toggle Bit I on DQ6 requires either OE# or  CE# to be de-asserted and reasserted to show  the 
change in state. 
DQ2: Toggle Bit II . The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a par-
ticular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether 
that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse 
in the command sequence. DQ2 toggles when the system reads at  addresses within those sectors 
that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively 
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, 
both status bits are required for sector and mode information. Refer to Table 7.23 to compare 
outputs for DQ2 and DQ6. See the following for additional information: Figure 7.6, the “DQ6: Tog-
gle Bit I” section, and Figures 11.17–11.20.

January 25, 2005 S29WS-N_00_G0 45

Advance Information

Ta b l e 7 . 2 3 . DQ6 and DQ2 Indications

Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status,

it must read DQ7–DQ0 at least twice in a row to det ermine whether a toggle bit is t oggling. Typ-

ically, the system would note and store the value of the toggle bit after the fi rst read. After th e

second read, the system would compare the new value of the toggle bit with the first. If the toggle

bit is not toggling, the device has completed the progra m or erases operation. The system can

read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read

cycles, the system determines that the toggle bit is still toggling, the system also should note

whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then deter-

mine again whether the toggle bit is toggling, since the toggle bit may ha ve stopped toggling just

as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed

the program or erases operation. If it is still toggling, the device did not complete the operation

successfully, and the system must write the reset command to return to reading array data. The

remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5

has not gone high. The system may continue to monitor the toggle bit and DQ5 through succes-

sive read cycles, determining the status as described in the previous paragraph. Alternatively, it

may choose to perform other system tasks. In this case, the system must start at the beginning

of the algorithm when it returns to determine the status of the operation. Refer to Figure 7.6 for

more details.

DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or er ase time has ex ceeded

a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that

the program or er ase cycle w as not successfully completed. The device ma y output a “1” on DQ5

if the system tries to program a “1” to a location that was previously programmed to “0. ” Only an

erase oper ation can change a “0” back to a “1.” Under this condition, the device halts the opera-

tion, and when the timing limit has been exceeded, DQ5 produces a “1.”Under both these

conditions, the system must write the reset command to return to the read mode (or to the erase-

suspend-read mode if a bank was previously in the erase-suspend-program mode).

DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence,

the system may read DQ3 to determine whether or not erasure has begun. (The sector erase

timer does not apply to the chip erase command.) If additional sectors are selected for erasure,

the entire time-out also applies after each additional sector erase command. When the time-out

period is complete, DQ3 switches from a “0” to a “1.” If the time between add itional sector erase

commands from the system can be assumed to be less than tSEA, the system need not monitor

DQ3. See Sector Erase Command Sequence for more details.

After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and

If device is and the system reads then DQ6 and DQ2

programming, at any address, toggles, does not toggle.

actively erasing,

at an address within a sector

selected for erasure, toggles, also toggles.

at an addre ss within sec tors not

selected for erasure, toggles, does not toggle.

erase suspended,

at an address within a sector

selected for erasure, does n ot toggle, toggles.

at an addre ss within sec tors not

selected for erasure, returns array data, returns array data. The sys te m can

read from any sect or not selected for

erasure.

programming in

erase suspend at any address, toggles, is not applicable.

46 S29WS-N_00_G0 January 25, 2005

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then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands

(except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0, ” the device

accepts additional sector erase commands. To ensure the command has been accepted, the sys -

tem software should check the status of DQ3 prior to and following each sub-sequent sector erase

command. If DQ3 is high on the second status check, the last command might not have been

accepted. Table 7.24 shows the status of DQ3 relative to the other status bits.

DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.

Under these conditions DQ1 produces a “1”. The system must issue the Write to Buffer Abort

Reset command sequence to return the device to reading array data. See Write Buffer Program -

ming Operation for more details.

Ta b l e 7 . 2 4 . Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embe dded Erase operation has exceeded the maximum timing limits. Refer to the

section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. Data are invalid for addresses in a Program Suspended sector.

4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.

5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming

indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.

Status

DQ7

(Note 2) DQ6

DQ5

(Note 1) DQ3

DQ2

(Note 2)

DQ1

(Note 4)

Standard

Mode

Embedded Program Algorithm

DQ7# Toggle 0N/A No toggle 0

Embedd ed Erase Algorith m 0Toggle 0 1 Toggle N/A

Program

Suspend

Mode

(Note 3)

Re ading within P rogram Suspended Sector INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

INVALID

(Not

Allowed)

Re ading within N on-Program Suspended

Sector Data Data Data Data Data Data

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector 1No toggle 0N/A Toggle N/A

Non-Erase Suspended

Sector Data Data Data Data Data Data

Erase-Suspend-Program DQ7# Toggle 0N/A N/A N/A

Write to

Buffer

(Note 5)

BUSY State DQ7# Toggle 0N/A N/A 0

Exceeded Timing Limits DQ7# Toggle 1N/A N/A 0

ABORT State DQ7# Toggle 0N/A N/A 1

January 25, 2005 S29WS-N_00_G0 47

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7.6 Simultaneous Read/Write

The simultaneous read/write featur e allows the host system to read data from one bank of mem-

ory while programming or erasing another bank of memory. An erase operation may also be

suspended to read from or program another location within the same bank (except the sector

being erased). Figure 11.24, Back-to-Back Read/Write Cycle Timings, shows how read and write

cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Character-

istics (CMOS Compatible) table for read-while-program and read-while-erase current

specification.

7.7 Writing Commands/Command Sequences

When the device is configured for Asynchronous read, only Asynchronous write operations are

allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able

to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address

latches are supported in the Synchronous progr amming mode. During a synchronous write oper-

ation, to write a command or command sequence (which includes programming data to the

device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE#

to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH

when writing commands or data. During an asynchronous write operat ion, the system must drive

CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses

are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of

WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.

Tables 6.1–6.3 indicate the address space that each sector occupies. The device address space is

divided into sixteen banks: Banks 1 through 14 contain only 64 K word sectors, while Banks 0 and

15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A “bank address” is the

set of address bits required to uniquely select a bank. Similarly, a “sector address” is the address

bits required to uniquely select a sector. ICC2 in “DC Characteristics” represents the active current

specification for the write mode. “AC Char acteristics-Synchronous” and “ AC Characteristics- Asyn-

chronous” contain timing specification tables and timing diagr ams for write operations.

7.8 Handshaking

The handshaking feature allows the host system to detect when data is ready to be read by simply

monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.

When the device is configured to operate in synchronous mode, and OE# is low (active), the initial

word of burst data becomes available after either the falling or rising edge of the RDY pin (de-

pending on the setting for bit 10 in the C onfiguration Reg ister). It is re commended th at the host

system set CR13–CR11 in the Configuration Regist er to the appropriate number of wait stat es to

ensure optimal burst mode operation (see Table 7.8, Configuration Register).

Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same

time that data is ready, or one cycle before data is ready.

48 S29WS-N_00_G0 January 25, 2005

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7.9 Hardware Reset

The RESET# input provides a hardware method of resetting the device to reading array data.

When RESET# is driven low for at least a period of tRP, the device immediately terminates any

operation in progress, tristates all outputs, resets the configur ation register, and ignores all read/

write commands for the duration of the RESET# pu lse. The device also resets the internal state

machine to reading array data.

To ensure data integrity the operation that was interrupted should be reinitiated once the device

is ready to accept another command sequence.

When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held

at VIL, but not at VSS, the standby current is greater.

RESET# may be tied to the system reset circuitry which enables the system to read the boot-up

firmware from the Flash memory upon a system reset.

See Figures 11.5 and 11.12 for timing diagrams.

7.10 Software Reset

Software reset is part of the command set (see Table 12.1) that also returns the device to array

read mode and must be used for the following conditions:

1. to exit Autoselect mode

2. when DQ5 goes high during write status operati on that indicates program or er ase cycle

was not successfully completed

3. exit sector lock/unlock operation.

4. to return to erase-suspend-read mode if the device was previously in Erase Suspend

mode.

5. after any aborted operations

Note: Base = Base Address.

The following is a C source code example of using the reset function. Refer to the Spansion

Low Level Driver User’s Guide (available on www .amd.com and www.fujits u.com) for general

information on Spansion Flash memory software development guidelines.

/* Example: Reset (software reset of Flash state machine) */

*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;

The following are additional points to consider when using the reset command:

This command resets the banks to the read and address bits are ignored.

Reset commands are ignored once erasure has begun until the operation is complete.

Once programming begins, the device ignores reset commands until the operation is

complete

The reset command may be written between the cycles in a program command sequence

before programming begins (prior to the third cycle). This resets the bank to which the

system was writing to the read mode.

Software Functions and Sample Code

Ta b l e 7 . 2 5 . R e s e t

(LLD Function = lld_Re setCmd)

Cycle Operation Byte Address Word Address Data

Res et Command W rite Base + xxxh Base + xxxh 00F0h

January 25, 2005 S29WS-N_00_G0 49

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If the program command sequence is written to a bank that is in the Erase Suspend

mode, writing the reset command returns that bank to the erase-suspend-read mode.

The reset command may be also written during an Autoselect command sequence.

If a bank has entered the Autoselect mod e whil e in the Er ase Susp end mode, writing the

reset command returns tha t bank to the erase-suspend-read mode.

If DQ1 goes high during a Write Buffer Programming operation, the system must write

the "Write to Buffer Abort Reset" command sequence to RESET the device to reading

array data. The standard RESET command does not work during this condition.

To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset

command sequence [see command table for details].

50 S29WS-N_00_G0 January 25, 2005

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8 Advanced Sector Protection/Unprotection

The Advanced Sector Protection/Unprotection feature disables or enables programming or erase

operations in any or all sectors and can be implemented through software and/or hardware meth-

ods, which are independent of each other. This section describes the various methods of

protecting data stored in the memory array. An overview of these methods in shown in Figure 8.1.

Figure 8.1. Advanced Sector Protection/Unprotection

Hardware Methods Software Methods

ACC = V

(

All sectors locked)

WP# = V

(All boot

sectors locked)

Password Method

(DQ2)

Persistent Method

(DQ1)

Lock Register

(One Time Programmable)

PPB Lock Bit

1,2,3

64-bit Password

(One Time Protect)

1 = PPBs Unlocked

0 = PPBs Locked

Memory Array

Sector 0

Sector 1

Sector 2

Sector N-2

Sector N-1

Sector N

PPB 0

PPB 1

PPB 2

PPB N-2

PPB N-1

PPB N

Persistent

Protection Bit

(PPB)

4,5

DYB 0

DYB 1

DYB 2

DYB N-2

DYB N-1

DYB N

Dynamic

Protection Bit

(PPB)

6,7,8

6. 0 = Sector Protected,

1 = Sector Unprotected.

7. Protect effective only if PPB Lock Bit

is unlocked and corresponding PPB

is “1” (unprotected).

8. Volatile Bits: defaults to user choice

upon power-up (see ordering

options).

4. 0 = Sector Protected,

1 = Sector Unprotected.

5. PPBs programmed individually,

but cleared collectively

1. Bit is volatile, and defaults to “1” on

reset.

2. Programming to “0” locks all PPBs to

their current state.

3. Once programmed to “0”, requires

hardware reset to unlock.

3. N = Highest Address Sector.

January 25, 2005 S29WS-N_00_G0 51

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8.1 Lock Register

As shipped from the factory , all devices default to the persistent mode when power is applied, and

all sectors are unprotected, unless otherwise chosen through the DYB ordering option (see Or-

dering Information). The device programmer or host system must then choose which sector

protection method to use. Programming (setting to “0”) any one of the following two one-time

programmable, non-volatile bits locks the part permanently in that mode:

Lock Register Persistent Protection Mode Lock Bit (DQ1)

Lock Register Password Protection Mode Lock Bit (DQ2)

Table 8.1. Lock Register

For programming lock register bits refer to Table 12.2.

Notes

1. If the pa ss word mod e is cho sen, the p asswor d m u st be p rog rammed be fore set ting t he cor-

responding lock register bit.

2. After the Lock Register Bits Command Set Entry command sequence is written, reads and

writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this

mode.

3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation

aborts.

4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently

disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent

Mode Lock Bit is programmed, the Password Mode is permanently disabled.

After selecting a sector protection method, each sector can operate in any of the following three

states:

1. Constantly locked. The selected sectors are protected and can not be reprogrammed

unless PPB lock bit is cleared via a password, hardware reset, or power cycle.

2. Dynamically locked. The selected sectors are protected and can be altered via software

commands.

3. Unlocked. The sectors are unprotected and can be erased and/or programmed.

These states are controlled by the bit types describ ed in Sections 8. 2–8.6.

8.2 Persistent Protection Bits

The Persistent Protection Bits are unique and nonvolatile for each sector and have the same en-

durances as the Flash memory. Preprogramming and v erification prior to er asure are handled by

the device, and therefore do not require system monitoring.

Notes

1. Each PPB is individually programmed and all are erased in parallel.

2. While pro gramming PPB for a sector, array data can be read from any other bank, ex-

cept Bank 0 (used for Data# Polling) and the bank in which sector PPB is being

programmed.

Device DQ15-05 DQ4 DQ3 DQ2 DQ1 DQ0

S29WS256N 1 1 1 Password

Protection

Mode Lock Bit

Persistent

Protection

Mode Lock Bit

Customer

SecSi Sector

Protection Bit

S29WS128N/

S29WS064N Undefined

DYB Lock Boot Bit

0 = sectors

power up

protected

1 = sectors

power up

unprotected

PPB One-Time

Programmable Bit

0 = All PPB erase

command disabled

1 = All PPB Erase

command enabled

Password

Protection

Mode Lock Bit

Persistent

Protection

Mode Lock Bit

SecSi Sector

Protection Bit

52 S29WS-N_00_G0 January 25, 2005

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3. Entry command disables reads and writes for the bank selected.

4. Reads within that bank return the PPB status for th at sector.

5. Reads from other banks are allowed while writes are not allowed.

6. All Reads must be performed using the Asynchronous mode.

7. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N)

are written at the same time as the program command.

8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and

times-out without programming or erasing the PPB.

9. There are no means for individually erasing a specific PPB and no specific sector address

is required for this operation.

10. Exit command must be issued afte r the exec ution which resets the device to read mode

and re-enables reads and writes for Bank 0

11. The programming state of the PPB for a given sector can be verified by writing a PPB

Status Read Command to the device as described by the flow chart shown in Figure 8.2.

January 25, 2005 S29WS-N_00_G0 53

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Figure 8.2. PPB Program/Erase Algorithm

8.3 Dynamic Protection Bits

Dynamic Protection Bits are volatile and unique for each sector and can be ind ividually modified.

DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared

(erased to “1”). By issuing the DYB Set or Clear command sequences, the DYBs are set (pro-

grammed to “0”) or cleared (erased to “1”), thus placing each sector in the protected or

unprotected state respectively. This feature allows software to easily protect sectors against in-

advertent changes yet does not prevent the easy removal of protection when changes are

needed.

Read Byte Twice

Addr = SA0

Enter PPB

Command Set.

Addr = BA

Program PPB Bit.

Addr = SA

DQ5 = 1?

Yes

DQ6 =

Toggle?

DQ6 =

Toggle? Read Byte.

Addr = SA

PASS

FAIL

Issue Reset

Command

Exit PPB

Command Set

DQ0 =

'1' (Erase)

'0' (Pgm.)?

Read Byte Twice

Addr = SA0

Wait 500 µs

54 S29WS-N_00_G0 January 25, 2005

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Notes

1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed.

When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or reset,

the DYBs can be set or cleared depending upon the ordering option chosen.

2. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectors

may be modified depending upon the PPB state of that sector (see Table 8.2).

3. The sectors would be in the protected state If the option to set the DYBs after power up

is chosen (programmed to “0”).

4. It is possible to have sectors that are persis tently locked with sectors that are left in the

dynamic state.

5. The DYB Set or Clear commands for the dynamic sectors signify protected or unpro-

tectedstate of the sect ors respectiv ely. However, if there i s a need to change the st atus

of the persistently lock ed sectors, a few more steps are required. First, the PPB Loc k Bit

must be cleared by either putting the device through a power-cycle, or hardware reset.

The PPBs can then be change d to reflect the desire d settings. Set ting the PPB Lock Bit

once again locks the PPBs, and the device operates normally again.

6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set com-

mand early in the boot code and protec t the boot code by holding WP# = V IL. Note that

the PPB and DYB bits have the same function when ACC = VHH as they do when ACC

=VIH.

8.4 Persistent Protection Bit Lock Bit

The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed

to “0”), it locks all PPBs and when cleared (programmed to “1”), allows the PPBs to be changed.

There is only one PPB Lock Bit per device.

Notes

1. No software command sequence unlocks this bit unless the device is in the password

protection mode; only a hardware reset or a power-up clears this bit.

2. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to

the desired settings.

8.5 Password Protection Method

The Password Protection Method allows an even higher level of security than the P ersistent Sector

Protection Mode by requiring a 6 4 bit password for unlocking the device PPB Lock Bit. In addition

to this password requirement, after power up and reset, the PPB Lock Bit is set “0” to maintain

the password mode of operation. Successful execution of the Password Unlock command by en-

tering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.

Notes

1. There is no special addres sing orde r requ ired for programming the password. Once the

Password is w ritten and verified, the P assword Mode Locking Bit must be set in order to

prevent access.

2. The Passwor d Progr am Comm and is onl y capabl e of progra mming “0” s. Pr ogramming a

“1” after a cell is programmed as a “0” results in a time-out with the cell as a “0”.

3. The password is all “1”s when shipped from the factory.

4. All 64-bit password combinations are valid as a password.

5. There is no means to verify what the password is after it is set.

6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the

data bus and further password programming.

7. The Password Mode Lock Bit is not erasable.

8. The lower two address bits (A1–A0) are v alid during the P assword R ead , Pass word Pro-

gram, and Password Unlock.

9. The exact password must be entered in order for the unlocking function to occur.

January 25, 2005 S29WS-N_00_G0 55

Advance Information

10. The Password Unlock command cannot be issued any faster than 1 µs at a time to pre-

vent a hacker from running through all the 64-bit combinations in an attempt to

correctly match a password.

11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password

is given to the device.

12. Password verification is only allowed during the password programming operation.

13. All further commands to the password region are disabled and all operations are

ignored.

14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear

the PPB Lock Bit.

15. Entry command sequence must be issued prior to any of any operation and it disables

reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are

allowed.

16. If the user attempts to program or erase a protected sector, the device ignores the com-

mand and returns to read mode.

17. A program or erase command to a protected sector enables status polling and returns

to read mode without having modified the contents of the protected sector.

18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by

writing individual status read commands DYB Status, PPB Status, and PPB Lock Status

to the device.

56 S29WS-N_00_G0 January 25, 2005

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Figure 8.3. Lock Register Program Algorithm

Write Unlock Cycles:

Address 555h, Data AAh

Address 2AAh, Data 55h

Write

Enter Lock Register Command:

Address 555h, Data 40h

Program Lock Register Data

Address XXXh, Data A0h

Address 77h*, Data PD

Unlock Cycle 1

Unlock Cycle 2

XXXh = Address don’t care

* Not on future devices

Program Data (PD): See text for Lock Register

definitions

Caution: Lock register can only be progammed

once.

Wait 4 µs

PASS. Write Lock Register

Exit Command:

Address XXXh, Data 90h

Address XXXh, Data 00h

Device returns to reading array.

Perform Polling Algorithm

(see Write Operation Status

flowchart)

Yes

Done?

DQ5 = 1? Error condition (Exceeded Timing Limits)

FAIL. Write rest command

to return to reading array.

January 25, 2005 S29WS-N_00_G0 57

Advance Information

8.6 Advanced Sector Protection Software Examples

Table 8.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the sta-

tus of the sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs

are allowed. The PPB Lock Bit can only be unlocked (reset to “1”) through a hardware reset or

power cycle. See also Figure 8.1 for an overview of the Advanced Sector Protection feature.

8.7 Hardware Data Protection Methods

The device offers two main types of data protection at the sector level via hardware control:

When WP# is at VIL, the four outermost sectors are locked (device specific).

When ACC is at VIL, all sectors are locked.

There are additional methods by which intended or accidental er asure of any sectors can be pre-

vented via hardware means. The following subsections describes these methods:

8.7.1. WP# Method

The Write Protect feature provides a hardware method of protecting the four outermost sectors.

This function is provided by the WP# pin and overrides the previously discussed Sector Protec-

tion/Unprotection method.

If the system asserts VIL on the WP# pin, the device disables progr am and er ase functions in the

“outermost” boot sectors. The outermost boot sectors are the sectors containing both the lower

and upper set of sectors in a dual-boot-configured device.

If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were

last set to be protected or unprotected. That is, sector protection or unprotection for these sectors

depends on whether they were last protected or unprotected.

Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the

device may result.

The WP# pin must be held stable during a command sequence execution

8.7.2 ACC Method

This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all

program and erase function s are disabled and hence all sectors are protected .

8.7.3 Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cy cles. This protects data during

VCC power-up and power-down.

Table 8.2. Sector Protection Schemes

Unique Device PPB Lock Bit

0 = locked

1 = unlocked

Sector PPB

0 = protected

1 = unprotected

Sector DYB

0 = protected

1 = unprotected

Sector Protection Status

Any Sector 0 0 x Protected through PPB

Any Sector 0 1 1 Unprotected

Any Sector 0 1 0 Protected through DYB

Any Sector 1 0 x Protected through PPB

Any Sector 1 1 0 Protected through DYB

Any Sector 1 1 1 Unprotected

58 S29WS-N_00_G0 January 25, 2005

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The command register and all internal progr am/erase circuits are disa bled, and the device resets

to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system

must provide the proper signals to the control inputs to prev ent unintenti onal writes when V CC is

greater than VLKO.

8.7.4 Write Pulse “Glitch Protection”

Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

8.7.5 Power-Up Write Inhibit

If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept com -

mands on the rising edge of WE#. The internal state machine is automatically reset to the read

mode on power-up.

January 25, 2005 S29WS-N_00_G0 59

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9 Power Conservation Modes

9.1 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby

mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the

high impedance state, independent of the OE# input. The device enters the CMOS standby mode

when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard

access time (tCE) for read access, before it is ready to read data. If the device is deselected during

erasure or progr amming, the device draws active current until the operation is completed. ICC3 in

“DC Characteristics” represents the standby current specification

9.2 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption while in asynchronous

mode. the device automatically enables this mode when addresses remain stable for tACC + 20

ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-

dard address access timings provide new data when addresses are changed. While in sleep mode,

output data is latched and always av ailable to the system. While in synchronous mode, the auto-

matic sleep mode is disabled. Note that a new burst operation is required to provide new data.

ICC6 in “DC Characteristics” represents the automatic sleep mode current specification.

9.3 Hardware RESET# Input Operation

The RESET# input provides a hardware method of resetting the device to reading array data.

When RESET# is driven low for at least a period of tRP, the device immediately terminates any

operation in progress, tristates all outputs, resets the configur ation register, and ignores all read/

write commands for the duration of the RESET# pu lse. The device also resets the internal state

machine to reading arr ay data. The opera tion that w as interrupted should be reinitiated once the

device is ready to accept another command sequence to ensure data integrity.

When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET#

is held at VIL but not within V SS ± 0.2 V, the standby current is greater.

RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the

Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

9.4 Output Disable (OE#)

When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the

high impedance state.

60 S29WS-N_00_G0 January 25, 2005

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10 Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector provides an extra Flash memory region that enables permanent part

identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words

in length that consists of 128 wo rds f or facto ry d ata and 128 words f or customer -secured a reas.

All Secured Silicon reads outside of the 256-word address range returns inv alid data. The Factory

Indicator Bit, DQ7, (at Autosele ct address 03h) is used to indicate whether or not the F actory Se-

cured Silicon Sector is locked when shipped fro m the factory. The Customer Indicator Bit (DQ6)

is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped

from the factory.

Please note the following general conditions:

While Secured Silicon Sector access is enabled, simultaneous operations are allowed ex-

cept for Bank 0.

On power-up, or following a hardw are reset, the device rev e rts to sending command s to

the normal address space.

Reads can be performed in the Asynchronous or Synchronous mode.

Burst mode reads within Secured Silicon Sector wrap from address FFh back to address

00h.

Reads outside of sector 0 return memory array data.

Continuous burst read past the maximum address is undefined.

Sector 0 is remapped from memory array to Secured Silicon Sector array.

Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit

command must be issued to exit Secured Silicon Sector Mode.

The Secured Silicon Sector is not accessible when the device is executing an Embedded

Program or Embedded Erase algorithm.

Table 10.1. Secured Silicon Sector Addresses

10.1 Factory Secured Silicon Sector

The Factory Secured Silicon Sector is always protected when shipped from the factory and has

the F actory Indicator Bit (DQ7) perm anently set to a “1”. This prevents cloning of a factory locked

part and ensures the security of the ESN and customer code once the product is shipped to the

field.

These devices are available pre prog rammed with one of the following:

A random, 8 Word secure ESN only within the Factory Secured Silicon Sector

Customer code within the Customer Secured Silicon Sector through the SpansionTM pro-

gramming service.

Both a random, secure ESN and customer code through the Spansion programming ser-

vice.

Customers may opt to have their code progr ammed through the Spansion programming services.

Spansion programs the customer's code, with or without the random ESN. The devices are then

shipped from the Spansion factory with the F actory Secured Silicon Sector and Customer Secured

Silicon Sector permanently locked. Contact your local representative for details on using Spansion

programming services.

Sector Sector Size Address Range

Customer 128 words 000080h-0000FFh

Fact ory 128 words 000000h-00007F h

January 25, 2005 S29WS-N_00_G0 61

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10.2 Customer Secured Silicon Sector

The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to “0”), al lowin g

customers to utilize that sector in any manner they choose. If the security feature is not required,

the Customer Secured Silicon Sector can be treated as an additional Flash memory space.

Please note the following:

Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit

is permanently set to “1.”

The Customer Secured Silicon Sector can be read any number of times, but can be pro-

grammed and locked only once. The Customer Secured Silicon Sector lock must be used

with caution as once locked, there is no procedure available for unlocking the Customer

Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector

memory space can be modified in any way.

The acceler ated p rogr amming (ACC ) and unloc k bypass functions are not a v ailable whe n

programming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is

available.

Once the Customer Secured Silicon Sector is locked and verified, the system must write

the Exit Secured Silicon Sector R egion command sequence which return the device to the

memory array at sector 0.

10.3 Secured Silicon Sector Entry and Secured Silicon Sector

Exit Command Sequences

The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured

Silicon Sector command sequence. The device continues to access the Secured Silicon Sector re-

gion until the system issues the four-cycle Exit Secured Silicon Sector command sequence.

See Command Definition Table [Secured Silicon Sector Command Table, Appendix

Table 12.1 for address and data requirements for both command sequences.

The Secured Silicon Sector Entry Command allows the following commands to be executed

Read customer and factory Secured Silicon areas

Program the customer Secured Silicon Sector

After the system has written the Enter Secured Silicon Sector command sequence, it may read

the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the

memory array. This mode of operation continues until the system issues the Exit Secured Silicon

Sector command sequence, or until power is removed from the device.

The following are C functions and source code examples of using the Secured Silicon Sector

Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User’s Guide

(av ailable soon on www .amd.com and www .fujitsu.com) for gener al informat ion on Spansion

Flash memory softwar e dev el opment gui deline s.

Note: Base = Base Address.

Software Functions and Sample Code

Table 10.2. Secured Silicon Sector Entry

(LLD Function = lld_SecSiSectorEntryCmd)

Cycle Operation Byte Address Word Address Data

Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh

Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h

Entry Cycle Write Base + AAAh Base + 555h 0088h

62 S29WS-N_00_G0 January 25, 2005

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/* Example: SecSi Sector Entry Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)base_addr + 0x555 ) = 0x0088; /* write Secsi Sector Entry Cmd */

Note: Base = Base Address.

/* Once in the SecSi Sector mode, you program */

/* words using the programming algorithm. */

Note: Base = Base Address.

/* Example: SecSi Sector Exit Command */

*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */

*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */

*( (UINT16 *)base_addr + 0x555 ) = 0x0090; /* write SecSi Sector Exit cycle 3 */

*( (UINT16 *)base_addr + 0x000 ) = 0x0000; /* write SecSi Sector Exit cycle 4 */

Table 10.3. Secured Silicon Sector Program

(LLD Function = lld_ProgramCmd)

Cycle Operation Byte Address Word Address Data

Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh

Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h

Program Setup Write Base + AAAh Base + 555h 00A0h

Program W rite Wo rd Address Word Address Data W ord

Table 10.4. Secured Silicon Sector Exit

(LLD Function = lld_SecSiSectorExitCmd)

Cycle Operation Byte Address Word Address Data

Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh

Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h

Exit Cycle Write Base + AAAh Base + 555h 0090h

January 25, 2005 S29WS-N_00_G0 63

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11 Electrical Specifications

11.1 Absolute Maximum Ratings

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C

Voltage with Respect to Ground:

All Inputs and I/O s except

as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to VIO + 0.5 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V

VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V

ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +9.5 V

Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Notes:

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or

I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1.

Maximum DC voltage on input or I/Os is VCC + 0.5 V. Du ring voltage transitions

outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11.2 .

2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may

overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1 . Maximum DC

voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.

3. No more than one output m ay be shorted to ground at a time. Duration of the short

circuit should not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

data sheet is not implied. Exposure of the device to absolute maximum rating conditions

for extended periods may affect device reliability.

64 S29WS-N_00_G0 January 25, 2005

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Notes:

1. The conten t in this document is Adv ance i nformation f or the S 29WS064N and S29WS128N. Co nten t in th is do cument is Preliminary for t he

S29W256N.

11.2 Operating Ranges

Wireless (W) Devices

Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Supply Voltages

VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V

VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V

(Contact local sales off ice fo r VIO = 1.35 to +1.70 V.)

Notes: Operating ranges define those limits between which the functionality of the device

is guaranteed.

11.3 Test Conditions

Figure 11.1. Maximum Negative Overshoot

Waveform

Figure 11.2. Maximum Positive Overshoot

Waveform

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

20 ns

+2.0 V

+0.5 V

20 ns

1.0 V

Device

Under

Test

Figure 11.3. Test Setup

January 25, 2005 S29WS-N_00_G0 65

Advance Information

Table 11.1. Test Specifications

Notes:

1. The conten t in this document is Adv ance i nformation f or the S 29WS064N and S29WS128N. Co nten t in th is do cument is Preliminary for t he

S29W256N.

11.4 Key to Switching Waveforms

Notes:

1. The conten t in this document is Adv ance i nformation f or the S 29WS064N and S29WS128N. Co nten t in th is do cument is Preliminary for t he

S29W256N.

Test Condition All Speed Options Unit

Output Load Capacitance, C

(including jig capacitance) 30 pF

Input Rise and Fall Times 3.0 @ 54, 66 MHz

2.5 @ 80 MHz ns

Input Pulse Levels 0.0– V

Input timing measurement

reference levels V

/2 V

Output timing meas urement

reference levels V

/2 V

Waveform Inputs Outputs

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitte d C hanging, Stat e Unknown

Does Not Apply Center Line is High Impedance State (High Z)

66 S29WS-N_00_G0 January 25, 2005

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11.5 Switching Waveforms

11.6 VCC Power-up

Notes:

1. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100µs

2. VCC ramp rate <1V / 100µs, a Hardware Reset is required.

3. The content in this document is Advance information for the S29WS064N and

S29WS128N. Content in this document is Preliminary for the S29W256N.

Figure 11.5. VCC Power-up Diagram

Parameter Description Test Setup Speed Unit

VCS

Setup Time Min 1 ms

VIO

0.0 V

OutputMeasurement LevelInput VIO/2 VIO/2All Inputs and Outputs

Figure 11.4. Input Waveforms and Measurement Levels

RESET#

VCS

January 25, 2005  S29WS-N_00_G0 67
Advance Information
11.7  DC Characteristics (CMOS Compatible)
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. VCC= VIO.
3. CE# must be set high when measuring the RDY pin.
4. The ICC current listed is typically less than 3 mA/MHz, with OE# at VIH.
5. ICC active while Embedded Erase or Embedded Program is in progress.
6. Device enters automatic sleep mode when addresses are s table for t ACC + 20 ns. 
Typical sleep mode current is equal to ICC3.
7. VIH = VCC ± 0.2 V and VIL > –0.1 V.
8. Total current during accelerated programming is the sum of VACC and VCC 
currents.
9. VACC = VHH on ACC input.
10.The content in this document is Advance information for the S29WS064N and 
S29WS128N. Content in this document is Preliminary for the S29W256N.
Parameter Description (Notes) Test Conditions (Notes 1, 2, 9) Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCCmax ±1 µA
ILO Output Leakage Current (3) VOUT = VSS to VCC, VCC = VCCmax ±1 µA
ICCB VCC Active burst Read Current
CE# = VIL, OE# = VIH, WE# 
= VIH, burst length = 8
54 MHz 27 54 mA
66 MHz 28 60 mA
80 MHz 30 66 mA
CE# = VIL, OE# = VIH, WE# 
= VIH, burst length = 16
54 MHz 28 48 mA
66 MHz 30 54 mA
80 MHz 32 60 mA
CE# = VIL, OE# = VIH, WE# 
= VIH, burst length = 32
54 MHz 29 42 mA
66 MHz 32 48 mA
80 MHz 34 54 mA
CE# = VIL, OE# = VIH, WE# 
= VIH, burst length = 
Continuous
54 MHz 32 36 mA
66 MHz 35 42 mA
80 MHz 38 48 mA
IIO1 VIO Non-active Output OE# = VIH 20 30 µA
ICC1 VCC Active Asynchronous  
Read Current (4) CE# = VIL, OE# = VIH, WE# 
= VIH
10 MHz 27 36 mA
5 MHz 13 18 mA
1 MHz 3 4 mA
ICC2 VCC Active Write Current (5) CE# = VIL, OE# = VIH, ACC 
= VIH
VACC 15µA
VCC 19 52.5 mA
ICC3 VCC Standby Current (6, 7) CE# = RESET# = 
VCC ± 0.2 V VACC 15µA
VCC 20 40 µA
ICC4 VCC Reset Current (7) RESET# = VIL, CLK = VIL 70 150 µA
ICC5 VCC Active Current  
(Read While Write) (7) CE# = VIL, OE# = VIH, ACC = VIH @ 
5 MHz 50 60 mA
ICC6 VCC Sleep Current (7) CE# = VIL, OE# = VIH 240µA
IACC Ac celerated Program Current (8) CE# = VIL, OE# = VIH, 
VACC = 9.5 V VACC 620mA
VCC 14 20 mA
VIL Input Low Voltage VIO = 1.8 V –0.5 0.4 V
VIH Input High Voltage VIO = 1.8 V VIO – 0.4 V IO + 0.4 V
VOL Output Low Voltage IOL = 100 µA, VCC = VCC min = VIO  0.1 V
VOH Output High Voltage IOH = –100 µA, VCC = VCC min = VIO  VIO – 0.1  V
VHH V oltage for Accelerated Progr am  8.5 9.5 V
VLKO Low VCC Lock-out Vo ltage 1.0 1.4 V

68 S29WS-N_00_G0 January 25, 2005

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11.8 AC Characteristics

11.8.1. CLK Characterization

Notes:

1. The content in this document is Advance information for the S29WS064N and

S29WS128N. Content in this document is Preliminary for the S29W256N.

Figure 11.6. CLK Characterization

Parameter Description 54 MHz 66 MHz 80 MHz Unit

CLK

CLK Frequency Max 54 66 80 MHz

CLK

CLK P eriod Min 18.5 15.1 12.5 ns

CLK High Time Min 7.4 6.1 5.0 ns

CLK Low Time

CLK Rise Time Max 3 3 2.5 ns

CLK Fall Time

tCLK

tCL

tCH

tCR tCF

CLK

January 25, 2005 S29WS-N_00_G0 69

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11.8.2 Synchronous/Burst Read

Notes:

1. Addresses are latched on the first rising edge of CLK.

2. Not 100% tested.

3. The content in this document is Advance information for the S29WS064N and

S29WS128N. Content in this document is Preliminary for the S29W256N.

Parameter

Description 54 MHz 66 MHz 80 MHz UnitJEDEC Standard

IACC

Latency Max 80 ns

BACC

Burst Access Time Valid Clock to Output Delay Max 13.5 11.2 9 ns

ACS

Address Setup Time to CLK (Note 1) Min 5 4 ns

ACH

Address Hold Tim e from CLK ( Note 1) Min 7 6 ns

BDH

Data Hold Time fro m Next Clo ck C ycle Min 4 3 ns

Chip Enable to RDY Valid Max 13.5 11.2 9 ns

Output Enable to Outpu t Valid Max 13.5 11.2 ns

CEZ

Chip En able to High Z (Note 2 ) Max 10 ns

OEZ

Output Enable to High Z (Note 2) Max 10 ns

CES

CE# Se tup Time to CLK Min 4 ns

RDYS

RDY Se tup Time to CLK Min 5 4 3.5 ns

RACC

Ready Access Time from CLK Max 13.5 11.2 9 ns

CAS

CE# Setup Time to AVD# M in 0 ns

AVC

AVD# Low to CLK Min 4 ns

AVD

A VD# Pulse Min 8 ns

AOE

AVD Low to OE# Low Max 38.4 ns

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11.8.3 Timing Diagrams

Notes:

1. Figure shows total number of wait states set to five cycles. The total number of

wait states can be programmed from two cycles to seven cycles.

2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”,

additional clock delay cycles are inserted , and are indicated by RDY.

3. The device is in synchronous mode.

Figure 11.7. CLK Synchronous Burst Mode Read

Da Da + 1 Da + n

OE#

Data (n)

Addresses

AVD#

RDY (n)

CLK

CE# t

CES

ACS

AVC

AVD

ACH

RACC

OEZ

CEZ

IACC

AOE

BDH

5 cycles for initial access shown.

18.5 ns typ. (54 MHz)

Hi-Z

Hi-Z Hi-Z

1234567

RDYS

BACC

Da + 3

Da + 2

Da Da + 1 Da + n

Data (n + 1)

RDY (n + 1)

Hi-Z

Hi-Z Hi-Z

Da + 2

Da Da + 1 Da + n

Data (n + 2)

RDY (n + 2)

Hi-Z

Hi-Z Hi-Z

Da + 1

Da Da Da + n

Data (n + 3)

RDY (n + 3)

Hi-Z

Hi-Z Hi-Z

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Notes:

1. Figure shows total n umber of wait states set to seven cycles. The to tal number o f wait states can be programmed from t wo cycl es to seven

cycles.

2. If any burst address o ccu rs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are in dicated

by RDY.

3. The device is in synchronous mode with wrap around.

4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure

is the 4th address in range (0-F).

Figure 11.8. 8-word Linear Burst with Wrap Around

Notes:

1. Figure shows total n umber of wait states set to seven cycles. The to tal number o f wait states can be programmed from t wo cycl es to seven

cycles. Clock is set for active rising edge.

2. If any burst address o ccu rs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are in dicated

by RDY.

3. The device is in asynchronous m ode with out wr ap around.

4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address i n figure

is the 1st address in range (c-13).

Figure 11.9. 8-word Linear Burst without Wrap Around

DC DD

OE#

Data

Addresses

AVD#

RDY

CLK

CE# t

CES

ACS

AVC

AVD

ACH

IACC

AOE

BDH

DE DF DB

7 cycles for initial access shown.

Hi-Z

RACC

1234567

RDYS

BACC

RACC

DC DD

OE#

Data

Addresses Ac

AVD#

RDY

CLK

CE# tCES

tACS

tAVC

tAVD

tACH

tOE

tIACC tBDH

DE DF D13

Hi-Z tRACC

1234567

tRDYS

tBACC

tCR

D10

tRACC

tAOE

7 cycles for initial access shown.

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Notes:

1. Figure assumes 6 wait states for initial access and synchronous read.

2. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one

cycle before valid data.

Figure 11.10. Linear Burst with RDY Set One Cycle Before Data

11.8.4 AC Characteristics—Asynchronous Read

Notes:

1. Not 100% tested.

2. The content in this document is Advance information for the S29WS064N and

S29WS128N. Content in this document is Preliminary for the S29W256N.

Parameter

Description 54 MHz 66 MHz

MHz UnitJEDEC Standard

Access Time from CE # Low Max 80 ns

ACC

Asynchronous Access T im e Max 80 ns

AVDP

AVD# Low Time Min 8 ns

AAVDS

Address Se tup Time to Rising Ed ge of AVD# Min 4 ns

AAVDH

Address Hold Time from Rising Edge of AVD# Min 7 6 ns

Output Enab le to Output Valid Max 13.5 ns

OEH

Output Enab le Hold Tim e Read Min 0 ns

Toggle and Data# Polling Min 10 ns

OEZ

Output Enab le to High Z (se e N ote) Max 10 ns

CAS

CE# Setup Time to AVD# Min 0 ns

Da+1Da Da+2 Da+3 Da + n

OE#

Data

Addresses Aa

AVD#

RDY

CLK

CE# tCES

tACS

tAVC

tAVD

tACH

tOE

tRACC tOEZ

tCEZ

tIACC

tAOE tBDH

6 wait cycles for initial access shown.

Hi-Z

Hi-Z Hi-Z

123456

tRDYS

tBACC

tCR

January 25, 2005 S29WS-N_00_G0 73

Advance Information

Note:

RA = Read Address, RD = Read Data.

Figure 11.11. Asynchronous Mode Read

WE#

Addresses

CE#

OE#

Valid RD

ACC

OEH

Data

OEZ

AAVDH

AVDP

AAVDS

AVD#

CAS

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11.8.5 Hardware Reset (RESET#)

Notes:

1. Not 100% tested.

2. The content in this document is Advance information for the S29WS064N and

S29WS128N. Content in this document is Preliminary for the S29W256N.

Figure 11.12. Reset Timings

Parameter

Description All Speed Options UnitJEDEC Std.

RESET# Pu lse Wi dth M in 30 µs

Re set High Tim e Before Read (See Note) Min 200 ns

RESET#

CE#, OE#

January 25, 2005 S29WS-N_00_G0 75

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11.8.6 Erase/Program Timing

Notes:

1. Not 100% tested.

2. Asynchronous read mode allows Asynchronous progr a m operation only. Synchronous read mode allows both Asynchronous and

Synchronous program operation.

3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing,

addresses are latched on the rising edge of CLK.

4. See the “Erase and Programming Performance” section for more information.

5. Does not include the preprogr amming time.

6. The conten t in this document is Adv ance i nformation f or the S 29WS064N and S29WS128N. Co nten t in th is do cument is Preliminary for t he

S29W256N.

Parameter

Description 54 MHz 66 MHz 80 MHz UnitJEDEC Standard

tAVAV tWC Write Cycle Time (Note 1) Min 80 ns

tAVWL tAS Address Setup Time (Notes 2, 3) Synchronous Min 5ns

Asynchronous 0 ns

tWLAX tAH Address Hold Time (Notes 2, 3) Synchronous Min 9ns

Asynchronous 20

tAVDP AVD# Low Time Min 8 ns

tDVWH tDS Data Setup Time Min 45 20 ns

tWHDX tDH Data Hold Time Min 0 ns

tGHWL tGHWL Read Recovery Time Before Write Min 0 ns

tCAS CE# Setup Time to AVD# Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 30 ns

tWHWL tWPH Write Pulse Width High Min 20 ns

tSR/W Latency Between Read and Write Operations Min 0 ns

tVID VACC Rise and Fall Time Min 500 ns

tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs

tVCS VCC Setup Time Min 50 µs

tELWL tCS CE# Setup Time to WE# Min 5 ns

tAVSW AVD# Setup Time to WE# Min 5 ns

tAVHW AVD# Hold Time to WE# Min 5 ns

tAVSC AVD# Setup Time to CLK Min 5 ns

tAVHC AVD# Hold Time to CLK Min 5 ns

tCSW Clock Setup Time to WE# Min 5 ns

tWEP Noise Pulse Margin on WE# Max 3 ns

tSEA Sector Erase Accept Time-out Max 50 µs

tESL Erase Suspend Latency Max 20 µs

tPSL Program Suspend Latency Max 20 µs

tASP Toggle Time During Sector Protec tion Typ 100 µs

tPSP Toggle Time During Programming Within a Protected Sector Typ 1 µs

76 S29WS-N_00_G0 January 25, 2005

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Figure 11.13. Chip/Sector Erase Operation Timings

OE#

CE#

Data

Addresses

AVD#

WE#

CLK

WPH

VCS

Progress

WHWH2

Complete

Erase Command Sequence (last two cycles) Read Status Data

10h for

chip erase

555h for

chip erase

AVDP

55h

2AAh

30h

January 25, 2005 S29WS-N_00_G0 77

Advance Information

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during

command sequence unlock cycles.

4. CLK can be either VIL or VIH.

5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the

Configuration Register.

Figure 11.14. Asynchronous Program Operation Timings

OE#

CE#

Data

Addresses

AVD#

WE#

CLK

555h

AVSW

AVHW

WPH

VCS

Progress

WHWH1

Complete

Program Command Sequence (last two cycles) Read Status Data

VIH

VIL

AVDP

A0h

CAS

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Advance Information

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. “In progress” and “complete” refer to status of program operation.

3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during

command sequence unlock cycles.

4. Addresses are latched on the first rising edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration

Figure 11.15. Synchronous Program Operation Timings

OE#

CE#

Data

Addresses

WE#

CLK

VCC

555h

tWC

tWPH

tWP

tVCS

tDH

tCH

Progress

tWHWH1

Complete

Program Command Sequence (last two cycles) Read Status Data

tDS

tAVDP

A0h

tAS

tCAS

tAH

tAVCH

tCSW

tAVSC

AVD#

January 25, 2005 S29WS-N_00_G0 79

Advance Information

Note: Use setup and hold times from conventional program operation.

Figure 11.16. Accelerated Unlock Bypass Programming Timing

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data#

Polling outputs true data.

Figure 11.17. Data# Polling Timings (During Embedded Algorithm)

CE#

AVD#

WE#

Addresses

Data

OE#

ACC

Don't Care Don't CareA0h Don't Care

VID

VIL or VIH

VID

VIDS

WE#

CE#

OE#

High Z

Addresses

AVD#

OEH

OEZ

CEZ

Status Data Status Data

ACC

VA VA

Data

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Advance Information

Notes:

1. Status reads in figure are shown as asynchronous.

2. VA = Valid Address. Two read cycles are required to determine status. When the E mbedded Algorith m operation is complete, the toggle bits

stop toggling.

Figure 11.18. Toggle Bit Timings (During Embedded Algorithm)

Notes:

1. The timings are similar to synchronous read timings.

2. VA = Valid Address. Two read cycles are required to determine status. When the E mbedded Algorith m operation is complete, the toggle bits

stop toggling.

3. RDY is a ctive with d ata (D8 = 1 in the Configu ration Regist er). W h en D8 = 0 i n t h e C on f ig u ra t i on R e g is t er , R D Y i s a ct i v e on e clock cycle before

data.

Figure 11.19. Synchronous Data Polling Timings/Toggle Bit Timings

WE#

CE#

OE#

High Z

tOE

High Z

Addresses

AVD#

tOEH

tCE

tCH tOEZ

tCEZ

Status Data Status Data

tACC

VA VA

Data

CE#

CLK

AVD#

Addresses

OE#

Data

RDY

Status Data Status Data

VA VA

IACC

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Advance Information

Notes:

1. RDY(1) active with data (D8 = 1 in the Configuration Register).

2. RDY(2) active one clock cycle before data (D8 = 0 in th e Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.

4. Figure shows the device not crossing a bank in the process of performing an erase or program.

5. RDY does no t go low and no addition al wait states are required if t he B urst freque ncy is < =6 6 MHz and th e Bo undary Crossing b it (D14) in

the Configuration Register is set to 0

Figure 11.21. Latency with Boundary Crossing when Frequency > 66 MHz

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#

to toggle DQ2 and DQ6.

Figure 11.20. DQ2 vs. DQ6

CLK

Address (hex)

C124 C125 C126 C127 C127 C128 C129 C130 C131

D124 D125 D126 D127 D128 D129 D130

(stays high)

AVD#

RDY(1)

Data

OE#,

CE# (stays low)

Address boundary occurs every 128 words, beginning at address

00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.

7C 7D 7E 7F 7F 80 81 82 83

latency

RDY(2) latency

RACC

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Notes:

1. RDY(1) active with data (D8 = 1 in the Configuration Register).

2. RDY(2) active one clock cycle before data (D8 = 0 in th e Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.

4. Figure shows the device crossing a bank in the process of performing an erase or program.

5. RDY does not go low and no additional wait states are required if the B urst frequency is < 66 MHz and the Bo undary Crossing bit (D14) in

the Configuration Register is set to 0.

Figure 11.22. Latency with Boundary Crossing into Program/Erase Bank

CLK

Address (hex)

C124 C125 C126 C127 C127

D124 D125 D126 D127 Read Status

(stays high)

AVD#

RDY(1)

Data

OE#,

CE# (stays low)

Address boundary occurs every 128 words, beginning at address

00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.

7C 7D 7E 7F 7F

latency

RDY(2) latency

RACC

January 25, 2005 S29WS-N_00_G0 83

Advance Information

Wait State Configuration Register Setup:

D13, D12, D11 = “111” ⇒ Reserv ed

D13, D12, D11 = “110” ⇒ Reserv ed

D13, D12, D11 = “101” ⇒ 5 progr ammed, 7 total

D13, D12, D11 = “100” ⇒ 4 progr ammed, 6 total

D13, D12, D11 = “011” ⇒ 3 programmed, 5 total

D13, D12, D11 = “010” ⇒ 2 progr ammed, 4 total

D13, D12, D11 = “001” ⇒ 1 progr ammed, 3 total

D13, D12, D11 = “000” ⇒ 0 progr ammed, 2 total

Note: Figure assumes address D0 is not at an address boundary, and wait state is set to “101”.

Figure 11.23. Example of Wait States Insertion

Data

AVD#

OE#

CLK

12345

D0 D1

total number of clock cycles

following addresses being latched

Rising edge of next clock cycle

following last wait state triggers

next burst data

number of clock cycles

programmed

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Advance Information

Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while

checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure

valid information.

Figure 11.24. Back-to-Back Read/Write Cycle Timings

OE#

CE#

WE#

tOEH

Data

Addresses

AVD#

PD/30h AAh

PA/SA

tWC

tDS tDH

tRC tRC

tOE

tAS

tAH

tACC

tOEH

tWP

tGHWL

tOEZ

tWC

tSR/W

Last Cycle in

Program or

Sector Erase

Command Sequence

Read status (at least two cycles) in same bank

and/or array data from other bank Begin another

write or program

command sequence

RA 555h

tWPH

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11.8.7 Erase and Programming Performance

Notes:

1. Typical program and erase times assu me the following conditio ns: 25°C, 1.8 V VCC, 10,000

cycles; checkerboard data pattern.

2. Under worst case conditions of 90°C, VCC = 1.70 V, 100,000 cycles.

3. Typical chip programming time is considerably less than the maximum chip programming

time listed, and is based on utilizing the Write Buffer.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed

to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence

for the program command. See the Appendix for further information on command

definitions.

6. C ontact the local sales office for minimum cycling endurance valu es in sp ecific applications

and operating condition s.

7. Refer to Application Note “Erase Suspend/Resume Timing” for more details.

8. Word programming specificati on i s ba se d upon a single word programming operation not

utilizing the write buffer.

9. The content in this document is Advance information for the S29WS064N and S29WS128N.

Content in this document is Preliminary for the S29W256N.

Parameter

Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 64 Kw ord V

0.6 3.5 s

Excludes 00h

programming prior

to erasure (Note 4)

16 Kword V

<0.15 2

Chip Erase Time

153.6 (WS256N)

77.4 (WS128N)

39.3 (WS064N)

308 (WS256N)

154 (WS128N)

78 (WS064N) s

ACC 130.6 (WS256N)

65.8 (WS128N)

33.4 (WS064N)

262 (WS256N)

132 (WS128N)

66 (WS064N)

Single Word Programming Time

(Note 8)

40 400 µs

ACC 24 240

Effective Word Programming Time

utilizing P rogra m Write Buffer V

9.4 94 µs

ACC 6 60

Total 32-Word Buffer P rog ramming

Time V

300 3000 µs

ACC 192 1920

Chip Programming Time (Note 3)

157.3 (WS256N)

78.6 (WS128N)

39.3 (WS064N)

314.6 (WS256N)

157.3 (WS128N)

78.6 (WS064N) sExcludes system

level o verhead

(Note 5)

ACC 100.7 (WS256N)

50.3 (WS128N)

25.2 (WS064N)

201.3 (WS256N)

100.7 (WS128N)

50.3 (WS064N)

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11.8.8 BGA Ball Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C; f = 1.0 MHz.

3. The content in this document is Advance information for the S29WS064N and

S29WS128N. Content in this document is Preliminary for the S29W256N.

Parameter

Symbol Parameter Description Test Setup Typ. Max Unit

Input Capacitance V

= 0 5.3 6.3 pF

OUT

Output Capacitance V

OUT

= 0 5.8 6.8 pF

IN2

Control Pin Capacitance V

= 0 6.3 7.3 pF

January 25, 2005 S29WS-N_00_G0 87

Advance Information

12 Appendix

This section contains information relating to software control or interfacing with the Flash device.

For additional information and assistance regarding software, see the Additional Resources sec-

tion on page 16, or explore the Web at www.amd.com and www.fujitsu.com.

88 S29WS-N_00_G0  January 25, 2005
Advance Information
Table 12.1.   Memory Array Commands
Command Sequence
(Notes)
Cycles
Bus Cycles (Notes 1–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Asynchronous Read (6) 1 RA RD
Reset (7) 1 XXX F0
Auto-
select (8)
Manufacturer ID 4 555 AA 2AA 55 [BA]555 90 [BA]X00 0001
Device ID (9) 6 555 AA 2AA 55 [BA]555 90 [BA]X01 227E BA+X0E Data BA+X0F 2200
Indicator Bits (10) 4 555 AA 2AA 55 [BA]555 90 [BA]X03 Data
Program 4 555 AA 2AA 55 555 A0 PA PD
Write to Buffer (11) 6 555 AA 2AA 55 PA 25 PA WC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort R eset (12) 3 555 AA 2AA 55 555 F0
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase/Program Suspend (13) 1 BA B0
Erase/Program Resume (14) 1 BA 30
Set Configuration Register (18) 4 555 AA 2AA 55 555 D0 X00 CR
Read Configuration Register 4 555 AA 2AA 55 555 C6 X00 CR
CFI Query (15) 1 [BA]555 98
Unlock Bypass 
Mode
Entry 3 555 AA 2AA 55 555 20
Program (16) 2 XXX A0 PA PD
CFI (16) 1 XXX 98
Reset 2 XXX 90 XXX 00
SecSi Sector
Entry 3 555 AA 2AA 55 555 88
Program (17) 4 555 AA 2AA 55 555 A0 PA PD
Read (17) 1 00 Data
Exit (17) 4 555 AA 2AA 55 555 90 XXX 00
Legend:
X = Don’t care.
RA = Read Address. 
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the 
AVD# pulse or active edge of CLK, whichever occurs first.
PD = Progra m Data. Data latc hes on the rising edge of WE# or C E# 
pulse, whichever occurs first.
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14; 
WS064N = A21–A14.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20; 
WS064N = A21–A18.
CR = Configuration Register data bits D15–D0.
WBL = Write Buffer Location. Address must be within the same write 
buffer page as PA.
WC = Word Count. Numbe r of write buffer  locations to load minu s 1. 
Notes:
1. See Table 7.1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are 
don’t cares (each hex digit implies 4 bits of data).
5. Writing incorrect address and data values or writing them in the 
improper sequence may place the device in an unknown state. 
The system must write the reset command to return the device 
to reading array data.
6. No unlock or command cycles required when bank is reading 
array data.
7. Reset command is required to return to reading array data (or to 
the erase-suspend-read mode if previously in Erase Suspend) 
when a bank is in the autoselect mode, or if DQ5 goes high 
(while the bank is providing status information) or performing 
sector lock/unlock.
8. T he system must provide the bank address. See Autoselect 
section for more information.
9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231 
(WS128N).
10. See Table 7.9 for indicator bit values.
11. Total number of cycles in the command sequence is dete rmined 
by the number of words written to the write buffer.
12. Command sequence reset s device  for  next command af ter write-
to-buffer operation.
13. System may read and program in non-erasing sectors, or enter 
the autoselect mode, wh en in the Erase Suspend mode. The 
Erase Suspend command is valid only during a sector erase 
operation, and re qu i res the bank address.
14. Erase Resume command is valid only during the Erase Suspend 
mode, and requires the bank address.
15. Command is valid when device is ready to read array data or 
when device is in autoselect mode. Address equals 55h on all 
future devices, but 555h for WS256N/128N/064N.
16. Requires Entry command sequence prior to execution. Unlock 
Bypass Reset command is required to return to reading array 
data.
17. Requires Entry command sequence prior to execution. SecSi 
Sector Exit Reset command is required to  exit this mode; device 
may otherwise be placed in an unknown state.
18. Requires reset command to configure the Configuration Register.

January 25, 2005 S29WS-N_00_G0 89

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Table 12.2. Sector Protection Commands

Command Sequence

(Notes)

Cycles

Bus Cycles (Notes 1–4)

First Second Third Fourth Fifth Sixth Seventh

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Lock

Bits

Command Set Entry (5) 3 555 AA 2AA 55 555 40

Program (6, 12) 2 XX A0 77/00 data

Read (6) 1 77 data

Comman d Set Exit (7) 2 XX 90 XX 00

Password

Protection

Command Set Entry (5) 3 555 AA 2AA 55 555 60

Program [0-3] (8) 2 XX A0 00 PWD[0-3]

Read (9) 4 0...00 PWD0 0...01 PWD1 0...02 PWD2 0...03 PWD3

Unlock 7 00 25 00 03 00 PWD0 01 PWD1 02 PWD2 03 PWD3 00 29

Comman d Set Exit (7) 2 XX 90 XX 00

Non-Volatile

Sector

Protection (PPB)

Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 C0

PPB Program (10) 2 XX A0 SA 00

All PPB Erase (10, 11) 2 XX 80 00 30

PPB Status Read 1 SA RD(0)

Comman d Set Exit (7) 2 XX 90 XX 00

Global

Volatile Sector

Protection

Freeze

(PPB Lock)

Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 50

PPB Lock Bit Set 2 XX A0 XX 00

PPB Lock Bit Status Read 1 BA RD(0)

Comman d Set Exit (7) 2 XX 90 XX 00

Volatile Sector

Protection

(DYB)

Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 E0

DYB Set 2 XX A0 SA 00

DYB Clear 2 XX A0 SA 01

DYB Status Read 1 SA RD(0)

Comman d Set Exit (7) 2 XX 90 XX 00

egen

X = Don’t care.

RA = Address of the memory location to be read.

PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0].

PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must

be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.

PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must

be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.

PD(3) = Protection Mode OT P Bit. PD(3) or bit[3].

SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;

WS064N = A21–A14.

BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;

WS064N = A21–A18.

PWD3–PWD0 = Password Data. PD3–PD0 present fou r 16 bit

combinations that represent the 64-bit P asswo r d

PWA = Password Address. Address bits A1 and A0 are used to select

each 16-bit portion of the 64-bit entity.

PWD = Password Data.

RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If

protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,

DQ2 = 1.

Notes:

1. All values are in hexadecimal.

2. Shaded cells indicate read cycles.

3. Address and data bits not specified in table, legend, or notes are

don’t cares (each hex digit implies 4 bits of data).

4. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state.

The system must write the reset command to return the device

to reading array data.

5. Entry commands are required to enter a specific mode to enable

instructions only available within that mode.

6. If both the Persistent Protection Mode Locking Bit and the

Password Protection Mode Locking Bit are set at the same time,

the command operation aborts and returns the device to the

default Persistent Sector Protection Mode during 2n d bus cycle.

Note that on all fu ture devices, addresses equal 00h, but is

currently 77h for the WS256N on ly. See Tables 8.1 and 8.2 for

explanation of lock bits.

7. Exit command must be issued to reset the device into read

mode; device may otherwise be placed in an unknown state.

8. Entire two bus-cycle sequence must be entered for each portion

of the password.

9. Full add ress range is required for reading password.

10. See Figure 8.2 for details.

11. “All PPB Erase” command pre-programs all PPBs before erasure

to prevent over -erasure.

12. The second cycle address for the lock register pr ogram operation

is 77 for S29Ws256N; however, for WS128N and Ws064N this

address is 00.

90 S29WS-N_00_G0 January 25, 2005

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12.1 Common Flash Memory Interface

The Common Flash Interface (CFI) specification outlines device and host system software inter-

rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for

entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-

dent, and forward- and back-ward-compatible for the specified flash device families. Flash

vendors can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Quer y mode when the system writes the CFI Query comm and, 98h, to

address (BA)555h any time the device is ready to read array data. The system can read CFI in-

formation at the addresses given in Tables 12.3–12.6) within that ba nk. A ll read s outsi de of the

CFI address range, within the bank, returns non-v alid data. R eads from other banks are allowed,

writes are not. To terminate reading CFI data, the system must write the re set command.

The following is a C source code example of using the CFI Entry and Exit functions. Refer to

the Spansion Low Level Driver User’s Guide (available on www.amd.com and

www.fujitsu.com) for general information on Spansion Flash m emory software development

guidelines.

/* Example: CFI Entry command */

*( (UINT16 *)bank_addr + 0x555 ) = 0x0098; /* write CFI entry command */

/* Example: CFI Exit command */

*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write cfi exit command */

For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A

and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these

documents.

Table 12.3. CFI Query Identification String

Addresses Data Description

10h

11h

12h

0051h

0052h

0059h Query Unique ASCII string “QRY”

13h

14h 0002h

0000h Primary OEM Command Set

15h

16h 0040h

0000h Address for Primary Extended Table

17h

18h 0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah 0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

Table 12.4. System Interface String

Addresses Data Description

1Bh 0017h VCC Min. (write/e rase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch 0019h VCC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 0000h VPP Min. voltage (00h = no VPP pin present)

1Eh 0000h VPP Max. voltage (00h = no VPP pin present)

1Fh 0006h Typical timeout per single byte/word write 2N µs

20h 0009h Typical timeout for Min. size buffer write 2N µs (00h = not supported)

21h 000Ah Typical timeout per individual block erase 2N ms

22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 0004h Max. timeout for byte/word write 2N times typical

24h 0004h Max. timeout for buffer write 2N times typical

25h 0003h Max. timeout per individual block erase 2N times typical

26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

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Table 12.5. Device Geometry Definition

Addresses Data Description

27h 0019h (WS256N)

0018h (WS128N)

0017h (WS064N)

Device Size = 2

byte

28h

29h 0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh 0006h

0000h

Max. number of bytes in multi-byte write = 2

(00h = not supported)

2Ch 0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0003h

0000h

0080h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h 00FDh (WS256N)

007Dh (WS128N)

003Dh (WS064N)

Erase Block Region 2 Information

32h

33h

34h

0000h

0002h

35h

36h

37h

38h

0003h

0000h

0080h

0000h

Erase Block Region 3 Information

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

92 S29WS-N_00_G0 January 25, 2005

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Table 12.6. Primary Vendor-Specific Extended Query

Addresses Data Description

40h

41h

42h

0050h

0052h

0049h

Query-unique A SCII string “PRI”

43h 0031h

Major version number, ASCII

44h 0034h

Minor version number, ASCII

45h 0100h

Address Sensitiv e Unlock (Bits 1-0)

0 = Required, 1 = Not Required

Silicon Technology (Bits 5-2) 0100 = 0.11 µm

46h 0002h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 0001h

Sector Protect

0 = Not S upported, X = Number o f sectors in p er gr oup

48h 0000h

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h 0008h

Sector Protect/Unprotect scheme

08 = Advanced Se ctor Protection

4Ah 00F3h (WS256N)

007Bh (WS128N)

003Fh (WS064N)

Simultaneou s Operation

Numbe r o f Sectors in all banks ex cept boot bank

4Bh 0001h

Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 0000h

Page Mode Type

00 = Not Supported, 01 = 4 W ord P age, 02 = 8 W ord Page, 04 = 16 W ord

Page

4Dh 0085h

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh 0095h

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh 0001h

Top/Bottom Boot Sector Flag

0001h = Dual Boot Device

50h 0001h

Progr am Suspend. 00h = not supported

51h 0001h

Unlock Bypass

00 = Not Supported, 01=Supported

52h 0007h

SecSi Sector (Customer OTP Area) Size 2

bytes

53h 0014h

Hardware Reset Lo w Time-ou t during an embedde d al gorithm to read

mode Maximum 2

54h 0014h

Hardware Reset Low Time-out not during an embedded algorithm to read

mode Maximum 2

55h 0005h

Erase Suspend Time-out Maximum 2

56h 0005h

Program Suspend Time-out Maximum 2

57h 0010h

Bank Organi zation: X = Num ber of banks

58h 0013h (WS256N)

000Bh (WS128N)

0007h (WS064N)

Bank 0 Region In formation. X = N umber of s ec tor s in bank

January 25, 2005 S29WS-N_00_G0 93

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59h 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 1 Region In formation. X = N umber of s ec tor s in bank

5Ah 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 2 Region In formation. X = N umber of s ec tor s in bank

5Bh 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 3 Region In formation. X = N umber of s ec tor s in bank

5Ch 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 4 Region In formation. X = N umber of s ec tor s in bank

5Dh 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 5 Region In formation. X = N umber of s ec tor s in bank

5Eh 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 6 Region In formation. X = N umber of s ec tor s in bank

5Fh 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 7 Region In formation. X = N umber of s ec tor s in bank

60h 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 8 Region In formation. X = N umber of s ec tor s in bank

61h 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 9 Region In formation. X = N umber of s ec tor s in bank

62h 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 10 Region Infor mation. X = Nu mber of sector s in bank

63h 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 11 Region Infor mation. X = Nu mber of sector s in bank

64h 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 12 Region Infor mation. X = Nu mber of sector s in bank

65h 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 13 Region Infor mation. X = Nu mber of sector s in bank

66h 0010h (WS256N)

0008h (WS128N)

0004h (WS064N)

Bank 14 Region Infor mation. X = Nu mber of sector s in bank

67h 0013h (WS256N)

000Bh (WS128N)

0007h (WS064N)

Bank 15 Region Infor mation. X = Nu mber of sector s in bank

Table 12.6. Primary Vendor-Specific Extended Query (Continued)

Addresses Data Description

94 S29WS-N_00_G0 January 25, 2005

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13 Commonly Used Terms

Term Definition

ACC ACCelerate.

A special purpose input signal which allows for faster pro gramming or

erase operation when raised to a specified voltage above V

. In some devices ACC

may prot ect all sectors when at a low voltage.

max

Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for

64Mbit]

min

Least significant bit of th e address input s ignals (A0 for all devices in this document).

Asynchronous Operatio n w here signal relationships are based only on propagation delays and are

unrelated to synchronous control (clock) signal.

Autoselect Read mode for obtaining manufacturer a nd device information as well as sector

protection status.

Bank Section of the memory array consisting of multiple consecutiv e sectors. A read

operat ion in one bank, can be independent of a program or erase operation in a

different bank for devices that offer simultaneous read and write feature.

Boot sector Smaller size sectors located at the top and or bottom of Flash device address space.

The smaller sector size allows for finer granularity control of erase and protection for

code or parameters used to initiate system operation a fter power- on or reset.

Boundary Location at the beginning or end of series of memory locations.

Burst Read See synchronous read.

Byte 8 bits

CFI Common Fla sh Interface. A Flash memory i ndustry standard specification [JEDE C 137-

A and JESD68.01] designed to allow a system to interrogate the Flash to determine its

size, type a n d other performance parameters.

Clear Zero (Logic Low Level)

Configuration Register Special purpose register which must be programmed to enable synchronous read

mode

Continuous Read Synchronous method of burst read whereb y the device reads con tinuously until it is

stopped by the host, or it has reached the highest address of the memory arr ay, after

which the read address wraps around to the lowest memory array address

Erase Returns bits of a Flash memory array to their default state of a logical One (High Level).

Erase Suspend/Erase R esume Halts an erase operation to a llow reading or p ro gramming in any sector that is no t

selected for erasure

BGA Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Gr id Array

and Fine-pitch Ball Grid Array . See the specific package drawing or connection diagram

for further details.

Linear Read Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with

or without wraparound before requiring a new initial address

MCP Multi-Ch ip P acka ge. A metho d of combining integr at ed circuits in a single packa ge by

“stacking” multiple die of the sam e or different devices.

Memory Array The programmable area of the product a vailable for data storage.

MirrorBit™ Technolog y Spansion™ trad emarked technology for storing multiple bits of d ata in the same

transistor.

January 25, 2005 S29WS-N_00_G0 95

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Page Group of words that may be accessed more rap idly as a group tha n if the words were

accessed indivi dually.

Page Read

Asynchronous read operation of several words in which the first word of the group

takes a longer initial access time a nd subsequent words in the group tak e less “page”

access time to be read. Different words in the group are accessed by changing only the

least significant address lines.

Password Protection Sector protection method which uses a programmable password, in ad dition to the

Persistent Protection method, for protection of sectors in the Flash memory device

Pers istent Protection Sector protection method that u se s com mands and only the standard core voltage

supply to control protection of sectors in the Flash memory device. This metho d

replaces a prio r techniqu e o f requ iring a 12V supply to cont rol the pro tection m etho d.

Program Stores data into a Flash memory b y selectively clearing bits of the mem ory array in

order to leave a data patter n of “ones” and “zeros”.

Program Suspend/Pr ogram

Resume Halts a progr ammin g oper ation to rea d data from an y loc ation that is not selected fo r

programming or erase.

Read Host bus cycle that causes the Flash to output data onto the data bus.

Registers Dynamic storage bits for holding device control information or tracking the status of

an operation.

Secured Silicon

Secured Silicon. An area consisting of 256 bytes in which any word may be

programm ed once, and the entire area ma y be protected once from any future

programming. Information in this area may be programm ed at the factory or by the

user. Once programmed and protected there is no way to change the secured

information. T his area is often used to store a softwa re readable identification such as

a serial number.

Sector Protectio n

Use of one or more control bits per sector to indicate whether each sector may be

programm ed or erased. If the Protection bit for a sector is set the embedded

algorithms for program or erase ignores program or erase commands related to that

sector.

Sector An Area of the memory arr ay in which all bits must be erased together by an erase

operation.

Simultaneous Operation

Mode of oper atio n in which a host system may issue a program or erase command to

one bank, that embedded algorithm operation may then proceed while the host

immediately follows the embedded algorithm command with reading from ano ther

bank.

Read ing may continue concurrently in any bank other than the one executing

the embedded algorithm operation.

Synchronous Operation Operation that progresses only when a timing signal, known as a clock, transitions

between logic levels (that is, at a clock edge).

VersatileIO™ (V

)Separate power suppl y o r voltage reference signa l that a llows the host system to set

the voltage levels that the device generates at its data outputs and the voltages

tolerated at its data inputs.

Unlock Bypass

Mode that facilitates faster program times by reducing the number of command bus

cycles required to issue a write oper ation command. In this mode the initia l two

“Unlock” write cycles, of the usual 4 cycle Program com mand, are not required –

reducing all Program commands to two bus cycles while in this mode.

Word T wo contiguous bytes (16 bits) located at an even byte boundary. A double word is two

contiguous words located on a two word boundary. A quad word is four contiguous

words located on a four word boundary.

Term Definition

96 S29WS-N_00_G0 January 25, 2005

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Wraparound

Special burst read mode where the read address “wraps” or returns back to the lowest

address boundary in the selected range of word s, after read ing the last By te or Word

in the range, e.g. for a 4 word range o f 0 to 3, a read beginning at word 2 would read

words in the sequence 2, 3, 0, 1.

Write Interchangeable term for a pr ogram/erase oper ation where the content of a register

and or memory location is being altered. The term w rite is often associated with

“writing command cycles” to enter or exit a particular mode of operation.

W rite Buffer Multi-wo rd area in which multiple words m ay be progr amme d as a single oper ation

W rit e Bu ffer ma y b e 16 to 32 wo rds lo ng and is located on a 16 or 32 word boundary

respectively.

W rite Buffer Progr amming Method of writing multiple w ords, up to the m aximu m siz e of the Write Buffer, in one

operat ion. Using Write Buffer Programming results in

≥

8 times faster programming

time than by using single word at a time programming commands.

W rite Operation Status Allows the host system to determine the status of a program or erase operation by

reading several special purpose register bits

Term Definition

January 25, 2005 S29WS-N_00_G0 97

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14 Revisions

Revision F (October 29, 2004)

Data sheet completely revised. Changed arrangement of sections; edited explanatory text, added

flowcharts. This document supersedes Revision E+1, issued August 9, 2004; only the changes

specified for Revision F in this section affect the document or device. All other device specifica-

tions remain the same as presented in Revision E+1.

Deleted product selector guide.

11.8.2, Synchronous/Burst Read

Deleted tAAS and tAAH from table. Modified Note 1.

Table 12.4, System Interface String

Changed data at address 23h from 0003h to 0004h.

Revision G (January 25, 2005)

Global

Updated tIACC, tBACC, tOE, CFI address 4Ah, and the Configuration Register.

Added Figure 8.2, “PPB Program/Erase Algorithm” .

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-

tioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other

abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development

by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided

as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement

of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the

use of the information in this document.

product names used in this publication are for identification purposes only and may be trademarks of their respective companies.