SY89856U
2GHz, Low-Power, 1:6 LVPECL Fanout Buffer
with 2:1 Input MUX and Internal Termination
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Oct. 1, 2013
Revision 3.1
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89856U is a 2.5V/3.3V precision, high-speed, 1:6
fanout capable of handling clocks up to 2.0GHz. A
differential 2:1 MUX input is included for redundant clock
switchover applications.
The differential input includes Micrel’s unique, 3-pin input
termination architecture that allows the device to interface
to any differential signal (AC- or DC-coupled) as small as
100mV (200mVpp) without any level shifting or termination
resistor networks in the signal path. The outputs are
LVPECL (100k, temperature compensated), with
extremely fast rise/fall times guaranteed to be less than
200ps.
The SY89856U operates from a 2.5V ±5% supply or a
3.3V ±10% supply and is guaranteed over the full industrial
temperature range of –40°C to +85°C. The SY89856U is
part of Micrel’s high-speed, Precision Edge® product line.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
6 ultra-low skew copies of the selected input
2:1 MUX input included for clock switchover applications
Low power: 225mW typical (2.5V)
2.5V to 3.3V supply voltage
Unique input isolation design minimizes crosstalk
Guaranteed AC performance over temperature and
voltage:
Clock frequency range: DC to >2.0GHz
<400ps IN-to-OUT tpd
<200ps tr/tf times
<30ps skew (output-to-output)
Ultra-low jitter design:
40fs RMS phase jitter
0.7psRMS crosstalk-induced jitter
Unique input termination and VT pin accepts DC- and
AC-coupled inputs (CML, PECL, LVDS)
100k LVPECL compatible output swing
–40°C to +85°C industrial temperature range
Available in 32-pin (5mm x 5mm) QFN package
Applications
Redundant clock distribution
All SONET/SDH clock/data distribution
All Fibre Channel distribution
All Gigabit Ethernet clock distribution
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
United States Patent No. RE44,134
Micrel, Inc.
SY89856U
Oct. 1, 2013
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Ordering Information(1)
Part Number
Package Type
Operating Range
Package Marking
Lead Finish
SY89856UMG
QFN-32
Industrial
SY89856U with Pb-Free bar-line indicator
NiPdAu Pb-Free
SY89856UMGTR(2)
QFN-32
Industrial
SY89856U with Pb-Free bar-line indicator
NiPdAu Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
32-Pin QFN
Micrel, Inc.
SY89856U
Oct. 1, 2013
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Pin Description
Pin Number
Pin Name
Pin Function
1, 4
5, 8
IN0, /IN0
IN1, /IN1
Differential Input: These input pairs are the differential signal inputs to the device. These inputs
accept AC- or DC-coupled signals as small as 100mV (200mVp-p). Each pin of a pair internally
terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if
left open. Please refer to the “Input Interface Applications” section for more details.
2, 6
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The
VT0 and VTI pins provide a center-tap to a termination network for maximum interface flexibility.
See the “Input Interface Applications” section for more details.
31
SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this
input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left
open. The MUX select switchover function is asynchronous.
10
NC
No connect.
11, 16, 18,
23, 25, 30
VCC
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to VCC pins as
possible.
29, 28
27, 26
22, 21
20, 19
15, 14
13, 12
Q0, /Q0,
Q1, /Q1,
Q2, /Q2,
Q3, /Q3,
Q4, /Q4,
Q5, /Q5
Differential Outputs: These 100k (temperature compensated) LVPECL output pairs are low skew
copies of the selected input. Unused output pins may be left floating. Please refer to the “LVPECL
Output Interface Applications” section for details.
9, 17, 24, 32
GND,
Exposed Pad
Ground: Ground pins and exposed pad must be connected to the same ground plane.
3, 7
VREF-AC0
VREF-AC1
Reference Voltage: This output biases to VCC – 1.2V. It is used for AC-coupling inputs (IN, /IN).
Connect VREF_AC directly to the VT pin. Bypass with 0.01µF low ESR capacitor to VCC. See the
“Input Interface Applications” section. Maximum sink/source current is ±1.5mA. Due to the limited
drive capability use for input at the same package only.
LVPECL Output Interface Applications
SEL
Output
0
IN0 Input Selected
1
IN1 Input Selected
Micrel, Inc.
SY89856U
Oct. 1, 2013
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Functional Block Diagram
Micrel, Inc.
SY89856U
Oct. 1, 2013
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Absolute Maximum Ratings(3)
Supply Voltage (VCC) .................................... –0.5V to +4.0V
Input Voltage (VIN) ............................................ –0.5V to VCC
LVPECL Output Current (IOUT)
Continuous ............................................................ 50mA
Surge .................................................................. 100mA
Termination Current
Source or sink current on VT ............................. ±100mA
VREF-AC Source or sink current………… .................... ±2.0mA
Lead Temperature (soldering, 20s) .......................... +260°C
Storage Temperature (Ts) ........................... –65°C to 150°C
Operating Ratings(4)
Supply Voltage (VCC) ............................ +2.375V to +2.625V
............................................................... +3.0V to +3.6V
Ambient Temperature (TA) .......................... –40°C to +85°C
Package Thermal Resistance(5)
QFN (JA)
Still-Air ............................................................... 35°C/W
QFN (JB)
Junction-to-Board .............................................. 16°C/W
DC Electrical Characteristics(6)
TA = –40°C to +85°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VCC
Power Supply Voltage
2.375
2.5
2.625
V
3.0
3.3
3.6
V
ICC
Power Supply Current
No load, max VCC.
90
140
mA
RIN
Input Resistance
(IN-to-VT)
45
50
55
Ω
RDIFF_IN
Differential Input Resistance
(IN-to-/IN)
90
100
110
Ω
VIH
Input High Voltage
(IN, /IN)
Note 7
VIH – 1.6
VCC
V
VIL
Input Low Voltage
(IN, /IN)
0
VIH–0.1
V
VIN
Input Voltage Swing
(IN, /IN)
See Figure 1.
0.1
1.7
V
VDIFF_IN
Differential Input Voltage Swing
|IN-/IN|
See Figure 2.
0.2
V
VT_IN
IN-to-VT
(IN, /IN)
1.28
V
VREF-AC
Output Reference Voltage
VCC – 1.3
VCC – 1.2
VCC – 1.1
V
Notes:
3. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods
may affect device reliability.
4. The datasheet limits are not guaranteed if the device is operated beyond the operating ratings.
5. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. JA and JB values
are determined for a 4-layer board in still air, unless otherwise stated.
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
7. VIH (min) not lower than 1.2V.
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SY89856U
Oct. 1, 2013
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LVPECL DC Electrical Characteristics(6)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C; RL = 50Ω to VCC – 2V, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VOH
Output HIGH Voltage
VCC – 1.145
VCC – 0.895
V
VOL
Output LOW Voltage
VCC – 1.945
VCC – 1.695
V
VOUT
Output Voltage Swing
See Figure 1.
550
800
mV
VDIFF-OUT
Differential Output Voltage
Swing
See Figure 2.
1.1
1.6
V
LVTTL/CMOS DC Electrical Characteristics(6)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VIH
Input HIGH Voltage
2.0
V
VIL
Input LOW Voltage
0.8
V
IIH
Input HIGH Current
–125
30
µA
IIL
Input LOW Current
–300
µA
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SY89856U
Oct. 1, 2013
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AC Electrical Characteristics(8)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, unless otherwise noted.
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Output-to-output skew is measured between outputs under identical input conditions.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
11. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the
inputs.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
fMAX
Maximum Operating Frequency
VOUT ≥ 400mV
2.0
3.0
GHz
tpd
Differential Propagation Delay
(IN0 or IN1-to-Q)
200
280
400
ps
(SEL-to-Q)
140
460
ps
∆tpd
Tempco
Differential Propagation Delay
Temperature Coefficient
65
fs/oC
tSKEW
Output-to-Output
Note 9
10
30
ps
Part-to-Part
Note 10
150
ps
tJITTER
RMS Phase Jitter
Output = 500MHz
Integration Range – 12kHz –
20MHz
40
fs
Adjacent Channel
Crosstalk-Induced Jitter
Note 11
0.7
ps(rms)
tr, tf
Output Rise/Fall Time
Full swing, 20% to 80%.
75
130
200
ps
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SY89856U
Oct. 1, 2013
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Typical Characteristics
VCC = 3.3V, GND = 0V, VIN ≥ 400mV, tr/tf ≤ 300ps, TA = 25°C, unless otherwise noted.
0
100
200
300
400
500
600
700
800
900
0 1000 2000 3000 4000 5000 6000
OUTPUT SWING (mV)
FREQUENCY (MHz)
Output Swing vs. Frequency
Micrel, Inc.
SY89856U
Oct. 1, 2013
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Functional Characteristics
VCC = 3.3V, GND = 0V, VIN ≥ 400mV, tr/tf ≤ 300ps, TA = 25°C, unless otherwise stated.
Micrel, Inc.
SY89856U
Oct. 1, 2013
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Singled-Ended and Differential Swings
Figure 1. Single-Ended Voltage Swing
Figure 2. Differential Voltage Swing
Timing Diagrams
Micrel, Inc.
SY89856U
Oct. 1, 2013
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Input and Output Stages
Figure 3. Simplified Differential
Figure 4. Simplified LVPECL Output Stage
Input Interface Applications
Figure 5. DC-Coupled LVPECL
Input Interface
Figure 6. AC-Coupled LVPECL
Input Interface
Figure 7. DC-Coupled CML
Input Interface
Figure 8. AC-Coupled CML
Input Interface
Figure 9. LVDS Input Interface
Micrel, Inc.
SY89856U
Oct. 1, 2013
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LVPECL Output Interface Applications
LVPECL has a high input impedance and a very low
output impedance (open emitter), and a small signal
swing which results in low EMI. LVPECL is ideal for
driving 50Ω and 100Ω-controlled impedance transmission
lines. There are several techniques for terminating the
LVPECL output: parallel termination-Thevenin equivalent,
parallel termination (3-resistor), and AC-coupled
termination. Unused output pairs may be left floating.
However, single-ended outputs must be terminated or
balanced.
Figure 10. Parallel Termination-Thevenin Equivalent
Note:
12. For 2.5V Systems: R1 = 250Ω, R2 = 62.5Ω.
Figure 11. Parallel Termination (3-Resistors)
Notes:
13. Power-saving alternative to Thevenin termination.
14. Place termination resistors as close to destination inputs as possible.
15. Rb resistor sets the DC bias voltage, equal to VT.
16. For 2.5V systems, Rb = 19Ω.
Related Documentation
Part Number
Function
Datasheet Link
SY58035U
4.5GHz, 1:6 LVPECL Fanout Buffer with
2:1 MUX Input and Internal Termination
www.micrel.com/_PDF/HBW/sy58035u.pdf
HBW Solutions
New Products and Applications
www.micrel.com/index.php/en/products/clock-timing/clock-data-
distribution.html
Micrel, Inc.
SY89856U
Oct. 1, 2013
13
Package Information(17)
32-Pin QFN (QFN-32)
Note:
17. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
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