STP3LN80K5, STU3LN80K5 N-channel 800 V, 2.75 typ., 2 A MDmeshTM K5 Power MOSFET in TO-220 and IPAK packages Datasheet - production data Features TAB Order code STP3LN80K5 STU3LN80K5 TAB IPAK TO-220 12 2 1 V DS 800 V RDS(on) max ID 3.25 2A 3 3 Figure 1: Internal schematic diagram Industry's lowest RDS(on) x area Industry's best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Switching applications D(2, TAB) Description These very high voltage N-channel Power MOSFET are designed using MDmeshTM K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM01476v1 Table 1: Device summary Order code Marking STP3LN80K5 STU3LN80K5 June 2016 Package Packing TO-220 3LN80K5 DocID027716 Rev 2 This is information on a product in full production. IPAK Tube 1/15 www.st.com Contents STP3LN80K5, STU3LN80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/15 4.1 IPAK package information ............................................................... 10 4.2 TO-220 type A package information................................................ 12 Revision history ............................................................................ 14 DocID027716 Rev 2 STP3LN80K5, STU3LN80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Gate-source voltage Value Unit 30 V ID Drain current (continuous) at TC = 25 C 2 A ID Drain current (continuous) at TC = 100 C 1.25 A Drain current (pulsed) 8 A W ID(1) PTOT Total dissipation at TC = 25 C 45 dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj V/ns - 55 to 150 Operating junction temperature range C Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area. 2 A, di/dt 100 A/s; VDSpeak < V(BR)DSS, VDD = 640 V. DS 640 V. Table 3: Thermal data Value Symbol Parameter Unit TO-220 Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient IPAK 2.78 62.5 C/W 100 C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 0.7 A EAS Single pulse avalanche energy (starting Tj = 25C, ID = IAR; VDD = 50 V) 155 mJ DocID027716 Rev 2 3/15 Electrical characteristics 2 STP3LN80K5, STU3LN80K5 Electrical characteristics (TC = 25 C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V Min. Typ. Max. 800 Unit V VDS = 800 V, VGS = 0 V 1 A VDS = 800 V, VGS = 0 V, TC = 125 C(1) 50 A Gate body leakage current VGS = 20 V, VGS = 0 V 10 A VGS(th) Gate threshold voltage VDS = VGS, ID = 100 A 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 1 A 2.75 3.25 Min. Typ. Max. Unit - 102 - pF - 11 - pF - 0.1 - pF - 20 - pF - 7 - pF IDSS Zero gate voltage drain current IGSS 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Cotr(1) Equivalent capacitance time related VDS = 0 to 640 V, VGS = 0 V Coer(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 12 - Qg Total gate charge - 2.63 - nC Qgs Gate-source charge - 0.91 - nC Qgd Gate-drain charge VDD = 640 V, ID = 2 A, VGS = 10 V ( see Figure 17: "Test circuit for gate charge behavior" ) - 1.53 - nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS 4/15 DocID027716 Rev 2 STP3LN80K5, STU3LN80K5 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-off delay time tf Fall time Test conditions Min. Typ. Max. Unit VDD = 400 V, ID = 1 A, RG = 4.7 , VGS = 10 V ( see Figure 16: "Test circuit for resistive load switching times" and Figure 21: "Switching time waveform" ) - 6.2 - ns - 7 - ns - 30 - ns - 26 - ns Min. Typ. Max. Unit Table 8: Source drain diode Symbol Parameter Test conditions ISD Source-drain current - 2 A ISDM(1) Source-drain current (pulsed) - 8 A VSD(2) Forward on voltage ISD = 2 A, VGS = 0 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current 1.5 V - 210 ns - 0.8 C - 7.6 A - 345 ns - 1.2 C - 7.2 A Test conditions Min. Typ. Max. Unit IGS = 1 mA, ID = 0 A 30 - - V ISD = 2 A, di/dt = 100 A/s, VDD = 60 V ( see Figure 18: "Test circuit for inductive load switching and diode recovery times" ) trr - ISD = 2 A, di/dt = 100 A/s, VDD = 60 V, Tj = 150 C, (see Figure 18: "Test circuit for inductive load switching and diode recovery times" ) Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 s, duty cycle 1.5%. Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID027716 Rev 2 5/15 Electrical characteristics 2.1 STP3LN80K5, STU3LN80K5 Electrical characteristics (curves) Figure 3: Thermal impedance for TO-220 Figure 2: Safe operating area for TO-220 Figure 5: Thermal impedance for IPAK Figure 4: Safe operating area for IPAK CG34360 K 0 10 c -1 10 -2 10 -5 10 Figure 6: Output characteristics 6/15 DocID027716 Rev 2 -4 10 -3 10 -2 10 -1 10 tp (s) Figure 7: Transfer characteristics STP3LN80K5, STU3LN80K5 Electrical characteristics Figure 8: Gate charge vs gate-source voltage Figure 9: Static drain-source on-resistance Figure 10: Capacitance variations Figure 11: Source-drain diode forward characteristics Figure 12: Normalized gate threshold voltage vs temperature Figure 13: Normalized on-resistance vs temperature DocID027716 Rev 2 7/15 Electrical characteristics STP3LN80K5, STU3LN80K5 Figure 14: Normalized V(BR)DSS vs temperature 8/15 Figure 15: Maximum avalanche energy vs starting TJ DocID027716 Rev 2 STP3LN80K5, STU3LN80K5 3 Test circuits Test circuits Figure 16: Test circuit for resistive load switching times Figure 17: Test circuit for gate charge behavior VDD RL IG= CONST VGS + pulse width 2200 F 100 D.U.T. 2.7 k VG 47 k 1 k AM01469v10 Figure 18: Test circuit for inductive load switching and diode recovery times Figure 19: Unclamped inductive load test circuit Figure 20: Unclamped inductive waveform DocID027716 Rev 2 Figure 21: Switching time waveform 9/15 Package information 4 STP3LN80K5, STU3LN80K5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK (R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 4.1 IPAK package information Figure 22: IPAK (TO-251) type A package outline 10/15 DocID027716 Rev 2 STP3LN80K5, STU3LN80K5 Package information Table 10: IPAK (TO-251) type A package mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 b 0.64 0.90 b2 b4 0.95 5.20 B5 5.40 0.30 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 E 6.40 6.60 e e1 2.28 4.40 H 4.60 16.10 L 9.00 9.40 L1 0.80 1.20 L2 0.80 V1 10 DocID027716 Rev 2 1.00 11/15 Package information 4.2 STP3LN80K5, STU3LN80K5 TO-220 type A package information Figure 23: TO-220 type A package outline 12/15 DocID027716 Rev 2 STP3LN80K5, STU3LN80K5 Package information Table 11: TO-220 type A mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.55 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10.00 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13.00 14.00 L1 3.50 3.93 L20 16.40 L30 28.90 oP 3.75 3.85 Q 2.65 2.95 DocID027716 Rev 2 13/15 Revision history 5 STP3LN80K5, STU3LN80K5 Revision history Table 12: Document revision history Date Revision 09-Jul-2015 1 Initial release 2 Updated title and features in cover page. Updated Section 1: "Electrical ratings". Updated Section 2: "Electrical characteristics". Added Section 2.1: "Electrical characteristics (curves)". Document status promoted from preliminary to production data. Minor text changes. 28-Jun-2016 14/15 Changes DocID027716 Rev 2 STP3LN80K5, STU3LN80K5 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved DocID027716 Rev 2 15/15