General Description
The MAX807 microprocessor (µP) supervisory circuit
reduces the complexity and number of components
needed to monitor power-supply and battery-control func-
tions in µP systems. A 70µA supply current makes the
MAX807 ideal for use in portable equipment, while a 2ns
chip-enable propagation delay and 250mA output current
capability (20mA in battery-backup mode) make it suit-
able for larger, higher-performance equipment.
The MAX807 comes in 16-pin DIP, SO, and TSSOP pack-
ages, and provides the following functions:
•µP reset. The active-low RESET output is asserted dur-
ing power-up, power-down, and brownout conditions,
and is guaranteed to be in the correct state for VCC
down to 1V.
•Active-high RESET output.
•Manual-reset input.
•Two-stage power-fail warning. A separate low-line
comparator compares VCC to a threshold 52mV above
the reset threshold. This low-line comparator is more
accurate than those in previous µP supervisors.
•Backup-battery switchover for CMOS RAM, real-time
clocks, µPs, or other low-power logic.
•Write protection of CMOS RAM or EEPROM.
•2.275V threshold detector provides for power-fail
warning and low-battery detection, or monitors a
power supply other than +5V.
•BATT OK status flag indicates that the backup-battery
voltage is above +2.275V.
•Watchdog-fault output—asserted if the watchdog input
has not been toggled within a preset timeout period.
Applications
Computers
Controllers
Intelligent Instruments
Critical µP Power Monitoring
Portable/Battery-Powered Equipment
Features
♦Precision 4.675V (MAX807L), 4.425V (MAX807M),
or 4.575V (MAX807N) Voltage Monitoring
♦200ms Power-OK/Reset Time Delay
♦RESET and RESET Outputs
♦Independent Watchdog Timer
♦1µA Standby Current
♦Power Switching
250mA in VCC Mode
20mA in Battery-Backup Mode
♦On-Board Gating of Chip-Enable Signals;
2ns CE Gate Propagation Delay
♦MaxCap®and SuperCap®Compatible
♦Voltage Monitor for Power Fail
♦Backup-Battery Monitor
♦Guaranteed RESET Valid to VCC = 1V
♦±1.5% Low-Line Threshold Accuracy 52mV above
Reset Threshold
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
________________________________________________________________ Maxim Integrated Products 1
19-0433; Rev 4; 11/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RESET RESET
WDO
CE IN
GND
VCC
OUT
BATT
TOP VIEW
MAX807
CE OUT
WDI
LOW LINE
MR
BATT OK
PFI
PFO
BATT ON
DIP/SO/TSSOP
Pin Configuration
Ordering Information and Typical Operating Circuit appear at end of data sheet.
SuperCap is a registered trademark of Baknor Industries. MaxCap is a registered trademark of Cesiwid, Inc.
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = 4.60V to 5.5V for the MAX807L, VCC = 4.50V to 5.5V for the MAX807N, VCC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0V, TA= TMIN to TMAX. Typical values are tested with VCC = 5V and TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Input Voltages (with respect to GND)
VCC ..........................................................................-0.3V to 6V
VBATT .......................................................................-0.3V to 6V
All Other Inputs......................................-0.3V to (VOUT + 0.3V)
Input Current
VCC Peak ...........................................................................1.0A
VCC Continuous .............................................................500mA
IBATT Peak......................................................................250mA
IBATT Continuous .............................................................50mA
GND .................................................................................50mA
All Other Inputs ................................................................50mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
TSSOP (derate 6.70 mW/°C above +70°C) .................533mW
Operating Temperature Ranges
MAX807_C_E ......................................................0°C to +70°C
MAX807_E_E ...................................................-40°C to +85°C
MAX807_MJE ................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
VBATT = 2.8V, VCC = 3.0V
VCC = 0V, VBATT = 2.8V
VCC = 3V, IOUT = 100mA
VCC = 4.5V,
IOUT = 250mA
VBATT = 2.0V, IOUT = 5mA, VCC = 0V
VBATT = 2.8V, IOUT = 10mA, VCC = 0V
VBATT = 4.5V, IOUT = 20mA, VCC = 0V
CONDITIONS
µA
-1.0 1.0
BATT Standby Current (Note 3)
-0.1 0.1
µA
50
Supply Current in Battery-
Backup Mode (excludes IOUT)
(Note 2)
5
0.4 1
µA70 110
Supply Current in Normal
Operating Mode (excludes IOUT)
V
VBATT - 0.20 VBATT - 0.08
VOUT in Battery-Backup Mode VBATT - 0.25 VBATT - 0.12
VBATT - 0.17
Ω
1.2 2.5
VCC to OUT On-Resistance 1.8
1.0 1.4
UNITSMIN TYP MAXSYMBOLPARAMETER
V0 5.5
Operating Voltage Range
VBATT, VCC (Note 1)
MAX807C/E
MAX807M
VBATT = 2.0V, IOUT = 5mA
VBATT = 2.8V, IOUT = 10mA
VBATT = 4.5V, IOUT = 20mA
Ω
16 40
BATT to OUT On-Resistance 12 25
8.5
TA= +25°C
MAX807C/E
MAX807M
TA= +25°C
TA= TMIN to
TMAX
VBATT = 2.8V Power up
Power down V
VBATT
Battery-Switchover Threshold VBATT + 0.05
VCC = 3V, VBATT = 2.8V, IOUT = 100mA
VCC = 4.5V
VCC - 0.02IOUT = 25mA
IOUT = 250mA,
MAX807C/E
IOUT = 250mA,
MAX807M
VOUT in Normal Operating
Mode V
VCC - 0.25 VCC - 0.12
VCC - 0.35 VCC - 0.22
VCC - 0.45
mV
0.1 0.4
Battery-Switchover Hysteresis 50
BATT ON Output, Low Voltage VRST (max), ISINK = 3.2mA V
2 2.7BATT ON Output, High Voltage VCC = 0V, ISOURCE = 0.1mA, VBATT = 2.8V V
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
_______________________________________________________________________________________ 3
VIH
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.60V to 5.5V for the MAX807L, VCC = 4.50V to 5.5V for the MAX807N, VCC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0V, TA= TMIN to TMAX. Typical values are tested with VCC = 5V and TA= +25°C, unless otherwise noted.)
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
Sink current 70
4.600 4.675 4.750
V
5
BATT ON Output
Short-Circuit Current Source current, VCC = 0V, VBATT = 2.8V
4.350 4.425 4.500
LOW LINE to RESET
Threshold Voltage VLR
Reset Threshold Hysteresis
VCC falling 30 52 70 mV
13 mV
4.500 4.575 4.650VRST
Reset Threshold VCC rising and falling
4.63 4.71MAX807N
VCC to LOW LINE Delay VCC falling at 1mV/µs 24 µs
µs26VCC to RESET Delay VCC falling at 1mV/µs
4.48 4.56MAX807M
Minimum Watchdog Input
Pulse Width
Watchdog-Timeout Period
VIL = 0.8V, VIH = 0.75 x VCC
tWD
100 ns
V
1.12 1.6 2.24 s
ms140 200 280tRP
RESET Active-Timeout Period VCC rising
4.73 4.81MAX807L
MAX807L
MAX807N
MAX807M
0.3
0.3
ISINK = 50µA,
VBATT = 0V, VCC falling
VCC - 1.5 VCC - 0.1
RESET Output Voltage
ISOURCE = 0.1mA
0.1 0.4ISINK = 3.2mA, VCC = 4.25V
mA
60Output sink current, VCC = 4.25V
1.6
ISC
RESET Output
Short-Circuit Current Output source current
VCC = 1V,
MAX807_C
VCC = 1.2V,
MAX807_E/M
V
0.4ISINK = 3.2mA
VCC - 1.5
RESET Output Voltage ISOURCE = 5mA
V
0.4ISINK = 3.2mA, VCC = 4.25V
VCC - 1.5
LOW LINE Output Voltage ISOURCE = 5mA
mA
60Output sink current
15
ISC
RESET Output
Short-Circuit Current Output source current, VCC = 4.25V
mA
28Output sink current, VCC = 4.25V
20
ISC
LOW LINE Output
Short-Circuit Current Output source current
V
0.4ISINK = 3.2mA
VCC - 1.5
WDO Output Voltage ISOURCE = 5mA
mA
mA
35Output sink current
20
ISC
WDO Output
Short-Circuit Current Output source current
VLL V
LOW LINE Threshold,
VCC Rising
V
0.75 x VCC
0.8
VIH
WDI Threshold Voltage
(Note 4) VIL
µA
-50 -10Reset deasserted, WDI = 0V
16 50
WDI Input Current Reset deasserted, WDI = VCC
RESET, LOW LINE, AND WATCHDOG TIMER
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
4_______________________________________________________________________________________
Note 1: Either VCC or VBATT can go to 0 if the other is greater than 2.0V.
Note 2: The supply current drawn by the MAX807 from the battery (excluding IOUT) typically goes to 15µA when (VBATT - 0.1V)
< VCC < VBATT. In most applications, this is a brief period as VCC falls through this region (see Typical Operating Characteristics).
Note 3: “+”= battery discharging current, “-”= battery charging current.
Note 4: WDI is internally connected to a voltage-divider between VCC and GND. If unconnected, WDI is driven to 1.8V (typical),
disabling the watchdog function.
Note 5: Overdrive (VOD) is measured from center of hysteresis band.
Note 6: The chip-enable resistance is tested with VCE IN = VCC/2, and ICE IN = 1mA.
Note 7: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.60V to 5.5V for the MAX807L, VCC = 4.50V to 5.5V for the MAX807N, VCC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0V, TA= TMIN to TMAX. Typical values are tested with VCC = 5V and TA= +25°C, unless otherwise noted.)
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
PFI Leakage Current ±0.005 ±40 nA
mV20PFI Hysteresis
µA±0.00002 ±1CE IN Leakage Current Disabled mode, MR = 0V
µs14PFI to PFO Delay (Note 5)
PFI Input Threshold VPFT VPFI falling
2.22 2.285 2.35 V
2.20 2.265 2.33
RESET to CE OUT Delay VCC falling 28 µs
Ω75 150
CE IN to CE OUT Resistance
(Note 6) Enabled mode, VCC = VRST (max)
MR Minimum Pulse Input 1µs
ns170
MR-to-RESET Propagation
Delay
mA17
CE OUT Short-Circuit Current
(RESET Active)
VCC = 5V, disabled mode,
CE OUT = 0, MR = 0V
ns28
CE IN to CE OUT
Propagation Delay (Note 7)
VCC = 5V, CLOAD = 50pF,
50Ωsource impedance driver
V
3.5
CE OUT Output Voltage High
(RESET Active) Disabled mode, MR = 0V
MR Threshold VIH 2.4 V
BATT OK Threshold VBOK 2.200 2.265 2.350 V
BATT OK Hysteresis 20 mV
Output Voltage
(PFO, BATT OK)
VOL ISINK = 3.2mA 0.4 V
Output Short-Circuit Current ISC Output sink current 35 mA
VPFI rising
VBATT - 0.1 VBATT
VCC = 5V,
IOUT = 2mA
VCC = 0V,
IOUT = 10µA
VIL 0.8
VOH ISOURCE = 5mA VCC - 1.5
Output source current 20
VOD = 30mV, VPFI falling
MR Pullup Current MR = 0V 50 100 200 µA
CHIP-ENABLE GATING
MANUAL RESET INPUT
BATT OK COMPARATOR
LOGIC OUTPUTS
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
_______________________________________________________________________________________ 5
__________________________________________Typical Operating Characteristics
(VCC = 5V, VBATT = 2.8V, PFI = 0, no load, TA= +25°C, unless otherwise noted.)
80
60
-60 -20 60 140
VCC SUPPLY CURRENT vs. TEMPERATURE
(NORMAL OPERATING MODE)
64
76
MAX807-01
TEMPERATURE (°C)
VCC SUPPLY CURRENT (µA)
20 100-40 40 120080
72
68
62
66
78
74
70
3.0
2.5
2.0
1.5
1.0
0.5
0
-60 -20 60 140
BATTERY SUPPLY CURRENT vs.
TEMPERATURE (BATTERY-BACKUP MODE)
MAX807-02
TEMPERATURE (°C)
BATTERY SUPPLY CURRENT (µA)
20 100-40 40 120080
6
5
4
3
2
1
0
-60 -20 60 140
CHIP-ENABLE PROPAGATION DELAY
vs. TEMPERATURE
MAX807-03
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
20 100-40 40 120080
30
5
-60 -20 60 140
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
10
25
MAX807-04
TEMPERATURE (°C)
BATT-TO-OUT ON-RESISTANCE (Ω)
20 100-40 40 120080
20
15
VBATT = 2.0V
VBATT = 2.8V
VBATT = 4.5V
VCC = 0V
IOUT = 10mA
4.70
4.65
4.60
4.55
4.50
4.45
4.40
-60 -20 60 140
RESET THRESHOLD
vs. TEMPERATURE
MAX807-07
TEMPERATURE (°C)
RESET THRESHOLD (V)
20 100-40 40 120080
MAX807L
MAX807N
MAX807M
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
-60 -20 60 140
VCC-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
MAX807-05
TEMPERATURE (°C)
VCC-TO-OUT ON-RESISTANCE (Ω)
20 100-40 40 120080
IOUT = 250mA
2.340
2.320
2.300
2.280
2.260
2.240
2.220
2.200
-60 -20 60 140
PFI THRESHOLD
vs. TEMPERATURE (VPFI FALLING)
MAX807-06
TEMPERATURE (°C)
PFI THRESHOLD (V)
20 100-40 40 120080
280
260
240
220
200
180
160
140
-60 -20 60 140
RESET TIMEOUT PERIOD
vs. TEMPERATURE (VCC RISING)
MAX807-08
TEMPERATURE (°C)
RESET TIMEOUT PERIOD (ms)
20 100-40 40 120080
0
10
20
30
40
50
60
70
80
-60 -20 60 140
LOW LINE -TO-RESET THRESHOLD
vs. TEMPERATURE (VCC FALLING)
MAX807-09
TEMPERATURE (°C)
LOW LINE-TO-RESET THRESHOLD (mV)
20 100-40 40 120080
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
6_______________________________________________________________________________________
Typical Operating Characteristics (contiued)
(VCC = 5V, VBATT = 2.8V, PFI = 0, no load, TA= +25°C, unless otherwise noted.)
4.75
4.80
4.70
4.65
4.60
4.55
4.50
4.45
4.40
-60 -20 60 140
LOW LINE THRESHOLD
vs. TEMPERATURE (VCC RISING)
MAX807-10
TEMPERATURE (°C)
LOW LINE THRESHOLD (V)
20 100-40 40 120080
L VERSION
N VERSION
M VERSION
0
5
10
15
20
25
30
35
40
-60 -20 60 140
LOW LINE COMPARATOR PROPAGATION
DELAY vs. TEMPERATURE (VCC FALLING)
MAX807-11
TEMPERATURE (°C)
LOW LINE COMPARATOR PROP DELAY (µs)
20 100-40 40 120080
VCC FALLING AT 1mV/µs
0
5
10
15
20
25
30
35
40
-60 -20 60 140
RESET COMPARATOR PROPAGATION
DELAY vs. TEMPERATURE (VCC FALLING)
MAX807-12
TEMPERATURE (°C)
RESET COMPARATOR PROP DELAY (µs)
20 100-40 40 120080
VCC FALLING AT 1mV/µs
0
2
4
6
8
10
12
14
16
2.5 2.6 2.7 2.8 2.9 3.0
BATTERY CURRENT
vs. INPUT SUPPLY VOLTAGE
MAX807-13
VCC (V)
BATTERY CURRENT (µA)
1000
100
10
1
110010 1000
VCC-TO-OUT vs.
OUTPUT CURRENT
MAX807-16
IOUT (mA)
VCC - VOUT (mV)
SLOPE = 1.0Ω
0
50Ω DRIVER
2
4
6
8
050100
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
MAX807-14
CLOAD (pF)
PROPAGATION DELAY (ns)
1000
100
10
110100
BATT-TO-OUT vs.
OUTPUT CURRENT
MAX807-15
IOUT (mA)
BATT-TO-OUT (mV)
VCC = 0V
SLOPE = 12Ω
1000
100
10
1
110010 1000
MAXIMUM TRANSIENT DURATION vs.
RESET COMPARATOR OVERDRIVE
MAX807-17
RESET COMPARATOR OVERDRIVE (mV)
MAXIMUM TRANSIENT DURATION (µs)
RESET OCCURS
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
_______________________________________________________________________________________ 7
Pin Description
Active-Low Reset Output. RESET is triggered and stays low when VCC is below the reset threshold or
when MR is low. It remains low 200ms after VCC rises above the reset threshold or MR returns high.
RESET has a strong pulldown but a relatively weak pullup, and can be wire-OR connected to logic gates.
Valid for VCC ≥1V. RESET swings between VCC and GND.
RESET9
Watchdog Output. This CMOS-logic output goes low if WDI remains high or low longer than the watch-
dog-timeout period (tWD), and remains low until the next transition of WDI. WDO remains high if WDI is
unconnected. WDO is high during reset. WDO swings between VCC and GND. Connect WDO to MR to
generate resets during watchdog faults.
WDO10
Chip-Enable Output. Output to the chip-enable gating circuit. CE OUT is pulled up to the higher of VCC
or VBATT, when the chip-enable gate is disabled.
CE OUT11
Chip-Enable InputCE IN12
Battery-On Output. CMOS-logic output/external bypass switch driver. High when OUT is connected to
BATT and low when OUT is connected to VCC. Connect the base of a PNP transistor or gate of a PMOS
transistor to BATT ON for IOUT requirements exceeding 250mA. BATT ON swings between the higher of
VCC and VBATT and GND.
BATT ON13
GroundGND5
Manual-Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR remains low
and for 200ms after MR returns high. MR is an active-low input with an internal pullup to VCC. It can be
driven using TTL or CMOS logic, or shorted to ground with a switch. Connect to VCC, or leave uncon-
nected if not used.
MR6
Low-Line Comparator Output. This CMOS-logic output goes low when VCC falls to 52mV above the reset
threshold. Use this output to generate an NMI to initiate an orderly shutdown routine when VCC is falling.
LOW LINE swings between VCC and GND.
LOW LINE7
Active-High Reset Output. RESET is the inverse of RESET. It is a CMOS output that sources and sinks
current. RESET swings between VCC and GND.
RESET8
Watchdog Input. If WDI remains high or low longer than the watchdog-timeout period (1.6s, typ), WDO
goes low. Leave unconnected to disable the watchdog function.
WDI4
Input Supply Voltage, nominally +5V. Bypass with a 0.1µF capacitor to GND.VCC
3
PIN
Power-Fail Output. This CMOS-logic output goes low when PFI is less than VPFT (2.265V). Valid for
VCC ≥4V. PFO swings between VCC and GND.
PFO2
Power-Fail Input. When PFI is less than VPFT (2.265V), PFO goes low. Connect to ground when unused.PFI1
FUNCTIONNAME
Backup-Battery Input. When VCC falls below the reset threshold and VBATT, OUT switches from VCC to
BATT. VBATT may exceed VCC. The battery can be removed while the MAX807 is powered-up, provided
BATT is bypassed with a 0.1µF capacitor to GND. If no battery is used, connect BATT to ground, and
connect VCC and OUT together.
BATT14
Battery-OK Signal Output. High in normal operating mode when VBATT exceeds VBOK (2.265V). Valid for
VCC ≥4V.
BATT OK15
Output Supply Voltage to CMOS RAM. When VCC exceeds the reset threshold or VCC > VBATT, OUT is
connected to VCC. When VCC falls below the reset threshold and VBATT, OUT connects to BATT. Bypass
OUT with a 0.1µF capacitor to GND.
OUT16
Detailed Description
The MAX807 µP supervisory circuit provides power-
supply monitoring, backup-battery switchover, and pro-
gram execution watchdog functions in µP systems
(Figure 1). Use of BiCMOS technology results in an
improved 1.5% reset-threshold precision, while keeping
supply currents typically below 70µA. The MAX807 is
intended for battery-powered applications that require
high reset-threshold precision, allowing a wide power-
supply operating range while preventing the system
from operating below its specified voltage range.
RESET and RESET Outputs
The MAX807’s RESET output ensures that the µP pow-
ers up in a known state, and prevents code execution
errors during power-down and brownout conditions. It
accomplishes this by resetting the µP, terminating pro-
gram execution when VCC dips below the reset thresh-
old or MR is pulled low. Each time RESET is asserted it
stays low for the 200ms reset timeout period, which is
set by an internal timer to ensure the µP has adequate
time to return to an initial state. Any time VCC goes
below the reset threshold before the reset-timeout peri-
od is completed, the internal timer restarts. The watch-
dog timer can also initiate a reset if WDO is connected
to MR (see the Watchdog Input section).
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
8_______________________________________________________________________________________
MAX807
CE IN
PFI
GND
VCC
BATT
VCC
THE HIGHER
OF VCC OR VBATT
BATTERY-BACKUP
COMPARATOR
RESET
COMPARATOR
LOW-LINE
COMPARATOR
BATTERY-OK
COMPARATOR
POWER-FAIL
COMPARATOR
2.275V
P
OUT
BATT ON
LOW LINE
BATT OK
PFO
WDI
MR
50kΩ
RESET
RESET
WDO
CE OUT
N
P
P
N
WATCHDOG
TRANSITION
DETECTOR
STATE
MACHINE
OSCILLATOR
Figure 1. Block Diagram
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
_______________________________________________________________________________________ 9
The RESET output is active low and implemented with a
strong pulldown/relatively weak pullup structure. It is
guaranteed to be a logic low for 0 < VCC < VRST, pro-
vided VBATT is greater than 2V. Without a backup bat-
tery, RESET is guaranteed valid for VCC ≥1. It typically
sinks 3.2mA at 0.1V saturation voltage in its active state.
The RESET output is the inverse of the RESET output; it
both sources and sinks current and cannot be wire-OR
connected. Figure 2a shows a timing diagram with VCC
rising and Figure 2b shows VCC falling.
Manual Reset Input
Many µP-based products require manual-reset capabil-
ity to allow an operator or test technician to initiate a
reset. The Manual Reset (MR) input permits the genera-
tion of a reset in response to a logic low from a switch,
WDO, or external circuitry. Reset remains asserted
while MR is low, and for 200ms after MR returns high.
MR has an internal 50µA to 200µA pullup current, so it
can be left open if it is not used. MR can be driven with
TTL or CMOS-logic levels, or with open-drain/collector
outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function;
external debounce circuitry is not required. If MR is dri-
ven from long cables or if the device is used in a noisy
environment, connect a 0.1µF capacitor from MR to
ground to provide additional noise immunity. As shown
in Figure 3, diode-ORed connections can be used to
allow manual resets from multiple sources. Figure 4
shows the reset timing.
Watchdog Timer
Watchdog Input
The watchdog circuit monitors the µP’s activity. If the
µP does not toggle the watchdog input (WDI) within
1.6s, WDO goes low. The internal 1.6s timer is cleared
and WDO returns high when reset is asserted or when
a transition (low-to-high or high-to-low) occurs at WDI
while RESET is high. As long as reset is asserted, the
timer remains cleared and does not count. As soon as
reset is released, the timer starts counting (Figure 5).
Supply current is typically reduced by 10µA when WDI
is at a valid logic level.
VRESET
VLOW LINE
VCC
VRESET
VCE OUT
VRST
VRST + VLR
VBATT
SHOWN FOR VCC = 5V to 0, VBATT = 2.8V, CE IN = GND
Figure 2a. Timing Diagram, VCC Rising Figure 2b. Timing Diagram, VCC Falling
Figure 3. Diode “OR” Connections Allow Multiple Reset
Sources to Connect to MR
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
10 ______________________________________________________________________________________
Watchdog Output
WDO remains high if there is a transition or pulse at
WDI during the watchdog-timeout period. WDO goes
low if no transition occurs at WDI during the watchdog-
timeout period. The watchdog function is disabled and
WDO is a logic high when VCC is below the reset
threshold or WDI is an open circuit. To generate a sys-
tem reset on every watchdog fault, diode-OR connect
WDO to MR (Figure 6). When a watchdog fault occurs
in this mode, WDO goes low, which pulls MR low, caus-
ing a reset pulse to be issued. As soon as reset is
asserted, the watchdog timer clears and WDO returns
high. With WDO connected to MR, a continuous high or
low on WDI will cause 200ms reset pulses to be issued
every 1.6s.
Chip-Enable Signal Gating
The MAX807 provides internal gating of chip-enable
(CE) signals to prevent erroneous data from corrupting
the CMOS RAM in the event of a power failure. During
normal operation, the CE gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The MAX807 uses a series
transmission gate from the Chip-Enable Input (CE IN) to
the Chip-Enable Output (CE OUT) (Figure 1).
The 8ns (max) chip-enable propagation from CE IN to
CE OUT enables the MAX807 to be used with most µPs.
Chip-Enable Input
CE IN is high impedance (disabled mode) while RESET
is asserted. During a power-down sequence when VCC
passes the reset threshold, the CE transmission gate
disables and CE IN becomes high impedance 28µs
after reset is asserted (Figure 7). During a power-up
sequence, CE IN remains high impedance (regardless
of CE IN activity) until reset is deasserted following the
reset-timeout period.
In the high-impedance mode, the leakage currents into
this input are ±1µA (max) over temperature. In the low-
impedance mode, the impedance of CE IN appears as
a 75Ωresistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
drive to CE IN and the capacitive loading on CE OUT
VCC
VRST
RESET
tWD
WDO
WDI
WDO CONNECTED TO µP INTERRUPT.
tRP
Figure 4. Manual-Reset Timing Diagram
Figure 5. Watchdog Timing Relationship
Figure 6. Generating a Reset on Each Watchdog Fault
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
______________________________________________________________________________________ 11
(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ωdriver and 50pF of load
capacitance (Figure 8). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low output-impedance driver.
Chip-Enable Output
In the enabled mode, the impedance of CE OUT is equiv-
alent to 75Ωin series with the source driving CE IN. In the
disabled mode, the 75Ωtransmission gate is off and CE
OUT is actively pulled to the higher of VCC or VBATT. This
source turns off when the transmission gate is enabled.
Low-Line Comparator
The low-line comparator monitors VCC with a threshold
voltage typically 52mV above the reset threshold, with
13mV of hysteresis. Use LOW LINE to provide a non-
maskable interrupt (NMI) to the µP when power begins
to fall to initiate an orderly software shutdown routine.
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered, and before reset asserts. If the system must
contend with a more rapid VCC fall time—such as when
the main battery is disconnected, a DC-DC converter
shuts down, or a high-side switch is opened during
normal operation—use capacitance on the VCC line to
provide time to execute the shutdown routine (Figure 9).
First calculate the worst-case time required for the
system to perform its shutdown routine. Then, with the
worst-case shutdown time, the worst-case load current,
and the minimum low-line to reset threshold (VLR(min)),
calculate the amount of capacitance required to allow the
shutdown routine to complete before reset is asserted:
CHOLD = (ILOAD x tSHDN) / VLR (min)
where tSHDN is the time required for the system to com-
plete the shutdown routine, and includes the VCC to
low-line propagation delay; and where ILOAD is the cur-
rent being drained from the capacitor, VLR is the low-
line to reset threshold.
MAX807
CE IN
50pF
CLOAD
CE OUT
GND
VRST MAX
50Ω DRIVER
VCC
Figure 7. Reset and Chip-Enable Timing Figure 8. CE Propagation Delay Test Circuit
Figure 9. Using LOW LINE to Provide a Power-Fail Warning to
the µP
MAX807L/M/N
Power-Fail Comparator
PFI is the noninverting input to an uncommitted com-
parator. If PFI is less than VPFT (2.265V), PFO goes low.
The power-fail comparator is intended to monitor the
preregulated input of the power supply, providing an
early power-fail warning so software can conduct an
orderly shutdown. It can also be used to monitor sup-
plies other than 5V. Set the power-fail threshold with a
resistor-divider, as shown in Figure 10.
Power-Fail Input
PFI is the input to the power-fail comparator. The typical
comparator delay is 14µs from VIL to VOL (power failing),
and 32µs from VIH to VOH (power being restored). If
unused, connect this input to ground.
Power-Fail Output
The Power-Fail Output (PFO) goes low when PFI goes
below VPFT. It typically sinks 3.2mA with a saturation
voltage of 0.1V. With PFI above VPFT, PFO is actively
pulled to VCC. Connecting PFI through a voltage-
divider to a preregulated supply allows PFO to gener-
ate an NMI as the preregulated power begins to fall
(Figure 11b). If the preregulated supply is inaccessible,
use LOW LINE to generate the NMI (Figure 11a). The
LOW LINE threshold is typically 52mV above the reset
threshold (see the Low-Line Comparator section).
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
12 ______________________________________________________________________________________
MAX807
VCC
GND
PFI PFO
R1
R2
VIN
0V VIN
PFO
VTRIP
VL
VPFT = 2.265V
VPFH = 20mV
WHERE
VTRIP = R2 +
R1
1
)
(
R2
1–R1
VCC
(VPFT + VPFH)
VL = R2 +
R1
1
)
(
R2
1–R1
VCC
(VPFT)
NOTE: VTRIP, VL ARE NEGATIVE.
VCC
MAX807
VCC
GND
PFI PFO
R1
R2
PFO
VTRIP VH
VIN
VTRIP =
)
(
R2
R1 + R2
VPFT
VH = (VPFT + VPFH)
VCC
VIN
MR
b)a)
)
(
R2
R1 + R2
MAX807
OUTVCC
FROM
REGULATED
SUPPLY POWER TO
CMOS RAM
BATT
RESET
LOW LINE
WDI
GND
RESET
NMI
I/O LINE
µP
µP POWER
0.1µF
0.1µF
2.8V
a)
b)
MAX807
OUTVCC
PFI
POWER TO
CMOS RAM
BATT
RESET
PFO
WDI
GND
VOLTAGE
REGULATOR
RESET
NMI
I/O LINE
µP
µP POWER
0.1µF
0.1µF
2.8V
Figure 10. Using the Power-Fail Comparator to Monitor an Additional Power Supply: a) VIN is Negative, b) VIN is Positive
Figure 11. a) If the preregulated supply is inaccessible, LOW
LINE generates the NMI for the µP. b) Use PFO to generate the
µP NMI if the preregulated supply is accessible.
Battery-Backup Mode
Battery backup preserves the contents of RAM in the
event of a brownout or power failure. With a backup
battery installed at BATT, the MAX807 automatically
switches RAM to backup power when VCC falls. Two
conditions are required for switchover to battery-back-
up mode: 1) VCC must be below the reset threshold; 2)
VCC must be below VBATT. Table 1 lists the status of
inputs and outputs during battery-backup mode.
Backup-Battery Input
The BATT input is similar to VCC, except the PMOS
switch is much smaller. This input is designed to con-
duct up to 20mA to OUT during battery backup. The
on-resistance of the PMOS switch is approximately
13Ω. Figure 12 shows the two series pass elements
between the BATT input and OUT that facilitate UL
approval. VBATT can exceed VCC during normal opera-
tion without causing a reset.
Output Supply Voltage
The output supply (OUT) transfers power from VCC or
BATT to the µP, RAM, and other external circuitry. At
the maximum source current of 250mA, VOUT will typi-
cally be 260mV below VCC. Decouple this terminal with
a 0.1µF capacitor.
BATT ON Output
The battery on (BATT ON) output indicates the status of
the internal battery switchover comparator, which con-
trols the internal VCC and BATT switches. For VCC
greater than VBATT (ignoring the small hysteresis
effect), BATT ON typically sinks 3.2mA at 0.4V. In bat-
tery-backup mode, this output sources approximately
5mA. Use BATT ON to indicate battery switchover sta-
tus, or to supply gate or base drive for an external pass
transistor for higher current applications (see the
Typical Operating Circuit).
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
______________________________________________________________________________________ 13
Figure 12. VCC and BATT-to-OUT Switch
Table 1. Input and Output Status in Battery-Backup Mode
The power-fail comparator remains active in battery-backup mode for VCC ≥4V. Below 4V, PFO is forced low.PFO2
WDI is ignored and goes high impedanceWDI4
Battery switchover comparator monitors VCC for active switchover.VCC
3
MR is ignoredMR6
Logic high; the open-circuit output voltage is equal to VCC.RESET8
Logic lowLOW LINE7
Ground—0V reference for all signalsGND5
Logic high. The open-circuit output voltage is equal to VCC.WDO10
High impedanceCE IN12
Logic high. The open-circuit output voltage is equal to VBATT.CE OUT11
Supply current is 1µA maximum for VBATT ≤2.8V.BATT14
PIN
OUT is connected to BATT through two internal PMOS switches in series.OUT16
The power-fail comparator remains active in battery-backup mode for VCC ≥4V.PFI1
FUNCTIONNAME
Logic high when VBATT exceeds 2.285V. Valid for VCC ≥4V. Below 4V, BATT OK is forced low.BATT OK15
Logic high. The open-circuit output voltage is equal to VBATT.BATT ON13
Logic lowRESET9
MAX807L/M/N
BATT OK Output
The BATT OK comparator monitors the backup battery
voltage, comparing it with a 2.265V reference (VCC ≥
4V). BATT OK remains high as long as the backup bat-
tery voltage remains above 2.265V, signaling that the
backup battery has sufficient voltage to maintain the
memory of static RAM. When the battery voltage drops
below 2.265V, the BATT OK output drops low, signaling
that the backup battery needs to be changed.
Applications Information
The MAX807 is not short-circuit protected. Shorting
OUT to ground, other than power-up transients such as
charging a decoupling capacitor, may destroy the
device. If long leads connect to the IC’s inputs, ensure
that these lines are free from ringing and other condi-
tions that would forward bias the IC’s protection diodes.
There are two distinct modes of operation:
1) Normal Operating Mode, with all circuitry powered
up. Typical supply current from VCC is 70µA, while
only leakage currents flow from the battery.
2) Battery-Backup Mode, where VCC is below VBATT
and VRST. The supply current from the battery is typ-
ically less than 1µA.
Using SuperCaps or
MaxCaps with the MAX807
BATT has the same operating voltage range as VCC, and
the battery-switchover threshold voltage is typically
VBATT when VCC is decreasing or VBATT + 0.06V when
VCC is increasing. This hysteresis allows use of a
SuperCap (e.g., order of 0.47F) and a simple charging
circuit as a backup source (Figure 13). Since VBATT can
exceed VCC while VCC is above the reset threshold,
there are no special precautions when using these µP
supervisors with a SuperCap.
Alternative Chip-Enable Gating
Using memory devices with CE and CE inputs allows
the MAX807 CE loop to be bypassed. To do this, con-
nect CE IN to ground, pull up CE OUT to OUT, and
connect CE OUT to the CE input of each memory
device (Figure 14). The CE input of each part then con-
nects directly to the chip-select logic, which does not
have to be gated by the MAX807.
Adding Hysteresis to the
Power-Fail Comparator
The power-fail comparator has a typical input hystere-
sis of 20mV. This is sufficient for most applications
where a power-supply line is being monitored through
an external voltage-divider (Figure 10).
Figure 15 shows how to add hysteresis to the power-fail
comparator. Select the ratio of R1 and R2 such that PFI
sees 2.265V when VIN falls to the desired trip point
(VTRIP). Resistor R3 adds hysteresis. It will typically be
an order of magnitude greater than R1 or R2. The cur-
rent through R1 and R2 should be at least 1µA to
ensure that the 25nA (max) PFI input current does not
shift the trip point. R3 should be larger than 10kΩto
prevent it from loading down the PFO pin. Capacitor C1
adds additional noise rejection.
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
14 ______________________________________________________________________________________
Figure 13. SuperCap or MaxCap on BATT
Figure 14. Alternate CE Gating
Backup-Battery Replacement
The backup battery may be disconnected while VCC is
above the reset threshold, provided BATT is bypassed
with a 0.1µF capacitor to ground. No precautions are
necessary to avoid spurious reset pulses.
Negative-Going VCC Transients
While issuing resets to the µP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going VCC
transients (glitches). It is usually undesirable to reset
the µP when VCC experiences only small glitches.
The Typical Operating Characteristics show Maximum
Transient Duration vs. Reset Comparator Overdrive, for
which reset pulses are not generated. The graph was
produced using negative-going VCC pulses, starting at
5V and ending below the reset threshold by the magni-
tude indicated (reset comparator overdrive). The graph
shows the maximum pulse width that a negative-going
VCC transient may typically have without causing a
reset pulse to be issued. As the amplitude of the tran-
sient increases (i.e., goes farther below the reset
threshold), the maximum allowable pulse width
decreases.
Typically, a VCC transient that goes 40mV below the
reset threshold and lasts for 3µs or less will not cause a
reset pulse to be issued.
A 0.1µF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
Watchdog Software Considerations
To help the watchdog timer keep a closer watch on soft-
ware execution, you can use the method of setting and
resetting the watchdog input at different points in the
program, rather than “pulsing” the watchdog input high-
low-high or low-high-low. This technique avoids a “stuck”
loop where the watchdog timer continues to be reset
within the loop, keeping the watchdog from timing out.
Figure 16 shows an example flow diagram where the
I/O driving the watchdog input is set high at the begin-
ning of the program, set low at the beginning of every
subroutine or loop, then set high again when the pro-
gram returns to the beginning. If the program should
“hang” in any subroutine, the I/O is continually set low
and the watchdog timer is allowed to time out, causing
a reset or interrupt to be issued.
Maximum VCC Fall Time
The VCC fall time is limited by the propagation delay of
the battery switchover comparator and should not
exceed 0.03V/µs. A standard rule for filter capacitance
on most regulators is on the order of 100µF per amp of
current. When the power supply is shut off or the main
battery is disconnected, the associated initial VCC fall
rate is just the inverse or 1A / 100µF = 0.01V/µs. The
VCC fall rate decreases with time as VCC falls exponen-
tially, which more than satisfies the maximum fall-time
requirement.
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
______________________________________________________________________________________ 15
Figure 15. Adding Hysteresis to the Power-Fail Comparator
Figure 16. Watchdog Flow Diagram
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
MAX807
RESET
RESET RESET
+12V SUPPLY FAILURE
BATT OK
PFO
WDO
LOW LINE
WDI
CE IN
CE OUT
+5V
+12V
SUPPLY
OUT
BATT
REAL-
TIME
CLOCK
*MaxCap.
MR
OTHER
SYSTEM
RESET
SOURCES
BATT ON
ADDRESS
DECODE
0.1µF
0.1µF
0.47F*
VCC
PFI
GND
µP
PUSH-
BUTTON
SWITCH
CMOS
RAM
A0–A15
I/O
NMI
RESET
INTERRUPT
WATCHDOG FAILURE
Typical Operating Circuit
___________________Chip Information
4.425 4.504.35M
4.675
4.575 4.65
TYP
4.75
RESET THRESHOLD (V)
4.60
4.50
MAX
MIN
N
L
SUFFIX
16 Plastic DIP-40°C to +85°CMAX807_EPE
16 Wide SO0°C to +70°CMAX807_CWE
16 CERDIP
16 Wide SO
16 Plastic DIP
PIN-PACKAGETEMP RANGE
0°C to +70°C
-40°C to +85°C
-55°C to +125°CMAX807_MJE
MAX807_EWE
MAX807_CPE
PART†
TRANSISTOR COUNT: 984
Ordering Information
† This part offers a choice of reset threshold voltage. From the
table below, select the suffix corresponding to the desired
threshold and insert it into the blank to complete the part number.
Devices in PDIP, SO and TSSOP packages are available in
both leaded and lead-free packaging. Specify lead free by
adding the + symbol at the end of the part number when
ordering. Lead free not available for CERDIP package.
16 TSSOP0°C to +70°CMAX807_CUE
16 TSSOP-40°C to +85°CMAX807_EUE
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