PIC16F505-I/PG - Microchip Technology

 2004 Microchip Technology Inc. Preliminary DS41236A

PIC12F508/509/16F505

Data Sheet

8/14-Pin, 8-Bit Flash Microcontrollers

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U. S. and

foreign patents and applications may be issued or pending.

DS41236A-page ii Preliminary  2004 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporated with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical

components in life support systems is not authorized except

with express written approval by Microchip. No licenses are

conveyed, implicitly or otherwise, under any intellectual

property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART ,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, MX DE V, MXLAB, PICMASTER, SEEV AL,

SmartSensor and The Embedded Control Solutions Company

are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fu zzy LAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Migra table Memory, MPASM,

MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,

PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,

PowerTool, rfLAB , rfPICDEM, Select Mode, Smart Serial,

SmartTel and Total Endurance are trademark s of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular M icrochip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrit y of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h a c t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 1

PIC12F508/509/16F505

Devices Included In Thi s Data Sheet:

•PIC12F508

•PIC12F509

•PIC16F505

High-Performance RISC CPU:

• Only 33 single-word instructions to learn

• All single-cycle instructions ex cept for program

branches, which are two-cycle

• 12-bit wide instructions

• 2-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

for data and instructions

• 8-bit wide data path

• 8 Special Function Hardware registers

• Operati ng spe ed:

- DC – 20 MHz clock input (PIC16F505 only)

- DC – 200 ns instruction cycle (PIC16F505

only)

- DC – 4 MHz clock input

- DC – 1000 ns instruction cycle

Special Microcontroller Features:

• 4 MHz precision internal oscillator:

- Factory calibrated to ±1%

• In-Circuit Serial Program ming™ (ICSP™)

• In-Circuit Debugging (ICD) support

• Power-on Reset (POR )

• Device Re se t Timer (DRT)

• Watchdog Timer (WDT) with dedicated on-chip

RC oscillator for reliable operation

• Programmable code protection

• Multiplexed MCLR input pin

• Internal weak pull-ups on I/O pins

• Power-saving Sleep mode

• Wake-up from Sleep on pin change

• Selectable oscillat or optio ns:

- INTRC: 4 MHz precision Internal oscillator

- EXTRC: External lo w-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High-speed crystal/resonator

(PIC16F5 05 onl y)

- LP: Power-saving, low -frequency crystal

- EC: High-speed ext ernal clock input

(PIC16F5 05 onl y)

Low-Power Features/CMOS Technology:

• Operating Current:

- < 350 µA @ 2V, 4 MHz

• Standby Current:

- 100 nA @ 2V, typi cal

• Low-power, high-speed Flash technology:

- 100,000 Flash endura nce

- > 40 year retention

• Fully static design

• Wide operating voltage range: 2.0V to 5.5V

• Wide temperature range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Peripheral Features (PIC12F508/509):

• 6 I/O pins:

- 5 I/O pins with individual direction control

- 1 in put only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pu ll-ups

• 8-bit real-time clock/counter (TMR0) wi th 8-bit

progra mmab le pres caler

Peripheral Feat ures (PIC16F505):

• 12 I/O pins:

- 11 I/O pins with ind iv idu al dire ct ion contro l

- 1 in put only pin

- High current sink/source for direct LED drive

- Wake-on-change

- Weak pu ll-ups

• 8-bit real-time clock/counter (TMR0) wi th 8-bit

progra mmab le pres caler

8/14-Pin, 8-Bit Flash Microcontroller

PIC12F508/509/16F505

DS41236A-page 2 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams

Device Program Me mory Data Memory I/O Timers

8-bit

Flash (words) SRAM (bytes)

PIC12F508 512 25 6 1

PIC12F509 1024 41 6 1

PIC16F505 1024 72 12 1

PDIP, SOIC, TSSOP

VDD

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

RB3/MCLR/VPP

VSS

RB0/ICSPDAT

PIC16F505

RC5/T0CKI

RC4

RC3

RB1/ISCPCLK

RB2

RC0

RC1

RC2

PDIP, SOIC, MSOP

VDD

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR/VPP

VSS

GP0/ICSPDAT

PIC12F508/509

GP1/ICSPCLK

GP2/T0CKI

 2004 Microchip Technology Inc. Preliminary DS41236A-page 3
PIC12F508/509/16F505
Table of Contents
1.0 General Description............... ....... .. .... .. .... .. ....... .... .. .... .. ....... .... .. .... .. .. ......... .. .... .. .. .... ................................................................... 5
2.0 PIC12F508/509/16F505 Device Varieties ...................... ......... .... .. .... ......... .... .. .... .... ......... .... .. .... ................................................ 7
3.0 Arc hitectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization................................................................................................................................................................. 15
5.0 I /O Po r t...................... ................... ................... ................... .................. ...................................................................................... 29
6.0 Timer0 Module and TMR0 Register.. ......................................................................................................................................... 33
7.0 Sp e cial Features Of The CPU.... .......... ................... ................... .......... ................... ................................................................... 39
8.0 Instruction Set Summ ary............................................................................................................................................................ 55
9.0 Development Support................................................................................................................................................................. 63
10.0 Electrical Characteristics............................................................................................................................................................ 69
11.0 DC and AC Characteristics Graphs and Charts......................... .... .... ......... .... .... .... ........... .... .... .... ............................................ 81
12.0 Packagin g  In fo rmation........................ ........... .................. ................... ................... ..................................................................... 83
Index .................................................................................................................................................................................................... 91
On-Line Support... .... .. ......... .... .. .... .. ......... .... .. .... ......... .. .... .. .... ......... .. .... .... .. ......... .. .... .... .. ................................................................... 93
Systems Information and Upgrade Hot Line........................................................................................................................................ 93
Reader Response................................................................................................................................................................................ 94
Product Identification System .............................................................................................................................................................. 95
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PIC12F508/509/16F505

DS41236A-page 4 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS41236A-page 5

PIC12F508/509/16F505

1.0 GENERAL DESCRIPTION

The PIC12F508/509/16F505 devices from Microchip

Technology a re low-cost, high-performan ce, 8-bit, full y-

static, Flash-based CMOS microcontrollers. They

employ a RISC architecture with only 33 single word/

single cycle instructions. All instructions are single

cycle (200 µs) except for program branches, which

take two cycles. The PIC12F508/509/16F505 devices

delive r perfor manc e an order of magnit ude high er than

their comp etitors i n the sa me price category. The 12-b it

wide instructions are highly symmetrical, resulting in a

typical 2:1 code compression over other 8-bit

microcontrollers in its class. The easy to use and easy

to remember instruction set reduces development time

significantly.

The PIC12F508/509/16F505 products are equipped

with special features that reduce system cost and

power requirements. The Power-on Reset (POR) and

Device Reset Timer (DRT) eliminate the need for

external Reset circuitry . Th ere are four oscillator confi g-

urations to choose from (six on the PIC16F505), includ-

ing INTRC Internal Oscillator mode and the power-

saving LP (Low-p ower) Oscillator mode. Power- saving

Sleep mode, Watchdog Timer and code protection

featur es improve sy ste m co st, pow e r and relia bil ity.

The PIC12F508/509/16F505 devices are available in

the cost-effective Flash programmable version, which

is suitable for production in any volume. The customer

can take full advantage of Microchip’s price leadership

in Flash programmable microcontrollers, while

benefiting from the Flash programmable flexibility.

The PIC12F508/509/16F505 products are supported

by a full-featured macro assembler, a software simu la-

tor, an in-circuit emulator, a ‘C’ compiler, a low-cost

development programmer and a full featured program-

mer. All the tools are supported on IBM® PC and

compatible machin es.

1.1 Applications

The PIC12F508/509/16F505 devices fit in applications

ranging from personal care appliances and security

systems to low-power remote transmitters/receivers.

The Flash technology makes customizing application

programs (transmitter codes, appliance settings,

receiver frequencies, etc.) extremely fast and conve-

nient. The smal l footpri nt p ackag es, for t hrough h ole or

surface mounting, make these microcontrollers perfect

for applications with space limitations. Low cost, low

power, high perform ance, ease of use and I/O flexi bility

make the PIC12F508/509/16F505 devices very versa-

tile even in areas where no microcontroller use has

been co nsidered befo re (e.g., timer f unctions, lo gic and

PLDs in l arge r s ystem s and coprocessor appl ic ati ons ).

TABLE 1-1: PIC12F508/509/16F505 DEVICES

PIC12F508 PIC12F509 PIC16F505

Clock Maximum Frequency of Operation (MHz) 4 4 20

Memory Flash Pr ogram Memory 512 1024 1024

Data Memory (bytes) 25 41 72

Peripherals Timer Module(s) TMR0 TMR0 TMR0

Wake- up from Sleep on Pin Change Yes Yes Yes

Features I/O Pi n s 5 5 11

Input Pins 1 1 1

Internal Pull-ups Yes Yes Yes

In-Circuit Serial Programming Yes Yes Yes

Number of Instructions 33 33 33

Packages 8-pin PDIP, SOIC,

MSOP 8-pin PDIP, SOIC,

MSOP 14-pin PDIP, SOIC,

TSSOP

The PIC12F508/509/16F505 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current

capability and precision internal oscillator.

The PIC12F508/509/16F505 device uses serial program ming with data pin RB0/GP0 and clock pin RB1/GP1.

PIC12F508/509/16F505

DS41236A-page 6 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS41236A-page 7

PIC12F508/509/16F505

2.0 P IC12F5 08 /50 9/1 6F5 05 D EVICE

VARIETIES

A variety of packaging options are available. Depend-

ing on application and production requirements, the

proper device option can be selected using the

information in this section . When placing orders, please

use the PIC12F508/509/16F505 Product Identification

System at the back of this data sheet to specify the

correct part numbe r.

2.1 Quick Turn Programming (QTP)

Devices

Microchip offers a QTP programming service for

factory production orders. This service is made

available for users who choose not to program

medium-to-high quantity units and whose code

patterns have stabilized. The devices are identical to

the Flash devices but with all Flash locations and fuse

options already programmed by the factory. Certain

code and prototype verification procedures do apply

before production shipments are available. Please

cont act your loc al Microchip Techn ology sales of fice for

more details.

2.2 Serialized Quick Turn

ProgrammingSM (SQTPSM) Devices

Microchip offers a unique programming service, where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number, which can serve as an entry code,

password or ID number.

PIC12F508/509/16F505

DS41236A-page 8 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS41236A-page 9

PIC12F508/509/16F505

3.0 ARCHITECTURAL OVERVIEW

The hi gh pe rf or ma nce of t he P IC 12F 508/ 509 /1 6F 505

devices can be attributed to a number of architectural

features commonly found in RISC microprocessors.

To begin with, the PIC12F508/509/16F505 devices

use a H arvard archit ectur e in whi ch progr am an d dat a

are accessed on separate buses. This improves

bandwidth over traditional von Neumann architec-

tures where program and data are fetched on the

same bus . Se para ti ng pro gr am an d data mem or y fur -

ther allows instructions to be sized differently than the

8-bit wide data wor d. Instruct ion opcode s are 12 bits

wide, making it possible to have all single-word

instructions. A 12-bit wide program memory access

bus fetches a 12-bit instruction in a single cycle. A

two-stage pipeline overlaps fetch and execution of

instructions. Consequently, all instructions (33)

execute in a single cycle (200 ns @ 20 MHz, 1 µs @

4 MHz) except for program branches.

The Table below lists program memory (Flash) and

data memory (RAM) for the PIC12F508/509/16F505

devices.

TABLE 3-1: PIC12F50 8/5 09/1 6F 505

MEMORY

The PIC12F508/509/16F505 devices can directly or

indirec tly addres s its register f iles and data m emory. All

Special Function Registers (SFR), including the PC,

are mapped in the data memory. The PIC12F508/509/

16F505 devices have a highly orthogonal (symmetri-

cal) instruction set that makes it possible to carry out

any operation, on any register, using any addressing

mode. This symmetrical nature and lack of “special

optimal situations” make programming with the

PIC12F508/509/16F505 devices simple, yet efficient.

In addition, the learning curve is reduced significantly.

The PIC12F508/509/16F505 devices contain an 8-bit

ALU and working register. The ALU is a general

purpose arithmetic unit. It performs arithmetic and

Boolean fu nctions be tween da ta in the w orking regist er

and any register file.

The ALU is 8 bits wide and capable of addition, subtrac-

tion, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two’s comple-

ment in nature. In two-operand instructions, one

operand is ty pi ca lly the W (working ) re gis ter. The oth er

operand is either a file register or an immediate

const ant. I n sing le ope rand in struc tions, the ope rand i s

either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC) and

Zero (Z) bits in the Status register. The C and DC bits

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

A simplified block diagram is shown in Figure 3-2, with

the corresponding device pins described in Table 3-3.

Device Memory

Program Data

PIC12F508 512 x 12 25 x 8

PIC12F509 1024 x 12 41 x 8

PIC16F505 1024 x 12 72 x 8

PIC12F508/509/16F505

DS41236A-page 10 Preliminary  2004 Microchip Technology Inc.

FIGURE 3-1: PIC12F50 8/509 BLOCK DIAGRAM

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

Flash

Program

Memory

12 Data Bus 8

Program

Bus

Instruction reg

Program Counter

RAM

File

Registers

Direct Addr 5

RAM Addr 9

Addr MUX

Indirect

Addr

FSR reg

Status reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2

MCLR VDD, VSS

Timer0

GPIO

GP4/OSC2

GP3/MCLR/VPP

GP2/T0CKI

GP1/ISCPCLK

GP0/ISCPDAT

5-7

GP5/OSC1/CLKIN

Stack 1

Stack 2

512 x 12 or

25 x 8 or

1024 x 12

41 x 8

Internal RC

OSC

 2004 Microchip Technology Inc. Preliminary DS41236A-page 11

PIC12F508/509/16F505

TABLE 3-2: PIC12F508/509 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

GP0/IC SPDA T GP0 TTL CMOS Bidirecti onal I/O pin. C an be software programmed for i nternal

weak pull-up and wake-up from Sleep on pin change.

ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.

GP1\IC SPCLK GP1 TTL CMOS Bidirectiona l I/O pin. Can b e software prog rammed for inte rnal

weak pull-up and wake-up from Sleep on pin change.

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.

GP2/T0CKI GP2 TTL CMOS Bidirectional I/O pin.

T0CKI ST — Clock input to TMR0.

GP3/MCLR/VPP GP3 TTL — Input pin. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is

an activ e-low Res et to the dev ice. V ol tage on MCLR/VPP must

not exceed VDD during normal device operation or the device

will enter Programming mode. Weak pull-up always on if

configured as MCLR.

VPP HV — Programming voltage input.

GP4/OSC2 GP4 TTL CMOS Bidirectional I/O pin.

OSC2 — XTAL Oscillator cr yst al output. Connect ions to cr ystal or resonato r in

Cryst al Oscill ator mode (XT and LP mode s only , G PIO in other

modes).

GP5/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O pin.

OSC1 XTAL — Oscillator crystal input.

CLKIN ST — External cl ock source input .

VDD VDD — P Positive supply for logic and I/O pins.

VSS VSS — P Ground reference for logic and I/O pins.

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input

PIC12F508/509/16F505

DS41236A-page 12 Preliminary  2004 Microchip Technology Inc.

FIGURE 3-2: PIC16F505 BLOCK DIAGRAM

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

Flash

Program

Memory

12 Data Bus 8

Program

Bus

Instruction reg

Program Counter

RAM

File

Registers

Direct Addr 5

RAM Addr 9

Addr MUX

Indirect

Addr

FSR r e g

Status reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS

Timer0

PORTB

RB4/OSC2/CLKOUT

RB3/MCLR/VPP

RB2

RB1/ICSPDAT

RB0/ICSPCLK

5-7

RB5/OSC1/CLKIN

Stack 1

Stack 2

1K x 12

72 bytes

Internal RC

OSC

PORTC

RC4

RC3

RC2

RC1

RC0

RC5/T0CKI

 2004 Microchip Technology Inc. Preliminary DS41236A-page 13

PIC12F508/509/16F505

TABLE 3-3: P IC16F505 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RB0/ICSPDAT RB0 TTL CMOS Bidirectional I/O pin. Can be so ftware program med for internal

weak pull-up and wake-up from Sleep on pin change.

ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.

RB1/ICSPCLK RB1 TTL CMOS Bidirectiona l I/O pin. Can be so ftware prog rammed for inte rnal

weak pull-up and wake-up from Sleep on pin change.

ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.

RB2 RB2 TTL CMOS Bidirectional I/O pin.

RB3/MCLR/VPP RB3 TTL — Input port. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is

an activ e-low Res et to the dev ice. V ol tage on MCLR/VPP must

not exceed VDD during normal device operation or the device

will enter Programming mode. Weak pull-up always on if

configured as MCLR.

VPP — — Programming voltage input.

RB4/OSC2 /CLKOUT RB4 TTL CMOS Bidirectional I/O pin. Can be so ftware program med for internal

weak pull-up and wake-up from Sleep on pin change.

OSC2 — XTAL Oscillator cr yst al output. Connect ions to cr ystal or resonato r in

Crystal Oscillator mode (XT, HS and LP modes only).

CLKOUT — CMOS In EXTRC and INTRC modes, the pin output can be

configu red for CLKOUT, which has 1/4 the frequency of O SC1

and denotes the instruction cycle rate.

RB5/OSC1/CLKIN RB5 TTL CMOS Bidirectional I/O pin.

OSC1 XTAL — Crystal input.

CLKIN ST — External cl ock source input.

RC0 RC0 TTL CMOS Bidirectional I/O pin.

RC1 RC1 TTL CMOS Bidirectional I/O pin.

RC2 RC2 TTL CMOS Bidirectional I/O pin.

RC3 RC3 TTL CMOS Bidirectional I/O pin.

RC4 RC4 TTL CMOS Bidirectional I/O pin.

RC5/T0CKI RC5 TTL CMOS Bidirectional I/O pin.

T0CKI ST — Clock input to TMR0.

VDD VDD — P Positive supply for logic and I/O pins.

VSS VSS — P Ground reference for logic and I/O pins.

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input

PIC12F508/509/16F505

DS41236A-page 14 Preliminary  2004 Microchip Technology Inc.

3.1 Clocking Scheme/Instruction

Cycle

The cloc k input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC

is incremented every Q1 and the instruction is fetched

from program memory and latched into the instruction

following Q1 through Q4. The clocks and instruction

execution flow is shown in Fi gure 3-3 and Example 3-1.

3.2 Instruction Flow/Pipelining

An instruction cycl e consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the PC to cha nge (e.g., GOTO), then two cyc le s

are req uired to com plete the ins truction (Ex ampl e 3-1).

A fetch cy cle begins with the PC incrementing in Q1.

In the ex ecution cycle , the fetched instruction i s latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q 3 and Q4 c ycles. Data mem ory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-3: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

PC PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC – 1) Fetch INST (PC + 1)

Execute INST (PC) Fetch INST (PC + 2)

Execute INST (PC + 1)

Internal

phase

clock

All instru ctions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

1. MOVLW 03H Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTB, BIT1 Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

 2004 Microchip Technology Inc. Preliminary DS41236A-page 15

PIC12F508/509/16F505

4.0 MEMORY ORGANIZATION

The PIC12F508/509/16F505 memories are organized

into program memory and data memory. For devices

with m ore than 512 bytes of program memo ry , a pa ging

scheme is used. Program memory pages are accessed

using one Status register bit. For the PIC12F509 and

PIC16F505, with data memory register files of more

than 32 registers, a banking scheme is used. Data

memory banks are accessed using the File Select

4.1 Program Memory Orga nization for

the PIC12F508/509

The PIC12F508 device has a 10-bit Program Counter

(PC) and PIC12F509 has a 11-bit Program Counter

(PC) cap able of add ressing a 2K x 12 p rogram memo ry

space.

Only the first 512 x 12 (0000h-01FFh) for the

PIC12F508, and 1K x 12 (0000h-03FFh) for the

PIC12F509 are physically implemented (see

Figure 4-1). Accessing a location above these

boundaries will cause a wraparound within the first

512 x 12 space (PIC12F508) or 1K x 12 space

(PIC12F509 ). The effective Reset vector is a 0000h

(see Figure 4-1). Location 01FFh (PIC12F508) and

location 03FFh (PIC12F509) contain the internal

clock oscillator calibration value. This value should

never be overw ritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC12F508/509

CALL, RETLW PC<11:0>

S tack Level 1

S tack Level 2

User Memory

Space

0000h

7FFh

01FFh

0200h

On-chip Program

Memory

Reset Vector(1)

Note 1: Address 0000h becomes the

effective Reset vector. Location

01FFh, 03FFh (PIC12F508,

PIC12F509) contains the MOVLW XX

internal oscillator calibration value.

512 Word

1024 Word 03FFh

0400h

On-chip Program

Memory

PIC12F508/509/16F505

DS41236A-page 16 Preliminary  2004 Microchip Technology Inc.

4.2 Program Memory Organization

For The PIC 16F505

The PIC16F505 device has a 11-bit Program Counter

(PC) cap able of add ressing a 2K x 12 p rogram memo ry

space.

The 1K x 12 (0000h-03FFh) for the PIC16F505 are

physically implemented. Refer to Figure 4-2. Access-

ing a location above this boundary will cause a wrap-

around within the first 1K x 12 space. The effective

Reset vector is at 0000h (see Figure 4-2). Location

03FFh co ntains the in tern al osc il la tor c ali bration value.

This value should never be overwritten.

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F505

4.3 Data Memory Organization

Data memory is composed of registers or bytes of

RAM. T herefore, dat a me mo ry for a device is specified

by its register file. The register file is divided into two

functional groups: Special Function Registers (SFR)

and General Purpose Registers (GPR).

The Specia l Func ti on R egi st ers in clude the TMR0 reg-

ister, the Program Counter (PCL), the Status register,

the I/O registers (ports) and the File Select Register

(FSR). In addition, Special Functio n Registers are used

to control the I/O port configuration and prescaler

options.

The General Purpose Registers are used for data and

control information und er com ma nd of t he instructions .

For the PIC12F508/509, the register file is composed of

7 Special Function Registers, 9 General Purpose

Registers and 16 or 32 General Purpose Registers

accessed by banking (see Figure 4-3 and Figure 4-4).

For the PIC16F505, the register file is composed of 8

Special Function Registers, 8 General Purpose

Registers and 64 General Purpose Registers accessed

by banking (Figure 4-5).

4.3. 1 GENERAL PURPOSE REGISTER

FILE

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 4.9 “Indirect Data Addressing:

INDF and FSR Registers”.

CALL, RETLW PC<11:0>

S tack Level 1

S tack Level 2

User Memory

Space

0000h

7FFh

01FFh

0200h

Reset Vector(1)

Note 1: Address 0000h becomes the

effective Reset vector. Location

03FFh contains the MOVLW XX

internal oscillator calibration value.

1024 Words 03FFh

0400h

On-chip Program

Memory

 2004 Microchip Technology Inc. Preliminary DS41236A-page 17

PIC12F508/509/16F505

FIGURE 4-3: PIC12F50 8 REGIST E R

FILE MAP FIGURE 4-4: PIC12F509 REGISTER

FILE MAP

FIGURE 4-5: PIC16F505 REGISTER FILE MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General

Purpose

Registers

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and

FSR Registers”.

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

0Fh 10h

Bank 0 Bank 1

3Fh

30h

20h

2Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

Addresses map

back to

addresses

in Bank 0.

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and F SR

Registers”.

FSR<6:5> 00 01

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

OSCCAL

PORTB

0Fh 10h

Bank 0 Bank 1

3Fh

30h

20h

2Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

Addresses map back to

addresses in Bank 0.

Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.

FSR<6:5> 00 01

Bank 3

7Fh

70h

60h

6Fh

General

Purpose

Registers

Bank 2

5Fh

50h

40h

4Fh

General

Purpose

Registers

08h

PORTC

PIC12F508/509/16F505
DS41236A-page 18 Preliminary  2004 Microchip Technology Inc.
4.3.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used b y the CPU  and periph eral functio ns to cont rol the
operation of the device (Table 4-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are  described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC12F508/509)   
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2  Bit 1 Bit 0 Value on
Power-On
Reset(2) Page #
00h INDF Uses Contents of FSR to Address Data Memory (not a physical 
register) xxxx xxxx 26
01h TMR 0 8-bit Real-Time Clock/Counter xxxx xxxx 33
02h(1) PCL Low-order 8 bits of PC 1111 1111 25
03h STATUS GPWUF —PA0
(5) TO PD Z DC C 0-01 1xxx(3) 20
04h FSR  Indirect Data Memory Address Pointer 111x xxxx 26
04h(4) FSR  Indirect Data Memory Address Pointer 110x xxxx 26
05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 24
06h GPIO —— GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 29
N/A TRISGPIO —— I/O Co ntro l Reg ister --11 1111 29
N/A OPTION GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 22
Legend: — = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition.
Note 1: The upper by te of the Program  Counter is n ot directly ac cessibl e. See Sec tion 4 .7 “Program Counter” fo r 
an explanation of how to access these bits.
2: Other (non Powe r-up ) Resets include externa l Rese t throu gh  MC L R, Watchdog Timer and wake-up on pin 
change Reset.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
4: PIC12F509 only.
5: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508. 

 2004 Microchip Technology Inc. Preliminary DS41236A-page 19
PIC12F508/509/16F505
TABLE 4-2: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505)  
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2  Bit 1 Bit 0 Value on
Power-On
Reset(2) Page #
00h INDF Uses Contents of FSR to Address Data Memory (not a physical 
register) xxxx xxxx 26
01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 33
02h(1) PCL Low-order 8 bits of PC 1111 1111 25
03h STATUS RBWUF —PA0TO PD Z DC C 0-01 1x xx 20
04h FSR  Indirect Data Memory Address Pointer 110x xxxx 26
05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 24
06h PORTB —— RB5 RB4 RB3 RB2 RB1 RB0 -- xx xxxx    29
07h PORTC —— RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 29
N/A TRISB —— I/O Control Register --11 1111 29
N/A TRISC —— I/O Control Register --11 1111 29
N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 23
Legend: — = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depen ds on con dit ion.
Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
2: Other (non Power-up) Resets include external reset through MCLR, Watchdog Timer and wake-up on pin 
change Reset.
    

PIC12F508/509/16F505

DS41236A-page 20 Preliminary  2004 Microchip Technology Inc.

4.4 Status Register

This register contains the arithmetic status of the ALU,

the Reset status and the page preselect bit.

The Status register can be the destination for any

instruction, as with any other register. If the Status

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

Status register as destination may be different than

intended.

For exam ple, CLRF STATUS, will clear the upper thre e

bits and set th e Z bit. Thi s leaves the Statu s regist er as

000u u1uu (where u = unchanged).

Therefore, it is recommended that only BCF, BSF and

MOVWF instructi on s be us ed to alt er the Status register.

These instructions do not af fect the Z, DC or C bit s from

the Status register. For other instructions which do

affect Status bits, see Section 8.0 “Instruction Set

Summary”.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

GPWUF —PA0TO PD ZDCC

bit 7 bit 0

bit 7 GPWUF: GPIO Reset bit

1 = Reset due to wake-up from Sleep on pin change

0 = After power-up or other Reset

bit 6 Reserved: Do not use

bit 5 PA0: Program Page Preselect bits(1)

1 = Page 1 (200h-3FFh)

0 = Page 0 (000h-1FFh)

Each page is 512 bytes.

Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page

preselect is not recommended, since this may affect upward compatibility with future products .

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instr uct ion, or SLEEP instructio n

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instructio n

0 = By execution of the SLEEP instruct i on

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)

ADDWF:

1 = A carry from the 4th low-order bit of the result occurred

0 = A carry from the 4th low-order bit of the result did not occur

SUBWF:

1 = A borrow from the 4t h low-order bit of the result did not occur

0 = A borrow from the 4th low-order bit of the result occurred

bit 0 C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF: SUBWF: RRF or RLF:

1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively

0 = A carry did not occur 0 = A borrow occurred

Note 1: This bit is used on the PIC12F509. For code compatibility do not use this bit on the

PIC12F508.

Legend:

R = Readable bit W = Writab le bit U = Un implemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = B it is unknown

 2004 Microchip Technology Inc. Preliminary DS41236A-page 21

PIC12F508/509/16F505

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

RBWUF —PA0TO PD ZDCC

bit 7 bit 0

bit 7 RBWUF: PORTB Reset bit

1 = Reset due to wake-up from Sleep on pin change

0 = After power-up or other Reset

bit 6 Reserved: Do not use

bit 5 PA0: Program Pa ge Preselect bits

1 = Page 1 (200h-3FFh)

0 = Page 0 (000h-1FFh)

Each page is 512 bytes.

Using the PA0 bit as a general purpose re ad/write b it in devi ces which do not use it fo r program

page preselect is not recommended, since this may affect upward compatibility with future

products.

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bi t

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit ca rry/borrow bit (for ADDWF and SUBWF instructions)

ADDWF:

1 = A carry from th e 4th low-order bit of th e result occurred

0 = A carry from the 4th low-order bit of the result did not occur

SUBWF:

1 = A borrow from the 4th low-order bit of the result did not occur

0 = A borrow from the 4th low-order bit of the result occurred

bit 0 C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF:SUBWF:RRF or RLF:

1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively

0 = A carry did not occur 0 = A borrow occurred

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is se t ‘0’ = Bit is cleared x = Bit is unknown

PIC12F508/509/16F505

DS41236A-page 22 Preliminary  2004 Microchip Technology Inc.

4.5 Option Register

The Option register is a 8-bit wide, write-only register,

which contains various control bits to configure the

Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of

the W regis ter will be transfe rred to the Option register.

A Reset sets the Option<7:0> bits.

Note: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled

for that pin (i.e., note that TRIS overrides

Option control of GPPU/RBPU and

GPWU/RBWU).

Note: If the T0CS bit is set to ‘1’, it will override

the TRIS functi on on the T0CKI pin.

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 GPWU: En able Wake-up on Pin Change bit (GP0, GP1, GP3)

1 = Disabled

0 = Enabled

bit 6 GPPU: Enable Weak Pull -ups bit (GP0, GP1, GP3)

1 = Disabled

0 = Enabled

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)

0 = Transition on internal instruction cycle clock, FOSC/4

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on the T0CKI pin

0 = Increment on low-to-high transition on the T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Presca ler assigned to the WDT

0 = Presca ler assigned to Timer0

bit 2-0 PS<2:0>: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is se t ‘0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value Timer0 Rate WDT Rate

 2004 Microchip Technology Inc. Preliminary DS41236A-page 23

PIC12F508/509/16F505

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4)

1 = Disabled

0 = Enabled

bit 6 RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)

1 = Disabled

0 = Enabled

bit 5 T0CS: Timer0 clock S ourc e Select bit

1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)

0 = Transition on internal instruction cycle clock, FOSC/4

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on the T0CKI pin

0 = Increment on low-to-high transition on the T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler assigned to the WDT

0 = Presca ler assigned to Timer0

bit 2-0 PS<2:0>: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is se t ‘0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value Timer0 Rate WDT Rate

PIC12F508/509/16F505

DS41236A-page 24 Preliminary  2004 Microchip Technology Inc.

4.6 OSCCAL Register

The Oscill ator Calibration (OSCCAL) register is used to

calibrate the internal precision 4 MHz oscillator. It

cont ains seven bits for calibra tio n.

After you move in the calibration constant, do not

change the value. See Section 7.2.5 “Internal 4 MHz

RC Oscillator”.

Note: Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0

CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —

bit 7 bit 0

bit 7-1 CAL<6:0>: Oscillator Calibration bits

0111111 =Maximum frequency

•

0000001

0000000 =Center frequency

1111111

•

1000000 =Minimum frequency

bit 0 Unimplemented: Read as ‘0’

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is se t ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41236A-page 25

PIC12F508/509/16F505

4.7 Program Counter

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The Program Counter

(PCL) is mapped to PC<7:0>. Bit 5 of the Status

(Figure 4-6).

For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are

provided by the instruction word. However, PC<8>

does not co me fro m the in stru ct ion word, but is alway s

cleared (Figure 4-6).

Instr uctions where the PCL is th e destinatio n, or modif y

PCL instructions, include MOVWF PC, ADDWF PC and

BSF PC,5.

FIGURE 4-6: LOADING OF PC

BRANCH INSTRUCTIONS

4.7.1 EFFECTS OF RESET

The PC is set upon a Reset, which means that the PC

addresses the last location in the last page (i.e., the

oscillator calibration instruction). After executing

MOVLW XX, the PC will roll over to location 00h and

begin executing user code.

The S t atus register page preselec t bits are cleared upon

a Reset, which means that p a ge 0 is pre-sele cted.

Therefore, upon a Reset, a GOTO instruction will

automat ically cause t he program to jump to page 0 until

the value of the page bits is altered.

4.8 Stack

The PIC12F508/509/16F505 devices have a 2-deep,

12-bit wide hardware PUSH/POP stack.

A CALL instruction will PUSH the current value of S tack 1

into Stack 2 an d t he n PUS H the current PC v a lu e, in cre -

mented by one, into Stack Level 1. If more than two

sequential CALLs are ex ecuted, o nly the mo st recen t two

return ad dresses are s tor ed .

A RETLW instruction will POP the contents of Stack

Level 1 into the PC and then copy Stack Level 2

content s into S ta ck Level 1. If more tha n two seq uential

RETLWs are executed, the stack will be filled with the

address previously stored in Stack Level 2. Note that

the W register will be loaded with the literal value

specif ied in the inst ruction. This i s particu larly useful f or

the implementation of data look-up tables within the

program me mory.

Note: Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction,

all subroutine calls or computed jumps are

limited to the first 256 locations of any

program mem ory pa ge (512 w ords long).

PA0

Status

PC 87 0

PCL

910

Inst ruction Word

GOTO Ins truction

CALL or Modify PCL Instruction

PA0

Status

PC 87 0

PCL

910

Inst ruction Word

Reset to ‘0’

Note 1: There are no Status bits to indicate stack

overflows or stack underflow conditions.

2: There are no instruction mnemonics

called PUSH or POP. These are actions

that occ ur from th e exec ution of the CALL

and RETLW instructions.

PIC12F508/509/16F505

DS41236A-page 26 Preliminary  2004 Microchip Technology Inc.

4.9 Indire ct Data Addressing: INDF

and FSR Registers

The INDF register is not a physical register.

Addressing INDF actually addresses the register

whose address i s contai ned in the FSR r egister (FSR

is a pointer). This is indirect addressing.

4.9.1 IND IRECT ADDRES SIN G

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 08)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no operation (although Status bits may be affected).

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

The FSR is a 5-bit wide register . It is used in conjunctio n

with the INDF register to indirectly address the data

memory area.

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

FIGURE 4-7: DIRECT/INDIRECT ADDRESSING (PIC12F508/509)

PIC12F508 – Does not use banking. FSR <7:5> are

unimplemented and read as ‘1’s.

PIC12F509 – Use s FSR<5>. Selec ts betwee n bank 0

and bank 1 . FSR<7:6> is unimp lemented , read as ‘1’.

PIC16F505 – U ses FSR<6:5>. S elects fro m bank 0 to

bank 3. FSR<7> is unimplemented, read as ‘1’.

MOVLW 0x10 ;initiali ze pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;c lear IN DF

;register

INCF FSR,F ;inc pointer

BTFSC FSR,4 ;all done?

GOTO NEXT ;NO, clear next

CONTINUE : ;YES, continue

Note 1: F or regist er map detail, see Section 4.3 “Data Memory Organization”.

2: PIC12F509.

Bank Location Select

Location Select

Bank Select

Indirect Addressing

Direct Addressing

Data

Memory(1) 0Fh

10h

Bank 0 Bank 1(2)

6(FSR)

00 01

00h

1Fh 3Fh

(opcode) 04

(FSR)

Addresses

map back to

addresses

in Bank 0.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 27

PIC12F508/509/16F505

FIGURE 4-8: DIRECT/INDIRECT ADDRESSING (PIC16F505)

Note 1: For register map detail, see Section 4 .3 “Data Memory Organizatio n ”.

Direct Addressing

(FSR)

6 5 4 (opcode) 0

Bank Select Location Select

00 01 10 11

00h

0Fh

10h

Data

Memory(1)

1Fh 3Fh 5Fh 7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Indirect Addressing

6 5 4 (FSR) 0

Bank Location Select

Addresses

map back to

addresses

in Bank 0.

PIC12F508/509/16F505

DS41236A-page 28 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS41236A-page 29

PIC12F508/509/16F505

5.0 I/O PORT

As with any other register, the I/O register(s) can be

written and read und er program contro l. Howeve r , read

instructions (e.g., MOVF PORTB,W) alwa ys r ead t he I/O

pins independent of the pin’s input/output modes. On

Reset, all I/O ports are defined as input (inputs are at

high-impedance) since the I/O control registers are all

set.

5.1 PORTB/GPIO

PORTB/GPIO is an 8-bit I/O register. Only the low-

order 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are

unimplemented and read as ‘0’ s. Please note that RB 3/

GP3 is an input only pin. The Configuration Word can

set se veral I/O’s to alternate fu nc tio ns. Wh en acting as

alternate func tions, the pins will read as ‘0’ during a port

read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4

can be configured with weak pull-ups and also for

wake-up on change. The wake-up on change and weak

pull-up functions are not pin selectable. If RB3/GP3/

MCLR is configured as MCLR, weak pull-up is always

on and wake-up on change for this pin is not enabled.

5.2 PORTC (PIC16F505 Only)

PORT C is an 8-bit I/O register . Only the low-order 6 bit s

are used (RC<5:0>). Bits 7 and 6 are unimplemented

and read as ‘0’s.

5.3 TRIS Registers

The Output Driver Control register is loaded with the

contents of the W register by executing the TRIS f

instruction. A ‘1’ from a TRIS regi ster bit pu ts the corre-

sponding output driver in a High-Impedance mode. A

‘0’ puts the contents of the output data latch on the

selected pins, enabling the output buffer. The excep-

tions are RB3/GP3, which is input only and the T0CKI

pin, which may be controlled by the Option register.

See R egister 4-3 and Regist er 4-4.

The TRIS registers are “write-only” and are set (output

drivers disabled) upon Reset.

5.4 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-2. All port pins, except RB3/GP3 which is

input only, may be used for bo th input an d output op er-

ations. For input operations, these ports are non-latch-

ing. Any input must be present until read by an input

instruction (e.g., MOVF PORTB, W). The outputs are

latched and remain unchanged until the output latch is

rewritten. To use a port pin as output, the correspond-

ing dir ectio n contro l bit in T RIS must be cleared (= 0).

For use as an input, the corresponding TRIS bit must

be set. Any I/O pin (except RB3/GP3) can be

programmed individually as input or output.

FIGURE 5-1: PIC12F508/509/16F505

EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Note: On the PIC12F508 /509, I /O POR TB i s ref-

erenced as GPIO. On the PIC16F505, I/O

PORTB is referenced as PORTB.

Note: A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driv en hig h,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

Data

Bus

CK P

Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O

Reg

Latch

Reset

Note 1: See Table 3-3 for buffer type.

VSS

VDD

(1)

PIC12F508/509/16F505

DS41236A-page 30 Preliminary  2004 Microchip Technology Inc.

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-On

Reset

Value on

All Other

Resets

N/A TRISGPIO(1) —— I/O Control Register --11 1111 --11 1111

N/A TRISB(2) —— I /O Control Register --11 1111 --11 1111

N/A TRISC(2) —— I/O Control Register --11 1111 --11 1111

N/A OPTION(1) GPWU GPPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111

N/A OPTION(2) RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111

03h STATUS(1) GPWUF —PAO TO PD ZDC C0-01 1xxx q00q quuu(3)

03h STATUS(2) RBWUF —PAO TO PD ZDC C0-01 1xxx q00q quuu(3)

06h GPIO(1) —— GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu

06h PORTB(2) —— RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu

07h PORTC(2) —— RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu

Legend: Shaded cells are not used by Port registers, read as ‘0’. — = unimplemented, read as ‘0’, x = unknown, u = unchanged,

q = depends on condition.

Note 1: PIC12F508/509 only.

2: PIC16F505 only.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 31

PIC12F508/509/16F505

5.5 I/O Programming Considerations

5.5.1 BI DIREC TION AL I/O PORTS

Some instructions operate internally as read followed

by write operations. The BCF and BSF instructions, for

exampl e, read the entire port into the CPU, execute the

bit operation and re-write the result. Caution must be

used when these instructions are applied to a port

where one or more pin s are use d as in put/outputs. For

exampl e, a BSF operation on bit 5 of PO RTB/ GPI O will

cause a ll eig ht b it s of PORTB/GPIO to be rea d in to the

CPU, bit 5 t o be se t and th e P ORTB /G P IO val u e to be

written to the output latches. If another bit of PORTB/

GPIO is used as a bidi rectio nal I/O pin (s ay bit 0) a nd it

is defined as an input at this time, the input signal

present on the pin it self would be read into the CPU and

rewritte n to the dat a latch o f this p articular pin, overwrit-

ing the p reviou s content. As long as t he pin st ays in th e

Input mode, no problem occurs. However, if bit 0 is

switched into Output mode later on, the content of the

data l atch may now be unk n own .

Example 5-1 shows the effect of two sequential

Read-Modify-Write instructions (e.g., BCF, BSF, etc.)

on an I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired OR”, “wired

AND”). The res ulting hig h output curre nts may dam age

the chip.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT(e.g. PIC16F505)

5.5.2 SUCCESSIVE OPERATIONS ON

I/O PORTS

The actual write to an I/O port happens at the end of an

instr uction cycl e, wher eas f or re ading , the d ata mu st be

valid at the beginning of the instruction cycle (Figure 5-2).

Therefore, care must be exercised if a write followed by

a read operation is carried out on the same I/O port. The

sequence of instructions should allow the pin voltage to

stabilize (load dependent) before the next instruction

caus es that fi le to be read into the CPU. Other wis e, the

previous state of that pin may be read into the CPU rather

than the new state. When in doubt, it is better to separate

these instructions with a NOP or another instruction not

access ing this I/O port.

FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC16F505 Shown)

;Initial PORTB Settings

;PORTB<5:3> Inputs

;PORTB<2:0> Outputs

;

; PORTB latch PORTB pins

; ---------- ----------

BCF PORTB, 5 ;--01 -ppp --11 pppp

BCF PORTB, 4 ;--10 -ppp --11 pppp

MOVLW 007h;

TRIS PORTB ;--10 -ppp --11 pppp

;

Note 1: The user may have expected the pin values to

be ‘--00 pppp’. The 2nd BCF caused RB5 to

be latched as the pin value (High).

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetched

RB<5:0>

MOVWF PORTB NOP

Port pin

sampled here

NOPMOVF PORTB, W

Instruction

Executed MOVWF PORTB

(Write to PORTB) NOPMOVF PORTB,W

This example shows a write to PORTB

followed by a read from PORTB.

Data s e tu p ti me = (0 .2 5 TCY – TPD)

where: TCY = instruction cycle.

TPD = propagation delay

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

(Read PORTB)

Port pi n

written here

PIC12F508/509/16F505

DS41236A-page 32 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS41236A-page 33

PIC12F508/509/16F505

6.0 TIMER0 MODULE AND TMR0

The Timer0 module has the following features:

• 8-bit time r/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(Option<5>). In Timer mode, the Timer0 module will

increm ent ev ery ins tru cti on cycle (witho ut p r es ca ler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-2 and Figure 6-3).

The user can work around this by writing an adjusted

value to the TMR0 register.

Counter mode is selected by setting the T0CS bit

(Option<5>). In this mode, Timer0 will in crement either

on every rising or falling edge of pin T0CKI. The T0SE

bit (Option<4>) determines the source edge. Clearing

the T0SE bit select s the rising edge. Restrictions on the

external clock input are discussed in detail in

Section 6.1 “Using T ime r0 w ith a n Exte rnal C lo ck” .

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit, PSA (Option<3>). Clearing the PSA bit will

assign the prescaler to Timer0. The prescaler is not

readable or writable. Whe n the prescaler is assi gned to

the Timer0 module, prescale values of 1:2, 1:4,...,

1:256 are selectable. Section 6 .2 “Prescaler” detai ls

the operation of the pres caler.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the Option register .

2: The prescaler is shared with the Wa tchdo g Timer (Figure 6-5).

T0CS(1)

FOSC/4

Programmable

Prescaler(2)

Sync with

Internal

Clocks TMR0 reg

PSOUT

(2 TCY delay)

PSOUT

Data Bus

PSA(1)

PS2, PS1, PS0(1)

Sync

T0SE

(GP2/RC5)/T0CKI

PC – 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetch

Timer0

PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6

T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PC + 5

(Program

Counter)

PIC12F508/509/16F505

DS41236A-page 34 Preliminary  2004 Microchip Technology Inc.

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Add r e s s Na m e Bit 7 Bit 6 Bit 5 B it 4 Bit 3 B it 2 Bit 1 Bit 0 Value o n

Power-On

Reset

Value on

All Other

Resets

01h TMR0 Timer0 – 8-bit real-time clock/counter xxxx xxxx uuuu uuuu

N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

N/A TRISGPIO(1), (3) —— I/O Control Register --11 1111 --11 1111

N/A TRISC(2), (3) —— RC5 RC4 RC3 RC2 RC1 RC0 --11 1111 --11 1111

Legend: Shaded cells are not used by Timer0. — = unimplemented, x = unknown, u = unchanged.

Note 1: PIC12F508/509 only.

2: PIC16F505 only.

3: The TRIS of the T0CKI pin is overridden when T0CS = 1.

PC – 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

Fetch

Timer0

PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6

T0 T0 + 1 NT0 NT0 + 1

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PC + 5

(Program

Counter)

 2004 Microchip Technology Inc. Preliminary DS41236A-page 35

PIC12F508/509/16F505

6.1 Using Timer0 with an External

Clock

When an external cl ock input i s used for T ime r0, it must

meet ce r tain r equ ir e me nts. The ex t er na l cl oc k r equ ir e-

ment is due to internal phase clock (TOSC) synchroniza-

tion. Also , there is a d ela y in the actua l incr ementin g of

Timer0 after synchronization.

6.1.1 EXT ERN AL CLOCK

SYNCHRONIZATION

When no pr escal er is used, t he ex tern al clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI with the internal phase clocks is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-4).

Therefore, it is necessary for T0CKI to be high for at

least 2 TOSC (and a small RC delay of 2 Tt0H) and low

for at least 2 TOSC (and a small RC delay of 2 Tt0H).

Refer to the electrical specification of the desired

device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

pres caler, so that th e presc aler out put is sy mmetric al.

For the external clock to meet the sampling require-

ment, the ripple counter must be taken into account.

Therefore, i t is nec essa ry for T0CKI to h ave a perio d of

at least 4 TOSC (and a small RC delay of 4 Tt0H) divided

by the presc aler value . The only requi rement on T0CK I

high and low time is that they do not violate the

minimum pulse width requirement of Tt0H. Refer to

param ete rs 40, 41 and 42 in the electrical spec if ication

of the desired device.

6.1.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-4 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOC K

Increment Timer0 (Q4)

External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Timer0 T0 T0 + 1 T0 + 2

Small pulse

misses sampling

External Clock/ Pres cale r

Output After Sampling (3)

Prescaler Output (2)

(1)

Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

PIC12F508/509/16F505

DS41236A-page 36 Preliminary  2004 Microchip Technology Inc.

6.2 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Section 7.6 “Watch-

dog Timer (WDT)”). For simplicity, this counter is

being referred to as “prescaler” throughout this data

sheet.

The PSA and PS<2:0> bits (Option<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 regist er (e.g., CLRF 1, MOVWF 1,

BSF 1, x, etc. ) will clear t he prescale r . When assi gned

to WDT, a CLRWDT instruction will clear the prescaler

along with the WDT. The prescaler is neither readable

nor writ able. On a Re set, the prescal er contains all ‘0’s.

6.2.1 SWITCHIN G PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

contr ol (i.e. , it can be c hanged “o n-the-f ly” duri ng pro-

gram ex ecution). To avoid an unintended device Reset,

the follow ing instruction sequence (Example 6-1) must

be executed when changing the prescaler assignment

from Timer0 to the WDT.

EXAMPLE 6-1: CHANGIN G PRESCALER

(TIMER0 → WDT)

To change the prescaler from the WDT to the Timer0

module , use the se quence sh own in Exa mple 6-2. This

sequenc e mus t be us ed ev en if th e WDT is disab led. A

CLRWDT instruction should be executed before

switching the prescaler.

EXAMPLE 6-2: CHANGIN G PRESCALER

(WDT → TIMER0)

Note: The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice versa.

CLRWDT ;Clear WDT

CLRF TMR0 ;Clear TMR0 & Prescaler

MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7)

OPTION ;are required only if

;desired

CLRWDT ;PS<2:0> are 000 or 001

MOVLW ‘00xx1xxx’b ;Set Postscaler to

OPTION ;desired WDT rate

CLRWDT ;Clear WDT and

;prescaler

MOVLW ‘xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

OPTION

 2004 Microchip Technology Inc. Preliminary DS41236A-page 37

PIC12F508/509/16F505

FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER(1), (2)

TCY (= FOSC/4)

Sync

Cycles TMR 0 r e g

8-bit Prescaler

8-to-1 MUX

MUX

Watchdog

Timer

PSA

WDT

Time-out

PS<2:0>

PSA

WDT Enable bit

Data Bus

PSA

T0CS

T0SE

(GP2/RC5)/T0CKI

Note 1: T0CS , T0SE , PSA, PS<2:0> are bits in the Option register.

2: T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F 508/5 09.

PIC12F508/509/16F505

DS41236A-page 38 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS41236A-page 39

PIC12F508/509/16F505

7.0 SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors a re special circuits that deal with the nee ds of real-

time applications. The PIC12F508/509/16F505

microcontrollers have a host of such features intended

to maximize system reliability, minimize cost through

elimination of external components, provide power-

saving operating modes and offer code protection.

These features are:

• Oscillator Selection

• Reset:

- Power-on Reset (POR)

- Device Reset Timer (DRT)

- Wake-up from Sleep on Pin Change

• Watchdog Timer (WDT)

• Sleep

• Code Protection

• ID Locations

• In-Circuit Serial Programming™

•Clock Out

The PIC12F508/509/16F505 devices h ave a W atchdog

Timer, wh ic h c an b e shu t of f only through co nfi gura t io n

bit WDTE. It runs off of its own RC oscillator for added

reliability . If using HS (PIC16F505) , XT or LP selectabl e

oscillator options, there is always an 18 ms (nominal)

delay provided by the Device Reset Timer (DRT),

intended to keep the chip in Reset until the crystal

oscillator is stable. If using INTRC or EXTRC, there is

an 18 ms delay only on VDD p ower -up. Wi th thi s time r

on-chip, most applications need no external Reset

circuitry.

The Sleep mo de is des igned to of fer a ve ry low current

Power-down mode. The user can wake-up from Sleep

through a change on in put pin s o r thr oug h a Watchdog

Timer time-out. Several oscillator options are also

made available to allow the part to fit the application,

including an internal 4 MHz oscillator. The EXTRC

oscillator option saves system cost while the LP crystal

option s aves power . A s et of configura tion bits are used

to select various options.

7.1 Configuration Bits

The PIC12F508/509/16F505 Configuration Words

consist of 12 bits. Configuration bits can be

programmed to select various device configurations.

Three bits are for the selection of the oscillator type;

(two bits on the PIC12F508/509), one bit is the

Watchdog Timer enable bit, one bit is the MCLR enable

bit and one bit is for code protection (Register 7-1,

— — — — — — — MCLRE CP WDTE FOSC1 FOSC0

bit 11 bit 0

bit 11-5 Unimplemented: Read as ‘0’

bit 4 MCLRE: GP3/MCLR Pin Function Select bit

1 = GP3/MCLR pin function is MCLR

0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD

bit 3 CP: Code Protection bit

1 = Code protection off

0 = Code protection on

bit 2 WDTE: Wat chdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0 FOSC<1:0>: Oscillator Selection bits

11 = EXTRC = external selection bits

10 = INTRC = internal RC oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Refer to the “PIC12F508/509 Memory Program ming S pecif ications” (DS41227) to determine how to access

the Configuration Word. The Configuration Word is not user addressable during device operation.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown

PIC12F508/509/16F505

DS41236A-page 40 Preliminary  2004 Microchip Technology Inc.

— — — — — — MCLRE CP WDTE FOSC2 FOSC1 FOSC0

bit 11 bit 0

bit 11-6 Unimplemented: Read as ‘0’

bit 5 MCLRE: RB3/MCLR Pin Function Select bit

1 = RB3/MCLR pin function is MCLR

0 = RB3/MCLR pin function is digital I/O, MCLR int erna lly tied to VDD

bit 4 CP: Code Protection bit

1 = Code protection off

0 = Code protection on

bit 3 WDTE: Watchdog Timer Enable bit

1 = WDT enab led

0 = WDT di sabled

bit 2-0 FOSC<1:0>: Oscillator Selection bits

111 = External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin

110 = External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin

101 = Internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin

100 = Internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin

011 = EC oscillator/RB4 function on RB4/OSC2/CLKOUT pin

010 = HS oscillator

001 = XT osci llator

000 = LP oscillator

Note 1: Refer to the “PIC16F505 Memory Programming Specifications” (DS41226) to determine how to

access the Configuration Word. The Configuration Word is not user addressable during device

operation.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41236A-page 41

PIC12F508/509/16F505

7.2 Oscillator Configurations

7.2.1 OSCILLATOR TYPES

The PIC12F508/509/16F505 devices can be operated

in up to six different oscillator modes. The user can

program up to three configuration bits (FOSC<1:0>

[PIC12F5 08/509], FOSC<2 :0> [PIC16F505 ]). To select

one of these modes:

• LP: Low-Power Crystal

• XT: Crystal/Resonator

• HS: High-Speed Crystal/Resonator

(PIC16F5 05 onl y)

• INTRC: Internal 4 MHz Oscillator

• EXTRC: External Resi st or/Capacitor

• EC: External Hi gh-Speed Clock Input

(PIC16F5 05 onl y)

7.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In HS (PIC16F505), XT or LP modes, a crystal or

ceramic resonator is connected to the (GP5/RB5)/

OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins

to establish oscillation (Figure 7-1). The PIC12F508/

509/16F505 oscillator designs require the use of a

parallel cut crystal. Use of a series cut crystal may give

a frequency out of the crystal manufacturers

specifications. When in HS (PIC16F505), XT or LP

modes, the device can have an external clock source

drive the (GP5/RB5)/OSC1/CLKIN pin (Figure 7-2).

FIGURE 7-1: CRYSTAL OPERATION

(OR CERAMIC

RESONATOR)

(HS, XT OR LP OSC

CONFIGURATION)

FIGURE 7-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR

LP OSC

CONFIGURATION)

T ABLE 7-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS –

PIC12F508/509/16F505(1)

Note 1: This device has been designed to per-

form to th e parame ters of its data sheet .

It has been tested to an electrical

specification designed to determine its

conformance with these parameters.

Due to process differences in the

manufacture of this device, this device

may have different performance charac-

teristics than its earlier version. These

differences may cause this device to

perform differently in your application

than the earlier version of this device.

2: The user should verify that the device

oscillator starts and performs as

expect ed. Adjusting the loading cap acitor

values and/or the Oscillator mode may

be required.

Osc

Type Resonator

Freq Cap. Range

C1 Cap. Range

XT 4.0 MHz 30 pF 30 pF

HS(2) 16 MH z 10-47 pF 10 -47 pF

Note 1: These values are for design guidance

only. Since each resonat or has it s own

characteristics, the user should consult

the resonator manufacturer for

appropriate values of external

components.

2: PIC16F505 only.

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for A T

strip cut crystals.

3: RF approx. value = 10 MΩ.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) Sleep

To internal

logic

RS(2)

PIC12F508/509

PIC16F505

Clock from

ext. system OSC1

OSC2 PIC16F505

Open

PIC12F508/509

PIC12F508/509/16F505

DS41236A-page 42 Preliminary  2004 Microchip Technology Inc.

TABLE 7-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR –

PIC12F508/509/16F505(2)

7.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Prepackaged oscillators

provide a wide operating range and better stability. A

well-designed cryst al oscillator will provide go od perfor-

mance with TTL gates. Two types of crystal oscillator

circuits can be used: one with parallel resonance, or

one with series resonance.

Figure 7-3 shows impl ementati on of a paralle l resonant

oscillator circuit. The circuit is designed to use the fun-

dament al frequen cy of the c rystal. The 74AS04 in verter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ potentiome-

ters bias the 74AS04 in the linear region. This circuit

could be used for external oscillator designs.

FIGURE 7-3: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 7-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a 180-

degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

FIGURE 7-4: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

7.2.4 EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device

option offers additiona l cos t sav in gs . The RC oscil lator

frequenc y is a fun ction of the suppl y vo ltage, the resis -

tor (REXT) and capacitor (C EXT) val ues, and th e operat-

ing temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to take into account

variation due to tolerance of external R and C

components used.

Figure 7-5 shows how the R/C combination is con-

nected to the PIC12F508/509/16F505 devices. For

REXT values bel ow 3.0 kΩ, the osci llator operat ion ma y

become unstable, or stop completely. For very high

REXT values (e.g., 1 MΩ), the oscillator becomes

sensitive to noise, humidity and leakage. Thus, we

recommend keeping REXT between 5.0 kΩ and

100 kΩ.

Osc

Type Resonator

Freq Cap.Range

C1 Cap. Range

LP 32 kHz(1) 15 pF 15 pF

XT 200 kHz

1 MHz

4 MHz

47-68 pF

15 pF

47-68 pF

15 pF

HS(3) 20 MHz 15-47 pF 15-47 pF

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

2: These values are for design guidance

only. R s may be required to avoid over-

driv ing crys tal s with lo w drive leve l speci fi-

cation. Since each crystal has its own

characteristics, the user should consult

the crystal manufacturer for appropriate

values of external components.

3: PIC16F5 05 onl y.

20 pF

+5V

20 pF

10k 4.7k

10k

74AS04

XTAL

10k

74AS04

PIC16F505

CLKIN

To Other

Devices

PIC12F508

PIC12F509

330

74AS04 74AS04

PIC16F505

CLKIN

To Other

Devices

XTAL

330

74AS04

0.1 mF PIC12F508

PIC12F509

 2004 Microchip Technology Inc. Preliminary DS41236A-page 43

PIC12F508/509/16F505

Although the oscillator will operate with no external

capacitor (CEXT = 0pF), we recommend using values

above 2 0 pF for noise a nd stability re as ons . W ith no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

Section 10.0 “Electrical Cha racteristic s”, shows R C

frequency variation from part-to-part due to normal

process variation. The variation is larger for larger val-

ues of R (since le akage current variation w ill affect RC

frequenc y more for la rge R) and for sm aller values of C

(since variation of input capacitance will affect RC

frequency more).

Also, see the Electrical Specifications section for

variation of oscillator frequency due to VDD for given

REXT/CEXT values, as well as frequency variation due

to operating temperature for given R, C and VDD

values.

FIGURE 7-5: EXTERNAL RC

OSCILLATOR MODE

7.2.5 INTERNAL 4 MHz RC OSCILLATOR

The inte rnal RC oscillator provides a fi xed 4 MHz (nom-

inal) system clock at VDD = 5V and 25°C, (see

Section 10.0 “Electrical Characteristics” for

information on variation over voltage and temperature).

In addit ion, a ca librati on in structi on is progra mmed into

the last ad dress of me mory, which cont ains the cal ibra-

tion value for the internal RC oscillator. This location is

always uncode protected, regardless of the code-pro-

tect settings. This value is programmed as a MOVLW XX

instruction where XX is the calibration value, and is

placed at th e Re set v ector. This will load the W reg ister

with the calibration value upon Reset and the PC will

then roll over to the users program at address 0x000.

The user th en ha s the option of writi ng the v alu e to th e

OSCCAL Register (05h) or ignoring it.

OSCCAL, when written to with the calibration va lue, will

“trim” the internal oscillator to remove process variation

from the oscil la tor frequ enc y.

For the PIC12F508/509/16F505 devices, only bits

<7:1> of OSCCAL are implemented. Bits CAL6-CAL0

are used for calibration. Adjusting CAL6-CAL0 from

‘0000000’ to ‘1111111’ changes the cloc k speed. See

VDD

REXT

CEXT

VSS

OSC1 Internal

clock

PIC16F505

FOSC/4 OSC2/CLKOUT

PIC12F508

PIC12F509

Note: Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

Note: The 0 bit of OSCCAL is unimplemented

and shoul d be written as 0 when modifying

OSCCAL for compatibility with future

devices.

PIC12F508/509/16F505

DS41236A-page 44 Preliminary  2004 Microchip Technology Inc.

7.3 Reset

The device differentiates between various kinds of

Reset:

• Power-on Reset (POR)

•MCLR

Reset during normal operation

•MCLR

Reset during Sleep

• WDT time-out Reset during normal operation

• WDT time-out Reset during Sleep

• Wake-up from Sleep on pin change

Some registers are not reset in any way, they are

unk nown on POR an d unch anged i n any other R eset .

Most other registers are reset to “Reset state” on

Power-on Reset (POR), MCLR, WDT or Wake-up on

pin change Reset during normal operation. They are

not affected by a WDT Reset during Sleep or MCLR

Reset during Sleep, since these Resets are viewed as

resump tion of normal op erati on . The ex ce pti ons to thi s

are TO, PD and RBWUF/GPWUF bits. They are set or

cleared differently in different Reset situations. These

bits are used in software to determine the nature of

Reset. See Table 7-4 for a full description of Reset

states of all regi ste rs.

7.3.1 EXTERNAL CLOCK IN

For applications where a clock is already available

elsewhere, users may directly drive the PIC12F508/

509/16F505 devices provided that this external clock

source meets the AC/DC timing requirements listed in

Section 7.6 “Watchdog Timer (WDT)”. Figure 7-6

below shows how an external clock circuit should be

configured.

FIGURE 7-6: EXTERNAL CLOCK INPUT

OPERATION

TABLE 7-3: RESET CONDITIONS FOR REGISTERS – PIC12F508/509

Clock From

ext. system PIC16F505

OSC2/CLKOUT/RB4

RB5/OSC1/CLKIN

OSC2/CLKOUT/RB4(1)

Clock From

ext. system

OSC2

GP5/OSC1/CLKIN

GP4/OSC2

PIC12F508

PIC12F509

PIC16F505: EC, HS, XT, LP

PIC12F508/509: XT, LP

Note 1: RB4 is available in EC mode only.

Wake-up On Pin Change

W—qqqq qqqu(1) qqqq qqqu(1)

INDF 00h xxxx xxxx uuuu uuuu

TMR0 01h xxxx xxxx uuuu uuuu

PC 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx q00q quuu(2), (3)

FSR(4) 04h 110x xxxx 11uu uuuu

FSR(5) 04h 111x xxxx 111u uuuu

OSCCAL 05h 1111 111- uuuu uuu-

GPIO 06h --xx xxxx --uu uuuu

OPTION — 1111 1111 1111 1111

TRIS — --11 1111 --11 1111

Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: Bit s <7 :2> o f W register c on t ai n oscillator ca li brat ion v al ues due to MOVLW XX instruction at top of memory .

2: See Table 7-8 for Reset value for specific conditions.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

4: PIC12F5 09 onl y.

5: PIC12F5 08 onl y.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 45

PIC12F508/509/16F505

TABLE 7-4: RESET CONDITIONS FOR REGISTERS – PIC16F505

TABLE 7-5: RESET CONDITION FOR SPECIAL REGISTERS

Wake-up On Pin Change

W—qqqq qqqu(1) qqqq qqqu(1)

INDF 00h xxxx xxxx uuuu uuuu

TMR0 01h xxxx xxxx uuuu uuuu

PC 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx q00q quuu(2), (3)

FSR 04h 110x xxxx 11uu uuuu

OSCCAL 05h 1111 111- uuuu uuu-

PORTB 06h --xx xxxx --uu uuuu

PORTC 07h --xx xxxx --uu uuuu

OPTION — 1111 1111 1111 1111

TRISB — --11 1111 --11 1111

TRISC — --11 1111 --11 1111

Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: Bit s <7:2 > of W regi ster co nta in osc illat or cali bration value s due to MOVLW XX instr uct ion at to p of me mo ry.

2: See Table 7-8 for Reset value for specific conditions.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

STATUS Addr: 03h PCL Addr: 02h

Power-on Reset 0001 1xxx 1111 1111

MCLR Reset during normal operation 000u uuuu 1111 1111

MCLR Reset during Sleep 0001 0uuu 1111 1111

WDT Reset during Sleep 0000 0uuu 1111 1111

WDT Reset normal operation 0000 uuuu 1111 1111

Wake-up from Sleep on pin change 1001 0uuu 1111 1111

Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’.

PIC12F508/509/16F505
DS41236A-page 46 Preliminary  2004 Microchip Technology Inc.
7.3.2 MCLR ENABLE
This configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR func tion is tied to the internal
VDD and the pin is assigned to be a I/O. See Figure 7-7.
FIGURE 7-7: MCL R SE L ECT
7.4 Power-on Reset (POR)
The PIC12F508/509/16F505 devices incorporate an
on-chip Power-on Reset (POR) circuitry, which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the (GP3/RB3)/MCLR/VPP pin as MCLR and tie
through a resistor to VDD, or program the pin as (GP3/
RB3). An internal weak pull-up resistor is implemented
using a transistor (refer to Table 10-2 for the pull-up
resisto r ranges). This will eli minate external RC compo-
nents usually needed to create a Power-on Reset. A
maximum rise time for VDD is specified. See
Section 10.0 “Electrical Characteristics” for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, fre quency, tem pera ture ,...)  m ust  be met to en su re
operation. If  these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 7-8. 
The Power-on Reset circuit and the Device Reset
Timer (see Section 7.5 “Device Reset  Timer (DRT)” )
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out  period, w hich is typic ally 18 ms, it wi ll reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low i s show n
in Figu re 7-9.  VDD is allowe d to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goes high.
In Figure 7-10, the on-chip Power-on Reset feature is
being use d (MCLR a nd V DD are tied together or the pin
is programmed to be (GP3/RB3). The VDD is stable
before the S tart-up timer times out and there is no prob-
lem in getting a proper Reset. However, Figure 7-11
depict s a pro ble m situ ation whe re VDD rises too slowly.
The time be tw ee n when the DR T senses  tha t MCLR  is
high and when MCLR and VDD actually reach their full
value, is too long. In this situation, when the start-up
timer times out, VDD has not reached the VDD (min)
value a nd  the chip may n ot function corre ct ly. For suc h
situations, we recommend that external RC circuits be
used to ac hieve  longer POR  delay ti mes (Fig ure 7-10).
For additional information, refer to Application Notes
AN522  “Power-Up Considerations” (DS00522) and
AN607 “Power-up Trouble Shooting” (DS00607).
(GP3/RB3)/MCLR/VPP
MCLRE Int ernal MCLR
GPWU/RBWU
Note: When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 47

PIC12F508/509/16F505

FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)

FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RI SE

TIME

VDD

(GP3/RB3)/MCLR/VPP

Power-up

Detect POR (Pow e r- on Reset)

WDT Reset CHIP Reset

MCLRE

Wake-up on pin Change Reset

Start-up Timer

(10 µs or 18 ms)

WDT Time-out

Pin Change

Sleep

MCLR Reset

VDD

MCLR

Internal POR

DRT T ime-out

Internal Reset

TDRT

VDD

MCLR

Internal POR

DRT Time-out

Internal Reset

TDRT

PIC12F508/509/16F505

DS41236A-page 48 Preliminary  2004 Microchip Technology Inc.

FIGURE 7-11: T IME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

VDD

MCLR

Internal POR

DRT Time-out

Internal Reset

TDRT

Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final

value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 49

PIC12F508/509/16F505

7.5 Device Reset Timer (DRT)

On the PIC1 2F5 08 /509 /16 F505 devices, t he D RT runs

any time the device is powered up. DRT runs from

Reset and varies based on oscillator selection and

Reset type (see Table 7-6).

The DRT operates on an internal RC oscillator. The

process or is kept in Reset as long as the DR T is active.

The DR T del ay allo w s VDD to rise above VDD min. and

for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic resona-

tors require a certain time after power-up to establish a

stable osci llation. The on-chip DR T keeps the devic es in

a Reset condition for approximately 18 ms after MC LR

has reached a logic high (VIH MCLR) level.

Programming (GP3/RB3)/MCLR/VPP as MCLR and

using an external RC network connected to the MCLR

input is not required in most cases. This allows savings

in cost-sensitive and/or sp ace res tricted applications, as

well as allowing the use of the (GP3/RB3)/MCLR/VPP

pin as a general purpose input.

The Device Reset Time delays will vary from chip-to-

chip due to VDD, temperature and process variation.

See AC parameters for details.

The D RT w ill also be tri ggered upon a Watchd og Timer

time-out from Sleep. This is particularly important for

applications using the WDT to wake from Sleep mode

automatically.

Reset sources are POR, MCLR, WDT time-out and

wake-up on pin change. See Section 7.9.2 “Wake-up

from Sleep”, Notes 1, 2 and 3.

7.6 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator, which does not require any external

components. This RC oscillator is separate from the

external RC oscillator of the (GP5/RB5)/OSC1/CLKIN

pin and the internal 4 MHz oscillator. This means that

the WDT will run even if the main processor clock has

been stopped, for example, by execution of a SLEEP

instruction. During normal operation or Sleep, a WDT

Reset or wake-up Reset, generates a device Reset.

The TO bit (Status<4>) will be cleared upon a

Watchdog Timer Reset.

The WDT can be permanently disabled by program-

ming the configuration WDTE as a ‘0’ (see Section 7.1

“Configuration Bits”). Refer to the PIC12F508/509/

16F505 Prog ram mi ng Spe ci fic ati ons to de termine how

to access the configuration word.

TABLE 7-6: DRT (DEVICE RESET TIMER

PERIOD)

7.6.1 WDT PERIOD

The WDT has a nomin al time-out perio d of 18 ms, (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by

writing to the O ption regi ster . Th us, a tim e-out period of

a nominal 2.3 seconds can be realized. These periods

vary with temperature, VDD and part-to-part process

variations (see DC specs).

Under w orst c ase co ndi tions (V DD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

7.6.2 WDT PROGRAMMING

CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

post scaler , if as signed to the WDT, and preven ts it from

timing out and generating a device Reset.

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum Sleep time before a WDT wake-up Reset.

Oscillator

Configuration POR Reset Subsequent

Resets

INTOSC, EXTRC 18 ms (typical) 10 µs (typical)

HS(1), XT, LP 18 ms (typical) 18 ms (typical)

EC(1) 18 ms (typical) 10 µs (typical)

Note 1: PIC16F505 only.

PIC12F508/509/16F505

DS41236A-page 50 Preliminary  2004 Microchip Technology Inc.

FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 7-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-On

Reset

Value on

All Other

Resets

N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: Shaded boxes = Not used by Wa tchdog Timer. — = unimplemented, read as ‘0’, u = unchanged.

Note 1: PIC12F508/509 only.

2: PIC16F505 only.

(Figure 6-5)

Postscaler

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the Option register .

WDT Time-out

Watchdog

Time

From Timer0 Clock Source

WDT Ena ble

Configuration

Bit

PSA

Postscaler

8-to-1 MUX PS<2:0>

(Figure 6-4)

To Timer0

PSA

MUX

 2004 Microchip Technology Inc. Preliminary DS41236A-page 51

PIC12F508/509/16F505

7.7 Time-out Sequence, Power-down

and Wake-up from Sleep Status

Bits (TO, PD, GPWUF/RBWUF)

The TO, PD and (GPWUF/RBWUF) bits in the Status

has been caused by a Power-up condition, a MCLR or

Watchdog Timer (WDT) Reset.

TABLE 7-8: TO/PD/(GPWUF/RBWUF)

STATUS AFTER RESET

7.8 Reset on Brown-out

A Brown-out is a condition where device power (VDD)

dips below it s minimum value, but no t to zero, an d then

recovers. The device should be reset in the event of a

Brown-out.

To reset PIC12F508/509/16F505 devices when a

Brown-out occurs, external Brown-out protection

circuits may be built, as shown in Figure 7-13 and

Figure 7-14.

FIGURE 7-13: BROW N-OUT

PROTECTION CIRCUIT 1

FIGURE 7-14: BROWN-OUT

PROTECTION CIRCUIT 2

FIGURE 7-15: BROWN-OUT

PROTECTION CIRCUIT 3

GPWUF/

RBWUF TO PD Reset Caused By

000WDT w ake-up from Sl eep

00uWDT time-out (not from

Sleep)

010MCLR wake-up from Sleep

011Power-up

0uuMCLR not during Sleep

110Wake-up from Sleep on pin

change

Legend: u = unchanged

Note 1: The TO, PD and GPWUF/RBWUF bits

maintain their status (u) until a Reset

occurs. A low-pulse on the MCLR input

does not change the TO, PD and

GPWUF/RBWUF status bits.

Note 1: This circuit will activate Reset when VDD goes

below Vz + 0.7V (where Vz = Zener voltage).

2: Pin must be confirmed as MCLR.

33k

10k

40k(1)

VDD

MCLR(2)

PIC16F505

VDD

Q1 PIC12F508

PIC12F509

Note 1: This brown-out circuit is less expensive,

although less accurate. Tr ansistor Q1 turns

off when VDD is below a certain level such

that:

2: Pin must be confirmed as MCLR.

VDD • R1

R1 + R2 = 0.7V

R2 40k(1)

VDD

MCLR(2)

PIC16F505

VDD

PIC12F508

PIC12F509

Note: This Brown-out Protection circuit em ploys

Microchip Technology’s MCP809 micro-

controller supervisor. There are 7 different

trip point selections to accommodate 5V to

3V systems.

MCLR

PIC16F505

VDD

VSS

RST

MCP809

VDD

Bypass

Capacitor

PIC12F508

PIC12F509

PIC12F508/509/16F505

DS41236A-page 52 Preliminary  2004 Microchip Technology Inc.

7.9 Power-down Mode (Sleep)

A device may be powered down (Sleep) and later

powered up (wake-up from Sleep).

7.9.1 SLEEP

The Power-down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keep s runnin g, the T O bit (S t atus< 4>) is set, the PD bit

(S ta tus<3>) is cle ared and the os cillator driver is turned

off. The I/O ports maintain the status they had before

the SLEEP instruction was executed (driving high,

driving low or high-impedance).

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

(GP3/RB3)/MCLR/VPP pin must be at a logic high

level if MCLR is ena bled.

7.9.2 WAKE-UP FR OM SLEEP

The device can wake-up from Sleep through one of

the following events:

1. An external reset input on (GP3/RB3)/MCLR/VPP

pin, when configured as MCL R.

2. A Watchdog Timer time-out Reset (if WDT was

enabled).

3. A change on input pin GP0/RB0, GP1/RB1,

GP3/RB3 or RB4 when wake-up on change is

enabled.

These events cause a device Reset. The TO, PD and

GPWUF/RBWUF bits can be used to determine the

cause of de vi ce Rese t . T he TO bit is cleared if a WDT

time-out occurred (and caused wake-up). The PD bit,

which is set on power-up, is cleared when SLEEP is

invoked. The GPWUF/RBWUF bit indicates a change

in state while in Sleep at pins GP0/RB0, GP1/RB1,

GP3/RB3 or RB4 (since the last file or bit operation on

GP/RB port).

The WDT is cleared when the device wakes from

Sleep, regardless of the wake-up source.

7.10 Program Verification/Code

Protection

If the cod e protection bit has not been programmed, the

on-chip program memory can be read out for

verification purposes.

The first 64 locations and the last location (OSCCAL)

can be read, regardless of the code protection bit

setting.

The last m emory locatio n can be read regardl ess of the

code protection bit setting on the PIC12F508/509/

16F505 devices.

7.11 ID Locations

Four memory locations are designated as ID locations

where the user can store checksum or other code

identification numbers. These locations are not

accessible during normal execution, but are readable

and writ ab le duri ng prog ram /v erify.

Use on ly the lower 4 bits o f the ID locati ons and al ways

program the upper 8 bits as ‘0’s.

7.12 In-Circuit Serial Programming™

The PIC12F508/509/16F505 microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock and data,

and three other lines for power, ground and the

programming voltage. This allows customers to manu-

facture boards with unprogrammed devices and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware, or

a custom firmw are, to be pro grammed.

The devices are placed into a Program/Verify mode by

holding the GP1/RB1 and GP0/RB0 pins low while rais-

ing the MC LR (VPP) pin from VIL to VIHH (see program-

ming specification). GP1/RB1 becomes the

programming clock and GP0/RB0 becomes the

programming data. Both GP1/RB1 and GP0/RB0 are

Schmitt Trigger inputs in this mode.

After Reset, a 6-bit command is then supplied to the

device. D ependi ng on the co mmand , 14 bits of program

data are then supplied to or from the device, depending

if the command was a Load or a Read. For complete

details of serial programming, please refer to the

PIC12F508/509/16F505 Programming Spec ification s.

A typical In-Circuit Serial Programming connection is

shown in Figure 7-16.

Note: A Reset generated by a WDT time-out

does not drive the MCLR pin low.

Note: Caution: Right before entering Sleep,

read the input pins. When in Sleep, wake

up occurs when the values at the pins

change from the state they were in at the

last reading. If a wake-up on change

occurs and the pins are not read before re-

entering Sleep, a wake-up will occur

immediately even if no pins change while

in Sleep mode.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 53

PIC12F508/509/16F505

FIGURE 7-16: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16F505

VDD

VSS

MCLR/VPP

GP1/RB1

GP0/RB0

+5V

VPP

CLK

Data I/O

VDD

PIC12F508

PIC12F509

PIC12F508/509/16F505

DS41236A-page 54 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS41236A-page 55

PIC12F508/509/16F505

8.0 INSTRUCTION SET SUMMARY

The PIC16 instruction set is highly orthogonal and is

comprised of three basic categories.

•Byte-oriented operations

•Bit-oriented operations

•Literal and cont rol operations

Each PIC16 instruction is a 12-bit word divided into an

opcode, which specifies the instruction type, and one

or mor e operands which further specify the operation

of the instruction. The formats for each of the catego-

ries is presented in Figure 8-1, while the various

opcode fields are su mmarized in Table 8-1.

For byte-oriented instru ctions, ‘f’ represents a file reg-

ister designator and ‘d’ represents a destination desig-

nator. The file register designator specifies which file

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is ‘0’, the result is

placed in the W reg is ter. If ‘d’ is ‘1’, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

design ator which sel ects the numb er o f the bit affe cte d

by the operation, while ‘f’ represent s the number of the

file in which the bit is located.

For literal and control operations, ‘k’ represents an

8 or 9-bit constant or literal value.

TABLE 8-1: OPCODE FIELD

DESCRIPTIONS

All instructions are executed within a single instruction

cycle, unless a conditional test is true or the program

counter is changed as a result of an instruction. In this

case, the execution takes two instruction cycles. One

instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

inst ruction ex ecution ti me is 1 µs. If a c onditiona l test is

true or the program count er is changed as a result of an

instruction, the instruction execution time is 2 µs.

Figure 8-1 shows the three general formats that the

instructions can have. All examples in the figure use

the following format to represent a hexadecimal

number:

0xhhh

wher e ‘h’ signifies a hex adecimal digit.

FIGURE 8-1: GENERAL FORMAT FOR

INSTRUCTIONS

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (a ccumulator)

bBit address wi thin an 8-b i t file regi ster

kLiteral field, constant data or label

xDon’t care locat i on (= 0 or 1)

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

dDestination select;

d = 0 (sto re resu l t in W)

d = 1 (store result in file register ‘f’)

Default is d = 1

label Label name

TOS Top-of-Stack

PC Progra m Counter

WDT Watchdog Timer counter

TO Time-out bit

PD Power-down bit

dest Destination, either the W register or the specified

[ ] Options

( ) Contents

→Assigned to

< > Register bit field

∈In the set of

italics User defined term (font is courier)

Byte-orie nted file register operations

11 6 5 4 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 5-bit file register address

Bit-oriented file register operati ons

11 8 7 5 4 0

OP C O DE b (BIT #) f ( F IL E #)

b = 3-bit bit address

f = 5-bit file register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations – GOTO instruction

11 9 8 0

OPCODE k (l i te ra l )

k = 9-bit immediate value

PIC12F508/509/16F505

DS41236A-page 56 Preliminary  2004 Microchip Technology Inc.

TABLE 8-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands Description Cycles 12-Bit Opcode Status

Affected Notes

MSb LSb

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

–

f, d

–

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Incr eme nt f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

Exclusive OR W with f

1(2)

0001

0000

0010

0000

0010

0011

0001

0010

0000

0011

0000

0011

0001

11df

01df

011f

0100

01df

11df

10df

11df

00df

001f

0000

01df

00df

10df

ffff

0000

ffff

0000

ffff

C, DC, Z

None

C, DC, Z

None

1, 2, 4

2, 4

1, 4

2, 4

1, 2, 4

2, 4

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1(2)

0100

0101

0110

0111

bbbf

ffff

None

2, 4

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

XORLW

–

AND literal with W

Call Subro uti ne

Clear Watchdog Timer

Unconditional branch

Inclusive OR literal with W

Move literal to W

Load Option register

Return, place literal in W

Go into Standby mode

Load TRIS register

Exclusive OR literal to W

1110

1001

0000

101k

1101

1100

0000

1000

0000

1111

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

0100

kkkk

0010

kkkk

0011

0fff

kkkk

None

TO, PD

None

TO, PD

None

Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for

GOTO. See Section 4.7 “Program Counter”.

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that

value pres ent on the pi ns thems elves. For ex ample , if the dat a latch is ‘1’ for a pi n co nfig ure d as input an d

is driven low by an external device, the data will be written back with a ‘0’.

3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state

latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler wi ll be

cleared (if assigned to TMR0).

 2004 Microchip Technology Inc. Preliminary DS41236A-page 57

PIC12F508/509/16F505

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) + (f) → (dest)

Status Affected: C, DC, Z

Description: Add the contents of the W register

and register ‘f’. If ‘d’ is’0’, the result

is stored in the W register. If ‘d’ is

‘1’, the resu lt is sto r ed bac k in

ANDLW AND literal with W

Syntax: [ label ] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W).AND. (k) → (W)

Status Affected: Z

Description: The contents of the W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) .AND. (f) → (dest)

Status Affected: Z

Description: The contents of the W register are

AND’ed with register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W register .

If ‘d’ is ‘1’, the result is stored back

in register ‘f’.

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affected: None

Description: Bit ‘b’ in register ‘f’ is cleared.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affected: None

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Descr iption : If bit ‘b’ in register ‘ f’ is ‘0’, then the

next instruction is skipped.

If bit ‘b’ is ‘0’, the n the nex t ins truc -

tion fetched during the current

instruction execution is discarded,

and a NOP is executed instead,

making this a 2-cycle instruction.

PIC12F508/509/16F505

DS41236A-page 58 Preliminary  2004 Microchip Technology Inc.

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Desc ription : If bit ‘b’ i n regis ter ‘f’ is ‘ 1’, the n the

next instruction is skipped.

If bit ‘b’ is ‘1’, then the nex t ins tru c-

tion fetched during the current

instruction execution, is discarded

and a NOP is executed instea d,

making this a 2-cycle instruction.

CALL Subroutine Call

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 255

Operation: (PC) + 1→ Top-of-Stack;

k → PC<7:0>;

(S tatus<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected: None

Description: Subroutine call. First, return

address (PC + 1) is pushed onto

the stack. The eight-bit immediate

address is loaded into PC

bits <7:0>. The upper bits

PC<10:9> are loaded from

Status<6:5>, PC<8> is cleared.

CALL is a two-cycle instruction.

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0 ≤ f ≤ 31

Operation: 00h → (f);

1 → Z

Status Affected: Z

Description: The contents of register ‘f’ are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W);

1 → Z

Status Affected: Z

Description: The W register is cleared. Zero bit

(Z) is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT;

0 → WDT prescaler (if assigned);

1 → TO;

1 → PD

Status Affected: TO, PD

Description: The CLRWDT instruction resets the

WDT. It also reset s the prescal er , if

the prescaler is assigned to the

WDT and not Timer0. Status bits

TO and PD are set.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in the W register . If

‘d’ is ‘1’, th e result is stored back in

 2004 Microchip Technology Inc. Preliminary DS41236A-page 59

PIC12F508/509/16F505

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) – 1 → (dest)

Status Affected: Z

Description: Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

stored back in register ‘f’.

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) – 1 → d; skip if resu lt = 0

Status Affected: None

Description: The contents of register ‘f’ are

decr emente d. If ‘d’ is ‘0’, the res ult

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘0’, the next instruc-

tion, which is already fetched, is

discarded and a NOP is executed

instead making it a two-cycle

instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 511

Operation: k → PC<8:0>;

Status<6:5> → PC<10:9>

Status Affected: None

Description: GOTO is an unconditi onal bran ch .

The 9-bit immediate value is

loaded into PC bits <8:0>. The

upper bits of PC are loaded from

Status<6:5>. GOTO is a two-cycle

instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) + 1 → (dest)

Status Affected: Z

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) + 1 → (dest), skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘0’, then the next

instruction, which is already

fetched, is discarded and a NOP is

executed instead maki ng it a

two-cycle instruction.

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. (k) → (W)

Status Affected: Z

Descripti on: The content s of the W register are

OR’ed with the eight bit literal ‘k’.

The result is placed in the

W register.

PIC12F508/509/16F505

DS41236A-page 60 Preliminary  2004 Microchip Technology Inc.

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W).OR. (f) → (dest)

Status Affected: Z

Description: Inclusive OR the W register with

placed in the W re gister. If ‘d’ is ‘1’,

the result is placed back in registe r

‘f’.

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Description: The contents of register ‘f’ are

moved to destina tion ‘d’. If ‘d ’ is ‘0’,

destination is the W register. If ‘d’

is ‘1’, the des tin ati on is fil e

test of a file register, since status

flag Z is affected.

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Description: The eight-bit literal ‘k’ is loaded

into the W register . The don’t cares

will assembled as ‘0’s.

MOVWF Mov e W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 31

Operation: (W) → (f)

Status Affected: None

Description: Move data from the W register to

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operati on: No operati on

Status Affected: None

Descr ipti on : No ope rati on.

OPTION Load Option Register

Syntax: [ label ] Option

Operands: None

Operation: (W) → Option

Status Affected: None

Description: The content of the W register is

loaded into the Option register.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 61

PIC12F508/509/16F505

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Description: The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return ad dress). This

is a two-cycle instruction.

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag . If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is stored bac k in reg-

ister ‘f’.

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag . If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

Cregister ‘f’

SLEEP Enter SLEEP Mode

Syntax: [label ]SLEEP

Operands: None

Operation: 00h → WDT;

0 → WDT prescaler;

1 → TO;

0 → PD

Status Affected: TO, PD, RBWUF

Description: Time-out S tat us bit (TO) is set. The

Power-dow n Status bit (PD) is

cleared.

RBWUF is unaffected.

The WDT and its prescaler are

cleared.

The proce sso r is pu t in to Sleep

mode wit h the osci llato r st op ped .

See Section 7.9 “Power-down

Mode (Sleep)” on Sleep for more

details.

SUBWF Subtract W from f

Syntax: [label ] SUBWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operati on: (f) – (W) → (dest)

Status Affected: C, DC, Z

Descr iption : Subtract (2’s complemen t method )

the W reg ister fr om regist er ‘f’. If ‘d’

is ‘0’, the result is stored in the W

stored back in register ‘f’.

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected: None

Description: The upper and lower nibbles of

‘0’, the result is placed in W

placed in regi ste r ‘f’.

PIC12F508/509/16F505

DS41236A-page 62 Preliminary  2004 Microchip Technology Inc.

TRIS Load TRIS Register

Syntax: [ label ] TRIS f

Operand s: f = 6

Operation: (W) → TRIS register f

Status Affected: None

Description: TRIS register ‘f’ (f = 6 or 7) is

loaded wi th the co nten t s of the W

XORLW Exclusive OR literal with W

Syntax: [label ]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Description: The contents of the W register are

XOR’ed w ith the eight- bit lite ral ‘k ’.

The result is placed in the W

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Status Affected: Z

Description: Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

stored back in register ‘f’.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 63

PIC12F508/509/16F505

9.0 DEV ELOP ME NT SUPPORT

The PICmicro® microcontrollers are supported with a

full ran ge of hardware a nd softwa re develo pment to ols:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C17 and MPLAB C18 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB C30 C Compiler

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

- MPLAB dsPIC30 Software Simulator

•Emulators

- MPLAB ICE 2000 In -Circuit Emulator

- MPLAB ICE 4000 In -Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mmers

-PRO MATE

® II Universal Device Progr a mm er

- PICSTART® Plus Development Programmer

• Low Cost Demons tration Boards

- PICDEMTM 1 Demonstration Board

- PICDEM.netTM De monstration Board

- PICDEM 2 Plus Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 4 Demonstration Board

- PICDEM 17 Demonstration Board

- PICDEM 18R Demonstration Board

- PICDEM L IN Demo nstration Board

- PICDEM USB Demonstration Board

• Evaluation Kits

-K

EELOQ®

- P ICDEM MSC

-microID

-CAN

- PowerSmart®

-Analog

9.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

based application that contains:

• An interface to deb ugging tools

- simulator

- programmer (sold separately)

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor with color coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High level source code debugging

• Mouse over variable inspection

• Exten si ve on-l in e help

The MPLAB IDE allows you to :

• Edit your sour ce files (either assemb ly or C)

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- source files (as sembl y or C)

- absolute listing file (mixed assembly and C)

- machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost effective

simulators, through low cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve whe n upgrading to tools with increasin g flexibi lity

and power.

9.2 MPASM Assembler

The MPASM assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

The MPASM assembler generates relocatable object

files for the MPLINK object linker, Intel® standard HEX

files, M AP files to detail memory u sage and symbol re f-

erence, a bsolute LST files that contain source lines and

generated machine code and COFF files for

debugging.

The MPASM assembler features include:

• Integration into MPLAB IDE projects

• User de fined m acros to strea mline asse mbly cod e

• Condit ion al as sem bl y for mult i-p urpo se sourc e

files

• Directi ves that allow complete control over the

assembly p rocess

PIC12F508/509/16F505

DS41236A-page 64 Preliminary  2004 Microchip Technology Inc.

9.3 MPLAB C17 and MPLAB C18

C Compilers

The MPLAB C17 and MPLAB C18 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

9.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can link

relocatable objects from pre-compiled libraries, using

directives from a linker script.

The MPLIB object librarian manages the creation and

modific ation of li brary fil es of pre-co mpiled c ode. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement , deletion and extr action

9.5 MPLAB C30 C Compiler

The MPLAB C30 C compiler is a full-featured, ANSI

compliant, optimizing compiler that translates standard

ANSI C programs into dsPIC30F assembly language

source. The compiler also supports many command-

line options and language extensions to take full

adv antage of the dsPIC 30F dev ice ha rdwar e capab ili-

ties, and afford fine control of the compiler code

generator.

MPLAB C30 is distributed with a complete ANSI C

standard library. All library functions have been vali-

dated an d c on form to the ANSI C li brary standard. The

library includes functions for string manipulation,

dynamic memory allocation, data conversion, time-

keeping, and math functions (trigonometric, exponen-

tial and hyperbolic). The compiler provides symbolic

information for high level source debugging with the

MPLAB IDE.

9.6 MPLAB ASM30 Assembler , Linker,

and Librarian

MPLAB ASM30 assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 compiler uses the

assembler to produce it’s object file. The assembler

generates relocatable object files that can then be

archived or lin ked with other relocatable object files and

arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatib ility

9.7 MPLAB SIM Software Simulator

The MPLAB SIM sof tware simulat or allows code deve l-

opment in a PC hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or use r de fined key p ress, to any pin. The exec u-

tion can be performed in Single-Step, Execute Until

Break, or Trace mode.

The MPLAB SIM simulator fully supports symbolic

debugging using the MPLAB C17 and MPLAB C18

C Compilers, as well as the MPASM assembler. The

software simulator offers the flexibility to develop and

debug code outside of the laboratory environment,

making it an excellent, economical software

development tool.

9.8 MPLAB SIM30 Software Simulator

The MPLAB SIM30 software simulator allows code

develop ment in a PC hosted en vironment by simulating

the dsPIC30F series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any of the pins.

The MPLAB SIM30 simulator fully supports symbolic

debugging using the MPLAB C30 C Compiler and

MPLAB ASM30 assembler . The simulator runs in either

a Command Line mode for automated tasks, or from

MPLAB IDE. This high speed simulator is designed to

debug, analyze and optimize time intensive DSP

routines.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 65

PIC12F508/509/16F505

9.9 MPLAB ICE 2000

High Performance Universal

In-Circui t Emu lator

The MPLAB ICE 2000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers. Software control of the

MPLAB ICE 2000 in-circuit emulator is advanced by

the MPLAB Integrated Development Environment,

which all ows ed iting, b uildin g, do wnlo ading and sourc e

debuggi ng from a singl e envi ronm en t.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

featur es. Interchangea ble processo r modules al low the

system to be easi ly reconfi gured for emula tion of d iffer-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

9.10 MPLAB ICE 4000

High Performance Universal

In-Circui t Emu lator

The MPLAB ICE 4000 universal in-circuit emulator is

intended to provide the product development engineer

with a co mplete micro controller de sign tool se t for high-

end PICm icro microcontrollers. Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debuggi ng from a singl e envi ronm en t.

The MPLAB ICD 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanc ed emulator fe atures inc lude complex t riggering

and timing, up to 2 Mb of emulation memory, and the

ability to view variables in real-time.

The MPLAB ICE 4000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Micro soft W indow s 32- bit op erat ing sy stem were c ho-

sen to best make t hes e fe atur es av ail able i n a si mple ,

unified application.

9.11 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low cost, run-time development tool,

connec ting to the h ost PC via an R S-232 or hig h speed

USB interface. This tool is based on the FLASH

PICmicro MCUs and can be used to develop for these

and other PICmicro microcontrollers. The MPLAB

ICD 2 utilizes the in-circuit debugging capability built

into the FLASH devices. This feature, along with

Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)

protocol, offers cost effective in-circuit FLASH debug-

ging from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by setting

breakpoints, single-stepping and watching variables,

CPU status and peripheral registers. Running at full

speed enables testing hardware and applications in

real-tim e. MPLAB ICD 2 also serves as a devel opment

programmer for selected PICmicro devices.

9.12 PRO MATE II Universal Device

Programmer

The PRO MATE II is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maxi mum reli abili ty. It features

an LCD display for instructions and error messages

and a modular detachable socket assembly to support

various package types. In Stand-Alone mode, the

PRO MATE II d ev ic e p rogra mmer ca n re ad, verify, and

program PICmicro devices without a PC connection. It

can also set code protection in this mode.

9.13 PICSTART Plus Development

Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient. The

PICSTART Plus development programmer supports

most PICmicro devices up to 40 pins. Larger pin count

devices, such as the PIC16C92X and PIC17C76X,

may be supported with an adapter socket. The

PICSTART Plus development programmer is CE

compliant.

PIC12F508/509/16F505

DS41236A-page 66 Preliminary  2004 Microchip Technology Inc.

9.14 PICDEM 1 PICmicro

Demonstration Board

The PICDEM 1 demo nstrat ion boa rd demo nstrate s the

capabilities of the PIC16C5X (PIC16C54 to

PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,

PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All

necessary hardware and software is included to run

basic demo programs. The sample microcontrollers

provi d ed wi t h the P IC DE M 1 de mo ns t rat i on b oar d c an

be pro gramme d with a PRO MATE II devic e progra m-

mer, or a PICSTART Plus development programmer.

The PICDE M 1 demonstrati on board can be conne cted

to the MPLAB ICE i n-circ uit emulato r for testi ng. A pro-

totype area extends the circuitry for additional applica-

tion components. Features include an RS-232

interface, a potentiometer for simulated analog input,

push button switches and eight LEDs.

9.15 PICDEM.net Internet/Ethernet

Demonstration Board

The PICDEM.net demonstration board is an Internet/

Ethernet demonstration board using the PIC18F452

microcontroller and TCP/IP firmware. The board

supports any 40-pin DIP device that conforms to the

standard pinout used by the PIC16F877 or

PIC18C452. This kit features a user friendly TCP/IP

stack, web server with HTML, a 24L256 Serial

EEPROM for Xmodem download to web pages into

Serial EEPROM, ICSP/MPLAB ICD 2 interface con-

nector, an Ethernet interface, RS-232 interface, and a

16 x 2 LCD display. Also included is the book and

CD-ROM “TCP/IP Lean, Web Servers for Embedded

Systems,” by J eremy Ben tham.

9.16 PICDEM 2 Plus

Demonstration Board

The PICDEM 2 Plus demonstration board supports

many 18-, 28-, and 40-pin microcontrollers, including

PIC16F87X and PIC18FXX2 devices. All the neces-

sary ha rdware and s oftware is included to run the dem -

onstration programs. The sample microcontrollers

provi d ed wi t h the P IC DE M 2 de mo ns t rat i on b oar d c an

be pro gramme d with a PRO MATE II devic e progra m-

mer, PICSTART Plus development programmer, or

MPLAB ICD 2 with a Universal Programmer Adapter.

The MPLAB I CD 2 and MPLAB I CE in-circuit emul ators

may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area extends the

circuitry for additional application components. Some

of the features include an RS-232 interface, a 2 x 16

LCD display , a piezo speaker , an on-board temperature

sensor, four LEDs, and sample PIC18F452 and

PIC16F8 77 FLASH microc on trol lers .

9.17 PICDEM 3 PIC16C92X

Demonstration Board

The PICDEM 3 demonstration board supports the

PIC16C923 and PIC16C924 in the PLCC package. All

the necessary hardware and softwa re is included to run

the demonstration programs.

9.18 PICDEM 4 8/14/18-Pin

Demonstration Board

The PICDEM 4 can be used to demonstrate the capa-

bilities of the 8-, 14-, and 18-pin PIC16XXXX and

PIC18XXXX MCUs, including the PIC16F818/819,

PIC16F8 7/88, PIC16 F62 XA and th e PIC18 F132 0 fam -

ily of microcontrollers. PICDEM 4 is intended to show-

case the many features of these low pin count parts,

including LIN and Motor Control using ECCP. Special

provisions are made for low power operation with the

supercapacitor circuit, and jumpers allow on-board

hardware to be disabled to eliminate current draw in

this mode. Included on the demo board are provisions

for Crystal, RC or Canned Oscillator modes, a five volt

regulato r for use with a ni ne volt wall ad apter or battery,

DB-9 RS-232 interface, ICD connector for program-

ming via ICSP and development with MPLAB ICD 2,

2x16 liquid crystal display, PC B footprints for H-Bridge

motor driver, LIN transceiver and EEPROM. Also

included are: header for expansion, eight LEDs, four

potentiometers, three push buttons and a prototyping

area. Included with the kit is a PIC16F627A and a

PIC18F1320. Tutorial firmware is included along with

the User’s Guide.

9.19 PICDEM 17 Demonstration Board

The P ICDEM 17 de mo ns t rat i on bo a rd is an ev al u at i on

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. A pro-

grammed sample i s included. T he PRO MA TE II device

programmer, or the PICSTART Plus development pro-

grammer, can b e used to repro gram the d evice f or user

tailored application development. The PICDEM 17

demonstration board supports program download and

execution from external on-board FLASH memory. A

generous proto typ e area is av ailab le for user hardw are

expansion.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 67

PIC12F508/509/16F505

9.20 PICDEM 18R PIC18C601/801

Demonstration Board

The PICDEM 18R demonstration board serves to assist

development of the PIC18C601/801 family of Microchip

microcontrollers. It provides hardware implementation

of both 8-bit Multiplexed/De-multiplexed and 16-bit

Memory modes. The board includes 2 Mb external

FLASH memory and 128 Kb SRAM memory , as well as

serial EEPROM, allowing access to the wide range of

memory types supported by the PIC18C601/801.

9.21 PICDEM LIN PIC16C43X

Demonstration Board

The pow erfu l LI N hard w are a nd s of tw are kit includes a

series of boards and three PICmicro microcontrollers.

The small footprint PIC16C432 and PIC16C433 are

used as slaves in the LIN communication and feature

on-board LIN transceivers. A PIC16F874 FLASH

microcontroller serves as the master. All three micro-

controllers are programmed with firmware to provide

LIN b us communication.

9.22 PICkitTM 1 Flash Starter Kit

A complete “development system in a box”, the PICkit

FLASH Starter Kit includes a convenient multi-section

board for programming, evaluation, and development

of 8/14-pi n FLAS H PI C® microc ontro ll ers . Pow ere d vi a

USB, the board operates un der a simple Windows GUI.

The PICkit 1 Starter Kit includes the user’s guide (on

CD ROM), PICkit 1 tutorial softw are and code for vari-

ous applications. Als o inc lu ded are MPLAB® IDE (Inte-

grated Development Environment) software, software

and hardware “Tips ‘n Tricks for 8-pin FLASH PIC®

Microcontrollers” Handbook and a USB Interface

Cable. Supports all current 8/14-pin FLASH PIC

microcontrollers, as well as many future planned

devices.

9.23 PICDEM USB PIC16C7X5

Demonstration Board

The PICDEM U SB Demo ns trati on Board sho w s o f f th e

capabilities of the PIC16C745 and PIC16C765 USB

microcontrollers. This board provides the basis for

future USB products.

9.24 Evaluation and

Programming Tools

In additio n to the PICDEM seri es of circuits, Microchip

has a line of evaluation kits and demonstration software

for the se products.

•K

EELOQ evaluation and prog ram mi ng too ls for

Microchip’s HCS Secure Data Products

• CAN developers kit for automotive network

applications

• Analog design boards and filter design software

• PowerS mart battery charging evaluation/

calibration kits

•IrDA

® development kit

• microID development and rfLabTM development

software

• SEEVAL® designer kit for memory ev al uat ion an d

endurance calculations

• PICDEM MSC demo boards for Switching mode

power supply, high power IR driver, delta sigma

ADC, and flow rate sensor

Check the Microchip web page and the latest Product

Line Card for the complete list of demonstration and

evaluation kits.

PIC12F508/509/16F505

DS41236A-page 68 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS41236A-page 69

PIC12F508/509/16F505

10.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

Ambient temperature under bias..........................................................................................................-40°C to +125°C

Storage temperature ............................................................................................................................-65°C to +150°C

Volt a ge on VDD with respect to VSS ...............................................................................................................0 to +6.5V

Volt a ge on MCLR with respect to VSS..........................................................................................................0 to +13.5V

Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation(1) ..................................................................................................................................800 mW

Max. current out of VSS pin.......... ...... ..... ...... ..... ...... ............................ ...... ............................ ..... ...... .................200 mA

Max. current into VDD pin...................................................................................................................................150 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA

Output clamp cur rent, IOK (VO < 0 or VO > VDD)...........................................................................................................±20 mA

Max. output current sunk by any I/O pin ..............................................................................................................25 mA

Max. output current sourced by any I/O pin.........................................................................................................25 mA

Max. output current sourced by I/O port ..............................................................................................................75 mA

Max. output current sunk by I/O port ...................................................................................................................75 mA

Note 1: Pow er dissipation is calc ulated as follows : PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – V OH) x IOH} + ∑(VOL x IOL)

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

thos e in di c at e d in t he o pe rat i o n l is tin g s o f t his s pecifi ca t io n is not i mp li e d. Ex po su r e to m ax im um r at i ng c ond it i on s

for extended periods may affect device reliability.

PIC12F508/509/16F505

DS41236A-page 70 Preliminary  2004 Microchip Technology Inc.

FIGURE 10-1: PIC12F508/509/16F505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

FIGURE 10-2: MAX IMU M OSCILLATOR FREQUENCY TA BLE

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz)

VDD

(Volts)

2.0

0200 kHz 4 MHz 20 MHz

Frequency (MHz)

XTRC

Oscillator Mode

INTOSC

 2004 Microchip Technology Inc. Preliminary DS41236A-page 71

PIC12F508/509/16F505

10.1 DC Characteristics: PIC12F508/509/16F505 (Industrial)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

Param

No. Sym Characteristic Min Typ(1) Max Units Conditions

D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1

D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode

D003 VPOR VDD Start Voltage to ensure

Power-on Reset —Vss— VSee Section 7.4 "DC Characteris-

tics" for details

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05

*— — V/ms See Section 7.4 "DC Characteris-

tics" for details

D010 IDD Supply Current(3) —

—

170

0.4

1.7

TBD

µA

FOSC = 4 MHz, VDD = 2.0V(4)

FOSC = 10 MHz, VDD = 3.0V

FOSC = 20 MHz, VDD = 5.0V

FOSC = 32 kHz, VDD = 2.0V, WDT

disabled

D020 IPD Power-down Current(5) —0.1TBDµAVDD = 2.0V

D022 ∆IWDT WDT Current(5) —1.0TBDµAVDD = 2.0V

Legend: TBD = To Be Determined.

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading , oscillator type, bu s rat e, in tern al c od e ex ec uti on pattern and te mp eratu re a lso hav e an impact on

the current consumption.

a) The tes t conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD,

MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that the device is in Sleep

mode.

4: Does not inclu de current through REXT (in EXTRC mode only). The current through the resistor can be

estimated by the formula:

I = VDD/2REXT (mA) with REXT in kΩ.

5: The Power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS.

PIC12F508/509/16F505

DS41236A-page 72 Preliminary  2004 Microchip Technology Inc.

10.2 DC Characteristics: PIC12F508/509/16F505 (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)

Operati ng Temperature - 40 °C ≤ TA ≤ +125°C (Extended)

Param

No. Sym Characteristic Min Typ(1) Max Units Conditions

D001 VDD Supply Voltage 2.0 5.5 V See Figure 10-1

D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode

D003 VPOR VDD Start Voltage to ensure

Power-on Reset —Vss— VSee Section 7.4 "DC Character-

istics" for details

D004 SVDD VDD Rise Rate to ensure

Power-on Reset 0.05* — — V/ms See Section 7.4 "DC Character-

istics" for details

D010 IDD Supply Current(3) —

—

170

0.4

1.7

TBD

µA

FOSC = 4 MHz, VDD = 2.0V(4)

FOSC = 10 MHz, VDD = 3.0V

FOSC = 20 MHz, VDD = 5.0V

FOSC = 32 kHz, VDD = 2.0V, WDT

disabled

D020 IPD Power-down Current(5) —0.1TBDµAVDD = 2.0V

D022 ∆IWDT WDT Current(5) —1.0TBDµAVDD = 2.0V

Legend: TBD = To Be Determined.

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

a) The test co nditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD,

MCLR = VDD;

WDT enabled/disabled as specified.

a) For standby current measurements, the conditions are the same, except that the device is in Sleep

mode.

4: Does not inclu de current through REXT (in EXTRC mode only). The current through the resistor can be

estimated by the formula:

I = VDD/2REXT (mA) with REXT in kΩ.

5: The Power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 73

PIC12F508/509/16F505

TABLE 10-1: DC CHARACTERISTICS: PIC12F508/509 /16F505 (Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating temperature -40°C ≤ TA ≤ + 85° C (in dus tri al)

-40°C ≤ TA ≤ +125°C (extend ed)

Operating voltage VDD range as described in DC specification

Param

No. Sym Characteristic Min Typ† Max Units Conditions

VIL Input Low Voltage

I/O ports:

D030 with TTL buffer Vss — 0.8V V For all 4.5 ≤ VDD ≤ 5.5V

D030A Vss — 0.15 VDD V Otherwise

D031 with Schmitt Trigger buffer Vss — 0.15 VDD V

D032 MCLR, T0CKI Vss — 0.15 VDD V

D033 OSC1 (in EXTRC) Vss — 0.15 VDD V(Note1)

D033 OSC1 (in HS) Vss — 0.3 VDD V(Note1)

D033 OSC1 (in XT and LP) Vss — 0.3 V (Note1)

VIH Input High Voltage

I/O ports: —

D040 with TTL buffer 2.0 — VDD V4.5 ≤ VDD ≤ 5.5V

D040A 0.25 VDD

+ 0.8 VDD —VDD V Otherwise

D041 with Schmitt Trigger buffer 0.85 VDD —VDD V For en tire VDD range

D042 MCLR , T0CKI 0.85 VDD —VDD V

D043 OSC1 (in EXTRC) 0.85 VDD —VDD V(Note1)

D043 OSC1 (in HS) 0.7 VDD —VDD V(Note1)

D043 OSC1 (i n XT and LP ) 1.6 — VDD V

D070 IPUR GPIO weak pull-up current(4) TBD 250 TBD µAVDD = 5V, VPIN = VSS

IIL Input Leakag e Current(2), (3)

D060 I/O ports — — ± 1 µAVss ≤ VPIN ≤ VDD, Pin at high-impedance

D061 GP3/RB3/MCLRI(5) ——± 30µAVss ≤ VPIN ≤ VDD

D061A GP3/RB3/MCLRI(6) ——± 5µAVss ≤ VPIN ≤ VDD

D063 OSC1 — — ± 5 µAVss ≤ VPIN ≤ VDD, XT, HS and LP oscillator

configuration

Output Low Voltage

D080 I/O ports/CLKOUT — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C

D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C

D083 OSC2 — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C

D083A — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C

Output High Voltage

D090 I/O ports/CLKOUT(3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C

D090A VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C

D092 OSC2 VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C

D092A VDD – 0.7 — — V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C

Capacitive Loading Specs on

Output Pins

D100 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is

used to drive OSC1.

D101 All I/O pins and OSC2 — — 50 pF

Legend: TBD = To Be Determined.

† Data in “Ty p” col um n is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F508/509/

16F505 be driven with external clock in RC mode.

2: The leak age curr ent on t he M CLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating

conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of t h e pin.

4: Does not include GP3/RB3. For GP3/RB3 see param eters D061 and D061A.

5: This specification applies to GP3/RB3/MCLR configured as external MCLR and GP3/R B3/ MCL R configured as input with internal pull-up

enabled.

6: This specification applies when GP3/RB3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit

is higher than the standard I/O logic.

PIC12F508/509/16F505

DS41236A-page 74 Preliminary  2004 Microchip Technology Inc.

TABLE 10-2: PULL-UP RESISTOR RANGES – PIC12F508/509/16F505

VDD (Volts) Temperature (°C) Min Typ Max Units

RB0/RB1/RB4

2.0 -40 TBD TBD TBD Ω

25 TBD TBD TBD Ω

85 TBD TBD TBD Ω

125 TBD TBD TBD Ω

5.5 -40 TBD TBD TBD Ω

25 TBD TBD TBD Ω

85 TBD TBD TBD Ω

125 TBD TBD TBD Ω

RB3

2.0 -40 TBD TBD TBD Ω

25 TBD TBD TBD Ω

85 TBD TBD TBD Ω

125 TBD TBD TBD Ω

5.5 -40 TBD TBD TBD Ω

25 TBD TBD TBD Ω

85 TBD TBD TBD Ω

125 TBD TBD TBD Ω

Legend: TBD = To Be determined.

* These parameters are characterized but not tested.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 75

PIC12F508/509/16F505

10.3 Timing Parameter Symbology and Load Conditions – PIC12F508/509/16F505

The timing parameter symbols have been created following one of the following formats:

FIGURE 10-3: LOAD CONDITIONS – PIC12F508/509/16F505

FIGURE 10-4: EXTERNAL CLOCK TIMING – PIC12F508/509/16F505

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase subscripts (pp) and their meanings:

pp2to mcMCLR

ck CLKOUT osc Oscillator

cy Cycle time os OSC1

drt Device Reset Timer t0 T0CKI

io I/O port wdt Watchd og Timer

Uppercase letters and their meanings:

FFall PPeriod

HHigh RRise

I Invalid (high-impedance) V Valid

L Low Z High-impedance

VSS

Legend:

CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

modes when external clock

is used to drive OSC1

OSC1

Q4 Q1 Q2 Q3 Q4 Q1

133

PIC12F508/509/16F505

DS41236A-page 76 Preliminary  2004 Microchip Technology Inc.

TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS – PIC12F508/509/16F505

AC CHARACTERISTICS

Standard Operating Conditi ons (unle ss otherw is e speci fied)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1 "DC

Characteristics"

Param

No. Sym Characteristic Min Typ(1) Max Units Conditions

1A FOSC External CLKIN Frequency(2) DC — 4 MHz XT Oscillator mode

DC — 2 0 MHz HS Oscillat or mode (PIC16F505

only)

DC — 200 kHz LP Oscillator mode

Oscillator Frequency(2) — — 4 MHz EXTRC Os cillator mode

0.1 — 4 MHz XT Oscillator mode

4 — 20 MHz HS Oscillator mode (PIC16F505

only)

— — 200 kHz LP Oscillator mode

OSC External CLKIN Period(2) 250 — — ns XT Oscillator mode

50 — — ns HS Oscilla tor mode (PIC16F 505

only)

5——µs LP Oscillator mode

Oscillator Period(2) 250 — — ns EXTRC Oscill ator mode

250 — 10,000 ns XT Oscillator mode

50 — 250 ns HS Oscillator mode (PIC16F505

only)

5——µs LP Oscillator mode

CY Instructi on Cy cle Time 200 4/FOSC —ns

3 TosL,

TosH Clock in (OSC1) Low or High

Time 50* — — ns XT Oscillator

2* — — µs LP Oscillator

10* — — ns HS Oscillator (PIC16F505 only)

4TosR,

TosF Clock in (OSC1) Rise or Fall

Time — — 25* ns XT Oscillator

— — 50* ns LP Oscillator

— — 15* ns HS Oscillator (PI C16F505 on ly)

* These parameters are characterized but not tested.

Note 1: Dat a in the T ypi cal (“T yp ”) column is at 5V, 25°C unless otherw ise st ated. These p aramete rs are for design

guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption. When an external clock

input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

 2004 Microchip Technology Inc. Preliminary DS41236A-page 77

PIC12F508/509/16F505

TABLE 10-4: CALIBRATED INTERNAL RC FREQUENCIES – PIC12F508/509/16F505

FIGURE 10-5: I/O TIMING – PIC12F508/509/16F505

AC CHARACTERISTICS

S tandard Operating Conditions (unle ss otherwis e speci fied)

Operati ng Temperatu re -40°C ≤ TA ≤ +85°C (industrial),

-40°C ≤ TA ≤ +125°C (extended)

Operati ng Voltage VDD range is described in

Section 10.1 "DC Characteristics"

Param

No. Sym Characteristic Freq

Tolerance Min Typ† Max Units Conditions

F10 FOSC Internal Ca librated

INTOSC Frequency(1) ± 1% TBD 4.00 TBD MHz VDD and Temperat ure

TBD

± 2% TBD 4.00 TBD MHz 2.5V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +8 5°C

± 5% TBD 4.00 TBD MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (Ind.)

-40°C ≤ TA ≤ +125°C (Ext.)

Legend: TBD = To Be Determined.

* These parameters are characterized but not tested.

† Data in the T ypical (“T yp”) column is at 5V, 25°C unless otherwise s tated. These p arameters are for design

guidance only and are not tested.

Note 1: To ensure the se osc il lat or freq uen cy tol eran ce s, V DD and VSS must be capacitively decou pled as close to

the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.

OSC1

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

20, 21

Old Value New Value

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

PIC12F508/509/16F505

DS41236A-page 78 Preliminary  2004 Microchip Technology Inc.

TABLE 10-5: TIMING REQUIREMENTS – PIC12F508/509/16F505

FIGURE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –

PIC12F508/509/16F505

CHARACTERISTIC

Standard Operating Conditions (unless otherwise specified)

Operati ng Temperatu re -40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

Operati ng Voltage VDD range is desc ribed in Section 10.1 "DC Characteristics"

Param

No. Sym Characteristic Min Typ(1) Max Units

17 TOSH2IOVOSC1↑ (Q1 cycle) to Port Out Valid(2), (3) — — 100* ns

18 TOSH2IOIOSC1↑ (Q2 cy cl e) to Port I npu t Inv al id (I /O in h ol d ti me)(2) TBD — — ns

19 TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time) TBD — — ns

20 TIOR Port Output Rise Time (3) —1025**ns

21 TIOF Port Output Fall Time(3) —1025**ns

Legend: TBD = To Be Determined.

* These pa rameters are characterized but not tested.

** These parameters are design targets and are not tested.

Note 1: Data in t he Typical (“Typ”) col umn is at 5V, 25°C unless oth erwi se stated. These p a r am ete rs a re for design

guidance only and are not tested.

2: Measurements are taken in EXTRC mode.

3: See Figure 10-3 for loading conditions.

VDD

MCLR

Internal

POR

DRT

Timeout(2)

Internal

Reset

Watchdog

Timer

Reset

I/O pin(1)

32 32

Note 1: I/O pins must be taken out of High-impedance mode by enabling the output drivers in software.

2: Runs in MCLR or WDT Reset only in XT, LP and HS (PIC16F505) modes .

 2004 Microchip Technology Inc. Preliminary DS41236A-page 79

PIC12F508/509/16F505

TABLE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F508/509/16F505

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in

Section 10.1 "DC Characteristics"

Param

No. Sym Characteristic Min Typ(1) Max Units Conditions

30 TMCLMCLR Pulse Width (low) 2000* — — ns VDD = 5.0V

31 TWDT Watchdog Timer Time-out Period

(no prescaler) 9*

9* 18*

18* 30*

40* ms

ms VDD = 5.0V (Industrial)

VDD = 5.0V (Extended)

32 TDRT Device Reset Timer Period(2) 9*

9* 18*

18* 30*

40* ms

ms VDD = 5.0V (Industrial)

VDD = 5.0V (Extended)

34 TIOZ I/O High-impedance from MCLR

low — — 2000* ns

* These parameters are characterized but not tested.

Note 1: Dat a in the Typical (“Typ”) column is at 5V, 25°C unless ot herwise stated . These p arameters are for desig n

guidance only and are not tested.

PIC12F508/509/16F505

DS41236A-page 80 Preliminary  2004 Microchip Technology Inc.

FIGURE 10-7: TIMER0 CLOCK TIMINGS – PIC12F508/509/16F505

TABLE 10-7: TIMER0 CLOCK REQUIREMENTS – PIC12F508/509/16F505

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industria l)

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in

Section 10.1 "DC Characteristics"

Param

No. Sym Characteristic Min Typ(1) Max Units Conditions

40 Tt0H T0CKI High Pulse

Width No Prescaler 0.5 TCY + 20* — — ns

With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse

Width No Prescaler 0.5 TCY + 20* — — ns

With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whichev er is grea ter.

N = Prescale Value

(1, 2, 4,..., 256)

* These pa rameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

T0CKI

40 41

 2004 Microchip Technology Inc. Preliminary DS41236A-page 81

PIC12F508/509/16F505

11.0 DC AND AC

CHARACTERISTICS GRAPHS

AND CHARTS

Graphs and charts are not available at this time.

PIC12F508/509/16F505

DS41236A-page 82 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS41236A-page 83

PIC12F508/509/16F505

12.0 P ACKAGING INFORMATION

12.1 Package Marking Information

XXXXXNNN

8-Lead PDIP

XXXXXXXX

YYWW /P017

Example

12F508-I

0410

8-Lead SOIC (.150”)

XXXXXXXX

XXXXYYWW

NNN

Example

12F509-I

/SN0410

017

8-Lead MSOP

XXXXXX

YWWNNN

Example

12F509

0431017

Legend: XX...X Customer specific information*

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanum eri c traceab ili ty code

Note: In the event the full M icroch ip p art nu mber ca nnot be m arked on one line, it w ill

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

PIC12F508/509/16F505

DS41236A-page 84 Preliminary  2004 Microchip Technology Inc.

12.1 Package Marking Information (Cont’d)

XXXXXXXXXXXXXX

YYWWNNN

14-Lead PDIP (300 mil)

14-Lead SOIC (150 mil)

XXXXXXXXXXX

YYWWNNN

Example

PIC16F505-E

0431017

XXXXXXXXXXX

14-Lead TSSOP (150 mil)

XXXXXXXX

YYWW

Example

16F505-I

0431

NNN 017

/SLG0125

Example

PIC16F505-I/PG

0410017

0215

 2004 Microchip Technology Inc. Preliminary DS41236A-page 85

PIC12F508/509/16F505

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

PIC12F508/509/16F505

DS41236A-page 86 Preliminary  2004 Microchip Technology Inc.

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significant Characteristic

 2004 Microchip Technology Inc. Preliminary DS41236A-page 87

PIC12F508/509/16F505

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

(F)

n 1

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037 REFFFootprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.003

.009

.006

.012

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff

Overall Width

Number of Pins

Pitch

.016 .024

.118 BSC

.000

.030

.193 TYP.

.033

MIN

Units

.026 BSC

NOM

INCHES

0.95 REF

.009

.016

0.08

0.22

0°

0.23

0.40

8°

MILLIMETERS*

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043

.031

.037

.006

0.40

0.00

0.75

MIN

MAX NOM

1.10

0.80

0.15

0.95

MAX

15°5° -

JEDEC Equivalent: MO-187

0° - 8°

5°

5° -

15°

PIC12F508/509/16F505

DS41236A-page 88 Preliminary  2004 Microchip Technology Inc.

14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dimen sion Li mits MIN NOM M AX MIN NOM MAX

Number of Pin s n14 14

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to S houlder Width E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overal l Length D .7 40 .75 0 .7 60 1 8.8 0 19.05 19.30

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacin g § eB .310 .37 0 .430 7.87 9.40 10 .92

Mold Draft Angle Top α5 10 15 5 10 15

β5 10 15 5 10 15Mold Draft Angle Bottom

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-005

§ Significant Characteristic

 2004 Microchip Technology Inc. Preliminary DS41236A-page 89

PIC12F508/509/16F505

14-Lead Plasti c Small Outline (SL) – N arrow, 150 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.250.230.20.010.009.008

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.510.380.25.020.015.010hChamfer Distance 8.818.698.56.347.342.337DOverall Length 3.993.903.81.157.154.150E1Molded Pa ckag e Width 6.205.995.79.244.236.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Mold ed Pa ckag e Thick ness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 1414

Number of Pins MAXNOMMINMAXNOMMINDimension Li mits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-065

§ Significant Characteristic

PIC12F508/509/16F505

DS41236A-page 90 Preliminary  2004 Microchip Technology Inc.

14-Lead Plastic Thin Shrink Small Outl ine (ST) – 4.4 mm (TSSOP)

840840

Foot A ngle

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Length 5.105.004.90.201.197.193DMolded Package Length 4.504.404.30.177.173.169E1Molded Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002A1Standoff § 0.950.900.85.037.035.033A2Molded Pa ckag e Thick ness 1.10.043AOverall Height 0.65.026

Pitch 1414

Number of Pins MAXNOMMINMAXNOMMINDimension Li mits MILLIMETERS*INCHESUnits

A2A1

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-087

§ Significant Characteristic

 2004 Microchip Technology Inc. Preliminary DS41236A-page 91
PIC12F508/509/16F505
INDEX
A
ALU.......................................................................................9
Assembler
MPASM Ass embler.....................................................63
B
Block Diagram
On-Chip Rese t Circuit.................. .......... ........... ..........47
Timer0.........................................................................33
TMR0/WDT Pr escaler.................................................37
Watchdog Timer...................... ....... .... .. .... .. .. ......... .. .. ..50
Brown-Out Protection Circuit ..............................................51
C
C Compilers
MPLAB C17..... ................... ................... ........... ..........64
MPLAB C18..... ................... ................... ........... ..........64
MPLAB C30..... ................... ................... ........... ..........64
Carry .....................................................................................9
Clocking Scheme................................................................14
Code Protection ............................................................39, 52
Configuration Bits................................................................39
Configur ation Word.............................................................40
D
DC and AC Characteristics.............................. .... ....... .... .. ..81
Demonstration Boards
PICDEM 1........ ........... ................... .......... ...................66
PICDEM 17.................................... .......... ...................66
PICDEM 18R PIC18 C6 01/801....... .......... ........... ........67
PICDEM 2 Plus............................ .......... ................... ..66
PICDEM 3 PIC16C92 X....... ........... .............................66
PICDEM 4........ ........... ................... .......... ...................66
PICDEM LIN PIC16C43 X ...........................................67
PICDEM USB PIC16C7 X5............. .......... ........... ........67
PICDEM.net Internet/Ethernet....................................66
Development Support .........................................................63
Digit Carry.............................................................................9
E
Errata ....................................................................................3
Evalu a tio n  a nd Pr o g ramming Tools............... ................... ..67
F
Family of Devices
PIC16F505....................................................................5
FSR.....................................................................................26
I
I/O Int e rfacing ...... ........... ................... .................. ........... ....29
I/O Ports....... ................... ................... .................. ...............29
I/O Prog ramming Consideratio n s......... ................... ............31
ID Locations..................................................................39, 52
INDF....................................................................................26
Indirect Data Addressing.....................................................26
Instruction Cycle .................................................................14
Instruction Flow/Pipelining..................................................14
Instruction Set Summary.....................................................56
L
Loading of PC ..................... .. .. .. .. .. ....... .. .. .. .. .. .. .. .. ....... .. .. .. ..25
M
Memory Organization..........................................................15
Data Memor y................................... ................... ........ 16
Program Memory (P IC12F508/ 509) ........................... 15
Program Memory (P IC16F505) .................................. 16
MPLAB ASM30 Assembler, Linker, Librarian............. ........ 64
MPLAB ICD 2 In-Circuit Debugger................................. .... 65
MPLAB ICE 2000 High Performance Universal
 In-Circuit Emulator.................... .......... ................... .... 65
MPLAB ICE 4000 High Performance Universal
 In-Circuit Emulator.................... .......... ................... .... 65
MPLAB Integrated Development Environment Software.... 63
MPL IN K Obje ct Link e r / M PLIB Ob j e ct Libra ri a n... .. ...... .. ..... 64
O
Option Register................................................................... 22
OSC selection..................................................................... 39
OSCCAL Register................. ................... ........... ................ 24
Oscillator Configurations. .. ......... ......................................... 41
Oscillator Types
HS............................................................................... 41
LP............................................................................... 41
RC .............................................................................. 41
XT............................................................................... 41
P
PIC12F508/509/16F505 Device Varieties ............................ 7
PICkit 1 FLASH Starter Kit.................................................. 67
PICSTART Plus Development Programmer....................... 65
PORDe v i ce  R e s et Timer (D RT) ... .. ...... ...... ..... ...... ...... . 39 , 4 9
PD............................................................................... 51
Power-on Reset (POR)............................................... 39
TO............................................................................... 51
PORTB ............................................................................... 29
Power-down Mode.............................................................. 52
Prescaler ............................................................................ 36
PRO MATE II Univer sal De vice Progr a mm er..... .......... ...... 65
Program Counter................................................................ 25
Q
Q cycles... ................... .......... ................... ................... ........ 14
R
RC Oscilla tor....................................................................... 42
Read-Modify-Write.............................................................. 31
Register File Map
PIC12F508 ................................................................. 17
PIC12F509 ................................................................. 17
PIC16F505 ................................................................. 17
Registers
Special Function......................................................... 18
Reset .................................................................................. 39
Reset on Brown -Out...................... .......... ................... ........ 51
S
Sleep ............................................................................ 39, 52
Softwar e  Simulator (MPLAB SIM )........................ .......... .... 64
Softwar e  Simulator (MPLAB SIM 3 0 )........................ .......... 64
Special Feature s of th e  CPU.............................................. 39
Special Function Registers................................................. 18
Stack................................................................................... 25
Statu s Reg i ster............... ........... .................. ................... 9, 20

PIC12F508/509/16F505
DS41236A-page 92 Preliminary  2004 Microchip Technology Inc.
T
Timer0
Timer0.........................................................................33
Timer0 (TMR0) Module...............................................33
TMR0 with External Clock...........................................35
Timing Diagrams and Specifications................ .... .. .... .. .......75
Timing Parameter Symbology and Load Conditions...........75
TRIS Registers............. ................... ........... .................. .......29
W
Wake-up from Sleep ...........................................................52
Watchdog Timer (WDT)................................. .. .... .... .. ...39, 49
Period..........................................................................49
Programming Consi der a tions .................. .......... .........49
WWW, On-Line Support ........................................................3
Z
Zero bit....................... ...................................... ................... ..9

 2003 Microchip Technology Inc. Preliminary DS41236A-page 93

PIC12F508/509/16F505

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web site.

The web site is used b y Micr ochip as a me ans to mak e

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Numbe rs are:

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042003

PIC12F508/509/16F505

DS41236A-page 94 Preliminary  2003 Microchip Technology Inc.

READER RESPONSE

It is ou r intention to pro vi de you with the b est do cu me nt ation possib le to e ns ure successful u se of y ou r Mic r oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, su bject m atter, and ways i n which o ur docum entatio n

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Please list the followi ng information, and use this outline to provide us with your comments about this document.

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DS41236APIC12F508/509/16F505

1. What are the best features of t his document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to foll ow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2004 Microchip Technology Inc. Preliminary DS41236A-page 95

PIC12F508/509/16F505

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device PIC16F505

PIC12F508

PIC12F509

PIC16F505T (Tape & Reel)

PIC12F508T (Tape & Reel)

PIC12F509T (Tape & Reel)

Temperatu re Rang e I = -40°C to +85°C (Industrial)

E= -40°C to +125°C (Extended)

Package PG = 300 mil PDIP (Pb-free)

SLG = 150 mil SOIC, 14-LD (Pb-free)

SNG = 150 mil SOIC, 8-LD (Pb-free)

MSG = MSOP (Pb- free )

STG = TSSOP (Pb-free)

Pattern Special Requirements

Examples:

a) PIC16F505-I/PG = Industrial temp., PDIP

package (Pb-free)

b) PIC16F505T-I/SLG = Industrial temp., SOIC

package (Pb-free), Tape and Reel

c) PIC16F505T-I/SLG = Industrial temp., SOIC

package (Pb-free), Tape and Reel

d) P IC12F5 08T-I/SNG = Indu stria l temp. , 15 0 mil

SOIC package (Pb-free), Tape and Reel

e) PIC12F508T-E/MSG = Extended temp., MSOP

package (Pb-free), Tape and Reel

f) PIC12F509-E/PG = Extended temp., PDIP

package (Pb-free)

g) PIC12F509-I/SMG = Industrial temp., 208 mil

SOIC package (Pb-free)

Note: Tap e an d Ree l avai la ble fo r only the fo llowi ng packag es: SOIC, MSOP

and TSSOP.

DS41236A-page 96 Preliminary  2004 Microchip Technology Inc.

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