HCS08
Microcontrollers
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MC9S08GB60A
MC9S08GB32A
MC9S08GT60A
MC9S08GT32A
Data Sheet
MC9S08GB60A
Rev. 2
07/2008
MC9S08GB60A Data Sheet
Covers: MC9S08GB60A
MC9S08GB32A
MC9S08GT60A
MC9S08GT32A
MC9S08GB60A
Rev. 2
07/2008
MC9S08GB60A Data Sheet, Rev. 2
6Freescale Semiconductor
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date Description of Changes
1.00 07/14/2005 Initial public release.
1.01 09/04/2007
Added a footnote to RTI of Table 3.2; Added RTI description to Section 3.5.6;
Added a sentence "If active BDM mode is enabled in stop3, the internal RTI
clock is not available." to the Section 5.7 Real Time Interrupt.
1.02 02/25/2008
Changed the Maximun Low Power of FBE and FEE in Ta bl e A - 9 to 10 MHz.
Changed the Title of Ta b l e 1 3 - 2 from “IIC1A Register Field Descriptions” to
“IIC1F Register Field Descriptions”
2 7/30/2008
Added 42-pin SDIP information.
Changed “However, when HGO=0, the maximum frequency is 8 MHz in FEE
and FBE modes.” to “However, when HGO=0, the maximum frequency is
10 MHz in FEE and FBE modes.” in Appendix B5.
Updated the “How to reach us” at backpage.
This product incorporates SuperFlash® technology licensed from SST.
Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2005-2008. All rights reserved.
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 3
List of Chapters
Chapter Number Title Page
Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Chapter 2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Chapter 3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Chapter 5 Resets, Interrupts, and System Configuration . . . . . . . . . . . . . . .65
Chapter 6 Parallel Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 7 Internal Clock Generator (S08ICGV2) . . . . . . . . . . . . . . . . . . . . .103
Chapter 8 Central Processor Unit (S08CPUV2) . . . . . . . . . . . . . . . . . . . . . . 129
Chapter 9 Keyboard Interrupt (S08KBIV1) . . . . . . . . . . . . . . . . . . . . . . . . . .149
Chapter 10 Timer/PWM (S08TPMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Chapter 11 Serial Communications Interface (S08SCIV1). . . . . . . . . . . . . . 171
Chapter 12 Serial Peripheral Interface (S08SPIV3). . . . . . . . . . . . . . . . . . . . 189
Chapter 13 Inter-Integrated Circuit (S08IICV1) . . . . . . . . . . . . . . . . . . . . . . .205
Chapter 14 Analog-to-Digital Converter (S08ATDV3) . . . . . . . . . . . . . . . . .223
Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Appendix B EB652: Migrating from the GB60 Series to the
GB60A Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Appendix C Ordering Information and Mechanical Drawings. . . . . . . . . .287
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 7
Chapter 1
Device Overview
1.1 Overview .........................................................................................................................................17
1.2 Features ...........................................................................................................................................17
1.2.1 Standard Features of the HCS08 Family .........................................................................17
1.2.2 Features of MC9S08GBxxA/GTxxA Series of MCUs ....................................................18
1.2.3 Devices in the MC9S08GBxxA/GTxxA Series ...............................................................19
1.3 MCU Block Diagrams .....................................................................................................................19
1.4 System Clock Distribution ..............................................................................................................21
Chapter 2
Pins and Connections
2.1 Introduction .....................................................................................................................................23
2.2 Device Pin Assignment ...................................................................................................................24
2.3 Recommended System Connections ...............................................................................................27
2.3.1 Power ...............................................................................................................................29
2.3.2 Oscillator ..........................................................................................................................29
2.3.3 Reset ................................................................................................................................29
2.3.4 Background / Mode Select (PTG0/BKGD/MS) ..............................................................30
2.3.5 General-Purpose I/O and Peripheral Ports .......................................................................30
2.3.6 Signal Properties Summary .............................................................................................32
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................35
3.2 Features ...........................................................................................................................................35
3.3 Run Mode ........................................................................................................................................35
3.4 Active Background Mode ...............................................................................................................35
3.5 Wait Mode .......................................................................................................................................36
3.6 Stop Modes ......................................................................................................................................36
3.6.1 Stop1 Mode ......................................................................................................................37
3.6.2 Stop2 Mode ......................................................................................................................37
3.6.3 Stop3 Mode ......................................................................................................................38
3.6.4 Active BDM Enabled in Stop Mode ................................................................................38
3.6.5 LVD Enabled in Stop Mode .............................................................................................39
3.6.6 On-Chip Peripheral Modules in Stop Modes ...................................................................39
Contents
Section Number Title Page
MC9S08GB60A Data Sheet, Rev. 2
8Freescale Semiconductor
Section Number Title Page
Chapter 4
Memory
4.1 MC9S08GBxxA/GTxxA Memory Map ..........................................................................................43
4.1.1 Reset and Interrupt Vector Assignments ..........................................................................43
4.2 Register Addresses and Bit Assignments ........................................................................................45
4.3 RAM ................................................................................................................................................50
4.4 Flash ................................................................................................................................................50
4.4.1 Features ............................................................................................................................51
4.4.2 Program and Erase Times ................................................................................................51
4.4.3 Program and Erase Command Execution ........................................................................52
4.4.4 Burst Program Execution .................................................................................................53
4.4.5 Access Errors ...................................................................................................................55
4.4.6 Flash Block Protection .....................................................................................................55
4.4.7 Vector Redirection ...........................................................................................................56
4.5 Security ............................................................................................................................................56
4.6 Flash Registers and Control Bits .....................................................................................................57
4.6.1 Flash Clock Divider Register (FCDIV) ...........................................................................57
4.6.2 Flash Options Register (FOPT and NVOPT) ...................................................................59
4.6.3 Flash Configuration Register (FCNFG) ..........................................................................60
4.6.4 Flash Protection Register (FPROT and NVPROT) .........................................................60
4.6.5 Flash Status Register (FSTAT) ........................................................................................62
4.6.6 Flash Command Register (FCMD) ..................................................................................63
Chapter 5
Resets, Interrupts, and System Configuration
5.1 Introduction .....................................................................................................................................65
5.2 Features ...........................................................................................................................................65
5.3 MCU Reset ......................................................................................................................................65
5.4 Computer Operating Properly (COP) Watchdog .............................................................................66
5.5 Interrupts .........................................................................................................................................66
5.5.1 Interrupt Stack Frame ......................................................................................................67
5.5.2 External Interrupt Request (IRQ) Pin ..............................................................................68
5.5.2.1 Pin Configuration Options ..............................................................................68
5.5.2.2 Edge and Level Sensitivity .............................................................................69
5.5.3 Interrupt Vectors, Sources, and Local Masks ..................................................................69
5.6 Low-Voltage Detect (LVD) System ................................................................................................71
5.6.1 Power-On Reset Operation ..............................................................................................71
5.6.2 LVD Reset Operation .......................................................................................................71
5.6.3 LVD Interrupt Operation .................................................................................................71
5.6.4 Low-Voltage Warning (LVW) .........................................................................................71
5.7 Real-Time Interrupt (RTI) ...............................................................................................................71
5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................72
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ...........................................73
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 9
Section Number Title Page
5.8.2 System Reset Status Register (SRS) ................................................................................74
5.8.3 System Background Debug Force Reset Register (SBDFR) ...........................................75
5.8.4 System Options Register (SOPT) ....................................................................................76
5.8.5 System Device Identification Register (SDIDH, SDIDL) ...............................................77
5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) ...............................78
5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ..........................79
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ..........................80
Chapter 6
Parallel Input/Output
6.1 Introduction .....................................................................................................................................81
6.2 Features ...........................................................................................................................................83
6.3 Pin Descriptions ..............................................................................................................................83
6.3.1 Port A and Keyboard Interrupts .......................................................................................83
6.3.2 Port B and Analog to Digital Converter Inputs ...............................................................84
6.3.3 Port C and SCI2, IIC, and High-Current Drivers ............................................................84
6.3.4 Port D, TPM1 and TPM2 ................................................................................................85
6.3.5 Port E, SCI1, and SPI ......................................................................................................85
6.3.6 Port F and High-Current Drivers .....................................................................................86
6.3.7 Port G, BKGD/MS, and Oscillator ..................................................................................86
6.4 Parallel I/O Controls ........................................................................................................................87
6.4.1 Data Direction Control ....................................................................................................87
6.4.2 Internal Pullup Control ....................................................................................................87
6.4.3 Slew Rate Control ............................................................................................................87
6.5 Stop Modes ......................................................................................................................................88
6.6 Parallel I/O Registers and Control Bits ...........................................................................................88
6.6.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) ................................................88
6.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) ................................................91
6.6.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) ................................................93
6.6.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ...............................................95
6.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) .................................................97
6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD) ..................................................99
6.6.7 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) .............................................100
Chapter 7
Internal Clock Generator (S08ICGV2)
7.1 Introduction ...................................................................................................................................105
7.1.1 Features ..........................................................................................................................106
7.1.2 Modes of Operation .......................................................................................................107
7.2 Oscillator Pins ...............................................................................................................................107
7.2.1 EXTAL— External Reference Clock / Oscillator Input ................................................107
7.2.2 XTAL— Oscillator Output ............................................................................................107
MC9S08GB60A Data Sheet, Rev. 2
10 Freescale Semiconductor
Section Number Title Page
7.2.3 External Clock Connections ..........................................................................................108
7.2.4 External Crystal/Resonator Connections .......................................................................108
7.3 Functional Description ..................................................................................................................109
7.3.1 Off Mode (Off) ..............................................................................................................109
7.3.1.1 BDM Active .................................................................................................109
7.3.1.2 OSCSTEN Bit Set .........................................................................................109
7.3.1.3 Stop/Off Mode Recovery ..............................................................................109
7.3.2 Self-Clocked Mode (SCM) ............................................................................................109
7.3.3 FLL Engaged, Internal Clock (FEI) Mode ....................................................................111
7.3.3.1 FLL Engaged Internal Unlocked ..................................................................111
7.3.3.2 FLL Engaged Internal Locked ......................................................................111
7.3.4 FLL Bypassed, External Clock (FBE) Mode ................................................................111
7.3.5 FLL Engaged, External Clock (FEE) Mode ..................................................................111
7.3.5.1 FLL Engaged External Unlocked .................................................................112
7.3.5.2 FLL Engaged External Locked .....................................................................112
7.3.6 FLL Lock and Loss-of-Lock Detection .........................................................................112
7.3.7 FLL Loss-of-Clock Detection ........................................................................................113
7.3.8 Clock Mode Requirements ............................................................................................114
7.3.9 Fixed Frequency Clock ..................................................................................................115
7.3.10 High Gain Oscillator ......................................................................................................115
7.4 Initialization/Application Information ..........................................................................................115
7.4.1 Introduction ....................................................................................................................115
7.4.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz .........................118
7.4.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz .............................119
7.4.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency .....................121
7.4.5 Example #4: Internal Clock Generator Trim .................................................................122
7.5 ICG Registers and Control Bits .....................................................................................................123
7.5.1 ICG Control Register 1 (ICGC1) ...................................................................................124
7.5.2 ICG Control Register 2 (ICGC2) ...................................................................................125
7.5.3 ICG Status Register 1 (ICGS1) ........................................................................126
7.5.4 ICG Status Register 2 (ICGS2) ......................................................................................127
7.5.5 ICG Filter Registers (ICGFLTU, ICGFLTL) .................................................................127
7.5.6 ICG Trim Register (ICGTRM) ......................................................................................128
Chapter 8
Central Processor Unit (S08CPUV2)
8.1 Introduction ...................................................................................................................................129
8.1.1 Features ..........................................................................................................................129
8.2 Programmer’s Model and CPU Registers .....................................................................................130
8.2.1 Accumulator (A) ............................................................................................................130
8.2.2 Index Register (H:X) .....................................................................................................130
8.2.3 Stack Pointer (SP) ..........................................................................................................131
8.2.4 Program Counter (PC) ...................................................................................................131
8.2.5 Condition Code Register (CCR) ....................................................................................131
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 11
Section Number Title Page
8.3 Addressing Modes .........................................................................................................................133
8.3.1 Inherent Addressing Mode (INH) ..................................................................................133
8.3.2 Relative Addressing Mode (REL) .................................................................................133
8.3.3 Immediate Addressing Mode (IMM) .............................................................................133
8.3.4 Direct Addressing Mode (DIR) .....................................................................................133
8.3.5 Extended Addressing Mode (EXT) ...............................................................................134
8.3.6 Indexed Addressing Mode .............................................................................................134
8.3.6.1 Indexed, No Offset (IX) ................................................................................134
8.3.6.2 Indexed, No Offset with Post Increment (IX+) ............................................134
8.3.6.3 Indexed, 8-Bit Offset (IX1) ...........................................................................134
8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .......................................134
8.3.6.5 Indexed, 16-Bit Offset (IX2) .........................................................................134
8.3.6.6 SP-Relative, 8-Bit Offset (SP1) ....................................................................134
8.3.6.7 SP-Relative, 16-Bit Offset (SP2) ..................................................................135
8.4 Special Operations .........................................................................................................................135
8.4.1 Reset Sequence ..............................................................................................................135
8.4.2 Interrupt Sequence .........................................................................................................135
8.4.3 Wait Mode Operation ....................................................................................................136
8.4.4 Stop Mode Operation .....................................................................................................136
8.4.5 BGND Instruction ..........................................................................................................137
8.5 HCS08 Instruction Set Summary ..................................................................................................138
Chapter 9
Keyboard Interrupt (S08KBIV1)
9.1 Introduction ...................................................................................................................................149
9.1.1 Port A and Keyboard Interrupt Pins ..............................................................................149
9.2 Features .........................................................................................................................................149
9.2.1 KBI Block Diagram .......................................................................................................151
9.3 Register Definition ........................................................................................................................151
9.3.1 KBI Status and Control Register (KBI1SC) ..................................................................152
9.3.2 KBI Pin Enable Register (KBI1PE) ..............................................................................153
9.4 Functional Description ..................................................................................................................153
9.4.1 Pin Enables ....................................................................................................................153
9.4.2 Edge and Level Sensitivity ............................................................................................153
9.4.3 KBI Interrupt Controls ...................................................................................................154
Chapter 10
Timer/PWM (S08TPMV1)
10.1 Introduction ...................................................................................................................................155
10.2 Features .........................................................................................................................................155
10.3 TPM Block Diagram .....................................................................................................................157
10.4 Pin Descriptions ............................................................................................................................158
10.4.1 External TPM Clock Sources ........................................................................................158
10.4.2 TPMxCHn — TPMx Channel n I/O Pins ......................................................................158
10.5 Functional Description ..................................................................................................................158
MC9S08GB60A Data Sheet, Rev. 2
12 Freescale Semiconductor
Section Number Title Page
10.5.1 Counter ..........................................................................................................................159
10.5.2 Channel Mode Selection ................................................................................................160
10.5.2.1 Input Capture Mode ......................................................................................160
10.5.2.2 Output Compare Mode .................................................................................160
10.5.2.3 Edge-Aligned PWM Mode ...........................................................................160
10.5.3 Center-Aligned PWM Mode ..........................................................................................161
10.6 TPM Interrupts ..............................................................................................................................163
10.6.1 Clearing Timer Interrupt Flags ......................................................................................163
10.6.2 Timer Overflow Interrupt Description ...........................................................................163
10.6.3 Channel Event Interrupt Description .............................................................................163
10.6.4 PWM End-of-Duty-Cycle Events ..................................................................................164
10.7 TPM Registers and Control Bits ...................................................................................................164
10.7.1 Timer x Status and Control Register (TPMxSC) ...........................................................165
10.7.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ..............................................166
10.7.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ..............................167
10.7.4 Timer x Channel n Status and Control Register (TPMxCnSC) .....................................168
10.7.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) .....................................169
Chapter 11
Serial Communications Interface (S08SCIV1)
11.1 Introduction ...................................................................................................................................171
11.1.1 Features ..........................................................................................................................173
11.1.2 Modes of Operation .......................................................................................................173
11.1.3 Block Diagram ...............................................................................................................174
11.2 Register Definition ........................................................................................................................176
11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) .........................................................176
11.2.2 SCI Control Register 1 (SCIxC1) ..................................................................................177
11.2.3 SCI Control Register 2 (SCIxC2) ..................................................................................178
11.2.4 SCI Status Register 1 (SCIxS1) .....................................................................................179
11.2.5 SCI Status Register 2 (SCIxS2) .....................................................................................181
11.2.6 SCI Control Register 3 (SCIxC3) ..................................................................................181
11.2.7 SCI Data Register (SCIxD) ...........................................................................................182
11.3 Functional Description ..................................................................................................................183
11.3.1 Baud Rate Generation ....................................................................................................183
11.3.2 Transmitter Functional Description ...............................................................................183
11.3.2.1 Send Break and Queued Idle ........................................................................184
11.3.3 Receiver Functional Description ...................................................................................184
11.3.3.1 Data Sampling Technique .............................................................................185
11.3.3.2 Receiver Wakeup Operation .........................................................................185
11.3.4 Interrupts and Status Flags .............................................................................................186
11.3.5 Additional SCI Functions ..............................................................................................187
11.3.5.1 8- and 9-Bit Data Modes ...............................................................................187
11.3.5.2 Stop Mode Operation ....................................................................................187
11.3.5.3 Loop Mode ....................................................................................................188
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 13
Section Number Title Page
11.3.5.4 Single-Wire Operation ..................................................................................188
Chapter 12
Serial Peripheral Interface (S08SPIV3)
12.1 Introduction ...................................................................................................................................189
12.1.1 Features ..........................................................................................................................191
12.1.2 Block Diagrams .............................................................................................................191
12.1.2.1 SPI System Block Diagram ..........................................................................191
12.1.2.2 SPI Module Block Diagram ..........................................................................192
12.1.3 SPI Baud Rate Generation .............................................................................................193
12.2 External Signal Description ..........................................................................................................194
12.2.1 SPSCK — SPI Serial Clock ..........................................................................................194
12.2.2 MOSI — Master Data Out, Slave Data In .....................................................................194
12.2.3 MISO — Master Data In, Slave Data Out .....................................................................194
12.2.4 SS — Slave Select .........................................................................................................194
12.3 Modes of Operation .......................................................................................................................195
12.3.1 SPI in Stop Modes .........................................................................................................195
12.4 Register Definition ........................................................................................................................195
12.4.1 SPI Control Register 1 (SPI1C1) ...................................................................................195
12.4.2 SPI Control Register 2 (SPI1C2) ...................................................................................196
12.4.3 SPI Baud Rate Register (SPI1BR) .................................................................................197
12.4.4 SPI Status Register (SPI1S) ...........................................................................................198
12.4.5 SPI Data Register (SPI1D) ............................................................................................199
12.5 Functional Description ..................................................................................................................200
12.5.1 SPI Clock Formats .........................................................................................................200
12.5.2 SPI Interrupts .................................................................................................................203
12.5.3 Mode Fault Detection ....................................................................................................203
Chapter 13
Inter-Integrated Circuit (S08IICV1)
13.1 Introduction ...................................................................................................................................205
13.1.1 Features ..........................................................................................................................207
13.1.2 Modes of Operation .......................................................................................................207
13.1.3 Block Diagram ...............................................................................................................208
13.2 External Signal Description ..........................................................................................................208
13.2.1 SCL — Serial Clock Line ..............................................................................................208
13.2.2 SDA — Serial Data Line ...............................................................................................208
13.3 Register Definition ........................................................................................................................208
13.3.1 IIC Address Register (IIC1A) ........................................................................................209
13.3.2 IIC Frequency Divider Register (IIC1F) .......................................................................209
13.3.3 IIC Control Register (IIC1C) .........................................................................................212
MC9S08GB60A Data Sheet, Rev. 2
14 Freescale Semiconductor
Section Number Title Page
13.3.4 IIC Status Register (IIC1S) ............................................................................................213
13.3.5 IIC Data I/O Register (IIC1D) .......................................................................................214
13.4 Functional Description ..................................................................................................................215
13.4.1 IIC Protocol ...................................................................................................................215
13.4.1.1 START Signal ...............................................................................................216
13.4.1.2 Slave Address Transmission .........................................................................216
13.4.1.3 Data Transfer .................................................................................................216
13.4.1.4 STOP Signal ..................................................................................................217
13.4.1.5 Repeated START Signal ...............................................................................217
13.4.1.6 Arbitration Procedure ...................................................................................217
13.4.1.7 Clock Synchronization ..................................................................................217
13.4.1.8 Handshaking .................................................................................................218
13.4.1.9 Clock Stretching ............................................................................................218
13.5 Resets ............................................................................................................................................218
13.6 Interrupts .......................................................................................................................................218
13.6.1 Byte Transfer Interrupt ..................................................................................................219
13.6.2 Address Detect Interrupt ................................................................................................219
13.6.3 Arbitration Lost Interrupt ..............................................................................................219
13.7 Initialization/Application Information ..........................................................................................220
Chapter 14
Analog-to-Digital Converter (S08ATDV3)
14.1 Introduction ...................................................................................................................................225
14.1.1 Features ..........................................................................................................................225
14.1.2 Modes of Operation .......................................................................................................225
14.1.2.1 Stop Mode .....................................................................................................225
14.1.2.2 Power Down Mode .......................................................................................225
14.1.3 Block Diagram ...............................................................................................................225
14.2 Signal Description .........................................................................................................................226
14.2.1 Overview ........................................................................................................................226
14.2.1.1 Channel Input Pins — AD1P7–AD1P0 ........................................................227
14.2.1.2 ATD Reference Pins — VREFH, VREFL ....................................................................... 227
14.2.1.3 ATD Supply Pins — VDDAD, VSSAD ........................................................................... 227
14.3 Functional Description ..................................................................................................................227
14.3.1 Mode Control .................................................................................................................227
14.3.2 Sample and Hold ............................................................................................................228
14.3.3 Analog Input Multiplexer ..............................................................................................230
14.3.4 ATD Module Accuracy Definitions ...............................................................................230
14.4 Resets ............................................................................................................................................233
14.5 Interrupts .......................................................................................................................................233
14.6 ATD Registers and Control Bits ....................................................................................................233
14.6.1 ATD Control (ATDC) ....................................................................................................234
14.6.2 ATD Status and Control (ATD1SC) ..............................................................................236
14.6.3 ATD Result Data (ATD1RH, ATD1RL) ........................................................................237
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Freescale Semiconductor 15
Section Number Title Page
14.6.4 ATD Pin Enable (ATD1PE) ...........................................................................................238
Chapter 15
Development Support
15.1 Introduction ...................................................................................................................................239
15.1.1 Features ..........................................................................................................................240
15.2 Background Debug Controller (BDC) ..........................................................................................240
15.2.1 BKGD Pin Description ..................................................................................................241
15.2.2 Communication Details .................................................................................................242
15.2.3 BDC Commands ............................................................................................................246
15.2.4 BDC Hardware Breakpoint ............................................................................................248
15.3 On-Chip Debug System (DBG) ....................................................................................................249
15.3.1 Comparators A and B ....................................................................................................249
15.3.2 Bus Capture Information and FIFO Operation ..............................................................249
15.3.3 Change-of-Flow Information .........................................................................................250
15.3.4 Tag vs. Force Breakpoints and Triggers ........................................................................250
15.3.5 Trigger Modes ................................................................................................................251
15.3.6 Hardware Breakpoints ...................................................................................................253
15.4 Register Definition ........................................................................................................................253
15.4.1 BDC Registers and Control Bits ....................................................................................253
15.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................254
15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................255
15.4.2 System Background Debug Force Reset Register (SBDFR) .........................................255
15.4.3 DBG Registers and Control Bits ...................................................................................256
15.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................256
15.4.3.2 Debug Comparator A Low Register (DBGCAL) .........................................256
15.4.3.3 Debug Comparator B High Register (DBGCBH) ........................................256
15.4.3.4 Debug Comparator B Low Register (DBGCBL) .........................................256
15.4.3.5 Debug FIFO High Register (DBGFH) ..........................................................257
15.4.3.6 Debug FIFO Low Register (DBGFL) ...........................................................257
15.4.3.7 Debug Control Register (DBGC) .................................................................258
15.4.3.8 Debug Trigger Register (DBGT) ..................................................................259
15.4.3.9 Debug Status Register (DBGS) ....................................................................260
Appendix A
Electrical Characteristics
A.1 Introduction ...................................................................................................................................261
A.2 Absolute Maximum Ratings ..........................................................................................................261
A.3 Thermal Characteristics .................................................................................................................262
A.4 Electrostatic Discharge (ESD) Protection Characteristics ............................................................263
A.5 DC Characteristics .........................................................................................................................263
MC9S08GB60A Data Sheet, Rev. 2
16 Freescale Semiconductor
Section Number Title Page
A.6 Supply Current Characteristics ......................................................................................................267
A.7 ATD Characteristics ......................................................................................................................271
A.8 Internal Clock Generation Module Characteristics .......................................................................273
A.8.1 ICG Frequency Specifications ........................................................................................274
A.9 AC Characteristics .........................................................................................................................275
A.9.1 Control Timing ...............................................................................................................276
A.9.2 Timer/PWM (TPM) Module Timing ..............................................................................277
A.9.3 SPI Timing ......................................................................................................................278
A.10 Flash Specifications .......................................................................................................................281
Appendix B
EB652: Migrating from the GB60 Series to the GB60A Series
B.1 Overview .......................................................................................................................................283
B.2 Flash Programming Voltage ..........................................................................................................283
B.3 Flash Block Protection: 60K Devices Only ..................................................................................283
B.4 Internal Clock Generator: High Gain Oscillator Option ...............................................................283
B.5 Internal Clock Generator: Low-Power Oscillator Maximum Frequency ......................................284
B.6 Internal Clock Generator: Loss-of-Clock Disable Option ............................................................284
B.7 System Device Identification Register ..........................................................................................285
Appendix C
Ordering Information and Mechanical Drawings
C.1 Ordering Information ....................................................................................................................287
C.2 Mechanical Drawings ....................................................................................................................288
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 17
Chapter 1
Device Overview
1.1 Overview
The MC9S08GBxxA/GTxxA are members of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types.
1.2 Features
Features have been organized to reflect:
• Standard features of the HCS08 Family
• Features of the MC9S08GBxxA/GTxxA MCU
1.2.1 Standard Features of the HCS08 Family
• 40-MHz HCS08 CPU (central processor unit)
• HC08 instruction set with added BGND instruction
• Background debugging system (see also Chapter 15, “Development Support”)
• Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two
more breakpoints in on-chip debug module)
• Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data. Debug module supports both tag and force
breakpoints.
• Support for up to 32 interrupt/reset sources
• Power-saving modes: wait plus three stops
• System protection features:
— Optional computer operating properly (COP) reset
— Low-voltage detection with reset or interrupt
— Illegal opcode detection with reset
— Illegal address detection with reset (some devices don’t have illegal addresses)
Chapter 1 Device Overview
MC9S08GB60A Data Sheet, Rev. 2
18 Freescale Semiconductor
1.2.2 Features of MC9S08GBxxA/GTxxA Series of MCUs
• On-chip in-circuit programmable flash memory:
— Fully read/write functional across voltage and temperature ranges
— Block protection and security options
— (see Table 1-1 for device-specific information)
• On-chip random-access memory (RAM) (see Table 1-1 for device specific information)
• 8-channel, 10-bit analog-to-digital converter (ATD)
• Two serial communications interface modules (SCI)
• Serial peripheral interface module (SPI)
• Multiple clock source options:
— Internally generated clock with ±0.2% trimming resolution and ±0.5% deviation across voltage
—Crystal
— Resonator
— External clock
• Inter-integrated circuit bus module to operate up to 100 kbps (IIC)
• One 3-channel and one 5-channel 16-bit timer/pulse width modulator (TPM) modules with
selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each
timer module may be configured for buffered, centered PWM (CPWM) on all channels (TPMx).
• 8-pin keyboard interrupt module (KBI)
• 16 high-current pins (limited by package dissipation)
• Software selectable pullups on ports when used as input. Selection is on an individual port bit basis.
During output mode, pullups are disengaged.
• Internal pullup on RESET and IRQ pin to reduce customer system cost
• Up to 56 general-purpose input/output (I/O) pins, depending on package selection
• 64-pin low-profile quad flat package (LQFP) — MC9S08GBxxA
• 48-pin quad flat package, no lead (QFN) — MC9S08GTxxA
• 44-pin quad flat package (QFP) — MC9S08GTxxA
• 42-pin skinny dual in-line package (SDIP) — MC9S08GTxxA
Chapter 1 Device Overview
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 19
1.2.3 Devices in the MC9S08GBxxA/GTxxA Series
Table 1-1 lists the devices available in the MC9S08GBxxA/GTxxA series and summarizes the differences
among them.
1.3 MCU Block Diagrams
These block diagrams show the structure of the MC9S08GBxxA/GTxxA MCUs.
Table 1-1. Devices in the MC9S08GBxxA/GTxxA Series
Device Flash RAM TPM I/O Packages
MC9S08GB60A 60K 4K One 3-channel and one
5-channel, 16-bit timer
56 64 LQFP
MC9S08GB32A 32K 2K One 3-channel and one
5-channel, 16-bit timer
56 64 LQFP
MC9S08GT60A 60K 4K Two 2-channel,
16-bit timers
39
36
33
48 QFN1
44 QFP
42 SDIP
1The 48-pin QFN package has one 3-channel and one 2-channel 16-bit TPM.
MC9S08GT32A 32K 2K Two 2-channel,
16-bit timers
39
36
33
48 QFN(1)
44 QFP
42 SDIP
Chapter 1 Device Overview
MC9S08GB60A Data Sheet, Rev. 2
20 Freescale Semiconductor
Figure 1-1. MC9S08GBxxA/GTxxA Block Diagram
PTD3/TPM2CH0
PTD4/TPM2CH1
PTD5/TPM2CH2
PTD6/TPM2CH3
PTC1/RxD2
PTC0/TxD2
VSS
VDD
PTE3/MISO1
PTE2/SS1
PTA7/KBI1P7–
PTE0/TxD1
PTE1/RxD1
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CH0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL1
PTC2/SDA1
PORT A
PORT C
PORT D
PORT E
8-BIT KEYBOARD
INTERRUPT MODULE
IIC MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
USER FLASH
USER RAM
(Gx60A = 4096 BYTES)
DEBUG
MODULE
(Gx60A = 61,268 BYTES)
HCS08 CORE
Note: Not all pins are bonded out in all packages. See Ta bl e 2- 2 for complete details.
3-CHANNEL TIMER/PWM
MODULE
PTB7/AD1P7–
PORT B
PTE5/SPSCK1
PTE4/MOSI1
PTE6
PTE7
INTERFACE MODULE
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
VOLTAGE
REGULATOR
RTI
SERIAL COMMUNICATIONS
COP
IRQ LVD
LOW-POWER OSCILLATOR
INTERNAL CLOCK
GENERATOR
RESET ANALOG-TO-DIGITAL
CONVERTER (10-BIT)
INTERFACE MODULE
SERIAL COMMUNICATIONS
5-CHANNEL TIMER/PWM
MODULE
PORT F
PTF7–PTF0
PTD7/TPM2CH4
8
PTA0/KBI1P0
8
PTB0/AD1P0
8
PTG3
PTG2/EXTAL
PTG0/BKGD/MS
PTG1/XTAL
PORT G
PTG7–PTG4
(Gx32A = 32,768 BYTES)
(Gx32A = 2048 BYTES)
CPU
(DBG)
(KBI1)
(ATD1)
(IIC1)
(SCI2)
(TPM2)
(TPM1)
(SPI1)
(SCI1)
(ICG)
8
8
SCL1
SDA1
SCL1
SCL1
5
3
SPSCK1
MOSI1
MISO1
SS1
RxD1
TxD1
VSSAD
VDDAD
VREFH
VREFL
EXTAL
XTAL
BKGD
BDC
4
= Not connected in 48-, 44-, and 42-pin packages
= Not connected in 44- and 42-pin packages
= Not connected in 42-pin packages
Block Diagram Symbol Key:
IRQ
Chapter 1 Device Overview
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 21
Table 1-2 lists the functional versions of the on-chip modules.
1.4 System Clock Distribution
Figure 1-2. System Clock Distribution Diagram
Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock
connection diagram. The ICG supplies the clock sources:
• ICGOUT is an output of the ICG module. It is one of the following:
— The external crystal oscillator
— An external clock source
— The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop
sub-module
Control bits inside the ICG determine which source is connected.
Table 1-2. Block Versions
Module Version
Analog-to-Digital Converter (ATD) 3
Internal Clock Generator (ICG) 2
Inter-Integrated Circuit (IIC) 1
Keyboard Interrupt (KBI) 1
Serial Communications Interface (SCI) 1
Serial Peripheral Interface (SPI) 3
Timer Pulse-Width Modulator (TPM) 1
Central Processing Unit (CPU) 2
ATD has min and max
frequency requirements. See
Chapter 1, “Device Overview” and
Appendix A, “Electrical Characteristics.
Flash has frequency
requirements for program
and erase operation.
See Appendix A, “Electrical
Characteristics.
* ICGLCLK is the alternate BDC clock source for the MC9S08GBxxA/GTxxA.
TPM1 TPM2 IIC1 SCI1 SCI2 SPI1
BDC
CPU ATD1 RAM FLASH
ICG
ICGOUT ÷2
FFE
SYSTEM
LOGIC
BUSCLK
ICGLCLK*
CONTROL
FIXED FREQ CLOCK (XCLK)
ICGERCLK RTI
÷2
Chapter 1 Device Overview
MC9S08GB60A Data Sheet, Rev. 2
22 Freescale Semiconductor
• FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency
of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK.
Otherwise the fixed-frequency clock will be BUSCLK.
• ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed
up BDC communications in systems where the bus clock is slow.
• ICGERCLK — External reference clock can be selected as the real-time interrupt clock source.
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 23
Chapter 2
Pins and Connections
2.1 Introduction
This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
24 Freescale Semiconductor
2.2 Device Pin Assignment
Figure 2-1. MC9S08GBxxA in 64-Pin LQFP Package
PTC3/SCL1
1
2
3
4
5
6
7
8
PTC0/TxD2
PTC1/RxD2
PTC4
PTC5
PTC6
PTC7
PTD0/TPM1CH0
VDD
VSS
PTE7
PTE6
PTE5/SPSCK1
PTE4/MOSI1
VREFH
VREFL
PTF5
PTF6
PTF7
PTB2/AD1P2
PTB7/AD1P7
PTA5/KBI1P5
PTF0
PTG6
VSSAD
VDDAD
PTF1
PTA2/KBI1P2
PTA6/KBI1P6
PTA7/KBI1P7
43
42
41
40
39
38
18
19
20 21 22 23
505152535455
17 32
33
49
48
64
9
PTF2
10
PTF3
11
PTF4
16
IRQ
PTD1/TPM1CH1
24
PTD2/TPM1CH2
25
PTD3/TPM2CH0
26
PTD4/TPM2CH1
27
PTB6/AD1P6
37
PTB5/AD1P5
36
PTB4/AD1P4
35
PTB3/AD1P3
34
PTG0/BKGD/MS
56
PTG1/XTAL
57
PTG2/EXTAL
58
PTG3
59
PTC2/SDA1
12
PTE0/TxD1
13
14
15
PTE1/RxD1
PTD5/TPM2CH2
28 29 30 31
PTA0/KBI1P0
44
45
46
PTA1/KBI1P1
47
PTG5
63 62 61
PTG4
60
RESET
PTG7
PTE2/SS1
PTE3/MISO1
PTD6/TPM2CH3
PTD7/TPM2CH4
PTB1/AD1P1
PTB0/AD1P0
PTA4/KBI1P4
PTA3/KBI1P3
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 25
Figure 2-2. MC9S08GTxxA in 48-Pin QFN Package
48
47
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
22
36
33
32
31
30
29
28
27
26
13
RESET
PTE0/TxD1
PTE1/RxD1
IRQ
PTC0/TxD2
PTC1/RxD2
PTC2/SDA1
PTC3/SCL1
PTC4
PTC5
PTC6
PTD1/TPM1CH1
PTD0/TPM1CH0
VDD
VSS1
PTE5/SPSCK1
PTE4/MOSI1
PTE3/MISO1
PTE2/SS1
PTD3/TPM2CH0
PTD4/TPM2CH1
PTB0/AD1P0
PTB6/AD1P6
PTB7/AD1P7
VREFH
VREFL
PTA0/KBI1P0
PTB2/AD1P2
PTB3/AD1P3
PTB1/AD1P1
PTB4/AD1P4
PTB5/AD1P5
PTA4/KBI1P4
PTA5/KBI1P5
VDDAD
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
VSSAD
PTA1/KBI1P1
PTA6/KBI1P6
PTA7/KBI1P7
PTA3/KBI1P3
PTA2/KBI1P2
24
23
25
35
34
37
38
12
PTC7
VSS2
PTD2/TPM1CH2
PTG3
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
26 Freescale Semiconductor
Figure 2-3. MC9S08GTxxA in 44-Pin QFP Package
44
34
43
42
41
40
39
38
37
36
35
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
12
23
RESET
PTE0/TxD1
PTE1/RxD1
IRQ
PTC0/TxD2
PTC1/RxD2
PTC2/SDA1
PTC3/SCL1
PTC4
PTC5
PTC6
PTD1/TPM1CH1
PTD0/TPM1CH0
VDD
VSS
PTE5/SPSCK1
PTE4/MOSI1
PTE3/MISO1
PTE2/SS1
PTD3/TPM2CH0
PTD4/TPM2CH1
PTB0/AD1P0
PTB6/AD1P6
PTB7/AD1P7
VREFH
VREFL
PTA0/KBI1P0
PTB2/AD1P2
PTB3/AD1P3
PTB1/AD1P1
PTB4/AD1P4
PTB5/AD1P5
PTA4/KBI1P4
PTA5/KBI1P5
VDDAD
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
VSSAD
PTA1/KBI1P1
PTA6/KBI1P6
PTA7/KBI1P7
PTA3/KBI1P3
PTA2/KBI1P2
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 27
Figure 2-4. . MC9S08GTxxA in 42-Pin SDIP Package
2.3 Recommended System Connections
Figure 2-4 shows pin connections that are common to almost all MC9S08GBxxA application systems.
MC9S08GTxxA connections will be similar except for the number of I/O pins available. A more detailed
discussion of system connections follows.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
IRQ
PTE1/RxD1
PTE0/TxD1
VDDAD
PTC2/SDA1
PTC3/SCL1
PTC4
PTB5/AD1P5
PTB6/AD1P6
PTB7/AD1P7
VREFH
VREFL
PTA0/KBI1P0
PTA1/KBI1P1
PTA2/KBI1P2
PTA4/KBI1P4
PTA3/KBI1P3
PTB4/AD1P4
PTA5/KBI1P5
PTA6/KBI1P6
PTA7/KBI1P7
VSSAD
PTG0/BKGD/MS
PTG1/XTAL
PTG2/EXTAL
RESET
PTC0/TxD2
PTC1/RXD2
15 28
PTE2/SS1PTB3/AD1P3
16 27
PTE3/MISO1 PTB2/AD1P2
17 26
PTE4/MOSI1 PTB1/AD1P1
18 25
PTE5/SPSCK1 PTB0/AD1P0
19 24
VSS PTD4/TPM2CH1
20 23
VDD PTD3/TPM2CH0
21 22
PTD0/TPM1CH0 PTD1/TPM1CH1
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
28 Freescale Semiconductor
Figure 2-5. Basic System Connections
V
DD
VDD
VSS
XTAL
EXTAL
BKGD/MS
RESET
OPTIONAL
MANUAL
RESET
PORT
A
V
DD
BACKGROUND HEADER
C2
C1 X1
RFRS
CBY
0.1 μF
CBLK
10 μF
+
3 V
+
SYSTEM
POWER
I/O AND
PERIPHERAL
INTERFACE TO
SYSTEM
APPLICATION
PTA0/KBI1P0
PTA1/KBI1P1
PTA2/KBI1P2
PTA3/KBI1P3
PTA4/KBI1P4
PTA5/KBI1P5
PTA6/KBI1P6
PTA7/KBI1P7
VDD
PORT
B
PTB0/AD1P0
PTB1/AD1P1
PTB2/AD1P2
PTB3/AD1P3
PTB4/AD1P4
PTB5/AD1P5
PTB6/AD1P6
PTB7/AD1P7
PORT
C
PTC0/TxD2
PTC1/RxD2
PTC2/SDA1
PTC3/SCL1
PTC4
PTC5
PTC6
PTC7
PORT
D
PTD0/TPM1CH0
PTD1/TPM1CH1
PTD2/TPM1CH2
PTD3/TPM2CH0
PTD4/TPM2CH1
PTD5/TPM2CH2
PTD6/TPM2CH3
PTD7/TPM2CH4
PORT
E
PTE0/TxD1
PTE1/RxD1
PTE2/SS1
PTE3/MISO1
PTE4/MOSI1
PTE5/SPSCK1
PTE6
PTE7
PORT
G
PTG0/BKDG/MS
PTG1/XTAL
PTG2/EXTAL
PTG3
PTG4
PTG5
PTG6
PTG7
PORT
F
PTF0
PTF1
PTF2
PTF3
PTF4
PTF5
PTF6
PTF7
IRQ
ASYNCHRONOUS
INTERRUPT
INPUT
NOTES:
1. Not required if using the
internal oscillator option.
2. These are the same pins as
PTG1 and PTG2.
3. BKGD/MS is the same pin
as PTG0.
4. The 48-pin QFN has 2 VSS
pins (VSS1 and VSS2), both
of which must be connected
to GND.
5. RC filters on RESET and
IRQ are recommended for
EMC-sensitive applications
NOTE 1
NOTE 2
NOTE 2
NOTE 3
MC9S08GBxxA/GTxxA
VDDAD
VSSAD
CBYAD
0.1 μF
VREFL
VREFH
NOTE 4
V
DD
4.7 k
Ω
–10 k
Ω
0.1
μ
F
4.7 k
Ω
–10 k
Ω
0.1
μ
F
NOTE 5
NOTE 5
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 29
2.3.1 Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-μF ceramic bypass capacitor located as close to the MCU power pins as
practical to suppress high-frequency noise.
VDDAD and VSSAD are the analog power supply pins for the MCU. This voltage source supplies power to
the ATD. A 0.1-μF ceramic bypass capacitor should be located as close to the MCU power pins as practical
to suppress high-frequency noise.
2.3.2 Oscillator
Out of reset, the MCU uses an internally generated clock (self-clocked mode — fSelf_reset), that is
approximately equivalent to an 8-MHz crystal rate. This frequency source is used during reset startup and
can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. This
MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU.
For more information on the ICG, see Chapter 7, “Internal Clock Generator (S08ICGV2).”
The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in
either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or
ceramic resonator, an external oscillator can be connected to the EXTAL input pin, and the XTAL output
pin can be used as general I/O.
Refer to Figure 2-4 for the following discussion. RS (when used) and RF should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to
humidity and lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C1 and C2 which are usually the same size. As a first-order approximation,
use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and
XTAL).
2.3.3 Reset
RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver,
and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
30 Freescale Semiconductor
debug connector so a development system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for approximately 34 cycles of fSelf_reset, released, and sampled again approximately 38
cycles of fSelf_reset later. If reset was caused by an internal source such as low-voltage reset or watchdog
timeout, the circuitry expects the reset pin sample to return a logic 1. The reset circuitry decodes the cause
of reset and records it by setting a corresponding bit in the system control reset status register (SRS).
In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-4 for
an example.
2.3.4 Background / Mode Select (PTG0/BKGD/MS)
The background/mode select (BKGD/MS) shares its function with an I/O port pin. While in reset, the pin
functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and
can be used for background debug communication. While functioning as a background/mode select pin,
the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew
rate control. When used as an I/O port (PTG0) the pin is limited to output only.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.3.5 General-Purpose I/O and Peripheral Ports
The remaining 55 pins are shared among general-purpose I/O and on-chip peripheral functions such as
timers and serial I/O systems. (17 of these pins are not bonded out on the 48-pin package, 20 of these pins
are not bonded out on the 44-pin package and 22 of hese pins are not bonded out on the 42-pin package.)
Immediately after reset, all 55 of these pins are configured as high-impedance general-purpose inputs with
internal pullup devices disabled.
NOTE
To prevent extra current drain from floating input pins, the reset
initialization routine in the application program should either enable
on-chip pullup devices or change the direction of unused pins to outputs so
the pins do not float.
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 31
For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate section from Table 2-1.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See Chapter 6, “Parallel Input/Output” for details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4
pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup
enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is configured
as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device
rather than a pullup device.
Table 2-1. Pin Sharing References
Port Pins Alternate
Function Reference1
1See this section for information about modules that share these pins.
PTA7–PTA0 KBI1P7–KBI1P0 Chapter 2, “Pins and Connections”
PTB7–PTB0 AD1P7–AD1P0 Chapter 14, “Analog-to-Digital Converter (S08ATDV3)”
PTC7–PTC4 — Chapter 6, “Parallel Input/Output”
PTC3–PTC2 SCL1–SDA1 Chapter 13, “Inter-Integrated Circuit (S08IICV1)”
PTC1–PTC0 RxD2–TxD2 Chapter 11, “Serial Communications Interface (S08SCIV1)”
PTD7–PTD3 TPM2CH4–
TPM2CH0 Chapter 10, “Timer/PWM (S08TPMV1)”
PTD2–PTD0 TPM1CH2–
TPM1CH0 Chapter 10, “Timer/PWM (S08TPMV1)”
PTE7–PTE6 — Chapter 6, “Parallel Input/Output”
PTE5
PTE4
PTE3
PTE2
SPSCK1
MISO1
MOSI1
SS1
Chapter 12, “Serial Peripheral Interface (S08SPIV3)”
PTE1–PTE0 RxD1–TxD1 Chapter 11, “Serial Communications Interface (S08SCIV1)”
PTF7–PTF0 — Chapter 6, “Parallel Input/Output”
PTG7–PTG3 — Chapter 6, “Parallel Input/Output”
PTG2–PTG1 EXTAL–XTAL Chapter 7, “Internal Clock Generator (S08ICGV2)”
PTG0 BKGD/MS Chapter 15, “Development Support”
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
32 Freescale Semiconductor
2.3.6 Signal Properties Summary
Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the
common pin interfaces are hardwired to internal circuits.
Table 2-2. Signal Properties
Pin
Name Dir High Current
Pin
Output
Slew 1Pull-Up2Comments
VDD ———
VSS ———
The 48-pin QFN package has two VSS pins — VSS1
and VSS2.
VDDAD ———
VSSAD ———
VREFH ———
VREFL ———
RESET I/O Y N Y Pin contains integrated pullup.
IRQ I— — Y
IRQPE must be set to enable IRQ function.
IRQ does not have a clamp diode to VDD. IRQ should
not be driven above VDD.
Pullup/pulldown active when IRQ pin function
enabled. Pullup forced on when IRQ enabled for
falling edges; pulldown forced on when IRQ enabled
for rising edges.
PTA0/KBI1P0 I/O N SWC SWC
PTA1/KBI1P1 I/O N SWC SWC
PTA2/KBI1P2 I/O N SWC SWC
PTA3/KBI1P3 I/O N SWC SWC
PTA4/KBI1P4 I/O N SWC SWC Pullup/pulldown active when KBI pin function
enabled. Pullup forced on when KBI1Px enabled for
falling edges; pulldown forced on when KBI1Px
enabled for rising edges.
PTA5/KBI1P5 I/O N SWC SWC
PTA6/KBI1P6 I/O N SWC SWC
PTA7/KBI1P7 I/O N SWC SWC
PTB0/AD1P0 I/O N SWC SWC
PTB1/AD1P1 I/O N SWC SWC
PTB2/AD1P2 I/O N SWC SWC
PTB3/AD1P3 I/O N SWC SWC
PTB4/AD1P4 I/O N SWC SWC
PTB5/AD1P5 I/O N SWC SWC
PTB6/AD1P6 I/O N SWC SWC
PTB7/AD1P7 I/O N SWC SWC
PTC0/TxD2 I/O Y SWC SWC When pin is configured for SCI function, pin is
configured for partial output drive.
PTC1/RxD2 I/O Y SWC SWC
PTC2/SDA1 I/O Y SWC SWC
PTC3/SCL1 I/O Y SWC SWC
PTC4 I/O Y SWC SWC
PTC5 I/O Y SWC SWC Not available on 42-pin package
PTC6 I/O Y SWC SWC Not available on 42-pin package
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 33
PTC7 I/O Y SWC SWC Not available on 42-pin package
PTD0/TPM1CH0 I/O N SWC SWC
PTD1/TPM1CH1 I/O N SWC SWC
PTD2/TPM1CH2 I/O N SWC SWC Not available on 42-pin , or 44-pin package
PTD3/TPM2CH0 I/O N SWC SWC
PTD4/TPM2CH1 I/O N SWC SWC
PTD5/TPM2CH2 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package
PTD6/TPM2CH3 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package
PTD7/TPM2CH4 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package
PTE0/TxD1 I/O N SWC SWC
PTE1/RxD1 I/O N SWC SWC
PTE2/SS1I/O N SWC SWC
PTE3/MISO1 I/O N SWC SWC
PTE4/MOSI1 I/O N SWC SWC
PTE5/SPSCK1 I/O N SWC SWC
PTE6 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package
PTE7 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package
PTF0 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package
PTF1 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package
PTF2 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package
PTF3 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package
PTF4 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package
PTF5 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package
PTF6 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package
PTF7 I/O Y SWC SWC Not available on 42-, 44-, or 48-pin package
PTG0/BKGD/MS O N SWC SWC Pullup enabled and slew rate disabled when BDM
function enabled.
PTG1/XTAL I/O N SWC SWC Pullup and slew rate disabled when XTAL pin
function.
PTG2/EXTAL I/O N SWC SWC Pullup and slew rate disabled when EXTAL pin
function.
PTG3 I/O N SWC SWC Not available on 42- or 44-pin package
PTG4 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package
PTG5 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package
PTG6 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package
PTG7 I/O N SWC SWC Not available on 42-, 44-, or 48-pin package
1SWC is software controlled slew rate, the register is associated with the respective port.
2SWC is software controlled pullup resistor, the register is associated with the respective port.
Table 2-2. Signal Properties (continued)
Pin
Name Dir High Current
Pin
Output
Slew 1Pull-Up2Comments
Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
34 Freescale Semiconductor
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 35
Chapter 3
Modes of Operation
3.1 Introduction
The operating modes of the MC9S08GBxxA/GTxxA are described in this section. Entry into each mode,
exit from each mode, and functionality while in each of the modes are described.
3.2 Features
• Active background mode for code development
• Wait mode:
— CPU shuts down to conserve power
— System clocks running
— Full voltage regulation maintained
• Stop modes:
— System clocks stopped; voltage regulator in standby
— Stop1 — Full power down of internal circuits for maximum power savings
— Stop2 — Partial power down of internal circuits, RAM contents retained
— Stop3 — All internal circuits powered for fast recovery
3.3 Run Mode
This is the normal operating mode for the MC9S08GBxxA/GTxxA. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset.
3.4 Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
• When the BKGD/MS pin is low at the rising edge of reset
• When a BACKGROUND command is received through the BKGD pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
Chapter 3 Modes of Operation
MC9S08GB60A Data Sheet, Rev. 2
36 Freescale Semiconductor
• When encountering a DBG breakpoint
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user’s application program.
Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed while the MCU is in the active background
mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can be executed only while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user’s application program (GO)
The active background mode is used to program a bootloader or user application program into the flash
program memory before the MCU is operated in run mode for the first time. When the
MC9S08GBxxA/GTxxA is shipped from the Freescale Semiconductor factory, the flash program memory
is erased by default unless specifically noted so there is no program that could be executed in run mode
until the flash memory is initially programmed. The active background mode can also be used to erase and
reprogram the flash memory after it has been previously programmed.
For additional information about the active background mode, refer to Chapter 15, “Development Support.
3.5 Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
3.6 Stop Modes
One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the
system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set
Chapter 3 Modes of Operation
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 37
when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal
opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
Table 3-1 summarizes the behavior of the MCU in each of the stop modes.
3.6.1 Stop1 Mode
The stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry
of the MCU to be powered down. Stop1 can be entered only if the LVD circuit is not enabled in stop modes
(either LVDE or LVDSE not set).
When the MCU is in stop1 mode, all internal circuits that are powered from the voltage regulator are turned
off. The voltage regulator is in a low-power standby state, as is the ATD.
Exit from stop1 is performed by asserting either of the wake-up pins on the MCU: RESET or IRQ. IRQ is
always an active low input when the MCU is in stop1, regardless of how it was configured before entering
stop1.
Entering stop1 mode automatically asserts LVD. Stop1 cannot be exited until VDD > VLVDH /L rising (VDD
must rise above the LVI rearm voltage).
Upon wake-up from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will
take the reset vector.
3.6.2 Stop2 Mode
The stop2 mode provides very low standby power consumption and maintains the contents of RAM and
the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in stop
modes (either LVDE or LVDSE not set).
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other
memory-mapped registers they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2,
these values can be restored by user software before pin latches are opened.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned
off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ATD. Upon entry
Table 3-1. Stop Mode Behavior
Mode PDC PPDC
CPU, Digital
Peripherals,
Flash
RAM ICG ATD Regulator I/O Pins RTI
Stop1 1 0 Off Off Off Disabled1
1Either ATD stop mode or power-down mode depending on the state of ATDPU.
Off Reset Off
Stop2 1 1 Off Standby Off Disabled Standby States held Optionally on
Stop3 0 Don’t
care
Standby Standby Off2
2Crystal oscillator can be configured to run in stop3. Please see the ICG registers.
Disabled Standby States held Optionally on
Chapter 3 Modes of Operation
MC9S08GB60A Data Sheet, Rev. 2
38 Freescale Semiconductor
into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting
stop2 mode until a 1 is written to PPDACK in SPMSC2.
Exit from stop2 is performed by asserting either of the wake-up pins: RESET or IRQ, or by an RTI
interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured
before entering stop2.
Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written
to PPDACK in SPMSC2.
To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the
contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to
the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the
register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch
to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3 Stop3 Mode
Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The
ICG is turned off, the ATD is disabled, and the voltage regulator is put in standby. The states of all of the
internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched
at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the
pins being maintained.
Exit from stop3 is performed by asserting RESET, an asynchronous interrupt pin, or through the real-time
interrupt. The asynchronous interrupt pins are the IRQ or KBI pins.
If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
Chapter 3 Modes of Operation
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 39
3.6.4 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the Chapter 15, “Development Support,” section of this data sheet. If ENBDM
is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain
active when the MCU enters stop mode so background debug communication is still possible. In addition,
the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If
the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After the device enters background debug mode, all
background commands are available. The table below summarizes the behavior of the MCU in stop when
entry into the background debug mode is enabled.
3.6.5 LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in SPMSC1 when
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the
user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE = 1), the MCU will
instead enter stop3. The table below summarizes the behavior of the MCU in stop when the LVD is
enabled.
3.6.6 On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
Table 3-2. BDM Enabled Stop Mode Behavior
Mode PDC PPDC
CPU, Digital
Peripherals,
Flash
RAM ICG ATD Regulator I/O Pins RTI1
1The 1 kHz internal RTI clock is not available in stop3 with active BDM enabled.
Stop3 Don’t
care
Don’t
care
Standby Standby Active Disabled2
2Either ATD stop mode or power-down mode depending on the state of ATDPU.
Active States held Optionally on
Table 3-3. LVD Enabled Stop Mode Behavior
Mode PDC PPDC
CPU, Digital
Peripherals,
Flash
RAM ICG ATD Regulator I/O Pins RTI
Stop3 Don’t
care
Don’t
care
Standby Standby Standby Disabled1
1Either ATD stop mode or power-down mode depending on the state of ATDPU.
Active States held Optionally on
Chapter 3 Modes of Operation
MC9S08GB60A Data Sheet, Rev. 2
40 Freescale Semiconductor
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop1
Mode,” Section 3.6.2, “Stop2 Mode,” and Section 3.6.3, “Stop3 Mode,” for specific information on
system behavior in stop modes.
I/O Pins
• All I/O pin states remain unchanged when the MCU enters stop3 mode.
• If the MCU is configured to go into stop2 mode, all I/O pins states are latched before entering stop.
• If the MCU is configured to go into stop1 mode, all I/O pins are forced to their default reset state
upon entry into stop.
Memory
• All RAM and register contents are preserved while the MCU is in stop3 mode.
• All registers will be reset upon wake-up from stop2, but the contents of RAM are preserved and
pin states remain latched until the PPDACK bit is written. The user may save any memory-mapped
register data into RAM before entering stop2 and restore the data upon exit from stop2.
• All registers will be reset upon wake-up from stop1 and the contents of RAM are not preserved.
The MCU must be initialized as upon reset. The contents of the flash memory are nonvolatile and
are preserved in any of the stop modes.
ICG — In stop3 mode, the ICG enters its low-power standby state. Either the oscillator or the internal
reference may be kept running when the ICG is in standby by setting the appropriate control bit. In both
stop2 and stop1 modes, the ICG is turned off. Neither the oscillator nor the internal reference can be kept
running in stop2 or stop1, even if enabled within the ICG module.
TPM — When the MCU enters stop mode, the clock to the TPM1 and TPM2 modules stop. The modules
halt operation. If the MCU is configured to go into stop2 or stop1 mode, the TPM modules will be reset
upon wake-up from stop and must be reinitialized.
ATD — When the MCU enters stop mode, the ATD will enter a low-power standby state. No conversion
operation will occur while in stop. If the MCU is configured to go into stop2 or stop1 mode, the ATD will
be reset upon wake-up from stop and must be reinitialized.
KBI — During stop3, the KBI pins that are enabled continue to function as interrupt sources that are
capable of waking the MCU from stop3. The KBI is disabled in stop1 and stop2 and must be reinitialized
after waking up from either of these modes.
RTI — During stop2 and stop3, the RTI continues to operate as an interrupt wakeup source. During stop1,
the RTI is disabled. In stop2, the RTI uses the internal 1 kHz RTI clock, but in stop3 mode, the RTI uses
either the external clock or the internal RTI clock. When the active BDM mode is enabled though, the
internal RTI clock is not operational.
SCI — When the MCU enters stop mode, the clocks to the SCI1 and SCI2 modules stop. The modules
halt operation. If the MCU is configured to go into stop2 or stop1 mode, the SCI modules will be reset
upon wake-up from stop and must be reinitialized.
SPI — When the MCU enters stop mode, the clocks to the SPI module stop. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wake-up from
stop and must be reinitialized.
Chapter 3 Modes of Operation
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 41
IIC — When the MCU enters stop mode, the clocks to the IIC module stops. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from
stop and must be reinitialized.
Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any
of the stop modes unless the LVD is enabled in stop mode or BDM is enabled.
Chapter 3 Modes of Operation
MC9S08GB60A Data Sheet, Rev. 2
42 Freescale Semiconductor
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 43
Chapter 4
Memory
4.1 MC9S08GBxxA/GTxxA Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08GBxxA/GTxxA series of MCUs consists of
RAM, flash program memory for nonvolatile data storage, plus I/O and control/status registers. The
registers are divided into three groups:
• Direct-page registers (0x0000 through 0x007F)
• High-page registers (0x1800 through 0x182B)
• Nonvolatile registers (0xFFB0 through 0xFFBF)
Figure 4-1. MC9S08GBxxA/GTxxA Memory Map
DIRECT PAGE REGISTERS
RAM
FLASH
HIGH PAGE REGISTERS
FLASH
4096 BYTES
1920 BYTES
59348 BYTES
0x0000
0x007F
0x0080
0x107F
0x1800
0x17FF
0x182B
0x182C
0xFFFF
0x1080
DIRECT PAGE REGISTERS
RAM
HIGH PAGE REGISTERS
FLASH
32768 BYTES
0x0000
0x007F
0x0080
0x087F
0x1800
0x17FF
0x182B
0x182C
0xFFFF
0x0880
2048 BYTES
UNIMPLEMENTED
26580 BYTES
UNIMPLEMENTED
3968 BYTES
0x8000
0x7FFF
MC9S08GB60A/MC9S08GT60A MC9S08GB32A/MC9S08GT32A
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
44 Freescale Semiconductor
4.1.1 Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale-provided equate file for the MC9S08GBxxA/GTxxA. For more details
about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets,
Interrupts, and System Configuration.”
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low) Vector Vector Name
0xFFC0:FFC1
0xFFCA:FFCB
Unused Vector Space
(available for user program)
0xFFCC:FFCD RTI Vrti
0xFFCE:FFCF IIC Viic1
0xFFD0:FFD1 ATD Conversion Vatd1
0xFFD2:FFD3 Keyboard Vkeyboard1
0xFFD4:FFD5 SCI2 Transmit Vsci2tx
0xFFD6:FFD7 SCI2 Receive Vsci2rx
0xFFD8:FFD9 SCI2 Error Vsci2err
0xFFDA:FFDB SCI1 Transmit Vsci1tx
0xFFDC:FFDD SCI1 Receive Vsci1rx
0xFFDE:FFDF SCI1 Error Vsci1err
0xFFE0:FFE1 SPI Vspi1
0xFFE2:FFE3 TPM2 Overflow Vtpm2ovf
0xFFE4:FFE5 TPM2 Channel 4 Vtpm2ch4
0xFFE6:FFE7 TPM2 Channel 3 Vtpm2ch3
0xFFE8:FFE9 TPM2 Channel 2 Vtpm2ch2
0xFFEA:FFEB TPM2 Channel 1 Vtpm2ch1
0xFFEC:FFED TPM2 Channel 0 Vtpm2ch0
0xFFEE:FFEF TPM1 Overflow Vtpm1ovf
0xFFF0:FFF1 TPM1 Channel 2 Vtpm1ch2
0xFFF2:FFF3 TPM1 Channel 1 Vtpm1ch1
0xFFF4:FFF5 TPM1 Channel 0 Vtpm1ch0
0xFFF6:FFF7 ICG Vicg
0xFFF8:FFF9 Low Voltage Detect Vlvd
0xFFFA:FFFB IRQ Virq
0xFFFC:FFFD SWI Vswi
0xFFFE:FFFF Reset Vreset
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 45
4.2 Register Addresses and Bit Assignments
The registers in the MC9S08GBxxA/GTxxA are divided into these three groups:
• Direct-page registers are located in the first 128 locations in the memory map, so they are
accessible with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and variables.
• The nonvolatile register area consists of a block of 16 locations in flash memory at
0xFFB0–0xFFBF.
Nonvolatile register locations include:
— Three values which are loaded into working registers at reset
— An 8-byte backdoor comparison key which optionally allows a user to gain controlled access
to secure memory
Because the nonvolatile register locations are flash memory, they must be erased and programmed
like other flash memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only
requires the lower byte of the address. Because of this, the lower byte of the address in column one is
shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In
Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart
from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with
a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
46 Freescale Semiconductor
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
AddressRegister NameBit 7654321Bit 0
0x0000 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
0x0001 PTAPE PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
0x0002 PTASE PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
0x0003 PTADD PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
0x0004 PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
0x0005 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
0x0006 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
0x0007 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
0x0008 PTCD PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
0x0009 PTCPE PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
0x000A PTCSE PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
0x000B PTCDD PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
0x000C PTDD PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
0x000D PTDPE PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
0x000E PTDSE PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
0x000F PTDDD PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
0x0010 PTED PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
0x0011 PTEPE PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
0x0012 PTESE PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
0x0013 PTEDD PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
0x0014 IRQSC 00 IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD
0x0015 Reserved ————————
0x0016 KBI1SC KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBF KBACK KBIE KBIMOD
0x0017 KBI1PE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
0x0018 SCI1BDH 000 SBR12 SBR11 SBR10 SBR9 SBR8
0x0019 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
0x001A SCI1C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
0x001B SCI1C2 TIE TCIE RIE ILIE TE RE RWU SBK
0x001C SCI1S1 TDRE TC RDRF IDLE OR NF FE PF
0x001D SCI1S2 0000000RAF
0x001E SCI1C3 R8 T8 TXDIR 0 ORIE NEIE FEIE PEIE
0x001F SCI1D Bit 7654321Bit 0
0x0020 SCI2BDH 000 SBR12 SBR11 SBR10 SBR9 SBR8
0x0021 SCI2BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
0x0022 SCI2C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
0x0023 SCI2C2 TIE TCIE RIE ILIE TE RE RWU SBK
0x0024 SCI2S1 TDRE TC RDRF IDLE OR NF FE PF
0x0025 SCI2S2 0000000RAF
0x0026 SCI2C3 R8 T8 TXDIR 0 ORIE NEIE FEIE PEIE
0x0027 SCI2D Bit 7654321Bit 0
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 47
0x0028 SPI1C1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
0x0029 SPI1C2 000 MODFEN BIDIROE 0 SPISWAI SPC0
0x002A SPI1BR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0
0x002B SPI1S SPRF 0 SPTEF MODF 0 0 0 0
0x002C Reserved 00000000
0x002D SPI1D Bit 7654321Bit 0
0x002E Reserved 00000000
0x002F Reserved 00000000
0x0030 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0031 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0032 TPM1CNTL Bit 7654321Bit 0
0x0033 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0034 TPM1MODL Bit 7654321Bit 0
0x0035 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x0036 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0037 TPM1C0VL Bit 7654321Bit 0
0x0038 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x0039 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x003A TPM1C1VL Bit 7654321Bit 0
0x003B TPM1C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0
0x003C TPM1C2VH Bit 15 14 13 12 11 10 9 Bit 8
0x003D TPM1C2VL Bit 7654321Bit 0
0x003E–
0x003F Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x0040 PTFD PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
0x0041 PTFPE PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
0x0042 PTFSE PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
0x0043 PTFDD PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
0x0044 PTGD PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
0x0045 PTGPE PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
0x0046 PTGSE PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
0x0047 PTGDD PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
0x0048 ICGC1 HGO RANGE REFS CLKS OSCSTEN LOCD 0
0x0049 ICGC2 LOLRE MFD LOCRE RFD
0x004A ICGS1 CLKST REFST LOLS LOCK LOCS ERCS ICGIF
0x004B ICGS2 0000000 DCOS
0x004C ICGFLTU 0000FLT
0x004D ICGFLTL FLT
0x004E ICGTRM TRIM
0x004F Reserved 00000000
Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)
AddressRegister NameBit 7654321Bit 0
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
48 Freescale Semiconductor
0x0050 ATD1C ATDPU DJM RES8 SGN PRS
0x0051 ATD1SC CCF ATDIE ATDCO ATDCH
0x0052 ATD1RH Bit 7654321Bit 0
0x0053 ATD1RL Bit 7654321Bit 0
0x0054 ATD1PE ATDPE7 ATDPE6 ATDPE5 ATDPE4 ATDPE3 ATDPE2 ATDPE1 ATDPE0
0x0055–
0x0057 Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x0058 IIC1A ADDR 0
0x0059 IIC1F MULT ICR
0x005A IIC1C IICEN IICIE MST TX TXAK RSTA 0 0
0x005B IIC1S TCF IAAS BUSY ARBL 0 SRW IICIF RXAK
0x005C IIC1D DATA
0x005D–
0x005F Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x0060 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0061 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0062 TPM2CNTL Bit 7654321Bit 0
0x0063 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0064 TPM2MODL Bit 7654321Bit 0
0x0065 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x0066 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0067 TPM2C0VL Bit 7654321Bit 0
0x0068 TPM2C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x0069 TPM2C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x006A TPM2C1VL Bit 7654321Bit 0
0x006B TPM2C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0
0x006C TPM2C2VH Bit 15 14 13 12 11 10 9 Bit 8
0x006D TPM2C2VL Bit 7654321Bit 0
0x006E TPM2C3SC CH3F CH3IE MS3B MS3A ELS3B ELS3A 0 0
0x006F TPM2C3VH Bit 15 14 13 12 11 10 9 Bit 8
0x0070 TPM2C3VL Bit 7654321Bit 0
0x0071 TPM2C4SC CH4F CH4IE MS4B MS4A ELS4B ELS4A 0 0
0x0072 TPM2C4VH Bit 15 14 13 12 11 10 9 Bit 8
0x0073 TPM2C4VL Bit 7654321Bit 0
0x0074–
0x007F Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
AddressRegister NameBit 7654321Bit 0
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 49
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
Nonvolatile flash registers, shown in Table 4-4, are located in the flash memory. These registers include
an 8-byte backdoor key which optionally can be used to gain access to secure memory resources. During
reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the flash memory
are transferred into corresponding FPROT and FOPT working registers in the high-page registers to
control security and block protection options.
Table 4-3. High-Page Register Summary
AddressRegister NameBit 7654321Bit 0
0x1800 SRS POR PIN COP ILOP 0ICG LVD 0
0x1801 SBDFR 0000000BDFR
0x1802 SOPT COPE COPT STOPE — 0 0 BKGDPE —
0x1803 –
0x1805 Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1806 SDIDH REV3 REV2 REV1 REV0 ID11 ID10 ID9 ID8
0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
0x1808 SRTISC RTIF RTIACK RTICLKS RTIE 0 RTIS2 RTIS1 RTIS0
0x1809 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0 0
0x180A SPMSC2 LVWF LVWACK LVDV LVWV PPDF PPDACK PDC PPDC
0x180B–
0x180F Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1810 DBGCAH Bit 15 14 13 12 11 10 9 Bit 8
0x1811 DBGCAL Bit 7654321Bit 0
0x1812 DBGCBH Bit 15 14 13 12 11 10 9 Bit 8
0x1813 DBGCBL Bit 7654321Bit 0
0x1814 DBGFH Bit 15 14 13 12 11 10 9 Bit 8
0x1815 DBGFL Bit 7654321Bit 0
0x1816 DBGC DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN
0x1817 DBGT TRGSEL BEGIN 00 TRG3 TRG2 TRG1 TRG0
0x1818 DBGS AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0
0x1819–
0x181F Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1820 FCDIV DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
0x1821 FOPT KEYEN FNORED 0000 SEC01 SEC00
0x1822 Reserved ————————
0x1823 FCNFG 00 KEYACC 00000
0x1824 FPROT FPOPEN FPDIS FPS2 FPS1 FPS0 0 0 0
0x1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
0x1826 FCMD FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0
0x1827–
0x182B Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
50 Freescale Semiconductor
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the flash if needed (normally through the background
debug interface) and verifying that flash is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC01:SEC00) to the unsecured state (1:0).
4.3 RAM
The MC9S08GBxxA/GTxxA includes static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after
wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided
that the supply voltage does not drop below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08GBxxA/GTxxA, it is usually best to re-initialize the stack pointer to the top of the RAM so the
direct page RAM can be used for frequently accessed RAM variables and bit-addressable program
variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast
is equated to the highest address of the RAM in the Freescale-provided equate file).
LDHX #RamLast+1 ;point one past RAM
TXS ;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See Section 4.5, “Security” for a detailed
description of the security feature.
4.4 Flash
The flash memory is intended primarily for program storage. In-circuit programming allows the operating
program to be loaded into the flash memory after final assembly of the application product. It is possible
Table 4-4. Nonvolatile Register Summary
AddressRegister NameBit 7654321Bit 0
0xFFB0 –
0xFFB7
NVBACKKEY 8-Byte Comparison Key
0xFFB8 –
0xFFBC
Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0xFFBD NVPROT FPOPEN FPDIS FPS2 FPS1 FPS0 0 0 0
0xFFBE Reserved1
1This location is used to store the factory trim value for the ICG.
————————
0xFFBF NVOPT KEYEN FNORED 0000 SEC01 SEC00
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 51
to program the entire array through the single-wire background debug interface. Because no special
voltages are needed for flash erase and programming operations, in-application programming is also
possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1/D.
4.4.1 Features
Features of the flash memory include:
•Flash Size
— MC9S08GB60A/MC9S08GT60A — 61268 bytes (120 pages of 512 bytes each)
— MC9S08GB32A/MC9S08GT32A— 32768 bytes (64 pages of 512 bytes each)
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection
• Security feature for flash and RAM
• Auto power-down for low-frequency read accesses
4.4.2 Program and Erase Times
Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be
written to set the internal clock for the flash module to a frequency (fFCLK) between 150 kHz and 200 kHz
(see Table 4.6.1). This register can be written only once, so normally this write is done during reset
initialization. FCDIV cannot be written if the access error flag, FACCERR in FSTAT, is set. The user must
ensure that FACCERR is not set before writing to the FCDIV register. One period of the resulting clock
(1/fFCLK) is used by the command processor to time program and erase pulses. An integer number of these
timing pulses is used by the command processor to complete a program or erase command.
Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK =1/f
FCLK. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where tFCLK =5μs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-5. Program and Erase Times
Parameter Cycles of FCLK Time if FCLK = 200 kHz
Byte program 9 45 μs
Byte program (burst) 4 20 μs1
1Excluding start/end overhead
Page erase 4000 20 ms
Mass erase 20,000 100 ms
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
52 Freescale Semiconductor
4.4.3 Program and Erase Command Execution
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and
any error flags cleared before beginning command execution. The command execution steps are:
1. Write a data value to an address in the flash array. The address and data information from this write
is latched into the flash interface. This write is a required first step in any command sequence. For
erase and blank check commands, the value of the data is not important. For page erase commands,
the address may be any address in the 512-byte page of flash to be erased. For mass erase and blank
check commands, the address can be any address in the flash memory. Whole pages of 512 bytes
are the smallest blocks of flash that may be erased. In the 60K version, there are two instances
where the size of a block that is accessible to the user is less than 512 bytes: the first page following
RAM, and the first page following the high page registers. These pages are overlapped by the RAM
and high page registers, respectively.
NOTE
Do not program any byte in the flash more than once after a successful erase
operation. Reprogramming bits in a byte which is already programmed is
not allowed without first erasing the page in which the byte resides or mass
erasing the entire flash memory. Programming without first erasing may
disturb data stored in the flash.
2. Write the command code for the desired command to FCMD. The five valid commands are blank
check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase
(0x41). The command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to
the memory array and before writing the 1 that clears FCBEF and launches the complete command.
Aborting a command in this way sets the FACCERR access error flag which must be cleared before
starting a new command.
A strictly monitored procedure must be adhered to, or the command will not be accepted. This minimizes
the possibility of any unintended change to the flash memory contents. The command complete flag
(FCCF) indicates when a command is complete. The command sequence must be completed by clearing
FCBEF to launch the command. Figure 4-2 is a flowchart for executing all of the commands except for
burst programming. The FCDIV register must be initialized before using any flash commands. This must
be done only once following a reset.
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 53
Figure 4-2. Flash Program and Erase Flowchart
4.4.4 Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the flash array
does not need to be disabled between program operations. Ordinarily, when a program or erase command
is issued, an internal charge pump associated with the flash memory must be enabled to supply high
voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst
program command is issued, the charge pump is enabled and then remains enabled after completion of the
burst program operation if the following two conditions are met:
1. The next burst program command has been queued before the current program operation has
completed.
2. The next sequential address selects a byte on the same physical row as the current byte being
programmed. A row of flash memory consists of 64 bytes. A byte within a row is selected by
addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero.
The first byte of a series of sequential bytes being programmed in burst mode will take the same amount
of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
NO
YES
FPVIO OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (2)
1
0
FCCF ?
ERROR EXIT
DONE
(2) Wait at least four bus cycles before
checking FCBEF or FCCF.
0
FACCERR ?
CLEAR ERROR
FACCERR ?
WRITE TO FCDIV(1) (1) Only required once
after reset.
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
54 Freescale Semiconductor
program time provided that the conditions above are met. In the case the next sequential address is the
beginning of a new row, the program time for that byte will be the standard time instead of the burst time.
This is because the high voltage to the array must be disabled and then enabled again. If a new burst
command has not been queued before the current command completes, then the charge pump will be
disabled and high voltage removed from the array.
Figure 4-3. Flash Burst Program Flowchart
1
0
FCBEF ?
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
NO
YES
FPVIO OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (2)
NO
YES
NEW BURST COMMAND ?
1
0
FCCF ?
ERROR EXIT
DONE
(2) Wait at least four bus cycles before
checking FCBEF or FCCF.
1
0
FACCERR ?
CLEAR ERROR
FACCERR ?
WRITE TO FCDIV(1) (1) Only required once
after reset.
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 55
4.4.5 Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
• Writing to a flash address before the internal flash clock frequency has been set by writing to the
FCDIV register
• Writing to a flash address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
• Writing a second time to a flash address before launching the previous command (There is only
one write to flash for every command.)
• Writing a second time to FCMD before launching the previous command (There is only one write
to FCMD for every command.)
• Writing to any flash control register other than FCMD after writing to a flash address
• Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41)
to FCMD
• Accessing (read or write) any flash control register other than the write to FSTAT (to clear FCBEF
and launch the command) after writing the command to FCMD
• The MCU enters stop mode while a program or erase command is in progress (The command is
aborted.)
• Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with
a background debug command while the MCU is secured (The background debug controller can
only do blank check and mass erase commands when the MCU is secure.)
• Writing 0 to FCBEF to cancel a partial command
4.4.6 Flash Block Protection
Block protection prevents program or erase changes for flash memory locations in a designated address
range. Mass erase is disabled when any block of flash is protected. The MC9S08GBxxA/GTxxA allows a
block of memory at the end of flash, and/or the entire flash memory to be block protected. A disable control
bit and a 3-bit control field, allows the user to set the size of this block. A separate control bit allows block
protection of the entire flash memory array. All seven of these control bits are located in the FPROT
register (see Section 4.6.4, “Flash Protection Register (FPROT and NVPROT)”).
At reset, the high-page register (FPROT) is loaded with the contents of the NVPROT location which is in
the nonvolatile register block of the flash memory. The value in FPROT cannot be changed directly from
application software so a runaway program cannot alter the block protection settings. If the last 512 bytes
of flash which includes the NVPROT register is protected, the application program cannot alter the block
protection settings (intentionally or unintentionally). The FPROT control bits can be written by
background debug commands to allow a way to erase a protected flash memory.
One use for block protection is to block protect an area of flash memory for a bootloader program. This
bootloader program then can be used to erase the rest of the flash memory and reprogram it. Because the
bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and
reprogram operation.
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
56 Freescale Semiconductor
4.4.7 Vector Redirection
Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector
redirection allows users to modify interrupt vector information without unprotecting bootloader and reset
vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register
located at address 0xFFBF to zero. For redirection to occur, at least some portion but not all of the flash
memory must be block protected by programming the NVPROT register located at address 0xFFBD. All
of the interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, while the reset vector
(0xFFFE:FFFF) is not. When more than 32K is protected, vector redirection must not be enabled.
For example, if 512 bytes of flash are protected, the protected address region is from 0xFE00 through
0xFFFF. The interrupt vectors (0xFFC0–0xFFFD) are redirected to the locations 0xFDC0–0xFDFD. Now,
if an SPI interrupt is taken for instance, the values in the locations 0xFDE0:FDE1 are used for the vector
instead of the values in the locations 0xFFE0:FFE1. This allows the user to reprogram the unprotected
portion of the flash with new program code including new interrupt vector values while leaving the
protected area, which includes the default vector locations, unchanged.
4.5 Security
The MC9S08GBxxA/GTxxA includes circuitry to prevent unauthorized access to the contents of flash and
RAM memory. When security is engaged, flash and RAM are considered secure resources. Direct-page
registers, high-page registers, and the background debug controller are considered unsecured resources.
Programs executing within secure memory have normal access to any MCU memory locations and
resources. Attempts to access a secure memory location with a program executing from an unsecured
memory space or through the background debug interface are blocked (writes are ignored and reads return
all 0s).
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in
the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from flash into
the working FOPT register in high-page register space. A user engages security by programming the
NVOPT location which can be done at the same time the flash memory is programmed. The 1:0 state
disengages security while the other three combinations engage security. Notice the erased state (1:1) makes
the MCU secure. During development, whenever the flash is erased, it is good practice to immediately
program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain
unsecured after a subsequent reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can still be used for background memory access commands, but the MCU cannot enter active
background mode except by holding BKGD/MS low at the rising edge of reset.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor
security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there
is no way to disengage security without completely erasing all flash locations. If KEYEN is 1, a secure
user program can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the flash module interpret writes to the
backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be
compared against the key rather than as the first step in a flash program or erase command.
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 57
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations.
These writes must be done in order, starting with the value for NVBACKKEY and ending with
NVBACKKEY+7. STHX should not be used for these writes because these writes cannot be done
on adjacent bus cycles. User software normally would get the key codes from outside the MCU
system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the
key stored in the flash locations, SEC01:SEC00 are automatically changed to 1:0 and security will
be disengaged until the next reset.
The security key can be written only from RAM, so it cannot be entered through background commands
without the cooperation of a secure user program. The flash memory cannot be accessed by read operations
while KEYACC is set.
The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in flash memory
locations in the nonvolatile register space so users can program these locations just as they would program
any other flash memory location. The nonvolatile registers are in the same 512-byte block of flash as the
reset and interrupt vectors, so block protecting that space also block protects the backdoor comparison key.
Block protects cannot be changed from user application programs, so if the vector space is block protected,
the backdoor security key mechanism cannot permanently change the block protect, security settings, or
the backdoor key.
Security can always be disengaged through the background debug interface by performing these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with background
debug commands, not from application software.
2. Mass erase flash, if necessary.
3. Blank check flash. Provided flash is completely erased, security is disengaged until the next reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0.
4.6 Flash Registers and Control Bits
The flash module has nine 8-bit registers in the high-page register space, three locations in the nonvolatile
register space in flash memory that are copied into three corresponding high-page control registers at reset.
There is also an 8-byte comparison key in flash memory. Refer to Table 4-3 and Table 4-4 for the absolute
address assignments for all flash registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
4.6.1 Flash Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written
only one time. Before any erase or programming operations are possible, write to this register to set the
frequency of the clock for the nonvolatile memory system within acceptable limits.
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
58 Freescale Semiconductor
if PRDIV8 = 0 — fFCLK = fBus ÷ ([DIV5:DIV0] + 1) Eqn. 4-1
if PRDIV8 = 1 — fFCLK = fBus ÷ (8 × ([DIV5:DIV0] + 1)) Eqn. 4-2
76543210
RDIVLD
PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
W
Reset00000000
= Unimplemented or Reserved
Figure 4-4. Flash Clock Divider Register (FCDIV)
Table 4-6. FCDIV Field Descriptions
Field Description
7
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for flash.
1 FCDIV has been written since reset; erase and program operations enabled for flash.
6
PRDIV8
Prescale (Divide) Flash Clock by 8
0 Clock input to the flash clock divider is the bus rate clock.
1 Clock input to the flash clock divider is the bus rate clock divided by 8.
5
DIV[5:0]
Divisor for Flash Clock Divider — The flash clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal flash clock must fall within the range of 200 kHz to 150 kHz for proper flash operations. Program/erase
timing pulses are one cycle of this internal flash clock, which corresponds to a range of 5 μs to 6.7 μs. The
automated programming logic uses an integer number of these pulses to complete an erase or program
operation. See Equation 4-1 and Equation 4-2. Ta ble 4 -7 shows the appropriate values for PRDIV8 and
DIV5:DIV0 for selected bus frequencies.
Table 4-7. Flash Clock Divider Settings
fBus
PRDIV8
(Binary)
DIV5:DIV0
(Decimal) fFCLK
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
20 MHz 1 12 192.3 kHz 5.2 μs
10 MHz 0 49 200 kHz 5 μs
8 MHz 0 39 200 kHz 5 μs
4 MHz 0 19 200 kHz 5 μs
2 MHz 0 9 200 kHz 5 μs
1 MHz 0 4 200 kHz 5 μs
200 kHz 0 0 200 kHz 5 μs
150 kHz 0 0 150 kHz 6.7 μs
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 59
4.6.2 Flash Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from flash into FOPT. Bits 5
through 2 are not used and always read 0. This register may be read at any time, but writes have no meaning
or effect. To change the value in this register, erase and reprogram the NVOPT location in flash memory
as usual and then issue a new MCU reset.
76543210
RKEYEN FNORED 0000SEC01 SEC00
W
Reset This register is loaded from nonvolatile location NVOPT during reset.
= Unimplemented or Reserved
Figure 4-5. Flash Options Register (FOPT)
Table 4-8. FOPT Field Descriptions
Field Description
7
KEYEN
Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to
disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM
commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5, “Security.”
0 No backdoor key access allowed.
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through
NVBACKKEY+7, in that order), security is temporarily disengaged until the next MCU reset.
6
FNORED
Vector Redirection Disable — When this bit is 1, vector redirection is disabled.
0 Vector redirection enabled.
1 Vector redirection disabled.
1:0
SEC0[1:0]
Security State Code — This 2-bit field determines the security state of the MCU as shown below. When the
MCU is secure, the contents of RAM and flash memory cannot be accessed by instructions from any unsecured
source including the background debug interface. For more detailed information about security, refer to
Section 4.5, “Security.”
00 Secure
01 Secure
10 Unsecured
11 Secure
SEC0[1:0] changes to 10 after successful backdoor key entry or a successful blank check of flash.
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
60 Freescale Semiconductor
4.6.3 Flash Configuration Register (FCNFG)
Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written.
4.6.4 Flash Protection Register (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT is copied from flash into FPROT. Bits 0,
1, and 2 are not used and each always reads as 0. This register may be read at any time, but user program
writes have no meaning or effect. Background debug commands can write to FPROT.
76543210
R0 0
KEYACC
00000
W
Reset00000000
= Unimplemented or Reserved
Figure 4-6. Flash Configuration Register (FCNFG)
Table 4-9. FCNFG Field Descriptions
Field Description
5
KEYACC
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5, “Security.”
0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a flash programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.
Reads of the flash return invalid data.
76543210
R FPOPEN FPDIS FPS2 FPS1 FPS0 0 0 0
W(1)
1Background commands can be used to change the contents of these bits in FPROT.
(1)(1)(1)(1)
Reset This register is loaded from nonvolatile location NVPROT during reset.
= Unimplemented or Reserved
Figure 4-7. Flash Protection Register (FPROT)
Table 4-10. FPROT Field Descriptions
Field Description
7
FPOPEN
Open Unprotected Flash for Program/Erase
0 Entire flash memory is block protected (no program or erase allowed).
1 Any flash location, not otherwise block protected or secured, may be erased or programmed.
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 61
6
FPDIS
Flash Protection Disable
0 Flash block specified by FPS2:FPS0 is block protected (program and erase not allowed).
1 No flash block is protected.
5:3
FPS[2:0]
Flash Protect Size Selects — When FPDIS = 0, this 3-bit field determines the size of a protected block of flash
locations at the high address end of the flash (see Ta bl e 4 -1 1). Protected flash locations cannot be erased or
programmed.
Table 4-11. High Address Protected Block
FPS2:FPS1:FPS0 Protected Address Range Protected Block Size Redirected Vectors1,2
1No redirection if FPOPEN = 0, or FNORED = 1.
2Reset vector is not redirected.
0:0:0 0xFE00–0xFFFF 512 bytes 0xFDC0–0xFDFD
0:0:1 0xFC00–0xFFFF 1024 bytes 0xFBC0–0xFBFD
0:1:0 0xF800–0xFFFF 2048 bytes 0xF7C0–0xF7FD
0:1:1 0xF000–0xFFFF 4096 bytes 0xEFC0–0xEFFD
1:0:0 0xE000–0xFFFF 8192 bytes 0xDFC0–0xDFFD
1:0:1 0xC000–0xFFFF 16384 bytes 0xBFC0–0xBFFD3
332K and 60K devices only.
1:1:0 0x8000–0xFFFF 32768 bytes 0x7FC0–0x7FFD4
460K devices only.
1:1:1 0x182C–0xFFFF 59,348 bytes No redirection allowed
Table 4-10. FPROT Field Descriptions (continued)
Field Description
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
62 Freescale Semiconductor
4.6.5 Flash Status Register (FSTAT)
Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits
that can be read at any time. Writes to these bits have special meanings that are discussed in the bit
descriptions.
76543210
R
FCBEF
FCCF
FPVIOL FACCERR
0FBLANK0 0
W
Reset11000000
= Unimplemented or Reserved
Figure 4-8. Flash Status Register (FSTAT)
Table 4-12. FSTAT Field Descriptions
Field Description
7
FCBEF
Flash Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the
command buffer is empty so that a new command sequence can be executed when performing burst
programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to
the array for programming. Only burst program commands can be buffered.
0 Command buffer is full (not ready for additional commands).
1 A new burst program command may be written to the command buffer.
6
FCCF
Flash Command Complete Flag — FCCF is set automatically when the command buffer is empty and no
command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to
FCBEF to register a command). Writing to FCCF has no meaning or effect.
0 Command in progress
1 All commands complete
5
FPVIOL
Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that
attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is
cleared by writing a 1 to FPVIOL.
0 No protection violation.
1 An attempt was made to erase or program a protected location.
4
FACCERR
Access Error Flag — FACCERR is set automatically when the proper command sequence is not followed
exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV
register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed
discussion of the exact actions that are considered access errors, see Section 4.4.5, “Access Errors.” FACCERR
is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
0 No access error has occurred.
1 An access error has occurred.
2
FBLANK
Flash Verified as All Blank (Erased) Flag — FBLANK is set automatically at the conclusion of a blank check
command if the entire flash array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a new
valid command. Writing to FBLANK has no meaning or effect.
0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the flash array is not
completely erased.
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the flash array is completely
erased (all 0xFF).
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 63
4.6.6 Flash Command Register (FCMD)
Only five command codes are recognized in normal user modes as shown in Table 4-14. Refer to
Section 4.4.3, “Program and Erase Command Execution” for a detailed discussion of flash programming
and erase operations.
All other command codes are illegal and generate an access error.
It is not necessary to perform a blank check command after a mass erase operation. Only blank check is
required as part of the security unlocking mechanism.
76543210
R00000000
W FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0
Reset00000000
Figure 4-9. Flash Command Register (FCMD)
Table 4-13. FCMD Field Descriptions
Field Description
7:0
FCMD[7:0]
See Tabl e 4- 1 4 for a description of FCMD[7:0].
Table 4-14. Flash Commands
Command FCMD Equate File Label
Blank check 0x05 mBlank
Byte program 0x20 mByteProg
Byte program — burst mode 0x25 mBurstProg
Page erase (512 bytes/page) 0x40 mPageErase
Mass erase (all flash) 0x41 mMassErase
Chapter 4 Memory
MC9S08GB60A Data Sheet, Rev. 2
64 Freescale Semiconductor
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 65
Chapter 5
Resets, Interrupts, and System Configuration
5.1 Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08GBxxA/GTxxA. Some interrupt sources from peripheral modules are discussed in greater
detail within other sections of this data manual. This section gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems with their own sections but are part of the system control logic.
5.2 Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation:
— Power-on detection (POR)
— Low voltage detection (LVD) with enable
— External RESET pin with enable
— COP watchdog with enable and two timeout choices
— Illegal opcode
— Serial command from a background debug host
• Reset status register (SRS) to indicate source of most recent reset
• Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-1)
5.3 MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
The MC9S08GBxxA/GTxxA has seven sources for reset:
• Power-on reset (POR)
• Low-voltage detect (LVD)
• Computer operating properly (COP) timer
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
66 Freescale Semiconductor
• Illegal opcode detect
• Background debug forced reset
• The reset pin (RESET)
• Clock generator loss of lock and loss of clock reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) module
switches to self-clocked mode with the frequency of fSelf_reset selected. The reset pin is driven low for 34
internal bus cycles where the internal bus frequency is half the ICG frequency. After the 34 cycles are
completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low
externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset pin
is the cause of the MCU reset.
5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it
times out, a system reset is generated to force the system back to a known starting point. The COP
watchdog is enabled by the COPE bit in SOPT (see Section 5.8.4, “System Options Register (SOPT)” for
additional information). The COP timer is reset by writing any value to the address of SRS. This write does
not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a
reset signal to the COP timer.
After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing
as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE
bit in the write-once SOPT register. Also, the COPT bit can be used to choose one of two timeout periods
(218 or 213 cycles of the bus rate clock). Even if the application will use the reset default settings in COPE
and COPT, the user should still write to write-once SOPT during reset initialization to lock in the settings.
That way, they cannot be changed accidentally if the application program gets lost.
The write to SRS that services (clears) the COP timer should not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
When the MCU is in active background mode, the COP timer is temporarily disabled.
5.5 Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Other
than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond until and unless the local interrupt enable is set to 1 to enable the interrupt. The I bit
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 67
in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset
which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and
performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence follows the same cycle-by-cycle sequence as the SWI instruction
and consists of:
• Saving the CPU registers on the stack
• Setting the I bit in the CCR to mask further interrupts
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending
• Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of
another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is
restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit
may be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other
interrupts can be serviced without waiting for the first service routine to finish. This practice is not
recommended for anyone other than the most experienced programmers because it can lead to subtle
program errors that are difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the
stack.
NOTE
For compatibility with the M68HC08, the H register is not automatically
saved and restored. It is good programming practice to push H onto the stack
at the start of the interrupt service routine (ISR) and restore it just before the
RTI that is used to return from the ISR.
When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced
first (see Table 5-1).
5.5.1 Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
68 Freescale Semiconductor
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part
of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address just recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag should be cleared at the beginning of the ISR so that if another interrupt is generated by
this same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2 External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQSC status and control register. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1 Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 for the IRQ pin to act as the
interrupt request (IRQ) input. When the pin is configured as an IRQ input, the user can choose the polarity
of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD),
and whether an event causes an interrupt or only sets the IRQF flag (which can be polled by software).
When the IRQ pin is configured to detect rising edges, an optional pulldown resistor is available rather
than a pullup resistor. BIH and BIL instructions may be used to detect the level on the IRQ pin when the
pin is configured to act as the IRQ input.
NOTE
The voltage measured on the pulled up IRQ pin may be as low as VDD – 0.7
V. The internal gates connected to this pin are pulled all the way to VDD. All
other pins with enabled pullup resistors will have an unloaded measurement
of VDD.
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
* High byte (H) of index register is not automatically stacked.
*
PROGRAM COUNTER LOW
²
²
²
²
70
UNSTACKING
ORDER
STACKING
ORDER
5
4
3
2
1
1
2
3
4
5
TOWARD LOWER ADDRESSES
TOWARD HIGHER ADDRESSES
SP BEFORE
SP AFTER
INTERRUPT STACKING
THE INTERRUPT
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 69
5.5.2.2 Edge and Level Sensitivity
The IRQMOD control bit re-configures the detection logic so it detects edge events and pin levels. In this
edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.5.3 Interrupt Vectors, Sources, and Local Masks
Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU
registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
70 Freescale Semiconductor
Table 5-1. Vector Summary
Vector
Priority
Vector
Number
Address
(High/Low) Vector Name Module Source Enable Description
Lower
Higher
26
through
31
0xFFC0/FFC1
through
0xFFCA/FFCB
Unused Vector Space
(available for user program)
25 0xFFCC/FFCD Vrti System
control
RTIF RTIE Real-time interrupt
24 0xFFCE/FFCF Viic1 IIC IICIS IICIE IIC control
23 0xFFD0/FFD1 Vatd1 ATD COCO AIEN AD conversion
complete
22 0xFFD2/FFD3 Vkeyboard1 KBI KBF KBIE Keyboard pins
21 0xFFD4/FFD5 Vsci2tx SCI2 TDRE
TC
TIE
TCIE
SCI2 transmit
20 0xFFD6/FFD7 Vsci2rx SCI2 IDLE
RDRF
ILIE
RIE
SCI2 receive
19 0xFFD8/FFD9 Vsci2err SCI2 OR
NF
FE
PF
ORIE
NFIE
FEIE
PFIE
SCI2 error
18 0xFFDA/FFDB Vsci1tx SCI1 TDRE
TC
TIE
TCIE
SCI1 transmit
17 0xFFDC/FFDD Vsci1rx SCI1 IDLE
RDRF
ILIE
RIE
SCI1 receive
16 0xFFDE/FFDF Vsci1err SCI1 OR
NF
FE
PF
ORIE
NFIE
FEIE
PFIE
SCI1 error
15 0xFFE0/FFE1 Vspi1 SPI SPIF
MODF
SPTEF
SPIE
SPIE
SPTIE
SPI
14 0xFFE2/FFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overflow
13 0xFFE4/FFE5 Vtpm2ch4 TPM2 CH4F CH4IE TPM2 channel 4
12 0xFFE6/FFE7 Vtpm2ch3 TPM2 CH3F CH3IE TPM2 channel 3
11 0xFFE8/FFE9 Vtpm2ch2 TPM2 CH2F CH2IE TPM2 channel 2
10 0xFFEA/FFEB Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1
9 0xFFEC/FFED Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0
8 0xFFEE/FFEF Vtpm1ovf TPM1 TOF TOIE TPM1 overflow
7 0xFFF0/FFF1 Vtpm1ch2 TPM1 CH2F CH2IE TPM1 channel 2
6 0xFFF2/FFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1
5 0xFFF4/FFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0
4 0xFFF6/FFF7 Vicg ICG ICGIF
(LOLS/LOCS)
LOLRE/LOCRE ICG
3 0xFFF8/FFF9 Vlvd System
control
LVDF LVDIE Low-voltage detect
2 0xFFFA/FFFB Virq IRQ IRQF IRQIE IRQ pin
1 0xFFFC/FFFD Vswi Core SWI
Instruction
— Software interrupt
0 0xFFFE/FFFF Vreset System
control
COP
LVD
RESET pin
Illegal opcode
COPE
LVD RE
—
—
Watchdog timer
Low-voltage detect
External pin
Illegal opcode
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 71
5.6 Low-Voltage Detect (LVD) System
The MC9S08GBxxA/GTxxA includes a system to protect against low voltage conditions to protect
memory contents and control MCU system states during supply voltage variations. The system comprises
a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (VLVDH)
or low (VLVDL). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected
by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless the LVDSE bit is
set. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2, and the current
consumption in stop3 with the LVD enabled will be greater.
5.6.1 Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the VPOR level, the
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in
reset until the supply has risen above the VLVDL level. Both the POR bit and the LVD bit in SRS are set
following a POR.
5.6.2 LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
either an LVD reset or POR.
5.6.3 LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE
set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur.
5.6.4 Low-Voltage Warning (LVW)
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching, but is still above, the LVD voltage. The LVW does not have an interrupt associated with it.
There are two user selectable trip voltages for the LVW, one high (VLVWH) and one low (VLVWL). The trip
voltage is selected by LVWV in SPMSC2.
5.7 Real-Time Interrupt (RTI)
The real-time interrupt function can be used to generate periodic interrupts based on a multiple of the
source clock's period. The RTI has two source clock choices, the external clock input (ICGERCLK) to the
ICG or the RTI's own internal clock. The RTI can be used in run, wait, stop2 and stop3 modes. It is not
available in stop1 mode.
In run and wait modes, only the external clock can be used as the RTI's clock source. In stop2 mode, only
the internal RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used.
When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
72 Freescale Semiconductor
configured for low bandwidth operation (RANGE = 0). If active BDM mode is enabled in stop3, the
internal RTI clock is not available.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS2:RTIS1:RTIS0) used to select one of seven RTI periods. The RTI has a local interrupt enable,
RTIE, to allow masking of the real-time interrupt. The module can be disabled by writing 0:0:0 to
RTIS2:RTIS1:RTIS0 in which case the clock source input is disabled and no interrupts will be generated.
See Section 5.8.6, “System Real-Time Interrupt Status and Control Register (SRTISC),” for detailed
information about this register.
5.8 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in Chapter 4, “Memory” of this data sheet for the absolute
address assignments for all registers. This section refers to registers and control bits only by their names.
A Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 73
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes two unimplemented bits which always read 0, four read/write bits, one
read-only status bit, and one write-only bit. These bits are used to configure the IRQ function, report status,
and acknowledge IRQ events.
76543210
R0 0
IRQEDG IRQPE
IRQF 0
IRQIE IRQMOD
W IRQACK
Reset00000000
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
Table 5-2. IRQSC Field Descriptions
Field Description
5
IRQEDG
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured
to detect rising edges, the optional pullup resistor is re-configured as an optional pulldown resistor.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
4
IRQPE
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can
be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down
resistor is enabled depending on the state of the IRQMOD bit.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
3
IRQF
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
2
IRQACK
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
1
IRQIE
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate a hardware
interrupt request.
0 Hardware interrupt requests from IRQF disabled (use polling).
1 Hardware interrupt requested whenever IRQF = 1.
0
IRQMOD
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See Section 5.5.2.2, “Edge and Level Sensitivity” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
74 Freescale Semiconductor
5.8.2 System Reset Status Register (SRS)
This register includes six read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will
be set. Writing any value to this register address clears the COP watchdog timer without affecting the
contents of this register. The reset state of these bits depends on what caused the MCU to reset.
Figure 5-3. System Reset Status (SRS)
76543210
RPOR PIN COP ILOP 0ICG LVD 0
W Writing any value to SIMRS address clears COP watchdog timer.
Power-on
reset:
10000010
Low-voltage
reset:
U0000010
Any other
reset:
0Note
(1)
1Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding to
sources that are not active at the time of reset will be cleared.
Note(1) Note(1) 0Note
(1) 00
U = Unaffected by reset
Table 5-3. SRS Field Descriptions
Field Description
7
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
6
PIN
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
5
COP
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 75
5.8.3 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
2
ICG
Internal Clock Generation Module Reset — Reset was caused by an ICG module reset.
0 Reset not caused by ICG module.
1 Reset caused by ICG module.
1
LVD
Low Voltage Detect — If the LVD reset is enabled (LVDE = LVDRE = 1) and the supply drops below the LVD trip
voltage, an LVD reset occurs. The LVD function is disabled when the MCU enters stop. To maintain LVD operation
in stop, the LVDSE bit must be set.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
76543210
R00000000
WBDFR1
1BDFR is writable only through serial background debug commands, not from user programs.
Reset00000000
= Unimplemented or Reserved
Table 5-4. SBDFR Field Descriptions
Field Description
0
BDFR
Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an
external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be
written from a user program.
Table 5-3. SRS Field Descriptions (continued)
Field Description
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
76 Freescale Semiconductor
5.8.4 System Options Register (SOPT)
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
should be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
76543210
R
COPE COPT STOPE
00
BKGDPE
W
Reset11010011
= Unimplemented or Reserved
Figure 5-5. System Options Register (SOPT)
Table 5-5. SOPT Field Descriptions
Field Description
7
COPE
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout — This write-once bit defaults to 1 after reset.
0 Short timeout period selected (213 cycles of BUSCLK).
1 Long timeout period selected (218 cycles of BUSCLK).
5
STOPE
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
BKGDPE
Background Debug Mode Pin Enable — The BKGDPE bit enables the PTG0/BKGD/MS pin to function as
BKGD/MS. When the bit is clear, the pin will function as PTG0, which is an output-only general-purpose I/O. This
pin always defaults to BKGD/MS function after any reset.
0 BKGD pin disabled.
1 BKGD pin enabled.
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 77
5.8.5 System Device Identification Register (SDIDH, SDIDL)
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
Figure 5-6. System Device Identification Register High (SDIDH)
76543210
R REV3 REV2 REV1 REV0 ID11 ID10 ID9 ID8
W
Reset 01
1The revision number that is hard coded into these bits reflects the current silicon revision level.
0(1) 0(1) 0(1) 0000
= Unimplemented or Reserved
Table 5-6. SDIDH Field Descriptions
Field Description
7:4
REV[3:0]
Revision Number — The high-order 4 bits of address 0x1806 are hard coded to reflect the current mask set
revision number (0–F).
3:0
ID[11:8]
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08GBxxA/GTxxA is hard coded to the value 0x002. See also ID bits in Tabl e 5- 7 .
76543210
R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
W
Reset00000010
= Unimplemented or Reserved
Figure 5-7. System Device Identification Register Low (SDIDL)
Table 5-7. SDIDL Field Descriptions
Field Description
3:0
ID[7:0]
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08GBxxA/GTxxA is hard coded to the value 0x002. See also ID bits in Tabl e 5- 6 .
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
78 Freescale Semiconductor
5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC)
This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay
selects, and three unimplemented bits, which always read 0.
76543210
RRTIF 0
RTICLKS RTIE
0
RTIS2 RTIS1RTIS0
WRTIACK
Reset00000000
= Unimplemented or Reserved
Figure 5-8. System RTI Status and Control Register (SRTISC)
Table 5-8. SRTISC Field Descriptions
Field Description
7
RTIF
Real-Time Interrupt Flag — This read-only status bit indicates the periodic wakeup timer has timed out.
0 Periodic wakeup timer not timed out.
1 Periodic wakeup timer timed out.
6
RTIACK
Real-Time Interrupt Acknowledge — This write-only bit is used to acknowledge real-time interrupt request
(write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0.
5
RTICLKS
Real-Time Interrupt Clock Select — This read/write bit selects the clock source for the real-time interrupt.
0 Real-time interrupt request clock source is internal oscillator.
1 Real-time interrupt request clock source is external clock.
4
RTIE
Real-Time Interrupt Enable — This read-write bit enables real-time interrupts.
0 Real-time interrupts disabled.
1 Real-time interrupts enabled.
2:0
RTIS[2:0]
Real-Time Interrupt Period Selects — These read/write bits select the wakeup period for the RTI. One clock
source for the real-time interrupt is its own internal clock source, which oscillates with a period of approximately
tRTI and is independent of other MCU clock sources. Using an external clock source the delays will be crystal
frequency divided by value in RTIS2:RTIS1:RTIS0. See Ta ble 5 - 9.
Table 5-9. Real-Time Interrupt Period
RTIS2:RTIS1:RTIS0 Internal Clock Source 1
(tRTI = 1 ms, Nominal)
1See Ta b l e A - 1 0 tRTI in Appendix A, “Electrical Characteristics,” for the tolerance on these values.
External Clock Source 2
Period = text
2text is based on the external clock source, resonator, or crystal selected by the ICG configuration. See Ta b l e A - 9 for details.
0:0:0 Disable periodic wakeup timer Disable periodic wakeup timer
0:0:1 8 ms text x 256
0:1:0 32 ms tex x 1024
0:1:1 64 ms tex x 2048
1:0:0 128 ms tex x 4096
1:0:1 256 ms text x 8192
1:1:0 512 ms text x 16384
1:1:1 1.024 s tex x 32768
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 79
5.8.7 System Power Management Status and Control 1 Register (SPMSC1)
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
76543210
RLVDF 0
LVDIE LVDRE1
1This bit can be written only one time after reset. Additional writes are ignored.
LVDS E(1) LVD E(1) 00
WLVDAC K
Reset00011100
= Unimplemented or Reserved
Table 5-10. SPMSC1 Field Descriptions
Field Description
7
LVD F
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
6
LVDAC K
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
5
LVD IE
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4
LVDRE
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
3
LVDS E
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
Chapter 5 Resets, Interrupts, and System Configuration
MC9S08GB60A Data Sheet, Rev. 2
80 Freescale Semiconductor
5.8.8 System Power Management Status and Control 2 Register (SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop
mode behavior of the MCU.
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
76543210
RLVW F 0
LVDV LVW V
PPDF 0
PDC PPDC
WLVWACK PPDACK
Power-on
reset:
0(1)
1 LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLV W.
0000000
LVD reset: 0(1) 0UU0000
Any other
reset:
0(1) 0UU0000
= Unimplemented or Reserved U = Unaffected by reset
Table 5-11. SPMSC2 Field Descriptions
Field Description
7
LVWF
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
6
LVWACK
Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge. Writing a 1
to LVWACK clears LVWF to 0 if a low voltage warning is not present.
5
LVDV
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (VLVD).
0 Low trip point selected (VLV D = VLVDL ).
1 High trip point selected (VLVD = VLV DH ).
4
LVWV
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (VLVW).
0 Low trip point selected (VLV W = VLVWL ).
1 High trip point selected (VLVW = VLVW H).
3
PPDF
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
2
PPDACK
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
1
PDC
Power Down Control — The write-once PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
1 Power down modes are enabled.
0
PPDC
Partial Power Down Control — The write-once PPDC bit controls which power down mode, stop1 or stop2, is
selected.
0 Stop1, full power down, mode enabled if PDC set.
1 Stop2, partial power down, mode enabled if PDC set.
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 81
Chapter 6
Parallel Input/Output
6.1 Introduction
This section explains software controls related to parallel input/output (I/O). The MC9S08GBxxA has
seven I/O ports which include a total of 56 general-purpose I/O pins (one of these pins is output only). The
MC9S08GTxxA has six I/O ports which include a total of up to 39 general-purpose I/O pins (one pin,
PTG0, is output only). See Chapter 2, “Pins and Connections,” for more information about the logic and
hardware aspects of these pins.
Many of these pins are shared with on-chip peripherals such as timer systems, external interrupts, or
keyboard interrupts. When these other modules are not controlling the port pins, they revert to
general-purpose I/O control. For each I/O pin, a port data bit provides access to input (read) and output
(write) data, a data direction bit controls the direction of the pin, and a pullup enable bit enables an internal
pullup device (provided the pin is configured as an input), and a slew rate control bit controls the rise and
fall times of the pins.
NOTE
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unconnected pins to outputs so the pins
do not float.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
82 Freescale Semiconductor
Figure 6-1. Block Diagram Highlighting Parallel Input/Output Pins
PTD3/TPM2CH0
PTD4/TPM2CH1
PTD5/TPM2CH2
PTD6/TPM2CH3
PTC1/RxD2
PTC0/TxD2
VSS
VDD
PTE3/MISO1
PTE2/SS1
PTA7/KBI1P7–
PTE0/TxD1
PTE1/RxD1
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CH0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL1
PTC2/SDA1
PORT A
PORT C
PORT D
PORT E
8-BIT KEYBOARD
INTERRUPT MODULE
IIC MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
USER FLASH
USER RAM
(Gx60A = 4096 BYTES)
DEBUG
MODULE
(Gx60A = 61,268 BYTES)
HCS08 CORE
3-CHANNEL TIMER/PWM
MODULE
PTB7/AD1P7–
PORT B
PTE5/SPSCK1
PTE4/MOSI1
PTE6
PTE7
INTERFACE MODULE
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
VOLTAGE
REGULATOR
RTI
SERIAL COMMUNICATIONS
COP
IRQ LVD
LOW-POWER OSCILLATOR
INTERNAL CLOCK
GENERATOR
RESET ANALOG-TO-DIGITAL
CONVERTER (10-BIT)
INTERFACE MODULE
SERIAL COMMUNICATIONS
5-CHANNEL TIMER/PWM
MODULE
PORT F
PTF7–PTF0
PTD7/TPM2CH4
8
PTA0/KBI1P0
8
PTB0/AD1P0
8
PTG3
PTG2/EXTAL
PTG0/BKGD/MS
PTG1/XTAL
PORT G
PTG7–PTG4
(Gx32A = 32,768 BYTES)
(Gx32A = 2048 BYTES)
CPU
(DBG)
(KBI1)
(ATD1)
(IIC1)
(SCI2)
(TPM2)
(TPM1)
(SPI1)
(SCI1)
(ICG)
8
8
SCL1
SDA1
SCL1
SCL1
5
3
SPSCK1
MOSI1
MISO1
SS1
RxD1
TxD1
VSSAD
VDDAD
VREFH
VREFL
EXTAL
XTAL
BKGD
BDC
4
IRQ
Note: Not all pins are bonded out in all packages. See Table 2-2 for complete details.
= Not connected in 48-, 44-, and 42-pin packages
= Not connected in 44- and 42-pin packages
= Not connected in 42-pin packages
Block Diagram Symbol Key:
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 83
6.2 Features
Parallel I/O features, depending on package choice, include:
• A total of 56 general-purpose I/O pins in seven ports (PTG0 is output only)
• High-current drivers on port C and port F pins
• Hysteresis input buffers
• Software-controlled pullups on each input pin
• Software-controlled slew rate output buffers
• Eight port A pins shared with KBI1
• Eight port B pins shared with ATD1
• Eight high-current port C pins shared with SCI2 and IIC1
• Eight port D pins shared with TPM1 and TPM2
• Eight port E pins shared with SCI1 and SPI1
• Eight high-current port F pins
• Eight port G pins shared with EXTAL, XTAL, and BKGD/MS
6.3 Pin Descriptions
The MC9S08GBxxA/GTxxA has a total of 56 parallel I/O pins (one is output only) in seven 8-bit ports
(PTA–PTG). Not all pins are bonded out in all packages. Consult the pin assignment in Chapter 2, “Pins
and Connections,” for available parallel I/O pins. All of these pins are available for general-purpose I/O
when they are not used by other on-chip peripheral systems.
After reset, BKGD/MS is enabled and therefore is not usable as an output pin until BKGDPE in SOPT is
cleared. The rest of the peripheral functions are disabled. After reset, all data direction and pullup enable
controls are set to 0s. These pins default to being high-impedance inputs with on-chip pullup devices
disabled.
The following paragraphs discuss each port and the software controls that determine each pin’s use.
6.3.1 Port A and Keyboard Interrupts
Figure 6-2. Port A Pin Names
Port A is an 8-bit port shared among the KBI keyboard interrupt inputs and general-purpose I/O. Any pins
enabled as KBI inputs will be forced to act as inputs.
Port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction
(PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers. Refer to Section 6.4, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
Port A Bit 7654321Bit 0
MCU Pin: PTA7/
KBI1P7
PTA6/
KBI1P6
PTA5/
KBI1P5
PTA4/
KBI1P4
PTA3/
KBI1P3
PTA2/
KBI1P2
PTA1/
KBI1P1
PTA0/
KBI1P0
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
84 Freescale Semiconductor
Port A can be configured to be keyboard interrupt input pins. Refer to Chapter 9, “Keyboard Interrupt
(S08KBIV1),” for more information about using port A pins as keyboard interrupts pins.
6.3.2 Port B and Analog to Digital Converter Inputs
j
Figure 6-3. Port B Pin Names
Port B is an 8-bit port shared among the ATD inputs and general-purpose I/O. Any pin enabled as an ATD
input will be forced to act as an input.
Port B pins are available as general-purpose I/O pins controlled by the port B data (PTBD), data direction
(PTBDD), pullup enable (PTBPE), and slew rate control (PTBSE) registers. Refer to Section 6.4, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
When the ATD module is enabled, analog pin enables are used to specify which pins on port B will be used
as ATD inputs. Refer to Chapter 14, “Analog-to-Digital Converter (S08ATDV3),” for more information
about using port B pins as ATD pins.
6.3.3 Port C and SCI2, IIC, and High-Current Drivers
Figure 6-4. Port C Pin Names
Port C is an 8-bit port which is shared among the SCI2 and IIC1 modules, and general-purpose I/O. When
SCI2 or IIC1 modules are enabled, the pin direction will be controlled by the module or function. Port C
has high current output drivers.
Port C pins are available as general-purpose I/O pins controlled by the port C data (PTCD), data direction
(PTCDD), pullup enable (PTCPE), and slew rate control (PTCSE) registers. Refer to Section 6.4, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
When the SCI2 module is enabled, PTC0 serves as the SCI2 module’s transmit pin (TxD2) and PTC1
serves as the receive pin (RxD2). Refer to Chapter 11, “Serial Communications Interface (S08SCIV1),”
for more information about using PTC0 and PTC1 as SCI pins
When the IIC module is enabled, PTC2 serves as the IIC modules’s serial data input/output pin (SDA1)
and PTC3 serves as the clock pin (SCL1). Refer to Chapter 13, “Inter-Integrated Circuit (S08IICV1),” for
more information about using PTC2 and PTC3 as IIC pins.
Port B Bit 7654321Bit 0
MCU Pin: PTB7/
AD1P7
PTB6/
AD1P6
PTB5/
AD1P5
PTB4/
AD1P4
PTB3/
AD1P3
PTB2/
AD1P2
PTB1/
AD1P1
PTB0/
AD1P0
Port C Bit 7653321Bit 0
MCU Pin: PTC7 PTC6 PTC5 PTC4 PTC3/
SCL1
PTC2/
SDA1
PTC1/
RxD2
PTC0/
TxD2
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 85
6.3.4 Port D, TPM1 and TPM2
Figure 6-5. Port D Pin Names
Port D is an 8-bit port shared with the two TPM modules, TPM1 and TPM2, and general-purpose I/O.
When the TPM1 or TPM2 modules are enabled in output compare or input capture modes of operation,
the pin direction will be controlled by the module function.
Port D pins are available as general-purpose I/O pins controlled by the port D data (PTDD), data direction
(PTDDD), pullup enable (PTDPE), and slew rate control (PTDSE) registers. Refer to Section 6.4, “Parallel
I/O Controls” for more information about general-purpose I/O control.
The TPM2 module can be configured to use PTD7–PTD3 as either input capture, output compare, PWM,
or external clock input pins (PTD3 only). Refer to Chapter 10, “Timer/PWM (S08TPMV1)” for more
information about using PTD7–PTD3 as timer pins.
The TPM1 module can be configured to use PTD2–PTD0 as either input capture, output compare, PWM,
or external clock input pins (PTD0 only). Refer to Chapter 10, “Timer/PWM (S08TPMV1)” for more
information about using PTD2–PTD0 as timer pins.
6.3.5 Port E, SCI1, and SPI
Figure 6-6. Port E Pin Names
Port E is an 8-bit port shared with the SCI1 module, SPI1 module, and general-purpose I/O. When the SCI
or SPI modules are enabled, the pin direction will be controlled by the module function.
Port E pins are available as general-purpose I/O pins controlled by the port E data (PTED), data direction
(PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. Refer to Section 6.4, “Parallel
I/O Controls” for more information about general-purpose I/O control.
When the SCI1 module is enabled, PTE0 serves as the SCI1 module’s transmit pin (TxD1) and PTE1
serves as the receive pin (RxD1). Refer to Chapter 11, “Serial Communications Interface (S08SCIV1)” for
more information about using PTE0 and PTE1 as SCI pins.
When the SPI module is enabled, PTE2 serves as the SPI module’s slave select pin (SS1), PTE3 serves as
the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5
serves as the SPI clock pin (SPSCK1). Refer to Chapter 12, “Serial Peripheral Interface (S08SPIV3) for
more information about using PTE5–PTE2 as SPI pins.
Port D Bit 7654321Bit 0
MCU Pin: PTD7/
TPM2CH4
PTD6/
TPM2CH3
PTD5/
TPM2CH2
PTD4/
TPM2CH1
PTD3/
TPM2CH0
PTD2/
TPM1CH2
PTD1/
TPM1CH1
PTD0/
TPM1CH0
Port E Bit 7654321Bit 0
MCU Pin: PTE7 PTE6 PTE5/
SPSCK1
PTE4/
MOSI1
PTE3/
MISO1
PTE2/
SS1
PTE1/
RxD1
PTE0/
TxD1
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
86 Freescale Semiconductor
6.3.6 Port F and High-Current Drivers
Figure 6-7. Port F Pin Names
Port F is an 8-bit port general-purpose I/O that is not shared with any peripheral module. Port F has high
current output drivers.
Port F pins are available as general-purpose I/O pins controlled by the port F data (PTFD), data direction
(PTFDD), pullup enable (PTFPE), and slew rate control (PTFSE) registers. Refer to Section 6.4, “Parallel
I/O Controls” for more information about general-purpose I/O control.
6.3.7 Port G, BKGD/MS, and Oscillator
Figure 6-8. Port G Pin Names
Port G is an 8-bit port which is shared among the background/mode select function, oscillator, and
general-purpose I/O. When the background/mode select function or oscillator is enabled, the pin direction
will be controlled by the module function.
Port G pins are available as general-purpose I/O pins controlled by the port G data (PTGD), data direction
(PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers. Refer to Section 6.4, “Parallel
I/O Controls” for more information about general-purpose I/O control.
The internal pullup for PTG0 is enabled when the background/mode select function is enabled, regardless
of the state of PTGPE0. During reset, the BKGD/MS pin functions as a mode select pin. After the MCU
is out of reset, the BKGD/MS pin becomes the background communications input/output pin. The PTG0
can be configured to be a general-purpose output pin. Refer to Chapter 3, “Modes of Operation”,
Chapter 5, “Resets, Interrupts, and System Configuration”, and Chapter 15, “Development Support” for
more information about using this pin.
The ICG module can be configured to use PTG2–PTG1 ports as crystal oscillator or external clock pins.
Refer to Chapter 13, “Inter-Integrated Circuit (S08IICV1)” for more information about using these pins as
oscillator pins.
Port F Bit 7654321Bit 0
MCU Pin: PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
Port G Bit 7654321Bit 0
MCU Pin: PTG7 PTG6 PTG5 PTG4 PTG3 PTG2/
EXTAL
PTG1/
XTAL
PTG0/
BKGD/MS
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 87
6.4 Parallel I/O Controls
Provided no on-chip peripheral is controlling a port pin, the pins operate as general-purpose I/O pins that
are accessed and controlled by a data register (PTxD), a data direction register (PTxDD), a pullup enable
register (PTxPE), and a slew rate control register (PTxSE) where x is A, B, C, D, E, F, or G.
Reads of the data register return the pin value (if PTxDDn = 0) or the contents of the port data register (if
PTxDDn = 1). Writes to the port data register are latched into the port register whether the pin is controlled
by an on-chip peripheral or the pin is configured as an input. If the corresponding pin is not controlled by
a peripheral and is configured as an output, this level will be driven out the port pin.
6.4.1 Data Direction Control
The data direction control bits determine whether the pin output driver is enabled, and they control what
is read for port data register reads. Each port pin has a data direction control bit. When PTxDDn = 0, the
corresponding pin is an input and reads of PTxD return the pin value. When PTxDDn = 1, the
corresponding pin is an output and reads of PTxD return the last value written to the port data register.
When a peripheral module or system function is in control of a port pin, the data direction control still
controls what is returned for reads of the port data register, even though the peripheral system has
overriding control of the actual pin direction.
For the MC9S08GBxxA/GTxxA MCU, reads of PTG0/BKGD/MS will return the value on the output pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
6.4.2 Internal Pullup Control
An internal pullup device can be enabled for each port pin that is configured as an input (PTxDDn = 0).
The pullup device is available for a peripheral module to use, provided the peripheral is enabled and is an
input function as long as the PTxDDn = 0.
For the four configurable KBI module inputs on PTA7–PTA4, when a pin is configured to detect rising
edges, the port pullup enable associated with the pin (PTAPEn) selects a pulldown rather than a pullup
device.
6.4.3 Slew Rate Control
Slew rate control can be enabled for each port pin that is configured as an output (PTxDDn = 1) or if a
peripheral module is enabled and its function is an output. Not all peripheral modules’ outputs have slew
rate control; refer to Chapter 2, “Pins and Connections” for more information about which pins have slew
rate control.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
88 Freescale Semiconductor
6.5 Stop Modes
Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An
explanation of I/O behavior for the various stop modes follows:
• When the MCU enters stop1 mode, all internal registers including general-purpose I/O control and
data registers are powered down. All of the general-purpose I/O pins assume their reset state:
output buffers and pullups turned off. Upon exit from stop1, all I/O must be initialized as if the
MCU had been reset.
• When the MCU enters stop2 mode, the internal registers are powered down as in stop1 but the I/O
pin states are latched and held. For example, a port pin that is an output driving low continues to
function as an output driving low even though its associated data direction and output data registers
are powered down internally. Upon exit from stop2, the pins continue to hold their states until a 1
is written to the PPDACK bit. To avoid discontinuity in the pin state following exit from stop2, the
user must restore the port control and data registers to the values they held before entering stop2.
These values can be stored in RAM before entering stop2 because the RAM is maintained during
stop2.
• In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.
6.6 Parallel I/O Registers and Control Bits
This section provides information about all registers and control bits associated with the parallel I/O ports.
Refer to tables in Chapter 4, “Memory” for the absolute address assignments for all parallel I/O registers.
This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file normally is used to translate these names into the appropriate absolute addresses.
6.6.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD)
Port A includes eight pins shared between general-purpose I/O and the KBI module. Port A pins used as
general-purpose I/O pins are controlled by the port A data (PTAD), data direction (PTADD), pullup enable
(PTAPE), and slew rate control (PTASE) registers.
If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as
an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of
PTAD will return the logic value of the corresponding pin, provided PTADD is 0.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 89
76543210
R
PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
W
Reset00000000
Figure 6-9. Port A Data Register (PTAD)
Table 6-1. PTAD Field Descriptions
Field Description
7:0
PTAD[7:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
76543210
R
PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
W
Reset00000000
Figure 6-10. Pullup Enable for Port A (PTAPE)
Table 6-2. PTAPE Field Descriptions
Field Description
7:0
PTAPE[7:0]
Pullup Enable for Port A Bits — For port A pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled provided the corresponding PTADDn is 0. For port A pins that are configured
as outputs, these bits are ignored and the internal pullup devices are disabled. When any of bits 7 through 4 of
port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits
enable pulldown rather than pullup devices.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
90 Freescale Semiconductor
76543210
R
PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
W
Reset00000000
Figure 6-11. Slew Rate Control Enable for Port A (PTASE)
Table 6-3. PTASE Field Descriptions
Field Description
7:0
PTASE[7:0]
Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port A pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
W
Reset00000000
Figure 6-12. Data Direction for Port A (PTADD)
Table 6-4. PTADD Field Descriptions
Field Description
7:0
PTADD[7:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 91
6.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD)
Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as
general-purpose I/O pins are controlled by the port B data (PTBD), data direction (PTBDD), pullup enable
(PTBPE), and slew rate control (PTBSE) registers.
If the ATD takes control of a port B pin, the corresponding PTBDD, PTBSE, and PTBPE bits are ignored.
When a port B pin is being used as an ATD pin, reads of PTBD will return a 0 of the corresponding pin,
provided PTBDD is 0.
76543210
R
PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
W
Reset00000000
Figure 6-13. Port B Data Register (PTBD)
Table 6-5. PTBD Field Descriptions
Field Description
7:0
PTBD[7:0]
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
76543210
R
PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
W
Reset00000000
Figure 6-14. Pullup Enable for Port B (PTBPE)
Table 6-6. PTBPE Field Descriptions
Field Description
7:0
PTBPE[7:0]
Pullup Enable for Port B Bits — For port B pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port B pins that are configured as outputs, these bits are ignored and the
internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
92 Freescale Semiconductor
76543210
R
PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
W
Reset00000000
Figure 6-15. Data Direction for Port A (PTBSE)
Table 6-7. PTBSE Field Descriptions
Field Description
7:0
PTBSE[7:0]
Slew Rate Control Enable for Port B Bits — For port B pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
W
Reset00000000
Figure 6-16. Data Direction for Port B (PTBDD)
Table 6-8. PTBDD Field Descriptions
Field Description
7:0
PTBDD[7:0]
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 93
6.6.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD)
Port C includes eight general-purpose I/O pins that share with the SCI2 and IIC modules. Port C pins used
as general-purpose I/O pins are controlled by the port C data (PTCD), data direction (PTCDD), pullup
enable (PTCPE), and slew rate control (PTCSE) registers.
If the SCI2 takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to
provide slew rate on the SCI2 transmit pin, TxD2. PTCPE can be used, provided the corresponding
PTCDD bit is 0, to provide a pullup device on the SCI2 receive pin, RxD2.
If the IIC takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to
provide slew rate on the IIC serial data pin (SDA1), when in output mode and the IIC clock pin (SCL1).
PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the IIC
serial data pin, when in receive mode.
Reads of PTCD will return the logic value of the corresponding pin, provided PTCDD is 0.
76543210
R
PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
W
Reset00000000
Figure 6-17. Port C Data Register (PTCD)
Table 6-9. PTCD Field Descriptions
Field Description
7:0
PTCD[7:0]
Port C Data Register Bits— For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
94 Freescale Semiconductor
76543210
R
PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
W
Reset00000000
Figure 6-18. Pullup Enable for Port C (PTCPE)
Table 6-10. PTCPE Field Descriptions
Field Description
7:0
PTCPE[7:0]
Pullup Enable for Port C Bits — For port C pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port C pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
76543210
R
PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
W
Reset00000000
Figure 6-19. Slew Rate Control Enable for Port C (PTCSE)
Table 6-11. PTCSE Field Descriptions
Field Description
7:0
PTCSE[7:0]
Slew Rate Control Enable for Port C Bits — For port C pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
W
Reset00000000
Figure 6-20. Data Direction for Port C (PTCDD)
Table 6-12. PTCDD Field Descriptions
Field Description
7:0
PTCDD[7:0]
Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for
PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 95
6.6.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD)
Port D includes eight pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as
general-purpose I/O pins are controlled by the port D data (PTDD), data direction (PTDDD), pullup enable
(PTDPE), and slew rate control (PTDSE) registers.
If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored. When the TPM is in
output compare mode, the corresponding PTDSE can be used to provide slew rate on the pin. When the
TPM is in input capture mode, the corresponding PTDPE can be used, provided the corresponding PTDDD
bit is 0, to provide a pullup device on the pin.
Reads of PTDD will return the logic value of the corresponding pin, provided PTDDD is 0.
76543210
R
PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
W
Reset00000000
Figure 6-21. Port D Data Register (PTDD)
Table 6-13. PTDD Field Descriptions
Field Description
7:0
PTDD[7:0]
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
76543210
R
PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
W
Reset00000000
Figure 6-22. Pullup Enable for Port D (PTDPE)
Table 6-14. PTDPE Field Descriptions
Field Description
7:0
PTDPE[7:0]
Pullup Enable for Port D Bits — For port D pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port D pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
96 Freescale Semiconductor
76543210
R
PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
W
Reset00000000
Figure 6-23. Slew Rate Control Enable for Port D (PTDSE)
Table 6-15. PTDSE Field Descriptions
Field Description
7:0
PTDSE[7:0]
Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port D pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
W
Reset00000000
Figure 6-24. Data Direction for Port D (PTDDD)
Table 6-16. PTDDD Field Descriptions
Field Description
7:0
PTDDD[7:0]
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 97
6.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD)
Port E includes eight general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used
as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup
enable (PTEPE), and slew rate control (PTESE) registers.
If the SCI1 takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to
provide slew rate on the SCI1 transmit pin, TxD1. PTEPE can be used, provided the corresponding PTEDD
bit is 0, to provide a pullup device on the SCI1 receive pin, RxD1.
If the SPI takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to
provide slew rate on the SPI serial output pin (MOSI1 or MISO1) and serial clock pin (SPSCK1)
depending on the SPI operational mode. PTEPE can be used, provided the corresponding PTEDD bit is 0,
to provide a pullup device on the SPI serial input pins (MOSI1 or MISO1) and slave select pin (SS1)
depending on the SPI operational mode.
Reads of PTED will return the logic value of the corresponding pin, provided PTEDD is 0.
76543210
R
PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
W
Reset00000000
Figure 6-25. Port E Data Register (PTED)
Table 6-17. PTED Field Descriptions
Field Description
7:0
PTED[7:0]
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits in this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
98 Freescale Semiconductor
76543210
R
PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
W
Reset00000000
Figure 6-26. Pullup Enable for Port E (PTEPE)
Table 6-18. PTEPE Field Descriptions
Field Description
7:0
PTEPE[7:0]
Pullup Enable for Port E Bits — For port E pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port E pins that are configured as outputs, these bits are ignored and the
internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
76543210
R
PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
W
Reset00000000
Figure 6-27. Slew Rate Control Enable for Port E (PTESE)
Table 6-19. PTESE Field Descriptions
Field Description
7:0
PTESE[7:0]
Slew Rate Control Enable for Port E Bits — For port E pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port E pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
W
Reset00000000
Figure 6-28. Data Direction for Port E (PTEDD)
Table 6-20. PTEDD Field Descriptions
Field Description
7:0
PTEDD[7:0]
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 99
6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD)
Port F includes eight general-purpose I/O pins that are not shared with any peripheral module. Port F pins
used as general-purpose I/O pins are controlled by the port F data (PTFD), data direction (PTFDD), pullup
enable (PTFPE), and slew rate control (PTFSE) registers.
76543210
R
PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
W
Reset00000000
Figure 6-29. Port PTF Data Register (PTFD)
Table 6-21. PTFD Field Descriptions
Field Description
7:0
PTFD[7:0]
Port PTF Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin. For port
F pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
76543210
R
PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
W
Reset00000000
Figure 6-30. Pullup Enable for Port F (PTFPE)
Table 6-22. PTFPE Field Descriptions
Field Description
7:0
PTFPE[7:0]
Pullup Enable for Port F Bits — For port F pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port F pins that are configured as outputs, these bits are ignored and the
internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
100 Freescale Semiconductor
6.6.7 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD)
Port G includes eight general-purpose I/O pins that are shared with BKGD/MS function and the oscillator
or external clock pins. Port G pins used as general-purpose I/O pins are controlled by the port G data
(PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers.
Port pin PTG0, while in reset, defaults to the BKGD/MS pin. After the MCU is out of reset, PTG0 can be
configured to be a general-purpose output pin. When BKGD/MS takes control of PTG0, the corresponding
PTGDD, PTGPE, and PTGPSE bits are ignored.
Port pins PTG1 and PTG2 can be configured to be oscillator or external clock pins. When the oscillator
takes control of a port G pin, the corresponding PTGD, PTGDD, PTGSE, and PTGPE bits are ignored.
Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD is 0.
76543210
R
PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
W
Reset00000000
Figure 6-31. Slew Rate Control Enable for Port F (PTFSE)
Table 6-23. PTFSE Field Descriptions
Field Description
7:0
PTFSE[7:0]
Slew Rate Control Enable for Port F Bits — For port F pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port F pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
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PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
W
Reset00000000
Figure 6-32. Data Direction for Port F (PTFDD)
Table 6-24. PTFDD Field Descriptions
Field Description
7:0
PTFDD[7:0]
Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for
PTFD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 101
76543210
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PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
W
Reset00000000
Figure 6-33. Port PTG Data Register (PTGD)
Table 6-25. PTGD Field Descriptions
Field Description
7:0
PTGD[7:0]
Port PTG Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port
G pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
76543210
R
PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
W
Reset00000000
Figure 6-34. Pullup Enable for Port G (PTGPE)
Table 6-26. PTGPE Field Descriptions
Field Description
7:0
PTGPE[7:0]
Pullup Enable for Port G Bits — For port G pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port G pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
102 Freescale Semiconductor
76543210
R
PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
W
Reset00000000
Figure 6-35. Slew Rate Control Enable for Port G (PTGSE)
Table 6-27. PTGSE Field Descriptions
Field Description
7:0
PTGSE[7:0]
Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
W
Reset00000000
Figure 6-36. Data Direction for Port G (PTGDD)
Table 6-28. PTGDD Field Descriptions
Field Description
7:0
PTGDD[7:0]
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 103
Chapter 7
Internal Clock Generator (S08ICGV2)
The MC9S08GBxxA/GTxxA microcontroller provides one internal clock generation (ICG) module to
create the system bus frequency. All functions described in this section are available on the
MC9S08GBxxA/GTxxA microcontroller. The EXTAL and XTAL pins share port G bits 2 and 1,
respectively. Analog supply lines VDDA and VSSA are internally derived from the MCU’s VDD and VSS
pins. Electrical parametric data for the ICG may be found in Appendix A, “Electrical Characteristics.”
Figure 7-1. System Clock Distribution Diagram
NOTE
Freescale Semiconductor recommends that flash location $FFBE be
reserved to store a nonvolatile version of ICGTRM. This will allow
debugger and programmer vendors to perform a manual trim operation and
store the resultant ICGTRM value for users to access at a later time.
ATD has min and max
frequency requirements. See
Chapter 1, “Device Overview” and
Appendix A, “Electrical Characteristics.
Flash has frequency
requirements for program
and erase operation.
See Appendix A, “Electrical
Characteristics.
* ICGLCLK is the alternate BDC clock source for the MC9S08GBxxA/GTxxA.
TPM1 TPM2 IIC1 SCI1 SCI2 SPI1
BDC
CPU ATD1 RAM FLASH
ICG
ICGOUT ÷2
FFE
SYSTEM
LOGIC
BUSCLK
ICGLCLK*
CONTROL
FIXED FREQ CLOCK (XCLK)
ICGERCLK RTI
÷2
Chapter 7 Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
104 Freescale Semiconductor
Figure 7-2. Block Diagram Highlighting ICG Module
PTD3/TPM2CH0
PTD4/TPM2CH1
PTD5/TPM2CH2
PTD6/TPM2CH3
PTC1/RxD2
PTC0/TxD2
VSS
VDD
PTE3/MISO1
PTE2/SS1
PTA7/KBI1P7–
PTE0/TxD1
PTE1/RxD1
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CH0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL1
PTC2/SDA1
PORT A
PORT C
PORT D
PORT E
8-BIT KEYBOARD
INTERRUPT MODULE
IIC MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
USER FLASH
USER RAM
(Gx60A = 4096 BYTES)
DEBUG
MODULE
(Gx60A = 61,268 BYTES)
HCS08 CORE
Note: Not all pins are bonded out in all packages. See Table 2-2 for complete details.
3-CHANNEL TIMER/PWM
MODULE
PTB7/AD1P7–
PORT B
PTE5/SPSCK1
PTE4/MOSI1
PTE6
PTE7
INTERFACE MODULE
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
VOLTAGE
REGULATOR
RTI
SERIAL COMMUNICATIONS
COP
IRQ LVD
LOW-POWER OSCILLATOR
INTERNAL CLOCK
GENERATOR
RESET ANALOG-TO-DIGITAL
CONVERTER (10-BIT)
INTERFACE MODULE
SERIAL COMMUNICATIONS
5-CHANNEL TIMER/PWM
MODULE
PORT F
PTF7–PTF0
PTD7/TPM2CH4
8
PTA0/KBI1P0
8
PTB0/AD1P0
8
PTG3
PTG2/EXTAL
PTG0/BKGD/MS
PTG1/XTAL
PORT G
PTG7–PTG4
(Gx32A = 32,768 BYTES)
(Gx32A = 2048 BYTES)
CPU
(DBG)
(KBI1)
(ATD1)
(IIC1)
(SCI2)
(TPM2)
(TPM1)
(SPI1)
(SCI1)
(ICG)
8
8
SCL1
SDA1
SCL1
SCL1
5
3
SPSCK1
MOSI1
MISO1
SS1
RxD1
TxD1
VSSAD
VDDAD
VREFH
VREFL
EXTAL
XTAL
BKGD
BDC
4
IRQ
= Not connected in 48-, 44-, and 42-pin packages
= Not connected in 44- and 42-pin packages
= Not connected in 42-pin packages
Block Diagram Symbol Key:
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 105
7.1 Introduction
Figure 7-3 is a top-level diagram that shows the functional organization of the internal clock generation
(ICG) module. This section includes a general description and a feature list.
Figure 7-3. ICG Block Diagram
The ICG provides multiple options for clock sources. This offers a user great flexibility when making
choices between cost, precision, current draw, and performance. As seen in Figure 7-3, the ICG consists
of four functional blocks. Each of these is briefly described here and then in more detail in a later section.
•Oscillator block — The oscillator block provides means for connecting an external crystal or
resonator. Two frequency ranges are software selectable to allow optimal startup and stability.
Alternatively, the oscillator block can be used to route an external square wave to the system clock.
External sources can provide a very precise clock source. The oscillator is capable of being
configured for low power mode or high amplitude mode as selected by HGO.
•Internal reference generator — The internal reference generator consists of two controlled clock
sources. One is designed to be approximately 8 MHz and can be selected as a local clock for the
background debug controller. The other internal reference clock source is typically 243 kHz and
can be trimmed for finer accuracy via software when a precise timed event is input to the MCU.
This provides a highly reliable, low-cost clock source.
•Frequency-locked loop — A frequency-locked loop (FLL) stage takes either the internal or
external clock source and multiplies it to a higher frequency. Status bits provide information when
the circuit has achieved lock and when it falls out of lock. Additionally, this block can monitor the
external reference clock and signals whether the clock is valid or not.
OSCILLATOR (OSC)
FREQUENCY
INTERNAL
EXTAL
XTAL
REFERENCE
GENERATORS
CLOCK
SELECT
8 MHz
IRG
LOSS OF LOCK
AND CLOCK DETECTOR
LOCKED
LOOP (FLL)
FIXED
CLOCK
SELECT
ICGOUT
TYP 243 kHz
RG
ICGLCLK
ICG
FFE
V
DDA
VSSA
(SEE NOTE 2)
(SEE NOTE 2)
DCO
WITH EXTERNAL REF
SELECT
REF
SELECT
LOCAL CLOCK FOR OPTIONAL USE WITH BDC
OUTPUT
CLOCK
SELECT
ICGDCLK /R
ICGERCLK
ICGIRCLK
NOTES:
1. See Table 7-1 for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK
2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments in
Chapter 2, “Pins and Connections for specifics.
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
106 Freescale Semiconductor
•Clock select block — The clock select block provides several switch options for connecting
different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out
of the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source,
and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency
clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC).
The module is intended to be very user friendly with many of the features occurring automatically without
user intervention. To quickly configure the module, go to Section 7.4, “Initialization/Application
Information” and pick an example that best suits the application needs.
7.1.1 Features
Features of the ICG and clock distribution system:
• Several options for the primary clock source allow a wide range of cost, frequency, and precision
choices:
— 32 kHz–100 kHz crystal or resonator
— 1 MHz–16 MHz crystal or resonator
— External clock
— Internal reference generator
• Defaults to self-clocked mode to minimize startup delays
• Frequency-locked loop (FLL) generates 8 MHz to 40 MHz (for bus rates up to 20 MHz)
— Uses external or internal clock as reference frequency
• Automatic lockout of non-running clock sources
• Reset or interrupt on loss of clock or loss of FLL lock
• Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast
frequency lock when recovering from stop3 mode
• DCO will maintain operating frequency during a loss or removal of reference clock
• Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128)
• Separate self-clocked source for real-time interrupt
• Trimmable internal clock source supports SCI communications without additional external
components
• Automatic FLL engagement after lock is acquired
• Selectable low-power/high-gain oscillator modes
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 107
7.1.2 Modes of Operation
This is a high-level description only. Detailed descriptions of operating modes are contained in
Section 7.3, “Functional Description.”
• Mode 1 — Off
The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is
executed.
• Mode 2 — Self-clocked (SCM)
Default mode of operation that is entered out of reset. The ICG’s FLL is open loop and the digitally
controlled oscillator (DCO) is free running at a frequency set by the filter bits.
• Mode 3 — FLL engaged internal (FEI)
In this mode, the ICG’s FLL is used to create frequencies that are programmable multiples of the
internal reference clock.
— FLL engaged internal unlocked is a transition state which occurs while the FLL is attempting
to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
— FLL engaged internal locked is a state which occurs when the FLL detects that the DCO is
locked to a multiple of the internal reference.
• Mode 4 — FLL bypassed external (FBE)
In this mode, the ICG is configured to bypass the FLL and use an external clock as the clock source.
• Mode 5 — FLL engaged external (FEE)
The ICG’s FLL is used to generate frequencies that are programmable multiples of the external
clock reference.
— FLL engaged external unlocked is a transition state which occurs while the FLL is attempting
to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
— FLL engaged external locked is a state which occurs when the FLL detects that the DCO is
locked to a multiple of the internal reference.
7.2 Oscillator Pins
The oscillator pins are used to provide an external clock source for the MCU.
7.2.1 EXTAL— External Reference Clock / Oscillator Input
If upon the first write to ICGC1, either FEE mode or FBE mode is selected, this pin functions as either the
external clock input or the input of the oscillator circuit as determined by REFS. If upon the first write to
ICGC1, either FEI mode or SCM mode is selected, this pin is not used by the ICG.
7.2.2 XTAL— Oscillator Output
If upon the first write to ICGC1, either FEE mode or FBE mode is selected, this pin functions as the output
of the oscillator circuit. If upon the first write to ICGC1, either FEI mode or SCM mode is selected, this
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
108 Freescale Semiconductor
pin is not used by the ICG. The oscillator is capable of being configured to provide a higher amplitude
output for improved noise immunity. This mode of operation is selected by HGO = 1.
7.2.3 External Clock Connections
If an external clock is used, then the pins are connected as shown in Figure 7-4.
Figure 7-4. External Clock Connections
7.2.4 External Crystal/Resonator Connections
If an external crystal/resonator frequency reference is used, then the pins are connected as shown in
Figure 7-5. Recommended component values are listed in Appendix A, “Electrical Characteristics.”
Figure 7-5. External Frequency Reference Connection
ICG
XTALEXTAL VSS
CLOCK INPUT
NOT CONNECTED
ICG
EXTAL XTALVSS
C1C2
CRYSTAL OR RESONATOR
RF
RS
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 109
7.3 Functional Description
This section provides a functional description of each of the five operating modes of the ICG. Also covered
are the loss of clock and loss of lock errors and requirements for entry into each mode. The ICG is very
flexible, and in some configurations, it is possible to exceed certain clock specifications. When using the
FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure
proper MCU operation.
7.3.1 Off Mode (Off)
Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state.
However there are two cases to consider when clock activity continues while the CPU is in stop mode.
7.3.1.1 BDM Active
When the BDM is enabled (ENBDM = 1), the ICG continues activity as originally programmed. This
allows access to memory and control registers via the BDC.
7.3.1.2 OSCSTEN Bit Set
When the oscillator is enabled in stop mode (OSCSTEN = 1), the individual clock generators are enabled
but the clock feed to the rest of the MCU is turned off. This option is provided to avoid long oscillator
startup times if necessary, or to run the RTI from the oscillator during stop3.
7.3.1.3 Stop/Off Mode Recovery
Upon the CPU exiting stop mode due to an interrupt, the previously set control bits are valid and the system
clock feed resumes. If FEE is selected, the ICG will source the internal reference until the external clock
is stable. If FBE is selected, the ICG will wait for the external clock to stabilize before enabling ICGOUT.
Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the
default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an
approximately 8 MHz DCO output (4 MHz bus clock) with trim value maintained. If using a crystal, 4096
clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time.
7.3.2 Self-Clocked Mode (SCM)
Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following
conditions occur:
• After any reset.
• Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state
temporarily until the DCO is stable (DCOS = 1).
• CLKS bits are written from X1 to 00.
• CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1).
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
110 Freescale Semiconductor
In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given
by fICGDCLK / R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value
into the filter registers (ICGFLTU and ICGFLTL). This is the only mode in which the filter registers can
be written.
If this mode is entered due to a reset, fICGDCLK will default to fSelf_reset which is nominally 8 MHz. If this
mode is entered from FLL engaged internal, fICGDCLK will maintain the previous frequency. If this mode
is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference
clock), fICGDCLK will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked.
If this mode is entered from off mode, fICGDCLK will be equal to the frequency of ICGDCLK before
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. Once ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
Figure 7-6. Detailed Frequency-Locked Loop Block Diagram
REFERENCE
DIVIDER (/7)
RFD
CLKST
SUBTRACTOR
LOOP
FILTER
DIGITALLY
CONTROLLED
OSCILLATOR
CLOCK ICGOUT
ICG2DCLK
RESET AND
INTERRUPT
IRQ
FLL ANALOG
SELECT
CIRCUIT
LOLS
PULSE
COUNTER
MFD
FREQUENCY-
ICGERCLK
LOCS
LOCK AND
DETECTOR
LOCK
CONTROL
LOLRE LOCRE
RESET
REDUCED
FREQUENCY
DIVIDER (R)
LOSS OF CLOCK
ICGIF
ERCS
ICGDCLK
LOOP (FLL)
DIGITAL
FLT
COUNTER ENABLE
LOCKED
OVERFLOW
1x
2x
ICGIRCLK
CLKST
DCOS
RANGE
RANGE
CLKS
LOCD
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 111
7.3.3 FLL Engaged, Internal Clock (FEI) Mode
FLL engaged internal (FEI) is entered when any of the following conditions occur:
• CLKS bits are written to 01
• The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01
In FLL engaged internal mode, the reference clock is derived from the internal reference clock
ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as
selected by the MFD bits.
7.3.3.1 FLL Engaged Internal Unlocked
FEI unlocked is a temporary state that is entered when FEI is entered and the count error (Δn) output from
the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the
lock detector to detect the unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum nlock or less than
the minimum nlock, as required by the lock detector to detect the lock condition.
In this state the output clock signal ICGOUT frequency is given by fICGDCLK / R.
7.3.3.2 FLL Engaged Internal Locked
FLL engaged internal locked is entered from FEI unlocked when the count error (Δn), which comes from
the subtractor, is less than nlock (max) and greater than nlock (min) for a given number of samples, as
required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is
given by fICGDCLK / R. In FEI locked, the filter value is only updated once every four comparison cycles.
The update made is an average of the error measurements taken in the four previous comparisons.
7.3.4 FLL Bypassed, External Clock (FBE) Mode
FLL bypassed external (FBE) is entered when any of the following conditions occur:
• From SCM when CLKS = 10 and ERCS is high
• When CLKS = 10, ERCS = 1 upon entering off mode, and off is then exited
• From FLL engaged external mode if a loss of DCO clock occurs and the external reference is still
valid (both LOCS = 1 and ERCS = 1)
In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock,
ICGERCLK. The output clock signal ICGOUT frequency is given by fICGERCLK / R. If an external clock
source is used (REFS = 0), then the input frequency on the EXTAL pin can be anywhere in the range
0 MHz to 40 MHz. If a crystal or resonator is used (REFS = 1), then frequency range is either low for
RANGE = 0 or high for RANGE = 1.
7.3.5 FLL Engaged, External Clock (FEE) Mode
The FLL engaged external (FEE) mode is entered when any of the following conditions occur:
• CLKS = 11 and ERCS and DCOS are both high.
• The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11.
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
112 Freescale Semiconductor
In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL
loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To
run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The
maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO.
The minimum multiplier for the FLL, from Table 7-7, is 4. Because 4 X 10 MHz is 40 MHz, which is the
operational limit of the DCO, the reference clock cannot be any faster than 10 MHz.
7.3.5.1 FLL Engaged External Unlocked
FEE unlocked is entered when FEE is entered and the count error (Δn) output from the subtractor is greater
than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the
unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum nlock or less than
the minimum nlock, as required by the lock detector to detect the lock condition.
In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to
lock it according to their operational descriptions later in this section. Upon entering this state and until
the FLL becomes locked, the output clock signal ICGOUT frequency is given by fICGDCLK / (2×R). This
extra divide by two prevents frequency overshoots during the initial locking process from exceeding
chip-level maximum frequency specifications. As soon as the FLL has locked, if an unexpected loss of
lock causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal
ICGOUT frequency is given by fICGDCLK / R.
7.3.5.2 FLL Engaged External Locked
FEE locked is entered from FEE unlocked when the count error (Δn) is less than nlock (max) and greater
than nlock (min) for a given number of samples, as required by the lock detector to detect the lock
condition. The output clock signal ICGOUT frequency is given by fICGDCLK/R. In FLL engaged external
locked, the filter value is only updated once every four comparison cycles. The update made is an average
of the error measurements taken in the four previous comparisons.
7.3.6 FLL Lock and Loss-of-Lock Detection
To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO
for one comparison cycle (see Table 7-2 for explanation of a comparison cycle) and passes this number to
the subtractor. The subtractor compares this value to the value in MFD and produces a count error, Δn. To
achieve locked status, Δn must be between nlock (min) and nlock (max). As soon as the FLL has locked, Δn
must stay between nunlock (min) and nunlock (max) to remain locked. If Δn goes outside this range
unexpectedly, the LOLS status bit is set and remains set until acknowledged or until the MCU is reset.
LOLS is cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced
reset (LOLRE = 1), or by any MCU reset.
If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN = 0, the FLL loses locked
status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock
condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 113
the off state. Because this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up
from stop.
Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the
TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the
LOLS will not be set.
7.3.7 FLL Loss-of-Clock Detection
The reference clock and the DCO clock are monitored under different conditions (see Table 7-1). Provided
the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum
frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls
below a certain frequency, fLOR and fLOD, respectively, the LOCS status bit will be set to indicate the error.
LOCS will remain set until it is cleared by software or until the MCU is reset. LOCS is cleared by reading
ICGS1 then writing 1 to ICGIF (LOCRE = 0), or by a loss-of-clock induced reset (LOCRE = 1), or by any
MCU reset.
If the ICG is in FEE, a loss of reference clock causes the ICG to enter SCM, and a loss of DCO clock causes
the ICG to enter FBE mode. If the ICG is in FBE mode, a loss of reference clock will cause the ICG to
enter SCM. In each case, the CLKST and CLKS bits will be automatically changed to reflect the new state.
A loss of clock will also cause a loss of lock when in FEE or FEI modes. Because the method of clearing
the LOCS and LOLS bits is the same, this would only be an issue in the unlikely case that LOLRE = 1 and
LOCRE = 0. In this case, the interrupt would be overridden by the reset for the loss of lock.
Table 7-1. Clock Monitoring (When LOCD = 0)
Mode CLKS REFST ERCS
External Reference
Clock
Monitored?
DCO Clock
Monitored?
Off
0X or 11 X Forced Low No No
10 0 Forced Low No No
10 1 Real-Time1
1If ENABLE is high (waiting for external crystal start-up after exiting stop).
Ye s (1) No
SCM
(CLKST = 00)
0X X Forced Low No Ye s 2
2DCO clock will not be monitored until DCOS = 1 upon entering SCM from off or FLL bypassed external mode.
10 0 Forced High No Ye s (2)
10 1 Real-Time Yes Ye s (2)
11 X Real-Time Yes Ye s (2)
FEI
(CLKST = 01)
0X X Forced Low No Yes
11 X Real-Time Yes Yes
FBE
(CLKST = 10)
10 0 Forced High No No
10 1 Real-Time Yes No
FEE
(CLKST = 11) 11 X Real-Time Yes Yes
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
114 Freescale Semiconductor
7.3.8 Clock Mode Requirements
A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by
CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should
be the same as the requested mode in CLKS1:CLKS0. Table 7-2 shows the relationship between CLKS,
CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS ≠ CLKST.
NOTE
If a crystal will be used before the next reset, then be sure to set REFS = 1
and CLKS = 1x on the first write to the ICGC1 register. Failure to do so will
result in “locking” REFS = 0, which will prevent the oscillator amplifier
from being enabled until the next reset occurs.
Table 7-2. ICG State Table
Actual
Mode
(CLKST)
Desired
Mode
(CLKS)
Range
Reference
Frequency
(fREFERENCE)
Comparison
Cycle Time ICGOUT Conditions1 for
CLKS = CLKST
1CLKST will not update immediately after a write to CLKS. Several bus cycles are required before CLKST updates to the new
value.
Reason
CLKS1 =
CLKST
Off
(XX)
Off
(XX) X0 — 0 — —
FBE
(10) X 0 — 0 — ERCS = 0
SCM
(00)
SCM
(00) XfICGIRCLK/72
2The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the comparisons
that determine the DCOS bit.
8/fICGIRCLK ICGDCLK/R Not switching from
FBE to SCM —
FEI
(01) 0fICGIRCLK/7(1) 8/fICGIRCLK ICGDCLK/R — DCOS = 0
FBE
(10) XfICGIRCLK/7(1) 8/fICGIRCLK ICGDCLK/R — ERCS = 0
FEE
(11) XfICGIRCLK/7(1) 8/fICGIRCLK ICGDCLK/R — DCOS = 0 or
ERCS = 0
FEI
(01)
FEI
(01) 0fICGIRCLK/7 8/fICGIRCLK ICGDCLK/R DCOS = 1 —
FEE
(11) XfICGIRCLK/7 8/fICGIRCLK ICGDCLK/R — ERCS = 0
FBE
(10)
FBE
(10) X 0 — ICGERCLK/R ERCS = 1 —
FEE
(11) X 0 — ICGERCLK/R — LOCS = 1 &
ERCS = 1
FEE
(11)
FEE
(11)
0fICGERCLK 2/fICGERCLK ICGDCLK/R3
3After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are
changed.
ERCS = 1 and
DCOS = 1 —
1fICGERCLK 128/fICGERCLK ICGDCLK/R(2) ERCS = 1 and
DCOS = 1 —
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 115
7.3.9 Fixed Frequency Clock
The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is
equal to the internal bus clock, BUSCLK, in FBE mode. In FEE mode, XCLK is equal to ICGERCLK ÷2
when the following conditions are met:
•(P × N) ÷ R ≥ 4 where P is determined by RANGE (see Table 7-4), N and R are determined by
MFD and RFD, respectively (see Table 7-5).
• LOCK = 1.
If the above conditions are not true, then XCLK is equal to BUSCLK.
When the ICG is in either FEI or SCM mode, XCLK is turned off. Any peripherals which can use XCLK
as a clock source must not do so when the ICG is in FEI or SCM mode.
7.3.10 High Gain Oscillator
The oscillator has the option of running in a high gain oscillator (HGO) mode, which improves the
oscillator's resistance to EMC noise when running in FBE or FEE modes. This option is selected by writing
a 1 to the HGO bit in the ICGC1 register. HGO is used with both the high and low range oscillators but is
only valid when REFS = 1 in the ICGC1 register. When HGO = 0, the standard low-power oscillator is
selected.
If the high gain option is to be switched after the initial write to the ICGC1 register, then the ICG should
first be changed to SCM or FEI mode to stop the external oscillator. Then the HGO bit can be modified
and FEE or FBE mode can be re-selected in the same write to ICGC1. The oscillator will go through the
standard start-up delay before the ICG switches to the external oscillator
7.4 Initialization/Application Information
7.4.1 Introduction
This section is intended to give some basic direction on which configuration a user would want to select
when initializing the ICG. For some applications, the serial communication link may dictate the accuracy
of the clock reference. For other applications, lowest power consumption may be the chief clock
consideration. Still others may have lowest cost as the primary goal. The ICG allows great flexibility in
choosing which is best for any application.
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
116 Freescale Semiconductor
The following sections contain initialization examples for various configurations.
NOTE
Hexadecimal values designated by a preceding $, binary values designated
by a preceding %, and decimal values have no preceding character.
Important configuration information is repeated here for reference.
Table 7-3. ICG Configuration Consideration
Clock Reference Source = Internal Clock Reference Source = External
FLL
Engaged
FEI
4 MHz < fBus < 20 MHz.
Medium power (will be less than FEE if oscillator
range = high)
Medium clock accuracy (After IRG is trimmed)
Lowest system cost (no external components
required)
IRG is on. DCO is on. 1
1The IRG typically consumes 100 μA. The FLL and DCO typically consumes 0.5 to 2.5 mA, depending upon output frequency.
For minimum power consumption and minimum jitter, choose N and R to be as small as possible.
FEE
4 MHz < fBus < 20 MHz
Medium power (will be less than FEI if oscillator
range = low)
Good clock accuracy
Medium/High system cost (crystal, resonator or
external clock source required)
IRG is off. DCO is on.
FLL
Bypassed
SCM
This mode is mainly provided for quick and reliable
system startup.
3 MHz < fBus < 5 MHz (default).
3 MHz < fBus < 20 MHz (via filter bits).
Medium power
Poor accuracy.
IRG is off. DCO is on and open loop.
FBE
fBus range <= 8 MHz when crystal or resonator is
used.
Lowest power
Highest clock accuracy
Medium/High system cost (Crystal, resonator or
external clock source required)
IRG is off. DCO is off.
Table 7-4. ICGOUT Frequency Calculation Options
Clock Scheme fICGOUT1
1Ensure that fICGDCLK, which is equal to fICGOUT * R, does not exceed fICGDCLKmax.
PNote
SCM — self-clocked mode (FLL bypassed
internal) fICGDCLK / R NA Typical fICGOUT =
8 MHz out of reset
FBE — FLL bypassed external fext / R NA
FEI — FLL engaged internal (fIRG / 7)* 64*N / R 64 Typical fIRG = 243 kHz
FEE — FLL engaged external fext * P * N / R Range = 0 ; P = 64
Range = 1; P = 1
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 117
Figure 7-7. ICG Register Set
Table 7-5. MFD and RFD Decode Table
MFD Value Multiplication Factor (N) RFD Division Factor (R)
000 4 000 ÷1
001 6 001 ÷2
010 8 010 ÷4
011 10 011 ÷8
100 12 100 ÷16
101 14 101 ÷32
110 16 110 ÷64
111 18 111 ÷128
RegisterBit 7654321Bit 0
ICGC1 HGO RANGE REFS CLKS OSCSTEN LOCD 0
ICGC2 LOLRE MFD LOCRE RFD
ICGS1 CLKST REFST LOLS LOCK LOCS ERCS ICGIF
ICGS2 0000000 DCOS
ICGFLTU 0000FLT
ICGFLTL FLT
ICGTRM TRIM
= Unimplemented or Reserved
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
118 Freescale Semiconductor
7.4.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz
In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to
8.38 MHz to achieve 4.19 MHz bus frequency.
After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately
8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (fBus).
The clock scheme will be FLL engaged, external (FEE). So
fICGOUT = fext * P * N / R ; P = 64, fext = 32 kHz Eqn. 7-1
Solving for N / R gives:
N / R = 8.38 MHz /(32 kHz * 64) = 4 ; we can choose N = 4 and R =1 Eqn. 7-2
The values needed in each register to set up the desired operation are:
ICGC1 = $38 (%00111000)
Bit 7 HGO 0 Configures oscillator for low-power operation
Bit 6 RANGE 0 Configures oscillator for low-frequency range; FLL prescale factor is 64
Bit 5 REFS 1 Oscillator using crystal or resonator is requested
Bits 4:3 CLKS 11 FLL engaged, external reference clock mode
Bit 2 OSCSTEN 0 Oscillator disabled in stop modes
Bit 1 LOCD 0 Loss-of-clock detection enabled
Bit 0 0 Unimplemented or reserved, always reads zero
ICGC2 = $00 (%00000000)
Bit 7 LOLRE 0 Generates an interrupt request on loss of lock
Bits 6:4 MFD 000 Sets the MFD multiplication factor to 4
Bit 3 LOCRE 0 Generates an interrupt request on loss of clock
Bits 2:0 RFD 000 Sets the RFD division factor to ÷1
ICGS1 = $xx
This is read only except for clearing interrupt flag
ICGS2 = $xx
This is read only; should read DCOS = 1 before performing any time critical tasks
ICGFLTLU/L = $xx
Only needed in self-clocked mode; FLT will be adjusted by loop to give 8.38 MHz DCO clock
Bits 15:12 unused 0000
Bits 11:0 FLT No need for user initialization
ICGTRM = $xx
Bits 7:0 TRIM Only need to write when trimming internal oscillator; not used when external
crystal is clock source
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 119
Figure 7-8 shows flow charts for three conditions requiring ICG initialization.
Figure 7-8. ICG Initialization for FEE in Example #1
7.4.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz
In this example, the FLL will be used (in FEE mode) to multiply the external 4 MHz oscillator up to
40-MHz to achieve 20 MHz bus frequency.
After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately
8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus).
During reset initialization software, the clock scheme will be set to FLL engaged, external (FEE). So
fICGOUT = fext * P * N / R ; P = 1, fext = 4.00 MHz Eqn. 7-3
Solving for N / R gives:
N / R = 40 MHz /(4 MHz * 1) = 10 ; We can choose N = 10 and R = 1 Eqn. 7-4
The values needed in each register to set up the desired operation are:
ICGC1 = $78 (%01111000)
Bit 7 HGO 0 Configures oscillator for low-power operation
Bit 6 RANGE 1 Configures oscillator for high-frequency range; FLL prescale factor is 1
Bit 5 REFS 1 Requests an oscillator
Bits 4:3 CLKS 11 FLL engaged, external reference clock mode
Bit 2 OSCSTEN 0 Disables the oscillator in stop modes
Bit 1 LOCD 0 Loss-of-clock detection enabled
Bit 0 0 Unimplemented or reserved, always reads zero
RECOVERY FROM
CONTINUE
RECOVERY FROM STOP3
CHECK
LOCK = 1?
NO
YES
FLL LOCK STATUS.
INITIALIZE ICG
ICG1 = $38
ICG2 = $00
RECOVERY FROM STOP3
OSCSTEN = 1 OSCSTEN = 0
CONTINUE
CHECK
LOCK = 1?
NO
YES
FLL LOCK STATUS.
CONTINUE
CHECK
LOCK = 1?
NO
YES
FLL LOCK STATUS.
NOTE: THIS WILL REQUIRE THE OSCILLATOR TO START AND
STABILIZE. ACTUAL TIME IS DEPENDENT ON CRYSTAL /RESONATOR
AND EXTERNAL CIRCUITRY.
QUICK RECOVERY FROM STOP MINIMUM CURRENT DRAW IN STOP
RESET, STIO1, STOP2
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
120 Freescale Semiconductor
ICGC2 = $30 (%00110000)
Bit 7 LOLRE 0 Generates an interrupt request on loss of lock
Bit 6:4 MFD 011 Sets the MFD multiplication factor to 10
Bit 3 LOCRE 0 Generates an interrupt request on loss of clock
Bit 2:0 RFD 000 Sets the RFD division factor to ÷1
ICGS1 = $xx
This is read only except for clearing interrupt flag
ICGS2 = $xx
This is read only. Should read DCOS before performing any time critical tasks
ICGFLTLU/L = $xx
Not used in this example
ICGTRM
Not used in this example
Figure 7-9. ICG Initialization and Stop Recovery for Example #2
RECOVERY FROM
CONTINUE
RECOVERY
CHECK
LOCK = 1?
NO
YES
FLL LOCK STATUS
INITIALIZE ICG
ICG1 = $7A
ICG2 = $30
CONTINUE
CHECK
LOCK = 1?
NO
YES
FLL LOCK STATUS
SERVICE INTERRUPT
SOURCE (fBus = 4 MHz)
FROM STOP3
RESET, STOP1, STOP2
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 121
7.4.4 Example #3: No External Crystal Connection, 5.4 MHz Bus
Frequency
In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate)
reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim
function to fine tune the frequency based on an external reference signal.
After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately
8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus).
The clock scheme will be FLL engaged, internal (FEI). So
fICGOUT = (fIRG / 7) * P * N / R ; P = 64, fIRG = 243 kHz Eqn. 7-5
Solving for N / R gives:
N / R = 10.8 MHz /(243/7 kHz * 64) = 4.86 ; We can choose N = 10 and R = 2. Eqn. 7-6
A trim procedure will be required to hone the frequency to exactly 5.4 MHz. An example of the trim
procedure is shown in example #4.
The values needed in each register to set up the desired operation are:
ICGC1 = $28 (%00101000)
Bit 7 HGO 0 Configures oscillator for low-power operation
Bit 6 RANGE 0 Configures oscillator for low-frequency range; FLL prescale factor is 64
Bit 5 REFS 1 Oscillator using crystal or resonator requested (bit is really a don’t care)
Bits 4:3 CLKS 01 FLL engaged, internal reference clock mode
Bit 2 OSCSTEN 0 Disables the oscillator in stop modes
Bit 1 LOCD 0 Loss-of-clock detection enabled
Bit 0 0 Unimplemented or reserved, always reads zero
ICGC2 = $31 (%00110001)
Bit 7 LOLRE 0 Generates an interrupt request on loss of lock
Bit 6:4 MFD 011 Sets the MFD multiplication factor to 10
Bit 3 LOCRE 0 Generates an interrupt request on loss of clock
Bit 2:0 RFD 001 Sets the RFD division factor to ÷2
ICGS1 = $xx
This is read only except for clearing interrupt flag
ICGS2 = $xx
This is read only; good idea to read this before performing time critical operations
ICGFLTLU/L = $xx
Not used in this example
ICGTRM = $xx
Bit 7:0 TRIM Only need to write when trimming internal oscillator; done in separate
operation (see example #4)
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
122 Freescale Semiconductor
Figure 7-10. ICG Initialization and Stop Recovery for Example #3
7.4.5 Example #4: Internal Clock Generator Trim
The internally generated clock source is guaranteed to have a period ± 25% of the nominal value. In some
case this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a
trimming procedure is provided that will allow a very accurate source. This section outlines one example
of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used.
RECOVERY FROM
CONTINUE
CHECK
LOCK = 1?
NO
YES
FLL LOCK STATUS.
INITIALIZE ICG
ICG1 = $28
ICG2 = $31
RECOVERY
CONTINUE
CHECK
LOCK = 1?
NO
YES
FLL LOCK STATUS.
NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND
STABILIZE.
FROM STOP3
RESET, STOP1, STOP2
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 123
Figure 7-11. Trim Procedure
In this particular case, the MCU has been attached to a PCB and the entire assembly is undergoing final
test with automated test equipment. A separate signal or message is provided to the MCU operating under
user provided software control. The MCU initiates a trim procedure as outlined in Figure 7-11 while the
tester supplies a precision reference signal.
If the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using
a reduction divisor (R) twice the final value. Once the trim procedure is complete, the reduction divisor
can be restored. This will prevent accidental overshoot of the maximum clock frequency.
7.5 ICG Registers and Control Bits
Refer to the direct-page register summary in Chapter 4, “Memory” of this data sheet for the absolute
address assignments for all ICG registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file is used to translate these names into the appropriate
absolute addresses.
Initial conditions:
1) Clock supplied from ATE has 500 μs duty period
2) ICG configured for internal reference with 4 MHz bus
START TRIM PROCEDURE
CONTINUE
CASE STATEMENT
COUNT > SZZEXPECTED = 500
.
MEASURE
INCOMING CLOCK WIDTH
ICGTRM = $80, n = 1
COUNT < EXPECTED = 500
COUNT = EXPECTED = 500
STORE ICGTRM VALUE
IN NON-VOLATILE
MEMORY
ICGTRM =
ICGTRM =
ICGTRM - 128 / (2**n) ICGTRM + 128 / (2**n)
n = n + 1
(COUNT = # OF BUS CLOCKS / 4)
(DECREASING ICGTRM
INCREASES THE FREQUENCY)
(INCREASING ICGTRM
DECREASES THE FREQUENCY)
NO
YES
IS n > 8?
(RUNNING TOO SLOW)
(RUNNING TOO FAST)
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
124 Freescale Semiconductor
7.5.1 ICG Control Register 1 (ICGC1)
76543210
R
HGO RANGE REFS CLKS OSCSTEN LOCD
0
W
Reset01000100
= Unimplemented or Reserved
Figure 7-12. ICG Control Register 1 (ICGC1)
Table 7-6. ICGC1 Field Descriptions
Field Description
7
HGO
High Gain Oscillator Select — The HGO bit is used to select between low-power operation and high-amplitude
operation.
0 Oscillator configured for low power operation.
1 Oscillator configured for high amplitude operation.
6
RANGE
Frequency Range Select — The RANGE bit controls the oscillator, reference divider, and FLL loop prescaler
multiplication factor (P). It selects one of two reference frequency ranges for the ICG. The RANGE bit is
write-once after a reset. The RANGE bit only has an effect in FLL engaged external and FLL bypassed external
modes.
0 Oscillator configured for low frequency range. FLL loop prescale factor P is 64.
1 Oscillator configured for high frequency range. FLL loop prescale factor P is 1.
5
REFS
External Reference Select — The REFS bit controls the external reference clock source for ICGERCLK. The
REFS bit is write-once after a reset.
0 External clock requested.
1 Oscillator using crystal or resonator requested.
4:3
CLKS
Clock Mode Select — The CLKS bits control the clock mode. If FLL bypassed external is requested, it will not
be selected until ERCS = 1. If the ICG enters off mode, the CLKS bits will remain unchanged. Writes to the CLKS
bits will not take effect if a previous write is not complete.
The CLKS bits are writable at any time, unless the first write after a reset was CLKS = 0X, the CLKS bits cannot
be written to 1X until after the next reset (because the EXTAL pin was not reserved).
00 Self-clocked
01 FLL engaged, internal reference
10 FLL bypassed, external reference
11 FLL engaged, external reference
2
OSCSTEN
Enable Oscillator in Off Mode — The OSCTEN bit controls whether or not the oscillator circuit remains enabled
when the ICG enters off mode.
0 Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1.
1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1.
1
LOCD
Loss of Clock Disable
0 Loss of clock detection enabled.
1 Loss of clock detection disabled.
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 125
7.5.2 ICG Control Register 2 (ICGC2)
76543210
R
LOLRE MFD LOCRE RFD
W
Reset00000000
Figure 7-13. ICG Control Register 2 (ICGC2)
Table 7-7. ICGC2 Field Descriptions
Field Description
7
LOLRE
Loss of Lock Reset Enable — The LOLRE bit determines what type of request is made by the ICG following a
loss of lock indication. The LOLRE bit only has an effect when LOLS is set.
0 Generate an interrupt request on loss of lock.
1 Generate a reset request on loss of lock.
6:4
MFD
Multiplication Factor — The MFD bits control the programmable multiplication factor in the FLL loop. The value
specified by the MFD bits establishes the multiplication factor (N) applied to the reference frequency. Writes to
the MFD bits will not take effect if a previous write is not complete. Select a low enough value for N such that
fICGDCLK does not exceed its maximum specified rating.
000 Multiplication Factor (N) = 4
001 Multiplication Factor (N) = 6
010 Multiplication Factor (N) = 8
011 Multiplication Factor (N) = 10
100 Multiplication Factor (N) = 12
101 Multiplication Factor (N) = 14
110 Multiplication Factor (N) = 16
111 Multiplication Factor (N) = 18
3
LOCRE
Loss of Clock Reset Enable — The LOCRE bit determines how the system handles a loss of clock condition.
0 Generate an interrupt request on loss of clock.
1 Generate a reset request on loss of clock.
2:0
RFD
Reduced Frequency Divider — The RFD bits control the value of the divider following the clock select circuitry.
The value specified by the RFD bits establishes the division factor (R) applied to the selected output clock source.
Writes to the RFD bits will not take effect if a previous write is not complete.
000 Division Factor (R) = 1
001 Division Factor (R) = 2
010 Division Factor (R) = 4
011 Division Factor (R) = 8
100 Division Factor (R) = 16
101 Division Factor (R) = 32
110 Division Factor (R) = 64
111 Division Factor (R) = 128
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
126 Freescale Semiconductor
7.5.3 ICG Status Register 1 (ICGS1)
76543210
R CLKST REFST LOLS LOCK LOCS ERCS ICGIF
W 1
Reset00000000
= Unimplemented or Reserved
Figure 7-14. ICG Status Register 1 (ICGS1)
Table 7-8. ICGS1 Field Descriptions
Field Description
7:6
CLKST
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00 Self-clocked
01 FLL engaged, internal reference
10 FLL bypassed, external reference
11 FLL engaged, external reference
5
REFST
Reference Clock Status — The REFST bit indicates which clock reference is currently selected by the
Reference Select circuit.
0 External Clock selected.
1 Crystal/Resonator selected.
4
LOLS
FLL Loss of Lock Status — The LOLS bit is an indication of FLL-lock status. If LOLS is set, it remains set until
cleared by clearing the ICGIF flag or an MCU reset.
0 FLL has not unexpectedly lost lock since LOLS was last cleared.
1 FLL has unexpectedly lost lock since LOLS was last cleared, LOLRE determines action taken.
3
LOCK
FLL Lock Status — The LOCK bit indicates whether the FLL has acquired lock. The LOCK bit is cleared in off,
self-clocked, and FLL bypassed modes.
0 FLL is currently unlocked.
1 FLL is currently locked.
2
LOCS
Loss Of Clock Status — The LOCS bit is an indication of ICG loss-of-clock status. If LOCS is set, it remains set
until cleared by clearing the ICGIF flag or an MCU reset.
0 ICG has not lost clock since LOCS was last cleared.
1 ICG has lost clock since LOCS was last cleared, LOCRE determines action taken.
1
ERCS
External Reference Clock Status — The ERCS bit is an indication of whether or not the external reference clock
(ICGERCLK) meets the minimum frequency requirement.
0 External reference clock is not stable, frequency requirement is not met.
1 External reference clock is stable, frequency requirement is met.
0
ICGIF
ICG Interrupt Flag — The ICGIF read/write flag is set when an ICG interrupt request is pending. It is cleared by
a reset or by reading the ICG status register when ICGIF is set and then writing a 1 to ICGIF. If another ICG
interrupt occurs before the clearing sequence is complete, the sequence is reset so ICGIF would remain set after
the clear sequence was completed for the earlier interrupt. Writing a 0 to ICGIF has no effect.
0 No ICG interrupt request is pending.
1 An ICG interrupt request is pending.
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 127
7.5.4 ICG Status Register 2 (ICGS2)
7.5.5 ICG Filter Registers (ICGFLTU, ICGFLTL)
The filter registers show the filter value (FLT).
76543210
R0000000DCOS
W
Reset00000000
= Unimplemented or Reserved
Figure 7-15. ICG Status Register 2 (ICGS2)
Table 7-9. ICGS2 Field Descriptions
Field Description
0
DCOS
DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error
has not changed by more than nunlock for two consecutive samples and the DCO clock is not static. This bit is
used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It is also used
in self-clocked mode to determine when to start monitoring the DCO clock. This bit is cleared upon entering the
off state.
0 DCO clock is unstable.
1 DCO clock is stable.
76543210
R0000
FLT
W
Reset00000000
= Unimplemented or Reserved
Figure 7-16. ICG Upper Filter Register (ICGFLTU)
Table 7-10. ICGFLTU Field Descriptions
Field Description
3:0
FLT
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete.
Internal Clock Generator (S08ICGV2)
MC9S08GB60A Data Sheet, Rev. 2
128 Freescale Semiconductor
7.5.6 ICG Trim Register (ICGTRM)
76543210
R
FLT
W
Reset11000000
= Unimplemented or Reserved
Figure 7-17. ICG Upper Filter Register (ICGFLTL)
Table 7-11. ICGFLTL Field Descriptions
Field Description
7:0
FLT
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete.
76543210
R
TRIM
W
POR:10000000
Reset:uuuuuuuu
= Unimplemented or Reserved u = Unaffected by MCU reset
Figure 7-18. ICG Trim Register (ICGTRM)
Table 7-12. ICGTRM Field Descriptions
Field Description
7:0
TRIM
ICG Trim Setting — The TRIM bits control the internal reference generator frequency. They allow a ± 25%
adjustment of the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice
as much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing the value
will decrease the period.
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 129
Chapter 8
Central Processor Unit (S08CPUV2)
8.1 Introduction
This section provides summary information about the registers, addressing modes, and instruction set of
the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference
Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D.
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several
instructions and enhanced addressing modes were added to improve C compiler efficiency and to support
a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers
(MCU).
8.1.1 Features
Features of the HCS08 CPU include:
• Object code fully upward-compatible with M68HC05 and M68HC08 Families
• All registers and memory are mapped to a single 64-Kbyte address space
• 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
• 16-bit index register (H:X) with powerful indexed addressing modes
• 8-bit accumulator (A)
• Many instructions treat X as a second general-purpose 8-bit register
• Seven addressing modes:
— Inherent — Operands in internal registers
— Relative — 8-bit signed offset to branch destination
— Immediate — Operand in next object code byte(s)
— Direct — Operand in memory at 0x0000–0x00FF
— Extended — Operand anywhere in 64-Kbyte address space
— Indexed relative to H:X — Five submodes including auto increment
— Indexed relative to SP — Improves C efficiency dramatically
• Memory-to-memory data move instructions with four address mode combinations
• Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on
the results of signed, unsigned, and binary-coded decimal (BCD) operations
• Efficient bit manipulation instructions
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• STOP and WAIT instructions to invoke low-power operating modes
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
130 Freescale Semiconductor
8.2 Programmer’s Model and CPU Registers
Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map.
Figure 8-1. CPU Registers
8.2.1 Accumulator (A)
The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit
(ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after
arithmetic and logical operations. The accumulator can be loaded from memory using various addressing
modes to specify the address where the loaded data comes from, or the contents of A can be stored to
memory using various addressing modes to specify the address where data from A will be stored.
Reset has no effect on the contents of the A accumulator.
8.2.2 Index Register (H:X)
This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit
address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All
indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer;
however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the
low-order 8-bit half (X).
Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data
values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer
instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations
can then be performed.
For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect
on the contents of X.
SP
PC
CONDITION CODE REGISTER
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
H X
0
0
0
7
15
15
70
ACCUMULATOR A
INDEX REGISTER (LOW)INDEX REGISTER (HIGH)
STACK POINTER
87
PROGRAM COUNTER
16-BIT INDEX REGISTER H:X
CCR
CV11HINZ
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 131
8.2.3 Stack Pointer (SP)
This 16-bit address pointer register points at the next available location on the automatic last-in-first-out
(LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can
be any size up to the amount of available RAM. The stack is used to automatically save the return address
for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The
AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most
often used to allocate or deallocate space for local variables on the stack.
SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs
normally change the value in SP to the address of the last location (highest address) in on-chip RAM
during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF).
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and
is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer.
8.2.4 Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
During normal program execution, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return
operations load the program counter with an address other than that of the next sequential location. This
is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF.
The vector stored there is the address of the first instruction that will be executed after exiting the reset
state.
8.2.5 Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of
the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code bits in general terms. For a more detailed explanation of how each
instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale
Semiconductor document order number HCS08RMv1.
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
132 Freescale Semiconductor
Figure 8-2. Condition Code Register
Table 8-1. CCR Register Field Descriptions
Field Description
7
V
Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs.
The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0 No overflow
1Overflow
4
H
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during
an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded
decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
3
I
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service
routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening
interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled
2
N
Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data
manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most significant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result
1
Z
Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the
loaded or stored value was all 0s.
0 Non-zero result
1Zero result
0
C
Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit
7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
0 No carry out of bit 7
1 Carry out of bit 7
CONDITION CODE REGISTER
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
70
CCR
CV11HINZ
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 133
8.3 Addressing Modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status
and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit
binary address can uniquely identify any memory location. This arrangement means that the same
instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile
program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
of an operand for a test and then use relative addressing mode to specify the branch destination address
when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in
the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.
8.3.1 Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU
registers so the CPU does not need to access memory to get any operands.
8.3.2 Relative Addressing Mode (REL)
Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit
offset value is located in the memory location immediately following the opcode. During execution, if the
branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current
contents of the program counter, which causes program execution to continue at the branch destination
address.
8.3.3 Immediate Addressing Mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is included in the object
code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand,
the high-order byte is located in the next memory location after the opcode, and the low-order byte is
located in the next memory location after that.
8.3.4 Direct Addressing Mode (DIR)
In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page
(0x0000–0x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the
high-order half of the address and the direct address from the instruction to get the 16-bit address where
the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit
address for the operand.
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
134 Freescale Semiconductor
8.3.5 Extended Addressing Mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).
8.3.6 Indexed Addressing Mode
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair
and two that use the stack pointer as the base reference.
8.3.6.1 Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.
8.3.6.2 Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV
and CBEQ instructions.
8.3.6.3 Indexed, 8-Bit Offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
8.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.
8.3.6.5 Indexed, 16-Bit Offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
8.3.6.6 SP-Relative, 8-Bit Offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 135
8.3.6.7 SP-Relative, 16-Bit Offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
8.4 Special Operations
The CPU performs a few special operations that are similar to instructions but do not have opcodes like
other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU
circuitry. This section provides additional information about these operations.
8.4.1 Reset Sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer
operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event
occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction
boundary before responding to a reset event). For a more detailed discussion about how the MCU
recognizes resets and determines the source, refer to the Resets, Interrupts, and System Configuration
chapter.
The reset event is considered concluded when the sequence to determine whether the reset came from an
internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the
CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the
instruction queue in preparation for execution of the first program instruction.
8.4.2 Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before responding to the
interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where
the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the
same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the
vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch three bytes of program information starting at the address indicated by the interrupt vector
to fill the instruction queue in preparation for execution of the first instruction in the interrupt
service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts
while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
136 Freescale Semiconductor
interrupt service routine, this would allow nesting of interrupts (which is not recommended because it
leads to programs that are difficult to debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H)
is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the
beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends
the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine
does not use any instructions or auto-increment addressing modes that might change the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the
global I bit in the CCR and it is associated with an instruction opcode within the program so it is not
asynchronous to program execution.
8.4.3 Wait Mode Operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the
CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that
will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume
and the interrupt or reset event will be processed normally.
If a serial BACKGROUND command is issued to the MCU through the background debug interface while
the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where
other serial background commands can be processed. This ensures that a host development system can still
gain access to a target MCU even if it is in wait mode.
8.4.4 Stop Mode Operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to
minimize power consumption. In such systems, external circuitry is needed to control the time spent in
stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike
the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of
clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU
from stop mode.
When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control
bit has been set by a serial command through the background interface (or because the MCU was reset into
active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this
case, if a serial BACKGROUND command is issued to the MCU through the background debug interface
while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode
where other serial background commands can be processed. This ensures that a host development system
can still gain access to a target MCU even if it is in stop mode.
Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop
mode. Refer to the Modes of Operation chapter for more details.
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 137
8.4.5 BGND Instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in
normal user programs because it forces the CPU to stop processing user instructions and enter the active
background mode. The only way to resume execution of the user program is through reset or by a host
debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug
interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the
BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active
background mode rather than continuing the user program.
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
138 Freescale Semiconductor
8.5 HCS08 Instruction Set Summary
Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in Table 8-2.
Operators
( ) = Contents of register or memory location shown inside parentheses
←=Is loaded with (read: “gets”)
&=Boolean AND
|=Boolean OR
⊕=Boolean exclusive-OR
×=Multiply
÷=Divide
:=Concatenate
+=Add
–=Negate (two’s complement)
CPU registers
A=Accumulator
CCR = Condition code register
H=Index register, higher order (most significant) 8 bits
X=Index register, lower order (least significant) 8 bits
PC = Program counter
PCH = Program counter, higher order (most significant) 8 bits
PCL = Program counter, lower order (least significant) 8 bits
SP = Stack pointer
Memory and addressing
M=A memory location or absolute data, depending on addressing mode
M:M + 0x0001= A 16-bit value in two consecutive memory locations. The higher-order (most
significant) 8 bits are located at the address of M, and the lower-order (least
significant) 8 bits are located at the next higher sequential address.
Condition code register (CCR) bits
V=Two’s complement overflow indicator, bit 7
H=Half carry, bit 4
I=Interrupt mask, bit 3
N=Negative indicator, bit 2
Z=Zero indicator, bit 1
C=Carry/borrow, bit 0 (carry out of bit 7)
CCR activity notation
–=Bit not affected
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 139
0=Bit forced to 0
1=Bit forced to 1
Þ=Bit set or cleared according to results of operation
U=Undefined after the operation
Machine coding notation
dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00)
ee = Upper 8 bits of 16-bit offset
ff = Lower 8 bits of 16-bit offset or 8-bit offset
ii = One byte of immediate data
jj = High-order byte of a 16-bit immediate data value
kk = Low-order byte of a 16-bit immediate data value
hh = High-order byte of 16-bit extended address
ll = Low-order byte of 16-bit extended address
rr = Relative offset
Source form
Everything in the source forms columns, except expressions in italic characters, is literal information that
must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a
literal expression. All commas, pound signs (#), parentheses, and plus signs (+) are literal characters.
n—Any label or expression that evaluates to a single integer in the range 0–7
opr8i —Any label or expression that evaluates to an 8-bit immediate value
opr16i —Any label or expression that evaluates to a 16-bit immediate value
opr8a —Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit
value as the low order 8 bits of an address in the direct page of the 64-Kbyte address
space (0x00xx).
opr16a —Any label or expression that evaluates to a 16-bit value. The instruction treats this
value as an address in the 64-Kbyte address space.
oprx8 —Any label or expression that evaluates to an unsigned 8-bit value, used for indexed
addressing
oprx16 —Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a
16-bit address bus, this can be either a signed or an unsigned value.
rel —Any label or expression that refers to an address that is within –128 to +127 locations
from the next address after the last byte of object code for the current instruction. The
assembler will calculate the 8-bit signed offset and include it in the object code for this
instruction.
Address modes
INH = Inherent (no operands)
IMM = 8-bit or 16-bit immediate
DIR = 8-bit direct
EXT = 16-bit extended
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
140 Freescale Semiconductor
IX = 16-bit indexed no offset
IX+ = 16-bit indexed no offset, post increment (CBEQ and MOV only)
IX1 = 16-bit indexed with 8-bit offset from H:X
IX1+ = 16-bit indexed with 8-bit offset, post increment
(CBEQ only)
IX2 = 16-bit indexed with 16-bit offset from H:X
REL = 8-bit relative offset
SP1 = Stack pointer with 8-bit offset
SP2 = Stack pointer with 16-bit offset
Table 8-2. HCS08 Instruction Set Summary (Sheet 1 of 7)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Bus Cycles1
VH I NZC
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
ADC oprx16,SP
ADC oprx8,SP
Add with Carry A ← (A) + (M) + (C) ¦¦–¦¦¦
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A9
B9
C9
D9
E9
F9
9ED9
9EE9
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
Add without Carry A ← (A) + (M) ¦¦–¦¦¦
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AB
BB
CB
DB
EB
FB
9EDB
9EEB
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
AIS #opr8i Add Immediate Value
(Signed) to Stack Pointer
SP ← (SP) + (M)
M is sign extended to a 16-bit value ––––––IMM A7ii 2
AIX #opr8i
Add Immediate Value
(Signed) to Index
Register (H:X)
H:X ← (H:X) + (M)
M is sign extended to a 16-bit value ––––––IMM AFii 2
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
Logical AND A ← (A) & (M) 0 – – ¦¦–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A4
B4
C4
D4
E4
F4
9ED4
9EE4
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
Arithmetic Shift Left
(Same as LSL) ¦––¦¦¦
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
5
1
1
5
4
6
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
Arithmetic Shift Right ¦––¦¦¦
DIR
INH
INH
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
ff
5
1
1
5
4
6
BCC rel Branch if Carry Bit Clear Branch if (C) = 0 – – – – – – REL 24 rr 3
C
b0
b7
0
b0
b7
C
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 141
BCLR n,opr8a Clear Bit n in Memory Mn ← 0 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BCS rel Branch if Carry Bit Set
(Same as BLO) Branch if (C) = 1 ––––––
REL 25 rr 3
BEQ rel Branch if Equal Branch if (Z) = 1 ––––––
REL 27 rr 3
BGE rel
Branch if Greater Than or
Equal To
(Signed Operands)
Branch if (N ⊕ V) = 0 ––––––
REL 90 rr 3
BGND Enter Active Background
if ENBDM = 1
Waits For and Processes BDM
Commands Until GO, TRACE1, or
TAGGO ––––––
INH 82 5+
BGT rel Branch if Greater Than
(Signed Operands) Branch if (Z) | (N ⊕ V) = 0 ––––––
REL 92 rr 3
BHCC rel Branch if Half Carry Bit
Clear Branch if (H) = 0 ––––––
REL 28 rr 3
BHCS rel Branch if Half Carry Bit
Set Branch if (H) = 1 ––––––
REL 29 rr 3
BHI rel Branch if Higher Branch if (C) | (Z) = 0 ––––––
REL 22 rr 3
BHS rel Branch if Higher or Same
(Same as BCC) Branch if (C) = 0 ––––––
REL 24 rr 3
BIH rel Branch if IRQ Pin High Branch if IRQ pin = 1 ––––––
REL 2F rr 3
BIL rel Branch if IRQ Pin Low Branch if IRQ pin = 0 ––––––
REL 2E rr 3
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
Bit Test
(A) & (M)
(CCR Updated but Operands
Not Changed) 0––¦¦–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A5
B5
C5
D5
E5
F5
9ED5
9EE5
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
BLE rel
Branch if Less Than
or Equal To
(Signed Operands)
Branch if (Z) | (N ⊕ V) = 1 ––––––
REL 93 rr 3
BLO rel Branch if Lower
(Same as BCS) Branch if (C) = 1 ––––––
REL 25 rr 3
BLS rel Branch if Lower or Same Branch if (C) | (Z) = 1 ––––––
REL 23 rr 3
BLT rel Branch if Less Than
(Signed Operands) Branch if (N ⊕ V ) = 1––––––
REL 91 rr 3
BMC rel Branch if Interrupt Mask
Clear Branch if (I) = 0 ––––––
REL 2C rr 3
BMI rel Branch if Minus Branch if (N) = 1 ––––––
REL 2B rr 3
BMS rel Branch if Interrupt Mask
Set Branch if (I) = 1 ––––––
REL 2D rr 3
BNE rel Branch if Not Equal Branch if (Z) = 0 ––––––
REL 26 rr 3
BPL rel Branch if Plus Branch if (N) = 0 ––––––
REL 2A rr 3
BRA rel Branch Always No Test ––––––
REL 20 rr 3
Table 8-2. HCS08 Instruction Set Summary (Sheet 2 of 7)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Bus Cycles1
VH I NZC
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
142 Freescale Semiconductor
BRCLR n,opr8a,rel Branch if Bit n in Memory
Clear Branch if (Mn) = 0 –––––¦
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel Branch Never Uses 3 Bus Cycles ––––––
REL 21 rr 3
BRSET n,opr8a,rel Branch if Bit n in Memory
Set Branch if (Mn) = 1 –––––¦
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET n,opr8a Set Bit n in Memory Mn ← 1 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BSR rel Branch to Subroutine
PC ← (PC) + 0x0002
push (PCL); SP ← (SP) – 0x0001
push (PCH); SP ← (SP) – 0x0001
PC ← (PC) + rel
––––––
REL AD rr 5
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Compare and Branch if
Equal
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
––––––
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
5
6
CLC Clear Carry Bit C ← 0 –––––0
INH 98 1
CLI Clear Interrupt Mask Bit I ← 0 ––0–––
INH 9A 1
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Clear
M ← 0x00
A ← 0x00
X ← 0x00
H ← 0x00
M ← 0x00
M ← 0x00
M ← 0x00
0––01–
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
ff
5
1
1
1
5
4
6
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
Compare Accumulator
with Memory
(A) – (M)
(CCR Updated But Operands Not
Changed)
¦––¦¦¦
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A1
B1
C1
D1
E1
F1
9ED1
9EE1
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
Complement
(One’s Complement)
M ← (M)= 0xFF – (M)
A ← (A) = 0xFF – (A)
X ← (X) = 0xFF – (X)
M ← (M) = 0xFF – (M)
M ← (M) = 0xFF – (M)
M ← (M) = 0xFF – (M)
0––¦¦1
DIR
INH
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
ff
5
1
1
5
4
6
CPHX opr16a
CPHX #opr16i
CPHX opr8a
CPHX oprx8,SP
Compare Index Register
(H:X) with Memory
(H:X) – (M:M + 0x0001)
(CCR Updated But Operands Not
Changed)
¦––¦¦¦
EXT
IMM
DIR
SP1
3E
65
75
9EF3
hh ll
jj kk
dd
ff
6
3
5
6
Table 8-2. HCS08 Instruction Set Summary (Sheet 3 of 7)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Bus Cycles1
VH I NZC
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 143
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
Compare X (Index
Register Low) with
Memory
(X) – (M)
(CCR Updated But Operands Not
Changed)
¦––¦¦¦
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A3
B3
C3
D3
E3
F3
9ED3
9EE3
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
DAA
Decimal Adjust
Accumulator After ADD or
ADC of BCD Values
(A)10 U–– ¦¦¦INH 72 1
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
Decrement and Branch if
Not Zero
Decrement A, X, or M
Branch if (result) ≠ 0
DBNZX Affects X Not H ––––––
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
7
4
4
7
6
8
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
Decrement
M ← (M) – 0x01
A ← (A) – 0x01
X ← (X) – 0x01
M ← (M) – 0x01
M ← (M) – 0x01
M ← (M) – 0x01
¦––¦¦–
DIR
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
ff
ff
5
1
1
5
4
6
DIV Divide A ← (H:A)÷(X)
H ← Remainder ––––¦¦INH 52 6
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
Exclusive OR
Memory with
Accumulator
A ← (A ⊕ M) 0––¦¦–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A8
B8
C8
D8
E8
F8
9ED8
9EE8
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
Increment
M ← (M) + 0x01
A ← (A) + 0x01
X ← (X) + 0x01
M ← (M) + 0x01
M ← (M) + 0x01
M ← (M) + 0x01
¦––¦¦–
DIR
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
ff
5
1
1
5
4
6
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
Jump PC ← Jump Address ––––––
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
3
4
4
3
3
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 0x0001
Push (PCH); SP ← (SP) – 0x0001
PC ← Unconditional Address
––––––
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
5
6
6
5
5
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
Load Accumulator from
Memory A ← (M) 0––¦¦–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A6
B6
C6
D6
E6
F6
9ED6
9EE6
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
Load Index Register (H:X)
from Memory H:X ← (M:M + 0x0001)0––¦¦–
IMM
DIR
EXT
IX
IX2
IX1
SP1
45
55
32
9EAE
9EBE
9ECE
9EFE
jj kk
dd
hh ll
ee ff
ff
ff
3
4
5
5
6
5
5
Table 8-2. HCS08 Instruction Set Summary (Sheet 4 of 7)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Bus Cycles1
VH I NZC
Chapter 8 Central Processor Unit (S08CPUV2)
MC9S08GB60A Data Sheet, Rev. 2
144 Freescale Semiconductor
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
Load X (Index Register
Low) from Memory X ← (M) 0––¦¦–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AE
BE
CE
DE
EE
FE
9EDE
9EEE
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL) ¦––¦¦¦
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
5
1
1
5
4
6
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
Logical Shift Right ¦––0¦¦
DIR
INH
INH
IX1
IX
SP1
34
44
54
64
74
9E64
dd
ff
ff
5
1
1
5
4
6
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
Move
(M)destination ← (M)source
H:X ← (H:X) + 0x0001 in
IX+/DIR and DIR/IX+ Modes
0––¦¦–
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
5
4
5
MUL Unsigned multiply X:A ← (X) × (A) –0–––0
INH 42 5
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
Negate
(Two’s Complement)
M ← – (M) = 0x00 – (M)
A ← – (A) = 0x00 – (A)
X ← – (X) = 0x00 – (X)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
¦––¦¦¦
DIR
INH
INH
IX1
IX
SP1
30
40
50
60
70
9E60
dd
ff
ff
5
1
1
5
4
6
NOP No Operation Uses 1 Bus Cycle ––––––
INH 9D 1
NSA Nibble Swap
Accumulator A ← (A[3:0]:A[7:4]) ––––––
INH 62 1
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
Inclusive OR Accumulator
and Memory A ← (A) | (M) 0––¦¦–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AA
BA
CA
DA
EA
FA
9EDA
9EEA
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
PSHA Push Accumulator onto
Stack Push (A); SP ← (SP) – 0x0001 ––––––
INH 87 2
PSHH Push H (Index Register
High) onto Stack Push (H); SP ← (SP) – 0x0001 ––––––
INH 8B 2
PSHX Push X (Index Register
Low) onto Stack Push (X); SP ← (SP) – 0x0001 ––––––
INH 89 2
PULA Pull Accumulator from
Stack SP ← (SP + 0x0001); Pull (A)––––––
INH 86 3
PULH Pull H (Index Register
High) from Stack SP ← (SP + 0x0001); Pull (H)––––––
INH 8A 3
PULX Pull X (Index Register
Low) from Stack SP ← (SP + 0x0001); Pull (X)––––––
INH 88 3
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
Rotate Left through Carry ¦––¦¦¦
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E69
dd
ff
ff
5
1
1
5
4
6
Table 8-2. HCS08 Instruction Set Summary (Sheet 5 of 7)
Source
Form Operation Description
Effect
on CCR
Address
Mode
Opcode
Operand
Bus Cycles1
VH I NZC
C
b0
b7
0
b0
b7
C0
C
b0
b7