STM8L052R8 Value Line, 8-bit ultralow power MCU, 64-KB Flash, 256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC Datasheet - production data Features Operating conditions - Operating power supply: 1.8 V to 3.6 V - Temperature range: -40 C to 85 C Low power features - 5 low power modes: Wait, Low power run (5.9 A), Low power wait (3 A), Active-halt with full RTC (1.4 A), Halt (400 nA) - Dynamic power consumption: 200 A/MHz + 330 A - Ultra-low leakage per I/0: 50 nA - Fast wakeup from Halt: 4.7 s Advanced STM8 core - Harvard architecture and 3-stage pipeline - Max freq. 16 MHz, 16 CISC MIPS peak - Up to 40 external interrupt sources Reset and supply management - Low power, ultra-safe BOR reset with 5 programmable thresholds - Ultra low power POR/PDR - Programmable voltage detector (PVD) Clock management - 32 kHz and 1 to 16 MHz crystal oscillators - Internal 16 MHz factory-trimmed RC - 38 kHz low consumption RC - Clock security system Low power RTC - BCD calendar with alarm interrupt - Digital calibration with +/- 0.5ppm accuracy - Advanced anti-tamper detection LCD: 8x24 or 4x28 w/ step-up converter Memories - 64 KB Flash program memory and 256 bytes data EEPROM with ECC, RWW - Flexible write and read protection modes - 4 KB of RAM May 2013 This is information on a product in full production. LQFP64 DMA - 4 channels supporting ADC, SPIs, I2C, USARTs, timers - 1 channel for memory-to-memory 12-bit ADC up to 1 Msps/27 channels - Internal reference voltage Timers - Three 16-bit timers with 2 channels (used as IC, OC, PWM), quadrature encoder - One 16-bit advanced control timer with 3 channels, supporting motor control - One 8-bit timer with 7-bit prescaler - 2 watchdogs: 1 Window, 1 Independent - Beeper timer with 1, 2 or 4 kHz frequencies Communication interfaces - Two synchronous serial interfaces (SPI) - Fast I2C 400 kHz SMBus and PMBus - Three USARTs (ISO 7816 interface + IrDA) Up to 54 I/Os, all mappable on interrupt vectors Development support - Fast on-chip programming and nonintrusive debugging with SWIM - Bootloader using USART Doc ID023337 Rev 2 1/109 www.st.com 1 Contents STM8L052R8 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 System configuration controller and routing interface . . . . . . . . . . . . . . . 19 3.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 2/109 3.2.1 3.11.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.2 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID023337 Rev 2 STM8L052R8 Contents 3.14.3 4 3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 5 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.4 8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 59 8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.3.9 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.3.11 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Doc ID023337 Rev 2 3/109 Contents 9 STM8L052R8 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4/109 Doc ID023337 Rev 2 STM8L052R8 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. High density value line STM8L05xxx low power device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Legend/abbreviation for Table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 High density value line STM8L05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 59 Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Total current consumption and timing in Low power run mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 69 Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 71 Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 72 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 85 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Doc ID023337 Rev 2 5/109 List of tables Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. 6/109 STM8L052R8 ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 LQFP64 - 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 105 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Doc ID023337 Rev 2 STM8L052R8 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. High density value line STM8L05xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . 12 High density value line STM8L05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM8L052R8 64-pin LQFP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz 1) . . . . . . . . . . . . . 64 Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz 1) . . . . . . . . . . . . 64 Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz 1) . . . . . . . . . . . . . 66 Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz 1) . . . . . . . . . . . . . . . . . . . 66 Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 68 Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF (1) . . . . . . . . . . . . . . . . . 69 Typical IDD(AH) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 72 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical pull-up current Ipu vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 100 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 100 LQFP64 - 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 105 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Doc ID023337 Rev 2 7/109 Introduction 1 STM8L052R8 Introduction This document describes the features, pinout, mechanical data and ordering information of the high density value line STM8L052R8 microcontroller with a Flash memory density of 64 Kbytes. For further details on the whole STMicroelectronics high density family please refer to Section 2.2: Ultra low power continuum. For detailed information on device operation and registers, refer to the reference manual (RM0031). For information on to the Flash program memory and data EEPROM, refer to the programming manual (PM0054). For information on the debug module and SWIM (single wire interface module), refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044). High density value line devices provide the following benefits: Integrated system - 64 Kbytes of high density embedded Flash program memory - 256 bytes of data EEPROM - 4 Kbytes of RAM - Internal high speed and low-power low speed RC - Embedded reset Ultra low power consumption - 1 A in Active-halt mode - Clock gated system and optimized power management - Capability to execute from RAM for Low power wait mode and low power run mode Advanced features - Up to 16 MIPS at 16 MHz CPU clock frequency - Direct memory access (DMA) for memory-to-memory or peripheral-to-memory access Short development cycles - Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals - Wide choice of development tools These features make the value line STM8L05xxx ultra low power microcontroller family suitable for a wide range of consumer and mass market applications. Refer to Table 1: High density value line STM8L05xxx low power device features and peripheral counts and Section 3: Functional overview for an overview of the complete range of peripherals proposed in this family. Figure 1 shows the block diagram of the high density value line STM8L05xxx family. 8/109 Doc ID023337 Rev 2 STM8L052R8 2 Description Description The high density value line STM8L05xxx devices are members of the STM8L ultra low power 8-bit family. The value line STM8L05xxx ultra low power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-application debugging and ultra-fast Flash programming. High density value line STM8L05xxx microcontrollers feature embedded data EEPROM and low-power, low-voltage, single-supply program Flash memory. All devices offer 12-bit ADC, real-time clock, four 16-bit timers, one 8-bit timer as well as standard communication interface such as two SPIs, I2C, three USARTs and 8x24 or 4x28segment LCD. The 8x24 or 4x 28-segment LCD is available on the high density value line STM8L05xxx. The STM8L05xxx family operates from 1.8 V to 3.6 V and is available in the -40 to +85 C temperature range. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. All value line STM8L ultra low power products are based on the same architecture with the same memory mapping and a coherent pinout. Doc ID023337 Rev 2 9/109 Description 2.1 STM8L052R8 Device overview Table 1. High density value line STM8L05xxx low power device features and peripheral counts Features STM8L052R8 Flash (Kbytes) 64 Data EEPROM (bytes) 256 RAM (Kbytes) 4 LCD Timers 8x24 or 4x28 Basic 1 (8-bit) General purpose 3 (16-bit) Advanced control 1 (16-bit) SPI Communication I2C interfaces USART 2 1 3 GPIOs 54(1) 12-bit synchronized ADC (number of channels) 1 (27) Others RTC, window watchdog, independent watchdog, 16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator CPU frequency 16 MHz Operating voltage 1.8 V to 3.6 V Operating temperature -40 to +85 C Package LQFP64 1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as general purpose output only (PA1). 10/109 Doc ID023337 Rev 2 STM8L052R8 2.2 Description Ultra low power continuum The ultra low power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the STM8L family, the devices are part of STMicroelectronics microcontrollers ultra low power strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features. They are all based on STMicroelectronics 0.13 m ultra-low leakage process. Note: 1 The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices. 2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family. Please refer to STM32L15x documentation for more information on these devices. Performance All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM CortexTM-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultra low power performance to range from 5 up to 33.3 DMIPs. Shared peripherals STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very easy migration from one family to another: Analog peripheral: ADC1 Digital peripherals: RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance, the STM8L and STM32L devices use a common architecture: Same power supply range from 1.8 to 3.6 V Architecture optimized to reach ultra-low consumption both in low power modes and Run mode Fast startup strategy from low power modes Flexible system clock Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on reset, power-down reset, brownout reset and programmable voltage detector Features ST ultra low power continuum also lies in feature compatibility: More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm Memory density ranging from 4 to 128 Kbytes Doc ID023337 Rev 2 11/109 Functional overview STM8L052R8 3 Functional overview Figure 1. High density value line STM8L05xxx device block diagram OSC_IN, OSC_OUT 16 MHz internal RC OSC32_IN, OSC32_OUT @VDD 1-16 MHz oscillator 32 kHz oscillator VDD18 Clock controller and CSS Clocks to core and peripherals 38 kHz internal RC Interrupt controller 16-bit Timer 2 2 channels 16-bit Timer 3 8-bit Timer 4 2 channels IR_TIM 16-bit Timer 5 Infrared interface DMA1 (4 channels) SCL, SDA, SMB SPI1_MOSI, SPI1_MISO, SPI1_SCK, SPI1_NSS SPI2_MOSI, SPI2_MISO, SPI2_SCK, SPI2_NSS USART1_RX, USART1_TX, USART1_CK USART2_RX, USART2_TX, USART2_CK USART3_RX, USART3_TX, USART3_CK V DDA, V SSA ADC1_INx V REF+ V REF- VREFINT out IC1 SPI1 SPI2 USART1 PVD A d d r ess , co n t r ol an d d at a b u ses 16-bit Timer 1 2 channels up to 4-Kbyte RAM Port A PA[7:0] Port B PB[7:0] Port C PC[7:0] Port D PD[7:0] Port E PE[7:0] Port F PF[7:0] USART2 USART3 @V /V DDA SSA 12-bit ADC1 PVD_IN up to 64-Kbyte Program memory 256 bytes Data EEPROM Port G PG[7:0] Beeper BEEP RTC ALARM, CALIB, TAMP1/2/3 IWDG (38 kHz clock) Internal reference voltage WWDG LCD driver YPSY V = 2.5 to 3.6 V LCD NRST BOR Debug module (SWIM) 3 channels RESET V DD=1.8 V to 3.6 V V SS POR/PDR STM8 Core SWIM Power VOLT. REG. SEGx, COMx LCD booster MS30323V1 1. Legend: ADC: Analog-to-digital converter BOR: Brownout reset DMA: Direct memory access IC: Inter-integrated circuit multimaster interface LCD: Liquid crystal display POR/PDR: Power on reset / power down reset RTC: Real-time clock SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous asynchronous receiver transmitter WWDG: Window watchdog IWDG: independent watchdog 12/109 Doc ID023337 Rev 2 STM8L052R8 3.1 Functional overview Low power modes The high density value line STM8L05xxx devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt, event or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode). Low power run mode: The CPU and the selected peripherals are running. Execution is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data EEPROM are stopped and the voltage regulator is configured in ultra low power mode. The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Low power wait mode: This mode is entered when executing a Wait for event in Low power run mode. It is similar to Low power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the system goes back to Low power run mode. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode. Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset. Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 s. Doc ID023337 Rev 2 13/109 Functional overview STM8L052R8 3.2 Central processing unit STM8 3.2.1 Advanced STM8 Core The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. Architecture and registers Harvard architecture 3-stage pipeline 32-bit wide program memory bus - single cycle fetching most instructions X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-Mbyte linear memory space 16-bit stack pointer - access to a 64-Kbyte level stack 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing 20 addressing modes Indexed indirect addressing mode for lookup tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing Instruction set 3.2.2 80 instructions with 2-byte average instruction size Standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division Bit manipulation Data transfer between stack and accumulator (push/pop) with direct stack access Data transfer using the X and Y registers or direct memory-to-memory transfers Interrupt controller The high density value line STM8L05xxx devices feature a nested vectored interrupt controller: 14/109 Nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority Up to 40 external interrupt sources on 11 vectors Trap and reset interrupts Doc ID023337 Rev 2 STM8L052R8 Functional overview 3.3 Reset and supply management 3.3.1 Power supply scheme The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows: VSS1, VDD1, VSS2, VDD2, VSS3, VDD3 = 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator. Provided externally through VDD pins, the corresponding ground pin is VSS. VSS1/VSS2/VSS3/VSS4 and VDD1/VDD2/VDD3 must not be left unconnected. 3.3.2 VSSA ; VDDA = 1.8 to 3.6 V: external power supplies for analog peripherals. VDDA and VSSA must be connected to VDD and VSS, respectively. VREF+ ; VREF- (for ADC1): external reference voltage for ADC1. Must be provided externally through VREF+ and VREF- pin. Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR), coupled with a brownout reset (BOR) circuitry that ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains under reset when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The high density value line STM8L05xxx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event (WFE) modes Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low power wait modes When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. Doc ID023337 Rev 2 15/109 Functional overview 3.4 STM8L052R8 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features 16/109 Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. System clock sources: 4 different clock sources can be used to drive the system clock: - 1-16 MHz High speed external crystal (HSE) - 16 MHz High speed internal RC oscillator (HSI) - 32.768 kHz Low speed external crystal (LSE) - 38 kHz Low speed internal RC (LSI) RTC and LCD clock sources: The above four sources can be chosen to clock the RTC and the LCD, whatever the system clock. Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Clock security system (CSS): This feature can be enabled by software. If a HSE clock failure occurs, the system clock is automatically switched to HSI. Configurable main clock output (CCO): This outputs an external clock for use by the application. Doc ID023337 Rev 2 STM8L052R8 Functional overview Figure 2. High density value line STM8L05xxx clock tree diagram CSS OSC_OUT OSC_IN HSE HSE OSC 1-16 MHz SYSCLK to core and HSI HSI RC 16 MHz memory SYSCLK Prescaler /1;2;4;8;16;32;64;128 LSI LSE Peripheral Clock enable (20 bits) LSE CLKBEEPSEL[1:0] LSI LSI RC 38 k Hz BEEPCLK to BEEP IWDGCLK to IWDG RTCCLK RTCSEL[3:0] OSC32_OUT OSC32_IN RTCCLK CSS_LSE RTCCLK/2 /2 CCO CCO prescaler /1;2;4;8;16;32;64 to LCD Halt LCDCLK configurable clock output to RTC LCD peripheral c lock enable (1 bit) RTC prescaler /1;2;4;8;16;32;64 LSE OSC 32 .768 kHz PCLK to peripherals HSI LSI HSE LSE SYSCLK to LCD LCD peripheral clock enable (1 bit) MS30324V1 1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031). 2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031). 3.5 Low power real-time clock The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically.The subsecond field can also be read in binary format. The calendar can be corrected from 1 to 32767 RTC clock pulses. This allows to make a synchronization to a master clock. The RTC offers a digital calibration which allows an accuracy of +/-0.5ppm. It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability. Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 s) is from min. 122 s to max. 3.9 s. With a different resolution, the wakeup time can reach 36 hours. Periodic alarms based on the calendar can also be generated from every second to every year. A clock security system detects a failure on LSE, and can provide an interrupt with wakeup capability. The RTC clock can automatically switch to LSI in case of LSE failure. The RTC also provides 3 anti-tamper detection pins. This detection embeds a programmable filter and can wakeup the MCU. Doc ID023337 Rev 2 17/109 Functional overview 3.6 STM8L052R8 LCD (Liquid crystal display) The LCD is only available on STM8L052xx devices. The liquid crystal display drives up to 8 common terminals and up to 24 segment terminals to drive up to 192 pixels. It can also be configured to drive up to 4 common and 28 segments (up to 112 pixels). Internal step-up converter to guarantee contrast control whatever VDD. Static 1/2, 1/3, 1/4, 1/8 duty supported. Static 1/2, 1/3, 1/4 bias supported. Phase inversion to reduce power consumption and EMI. Up to 8 pixels which can be programmed to blink. The LCD controller can operate in Halt mode. Note: Unnecessary segments and common pins can be used as general I/O pins. 3.7 Memories The high density value line STM8L05xxx devices have the following main features: 4 Kbytes of RAM The non-volatile memory is divided into three arrays: - 64 Kbytes of high density embedded Flash program memory - 256 bytes of data EEPROM - Option bytes The EEPROM embeds the error correction code (ECC) feature. It supports the read-whilewrite (RWW): it is possible to execute the code from the program matrix while programming/erasing the data matrix. The option byte protects part of the Flash program memory from write and readout piracy. 3.8 DMA A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, I2C1, SPI1, SPI 2, USART1, USART2, USART3 and the five timers. 18/109 Doc ID023337 Rev 2 STM8L052R8 3.9 Functional overview Analog-to-digital converter 12-bit analog-to-digital converter (ADC1) with 27 channels (including 4 fast channels) and internal reference voltage Conversion time down to 1 s with fSYSCLK= 16 MHz Programmable resolution Programmable sampling time Single and continuous mode of conversion Scan capability: automatic conversion performed on a selected group of analog inputs Analog watchdog: interrupt generation when the converted voltage is outside the programmed threshold Triggered by timer Note: ADC1 can be served by DMA1. 3.10 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface allows application software to control the routing of different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog signals to ADC1 and the internal reference voltage VREFINT. 3.11 Timers The high density value line STM8L05xxx devices contain one advanced control timer (TIM1), three 16-bit general purpose timers (TIM2, TIM3 and TIM5) and one 8-bit basic timer (TIM4). All the timers can be served by DMA1. Table 2 compares the features of the advanced control, general-purpose and basic timers. Table 2. Timer Timer feature comparison Counter Counter resolution type DMA1 request generation Any integer from 1 to 65536 TIM1 TIM2 Prescaler factor 16-bit Capture/compare channels Complementary outputs 3+1 3 up/down Any power of 2 from 1 to 128 TIM3 Yes 2 None TIM5 TIM4 8-bit up Any power of 2 from 1 to 32768 Doc ID023337 Rev 2 0 19/109 Functional overview 3.11.1 STM8L052R8 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver. 3.11.2 3.11.3 16-bit up, down and up/down autoreload counter with 16-bit prescaler 3 independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output 1 additional capture/compare channel which is not connected to an external I/O Synchronization module to control the timer with external signals Break input to force timer outputs into a defined state 3 complementary outputs with adjustable dead time Encoder mode Interrupt capability on various events (capture, compare, overflow, break, trigger) 16-bit general purpose timers 16-bit autoreload (AR) up/down-counter 7-bit prescaler adjustable to fixed power of 2 ratios (1...128) 2 individually configurable capture/compare channels PWM mode Interrupt capability on various events (capture, compare, overflow, break, trigger) Synchronization with other timers or external signals (external clock, reset, trigger and enable) 8-bit basic timer The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow. 3.12 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. 3.12.1 Window watchdog timer The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.12.2 Independent watchdog timer The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the internal LSI RC clock source, and thus stays active even in case of a CPU clock failure. 20/109 Doc ID023337 Rev 2 STM8L052R8 3.13 Functional overview Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. 3.14 Communication interfaces 3.14.1 SPI The serial peripheral interfaces (SPI1 and SPI2) provide half/ full duplex synchronous serial communication with external devices. Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on 2 lines with a possible bidirectional data line Master or slave operation - selectable by hardware or software Hardware CRC calculation Slave/master selection input pin Note: SPI1 and SPI2 can be served by the DMA1 Controller. 3.14.2 IC The I2C bus interface (I2C1) provides multi-master capability, and controls all IC busspecific sequencing, protocol, arbitration and timing. Master, slave and multi-master capability Standard mode up to 100 kHz and fast speed modes up to 400 kHz 7-bit and 10-bit addressing modes SMBus 2.0 and PMBus support Hardware CRC calculation Note: I2C1 can be served by the DMA1 Controller. 3.14.3 USART The USART interfaces (USART1, USART2 and USART3) allow full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. 1 Mbit/s full duplex SCI SPI1 emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder Single wire half duplex mode Note: USART1, USART2 and USART3 can be served by the DMA1 Controller. Doc ID023337 Rev 2 21/109 Functional overview 3.15 STM8L052R8 Infrared (IR) interface The high density value line STM8L05xxx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 3.16 Development support Development tools Development tools for the STM8 microcontrollers include: The STice emulation system offering tracing and code profiling The STVD high-level language debugger including C compiler, assembler and integrated development environment The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers. Bootloader A bootloader is available to reprogram the Flash memory using the USART1, USART2, USART3 (USARTs in asynchronous mode), SPI1 or SPI2 interfaces. The reference document for the bootloader is UM0560: STM8 bootloader user manual. The bootloader is used to download application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface. 22/109 Doc ID023337 Rev 2 STM8L052R8 Pin description STM8L052R8 64-pin LQFP64 package pinout PE7 PE6 PC7 PC6 PC5 PC4 PC3 PC2 VSS2 V DD2 PC1 PC0 PG7 PG6 PG5 PG4 Figure 3. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PA0 NRST/PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSSA/VREFVSS1 VDD1 VDDA VREF+ PG0 PG1 PG2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PD7 PD6 PD5 PD4 PF7 PF6 PF5 PF4 PF1 PF0 PB7 PB6 PB5 PB4 PB3 PB2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PG3 VLCD PE0 PE1 PE2 PE3 PE4 PE5 PD0 PD1 PD2 PD3 V DD3 V SS3 PB0 PB1 4 Pin description ai17835 Doc ID023337 Rev 2 23/109 Pin description STM8L052R8 Table 3. Legend/abbreviation for Table 4 Type Level I= input, O = output, S = power supply FT Five-volt tolerant TT 3.6 V tolerant Output HS = high sink/source (20 mA) Port and control Input configuration Output Reset state T = true open drain, OD = open drain, PP = push pull Bold X (pin state after reset release). Unless otherwise specified, the pin state is the same during the reset phase (i.e. "under reset") and after internal reset release (i.e. at reset state). High density value line STM8L05xxx pin description High sink/source OD PP X Reset X HS X HSE oscillator input / X Port A2 [USART1 transmit] / [SPI1 master in- slave out] X X HS X HSE oscillator output / X Port A3 [USART1 receive]/ [SPI1 master out/slave in]/ X X HS X Timer 2 - break input X Port A4 /[Timer 2 - trigger]/ LCD COM 0 / ADC1 input 2 HS X Timer 3 - break input /[Timer 3 - trigger]/ X Port A5 LCD_COM 1 / ADC1 input 1 X HS X [ADC1 - trigger] / X Port A6 LCD_COM2 / ADC1 input 0 X X HS X X Port A7 LCD segment 0/ TIM5 channel 1 X X X HS X X Port B0 Timer 2 - channel 1 / LCD segment 10 / ADC1_IN18 X X X HS X X Port B1 Timer 3 - channel 1 / LCD segment 11 / ADC1_IN17 Ext. interrupt X 2 NRST/PA1(1) I/O 3 PA2/OSC_IN/ [USART1_TX](8)/ [SPI1_MISO] (8) I/O X X 4 PA3/OSC_OUT/[USART1_ RX](8)/[SPI1_MOSI](8) I/O X 5 PA4/TIM2_BKIN/ [TIM2_ETR](8)/ LCD_COM0/ADC1_IN2 I/O FT(2) X 6 PA5/TIM3_BKIN/ [TIM3_ETR](8)/ LCD_COM1/ADC1_IN1 I/O FT(2) X X X 7 PA6/[ADC1_TRIG]/ LCD_COM2/ADC1_IN0 I/O FT(2) X X 8 PA7/LCD_SEG0(2) /TIM5_CH1 I/O FT(2) X 31 PB0(3)/TIM2_CH1/ LCD_SEG10/ADC1_IN18 I/O FT(2) 32 PB1/TIM3_CH1/ LCD_SEG11/ ADC1_IN17 I/O FT(2) 24/109 Main function (after reset) Output HS floating Pin name I/O level Input Type LQFP64 Pin number wpu Table 4. float = floating, wpu = weak pull-up X Doc ID023337 Rev 2 Default alternate function PA1 STM8L052R8 High density value line STM8L05xxx pin description (continued) Pin number Output wpu Ext. interrupt High sink/source OD PP PB2/ TIM2_CH2/ LCD_SEG12/ ADC1_IN16 I/O FT(2) X X X HS X X Port B2 Timer 2 - channel 2 / LCD segment 12 / ADC1_IN16 34 PB3/TIM2_ETR/ LCD_SEG13/ ADC1_IN15 I/O FT(2) X X X HS X X Port B3 Timer 2 - trigger / LCD segment 13 /ADC1_IN15 35 PB4(3)/[SPI1_NSS](8)/ LCD_SEG14/ ADC1_IN14 I/O FT(2) X(3) X(3) X HS X [SPI1 master/slave select] / X Port B4 LCD segment 14 / ADC1_IN14 36 PB5/[SPI1_SCK](8)/ LCD_SEG15/ ADC1_IN13 I/O FT(2) X X X HS X X Port B5 37 PB6/[SPI1_MOSI](8)/ LCD_SEG16/ ADC1_IN12 I/O FT(2) X X X HS X [SPI1 master out/slave in]/ X Port B6 LCD segment 16 / ADC1_IN12 38 PB7/[SPI1_MISO](8)/ LCD_SEG17/ ADC1_IN11 I/O FT(2) X X X HS X [SPI1 master in- slave out] X Port B7 /LCD segment 17 / ADC1_IN11 53 PC0(2)/I2C1_SDA I/O FT(2) X 54 PC1 (2)/I2C1_SCL I/O FT(2) 57 PC2/USART1_RX/ LCD_SEG22/ADC1_IN6/ VREFINT I/O FT(2) X X X HS X USART1 receive / LCD segment 22 / X Port C2 ADC1_IN6 /Internal voltage reference output 58 PC3/USART1_TX/ LCD_SEG23/ ADC1_IN5 I/O FT(2) X X X HS X USART1 transmit / X Port C3 LCD segment 23 / ADC1_IN5 59 PC4/USART1_CK/ I2C1_SMB/CCO/ ADC1_IN4 I/O FT(2) X X X HS X USART1 synchronous clock / I2C1_SMB / X Port C4 Configurable clock output / ADC1_IN4 60 PC5/OSC32_IN /[SPI1_NSS](8)/ [USART1_TX](8) I/O FT(2) X X X HS X LSE oscillator input / [SPI1 X Port C5 master/slave select] / [USART1 transmit] 61 PC6/OSC32_OUT/ [SPI1_SCK](8)/ [USART1_RX](8) I/O FT(2) X X X HS X LSE oscillator output / X Port C6 [SPI1 clock] / [USART1 receive] 62 PC7/ADC1_IN3 I/O FT(2) X X X HS X X Port C7 ADC1_IN3 LQFP64 I/O level 33 Pin name Type floating Input Main function (after reset) Table 4. Pin description X Default alternate function [SPI1 clock] / LCD segment 15 / ADC1_IN13 X T(4) Port C0 I2C1 data X T(4) Port C1 I2C1 clock Doc ID023337 Rev 2 25/109 Pin description High density value line STM8L05xxx pin description (continued) Pin number Output wpu Ext. interrupt High sink/source OD PP I/O FT(2) X X X HS X Timer 3 - channel 2 / X Port D0 [ADC1_Trigger] / LCD segment 7 / ADC1_IN22 26 PD1/TIM3_ETR/ LCD_COM3/ ADC1_IN21 I/O FT(2) X X X HS X X Port D1 Timer 3 - trigger / LCD_COM3 / ADC1_IN21 27 PD2/TIM1_CH1 /LCD_SEG8/ ADC1_IN20 I/O FT(2) X X X HS X X Port D2 Timer 1 - channel 1 / LCD segment 8 / ADC1_IN20 28 PD3/ TIM1_ETR/ LCD_SEG9/ADC1_IN19 I/O FT(2) X X X HS X X Port D3 Timer 1 - trigger / LCD segment 9 / ADC1_IN19 45 PD4/TIM1_CH2 /LCD_SEG18/ ADC1_IN10 I/O FT(2) X X X HS X X Port D4 Timer 1 - channel 2 / LCD segment 18 / ADC1_IN10 46 PD5/TIM1_CH3 /LCD_SEG19/ ADC1_IN9 I/O FT(2) X X X HS X X Port D5 Timer 1 - channel 3 / LCD segment 19 / ADC1_IN9 47 PD6/TIM1_BKIN /LCD_SEG20/ ADC1_IN8/RTC_CALIB/ /VREFINT X Timer 1 - break input / LCD segment 20 / ADC1_IN8 / X Port D6 RTC calibration / Internal voltage reference output 48 PD7/TIM1_CH1N /LCD_SEG21/ I/O FT(2) ADC1_IN7/RTC_ALARM/V REFINT X X X HS X Timer 1 - inverted channel 1/ LCD segment 21 / X Port D7 ADC1_IN7 / RTC alarm / Internal voltage reference output 49 PG4/SPI2_NSS I/O FT(2) X X X HS X X Port G4 50 PG5/SPI2_SCK I/O FT(2) X X X HS X X Port G5 SPI2 clock 51 PG6/SPI2_MOSI I/O FT(2) X X X HS X X Port G6 SPI2 master out- slave in 52 PG7/SPI2_MISO I/O FT(2) X X X HS X X Port G7 SPI2 master in- slave out 19 PE0(2)/LCD_SEG1/TIM5_C I/O FT(2) H2/RTC_TAMP1 X X X HS X X Port E0 LCD segment 1/Timer 5 channel 2/RTC tamper 1 20 PE1/TIM1_CH2N/ LCD_SEG2/RTC_TAMP2 X X X HS X Timer 1 - inverted channel X Port E1 2 / LCD segment 2/ RTC tamper 2 26/109 I/O level PD0/TIM3_CH2/ [ADC1_TRIG](8)/ LCD_SEG7/ADC1_IN22/ Pin name Type 25 LQFP64 floating Input Main function (after reset) Table 4. STM8L052R8 (2) I/O FT I/O FT(2) X X X HS Doc ID023337 Rev 2 Default alternate function SPI2 master/slave select STM8L052R8 High density value line STM8L05xxx pin description (continued) Pin number Output wpu Ext. interrupt High sink/source OD PP PE2/TIM1_CH3N/ LCD_SEG3/RTC_TAMP3 I/O FT(2) X X X HS X Timer 1 - inverted channel X Port E2 3 / LCD segment 3/ RTC tamper 3 22 PE3/LCD_SEG4 /USART2_RX I/O FT(2) X X X HS X X Port E3 LCD segment 4 /USART2 receive 23 PE4/LCD_SEG5 /USART2_TX I/O FT(2) X X X HS X X Port E4 LCD segment 5 /USART2 transmit 24 PE5/LCD_SEG6/ ADC1_IN23/USART2_CK I/O FT(2) X X X HS X LCD segment 6 / X Port E5 ADC1_IN23/USART2 synchronous clock 63 PE6/PVD_IN/TIM5_BKIN I/O FT(2) X X X HS X X Port E6 64 PE7 /TIM5_ETR I/O FT(2) X X X HS X X Port E7 TIM5 trigger 39 PF0/ADC1_IN24 /[USART3_TX] I/O X X X HS X X Port F0 ADC1_IN24/ [USART3 transmit] 40 PF1/ADC1_IN25/ [USART3_RX] I/O X X X HS X X Port F1 ADC1_IN25/ [USART3 receive] 41 PF4/LCD_SEG36 /LCD_COM4(5) I/O FT(2) X X X HS X X Port F4 LCD_SEG36/ LCD COM4(5) 42 PF5/LCD_SEG37/ LCD_COM5(5) I/O FT(2) X X X HS X X Port F5 LCD_SEG37/ LCD COM5(5) 43 PF6/LCD_SEG38/ LCD_COM6(5) I/O FT(2) X X X HS X X Port F6 LCD_SEG38/ LCD COM6(5) 44 PF7/LCD_SEG39/ LCD_COM7(5) I/O FT(2) X X X HS X X Port F7 LCD_SEG39/ LCD COM7(5) 18 VLCD S LCD booster external capacitor 11 VDD1 S Digital power supply 10 VSS1 12 VDDA S Analog supply voltage 13 VREF+ S ADC1 positive voltage reference 14 PG0/USART3_RX/ [TIM2_BKIN] I/O FT(2) X X X HS X X Port G0 USART3 receive / [Timer 2 - break input] 15 PG1/USART3_TX/ [TIM3_BKIN] I/O FT(2) X X X HS X X Port G1 USART3 transmit / [Timer 3 -break input] LQFP64 I/O level 21 Pin name Type floating Input Main function (after reset) Table 4. Pin description Default alternate function PVD_IN /TIM5 break input I/O ground Doc ID023337 Rev 2 27/109 Pin description High density value line STM8L05xxx pin description (continued) Pin number Output wpu Ext. interrupt High sink/source OD PP PG2/USART3_CK I/O FT(2) X X X HS X X Port G2 17 PG3[TIM3_ETR] I/O FT(2) X X X HS X X Port G3 [Timer 3 - trigger] 9 VSSA/VREF- S Analog ground voltage / ADC1 negative voltage reference 55 VDD2 S IOs supply voltage 56 VSS2 S IOs ground voltage 1 PA0(6)/[USART1_CK](8)/ SWIM/BEEP/IR_TIM (7) 29 VDD3 S IOs supply voltage 30 VSS3 S IOs ground voltage LQFP64 I/O level 16 Pin name Type floating Input Main function (after reset) Table 4. STM8L052R8 I/O X X X HS X X Port A0 Default alternate function USART 3 synchronous clock [USART1 synchronous clock](8) / SWIM input and output /Beep output / Infrared Timer output 1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031). 2. In the 5 V tolerant I/Os, protection diode to VDD is not implemented. 3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release. 4. In the open-drain output column, `T' defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented). 5. SEG/COM multiplexing available on medium+ and high density devices. SEG signals are available by default (see reference manual for details). 6. The PA0 pin is in input pull-up during the reset phase and after reset release. 7. High Sink LED driver capability available on PA0. 8. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 28/109 Doc ID023337 Rev 2 STM8L052R8 4.1 Pin description System configuration options As shown in Table 4: High density value line STM8L05xxx pin description, some alternate functions can be remapped on different I/O ports by programming one of the two remapping registers described in the "Routing interface (RI) and system configuration controller" section in the STM8L15x and STM8L16x reference manual (RM0031). Doc ID023337 Rev 2 29/109 Memory and register map STM8L052R8 5 Memory and register map 5.1 Memory mapping The memory map is shown in Figure 4. Figure 4. Memory map 0x00 0000 0x00 07FF 0x00 0800 0x00 0FFF 0x00 1000 0x00 10FF 0x00 1100 RAM (4 Kbytes) (1) including Stack (513 bytes) (1) Reserved Data EEPROM (256 bytes) 0x00 5000 0x00 5050 Reserved 0x00 47FF 0x00 4800 0x00 48FF 0x00 4900 0x00 5070 0x00 509D Option bytes 0x00 50A0 0x00 50A6 0x00 50B0 0x00 50B2 0x00 50C0 0x00 50D3 Reserved 0x00 50E0 0x00 50F0 0x00 5140 0x00 4FFF 0x00 5000 0x00 5200 0x00 5210 GPIO and peripheral registers 0x00 57FF 0x00 5800 0x00 5FFF 0x00 6000 0x00 67FF 0x00 6800 0x00 5250 0x00 5280 Reserved 0x00 52B0 0x00 52E0 Boot ROM (2 Kbytes) 0x00 52FF 0x00 5300 Flash DMA1 SYSCFG ITC-EXTI WFE RST PWR CLK WWDG IWDG BEEP RTC SPI1 I2C1 USART1 TIM2 TIM3 TIM1 TIM4 IRTIM TIM5 0x00 5340 Reserved 0x00 5380 0x00 7EFF 0x00 7F00 0x00 53C0 CPU/SWIM/Debug/ITC Registers 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 0x00 5230 GPIO Ports 0x00 53E0 0x00 53F0 0x00 5400 Reset and interrupt vectors 0x00 5430 0x00 5440 High density Flash program memory (64 Kbytes) 0x00 5444 ADC1 Reserved SPI2 USART2 USART3 LCD RI Reserved 0x00 FFFF 1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. 30/109 Doc ID023337 Rev 2 STM8L052R8 Table 5. Memory and register map Flash and RAM boundary addresses Memory area Size Start address End address RAM 4 Kbytes 0x00 0000 0x00 0FFF Flash program memory 64 Kbytes 0x00 8000 0x01 7FFF 5.2 Register map Table 6. I/O port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xXX PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x01 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xXX PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register 0xXX PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x00 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register 0xXX PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 0x00 5016 Block Port A Port B Port C Port D Port E Doc ID023337 Rev 2 31/109 Memory and register map Table 6. STM8L052R8 I/O port hardware register map (continued) Register label Register name Reset status 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0xXX PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E PG_ODR Port F data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0xXX PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 Address 0x00 501B 0x00 5020 Block Port F Port G 0x00 5023 to 0x00 502C Table 7. Reserved area (10 bytes) General hardware register map Address Block Register label 0x00 502E to 0x00 5049 Register name Reset status Reserved area (27 bytes) 0x00 5050 FLASH_CR1 Flash control register 1 0x00 0x00 5051 FLASH_CR2 Flash control register 2 0x00 FLASH _PUKR Flash program memory unprotection key register 0x00 0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00 0x00 5054 FLASH _IAPSR Flash in-application programming status register 0x00 0x00 5052 0x00 5055 to 0x00 506F 32/109 Flash Reserved area (27 bytes) Doc ID023337 Rev 2 STM8L052R8 Table 7. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 5070 DMA1_GCSR DMA1 global configuration & status register 0xFC 0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00 Address Block 0x00 5072 to 0x00 5074 Reserved area (3 bytes) 0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00 0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00 0x00 5077 DMA1_C0NDTR DMA1 number of data to transfer register (channel 0) 0x00 0x00 5078 DMA1_C0PARH DMA1 peripheral address high register (channel 0) 0x52 0x00 5079 DMA1_C0PARL DMA1 peripheral address low register (channel 0) 0x00 0x00 507A Reserved area (1 byte) DMA1 0x00 507B DMA1_C0M0ARH DMA1 memory 0 address high register (channel 0) 0x00 0x00 507C DMA1_C0M0ARL DMA1 memory 0 address low register (channel 0) 0x00 0x00 507D 0x00 507E Reserved area (2 bytes) 0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00 0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00 0x00 5081 DMA1_C1NDTR DMA1 number of data to transfer register (channel 1) 0x00 0x00 5082 DMA1_C1PARH DMA1 peripheral address high register (channel 1) 0x52 0x00 5083 DMA1_C1PARL DMA1 peripheral address low register (channel 1) 0x00 Doc ID023337 Rev 2 33/109 Memory and register map Table 7. STM8L052R8 General hardware register map (continued) Address Block Register label 0x00 5084 Register name Reset status Reserved area (1 byte) 0x00 5085 DMA1_C1M0ARH DMA1 memory 0 address high register (channel 1) 0x00 0x00 5086 DMA1_C1M0ARL DMA1 memory 0 address low register (channel 1) 0x00 0x00 5087 0x00 5088 Reserved area (2 bytes) 0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00 0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00 0x00 508B DMA1_C2NDTR DMA1 number of data to transfer register (channel 2) 0x00 0x00 508C DMA1_C2PARH DMA1 peripheral address high register (channel 2) 0x52 0x00 508D DMA1_C2PARL DMA1 peripheral address low register (channel 2) 0x00 0x00 508E Reserved area (1 byte) 0x00 508F DMA1_C2M0ARH DMA1 memory 0 address high register (channel 2) 0x00 DMA1_C2M0ARL DMA1 memory 0 address low register (channel 2) 0x00 DMA1 0x00 5090 0x00 5091 0x00 5092 Reserved area (2 bytes) 0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00 0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00 0x00 5095 DMA1_C3NDTR DMA1 number of data to transfer register (channel 3) 0x00 0x00 5096 DMA1_C3PARH_ C3M1ARH DMA1 peripheral address high register (channel 3) 0x40 0x00 5097 DMA1_C3PARL_ C3M1ARL DMA1 peripheral address low register (channel 3) 0x00 0x00 5098 Reserved area (1 byte) 0x00 5099 DMA1_C3M0ARH DMA1 memory 0 address high register (channel 3) 0x00 0x00 509A DMA1_C3M0ARL DMA1 memory 0 address low register (channel 3) 0x00 0x00 509B to 0x00 509C 34/109 Reserved area (2 bytes) Doc ID023337 Rev 2 STM8L052R8 Table 7. Memory and register map General hardware register map (continued) Register label Register name Reset status SYSCFG_RMPCR3 Remapping register 3 0x00 SYSCFG_RMPCR1 Remapping register 1 0x00 0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 EXTI_CR3 External interrupt control register 3 0x00 0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00 0x00 50A6 WFE_CR1 WFE control register 1 0x00 WFE_CR2 WFE control register 2 0x00 0x00 50A8 WFE_CR3 WFE control register 3 0x00 0x00 50A9 WFE_CR4 WFE control register 4 0x00 EXTI_CR4 External interrupt control register 4 0x00 EXTI_CONF2 External interrupt port select register 2 0x00 Address Block 0x00 509D 0x00 509E SYSCFG SYSCFG 0x00 50A2 ITC - EXTI 0x00 50A7 WFE 0x00 50AA ITC - EXTI 0x00 50AB 0x00 50A9 to 0x00 50AF Reserved area (7 bytes) 0x00 50B0 RST_CR Reset control register 0x00 RST_SR Reset status register 0x01 PWR_CSR1 Power control and status register 1 0x00 PWR_CSR2 Power control and status register 2 0x00 RST 0x00 50B1 0x00 50B2 PWR 0x00 50B3 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) Doc ID023337 Rev 2 35/109 Memory and register map Table 7. STM8L052R8 General hardware register map (continued) Register label Register name Reset status 0x00 50C0 CLK_CKDIVR Clock master divider register 0x03 0x00 50C1 CLK_CRTCR Clock RTC register 0x00(1) 0x00 50C2 CLK_ICKR Internal clock control register 0x11 0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00 0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x00 0x00 50C5 CLK_CCOR Configurable clock control register 0x00 0x00 50C6 CLK_ECKR External clock control register 0x00 0x00 50C7 CLK_SCSR System clock status register 0x01 CLK_SWR System clock switch register 0x01 0x00 50C9 CLK_SWCR Clock switch control register 0xX0 0x00 50CA CLK_CSSR Clock security system register 0x00 0x00 50CB CLK_CBEEPR Clock BEEP register 0x00 0x00 50CC CLK_HSICALR HSI calibration register 0xXX 0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00 0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x 0x00 50D0 CLK_PCKENR3 Peripheral clock gating register 3 0x00 Address 0x00 50C8 Block CLK 0x00 50D1 to 0x00 50D2 Reserved area (2 bytes) 0x00 50D3 WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F WWDG 0x00 50D4 0x00 50D5 to 00 50DF Reserved area (11 bytes) 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 IWDG_KR IWDG key register 0xXX IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 0x00 50F1 0x00 50F2 0x00 50F3 0x00 50F4 to 0x00 513F 36/109 BEEP_CSR1 BEEP BEEP control/status register 1 0x00 Reserved area (2 bytes) BEEP_CSR2 BEEP control/status register 2 Reserved area (76 bytes) Doc ID023337 Rev 2 0x1F STM8L052R8 Table 7. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 5140 RTC_TR1 Time register 1 0x00 0x00 5141 RTC_TR2 Time register 2 0x00 0x00 5142 RTC_TR3 Time register 3 0x00 Address Block 0x00 5143 Reserved area (1 byte) 0x00 5144 RTC_DR1 Date register 1 0x01 0x00 5145 RTC_DR2 Date register 2 0x21 0x00 5146 RTC_DR3 Date register 3 0x00 0x00 5147 Reserved area (1 byte) 0x00 5148 RTC_CR1 Control register 1 0x00(1) 0x00 5149 RTC_CR2 Control register 2 0x00(1) 0x00 514A RTC_CR3 Control register 3 0x00(1) 0x00 514B Reserved area (1 byte) 0x00 514C RTC_ISR1 Initialization and status register 1 0x01 0x00 514D RTC_ISR2 Initialization and Status register 2 0x00 0x00 514E 0x00 514F Reserved area (2 bytes) RTC_SPRERH(1) Synchronous prescaler register high 0x00(1) 0x00 5151 RTC_SPRERL(1) Synchronous prescaler register low 0xFF(1) 0x00 5152 RTC_APRER(1) Asynchronous prescaler register 0x7F(1) 0x00 5150 RTC 0x00 5153 Reserved area (1 byte) 0x00 5154 RTC_WUTRH(1) Wakeup timer register high 0xFF(1) 0x00 5155 RTC_WUTRL(1) Wakeup timer register low 0xFF(1) 0x00 5156 Reserved area (1 bytes) 0x00 5157 RTC_SSRL Subsecond register low 0x00 0x00 5158 RTC_SSRH Subsecond register high 0x00 0x00 5159 RTC_WPR Write protection register 0x00 0x00 515A RTC_SHIFTRH Shift register high 0x00 0x00 515B RTC_SHIFTRL Shift register low 0x00 0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00(1) 0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00(1) 0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00(1) 0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00(1) 0x00 5160 to 0x00 5163 Reserved area (4 bytes) Doc ID023337 Rev 2 37/109 Memory and register map Table 7. STM8L052R8 General hardware register map (continued) Address Block 0x00 5164 0x00 5165 RTC 0x00 5166 Register label Register name Reset status RTC_ALRMASSRH Alarm A subsecond register high 0x00(1) RTC_ALRMASSRL Alarm A subsecond register low 0x00(1) RTC_ALRMASSMS KR Alarm A masking register 0x00(1) 0x00 5167 to 0x00 5169 Reserved area (3 bytes) RTC_CALRH Calibration register high 0x00(1) RTC_CALRL Calibration register low 0x00(1) 0x00 516C RTC_TCR1 Tamper control register 1 0x00(1) 0x00 516D RTC_TCR2 Tamper control register 2 0x00(1) 0x00 516A 0x00 516B RTC 0x00 516E to 0x00 518A 0x00 5190 Reserved area CSSLSE CSSLSE_CSR 0x00 519A to 0x00 51FF CSS on LSE control and status register 0x00(1) Reserved area 0x00 5200 SPI1_CR1 SPI1 control register 1 0x00 0x00 5201 SPI1_CR2 SPI1 control register 2 0x00 0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00 SPI1_SR SPI1 status register 0x02 0x00 5204 SPI1_DR SPI1 data register 0x00 0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07 0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00 0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00 0x00 5203 SPI1 0x00 5208 to 0x00 520F 38/109 Reserved area (8 bytes) Doc ID023337 Rev 2 STM8L052R8 Table 7. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 5210 I2C1_CR1 I2C1 control register 1 0x00 0x00 5211 I2C1_CR2 I2C1 control register 2 0x00 0x00 5212 I2C1_FREQR I2C1 frequency register 0x00 0x00 5213 I2C1_OARL I2C1 own address register low 0x00 0x00 5214 I2C1_OARH I2C1 own address register high 0x00 0x00 5215 I2C1_OARH I2C1 own address register for dual mode 0x00 0x00 5216 I2C1_DR I2C1 data register 0x00 I2C1_SR1 I2C1 status register 1 0x00 0x00 5218 I2C1_SR2 I2C1 status register 2 0x00 0x00 5219 I2C1_SR3 I2C1 status register 3 0x0x 0x00 521A I2C1_ITR I2C1 interrupt control register 0x00 0x00 521B I2C1_CCRL I2C1 clock control register low 0x00 0x00 521C I2C1_CCRH I2C1 clock control register high 0x00 0x00 521D I2C1_TRISER I2C1 TRISE register 0x02 0x00 521E I2C1_PECR I2C1 packet error checking register 0x00 Address Block 0x00 5217 I2C1 0x00 521F to 0x00 522F Reserved area (17 bytes) 0x00 5230 USART1_SR USART1 status register 0xC0 0x00 5231 USART1_DR USART1 data register 0xXX 0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00 0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00 0x00 5234 USART1_CR1 USART1 control register 1 0x00 USART1_CR2 USART1 control register 2 0x00 0x00 5236 USART1_CR3 USART1 control register 3 0x00 0x00 5237 USART1_CR4 USART1 control register 4 0x00 0x00 5238 USART1_CR5 USART1 control register 5 0x00 0x00 5239 USART1_GTR USART1 guard time register 0x00 0x00 523A USART1_PSCR USART1 prescaler register 0x00 0x00 5235 0x00 523B to 0x00 524F USART1 Reserved area (21 bytes) Doc ID023337 Rev 2 39/109 Memory and register map Table 7. STM8L052R8 General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM2_CR1 TIM2 control register 1 0x00 0x00 5251 TIM2_CR2 TIM2 control register 2 0x00 0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00 0x00 5253 TIM2_ETR TIM2 external trigger register 0x00 0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00 0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5256 TIM2_SR1 TIM2 status register 1 0x00 0x00 5257 TIM2_SR2 TIM2 status register 2 0x00 0x00 5258 TIM2_EGR TIM2 event generation register 0x00 0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 0x00 525C TIM2_CNTRH TIM2 counter high 0x00 0x00 525D TIM2_CNTRL TIM2 counter low 0x00 0x00 525E TIM2_PSCR TIM2 prescaler register 0x00 0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00 0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5265 TIM2_BKR TIM2 break register 0x00 0x00 5266 TIM2_OISR TIM2 output idle state register 0x00 Address 0x00 525B 0x00 5267 to 0x00 527F 40/109 Block TIM2 Reserved area (25 bytes) Doc ID023337 Rev 2 STM8L052R8 Table 7. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 5280 TIM3_CR1 TIM3 control register 1 0x00 0x00 5281 TIM3_CR2 TIM3 control register 2 0x00 0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00 0x00 5283 TIM3_ETR TIM3 external trigger register 0x00 0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00 0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5286 TIM3_SR1 TIM3 status register 1 0x00 0x00 5287 TIM3_SR2 TIM3 status register 2 0x00 0x00 5288 TIM3_EGR TIM3 event generation register 0x00 0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00 0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00 TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00 0x00 528C TIM3_CNTRH TIM3 counter high 0x00 0x00 528D TIM3_CNTRL TIM3 counter low 0x00 0x00 528E TIM3_PSCR TIM3 prescaler register 0x00 0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF 0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF 0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00 0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00 0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00 0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00 0x00 5295 TIM3_BKR TIM3 break register 0x00 0x00 5296 TIM3_OISR TIM3 output idle state register 0x00 Address 0x00 528B 0x00 5297 to 0x00 52AF Block TIM3 Reserved area (25 bytes) Doc ID023337 Rev 2 41/109 Memory and register map Table 7. STM8L052R8 General hardware register map (continued) Register label Register name Reset status 0x00 52B0 TIM1_CR1 TIM1 control register 1 0x00 0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00 0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00 0x00 52B3 TIM1_ETR TIM1 external trigger register 0x00 0x00 52B4 TIM1_DER TIM1 DMA1 request enable register 0x00 0x00 52B5 TIM1_IER TIM1 Interrupt enable register 0x00 0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00 0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00 0x00 52B8 TIM1_EGR TIM1 event generation register 0x00 0x00 52B9 TIM1_CCMR1 TIM1 Capture/Compare mode register 1 0x00 0x00 52BA TIM1_CCMR2 TIM1 Capture/Compare mode register 2 0x00 0x00 52BB TIM1_CCMR3 TIM1 Capture/Compare mode register 3 0x00 0x00 52BC TIM1_CCMR4 TIM1 Capture/Compare mode register 4 0x00 0x00 52BD TIM1_CCER1 TIM1 Capture/Compare enable register 1 0x00 0x00 52BE TIM1_CCER2 TIM1 Capture/Compare enable register 2 0x00 0x00 52BF TIM1_CNTRH TIM1 counter high 0x00 TIM1_CNTRL TIM1 counter low 0x00 0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 52C3 TIM1_ARRH TIM1 Auto-reload register high 0xFF 0x00 52C4 TIM1_ARRL TIM1 Auto-reload register low 0xFF 0x00 52C5 TIM1_RCR TIM1 Repetition counter register 0x00 0x00 52C6 TIM1_CCR1H TIM1 Capture/Compare register 1 high 0x00 0x00 52C7 TIM1_CCR1L TIM1 Capture/Compare register 1 low 0x00 0x00 52C8 TIM1_CCR2H TIM1 Capture/Compare register 2 high 0x00 0x00 52C9 TIM1_CCR2L TIM1 Capture/Compare register 2 low 0x00 0x00 52CA TIM1_CCR3H TIM1 Capture/Compare register 3 high 0x00 0x00 52CB TIM1_CCR3L TIM1 Capture/Compare register 3 low 0x00 0x00 52CC TIM1_CCR4H TIM1 Capture/Compare register 4 high 0x00 0x00 52CD TIM1_CCR4L TIM1 Capture/Compare register 4 low 0x00 0x00 52CE TIM1_BKR TIM1 break register 0x00 0x00 52CF TIM1_DTR TIM1 dead-time register 0x00 0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00 0x00 52D1 TIM1_DCR1 DMA1 control register 1 0x00 Address Block 0x00 52C0 TIM1 42/109 Doc ID023337 Rev 2 STM8L052R8 Table 7. Memory and register map General hardware register map (continued) Address Block 0x00 52D2 Register label Register name Reset status TIM1_DCR2 TIM1 DMA1 control register 2 0x00 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00 TIM1 0x00 52D3 0x00 52D4 to 0x00 52DF Reserved area (12 bytes) 0x00 52E0 TIM4_CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00 0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00 TIM4_IER TIM4 Interrupt enable register 0x00 0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00 0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00 0x00 52E7 TIM4_CNTR TIM4 counter 0x00 0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00 0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00 0x00 52E4 TIM4 0x00 52EA to 0x00 52FE 0x00 52FF Reserved area (21 bytes) IR_CR Infrared control register 0x00 0x00 5300 TIM5_CR1 TIM5 control register 1 0x00 0x00 5301 TIM5_CR2 TIM5 control register 2 0x00 0x00 5302 TIM5_SMCR TIM5 Slave mode control register 0x00 0x00 5303 TIM5_ETR TIM5 external trigger register 0x00 0x00 5304 TIM5_DER TIM5 DMA1 request enable register 0x00 0x00 5305 TIM5_IER TIM5 interrupt enable register 0x00 0x00 5306 TIM5_SR1 TIM5 status register 1 0x00 0x00 5307 TIM5_SR2 TIM5 status register 2 0x00 TIM5_EGR TIM5 event generation register 0x00 0x00 5309 TIM5_CCMR1 TIM5 Capture/Compare mode register 1 0x00 0x00 530A TIM5_CCMR2 TIM5 Capture/Compare mode register 2 0x00 0x00 530B TIM5_CCER1 TIM5 Capture/Compare enable register 1 0x00 0x00 530C TIM5_CNTRH TIM5 counter high 0x00 0x00 530D TIM5_CNTRL TIM5 counter low 0x00 0x00 530E TIM5_PSCR TIM5 prescaler register 0x00 0x00 530F TIM5_ARRH TIM5 Auto-reload register high 0xFF 0x00 5310 TIM5_ARRL TIM5 Auto-reload register low 0xFF 0x00 5308 IRTIM TIM5 Doc ID023337 Rev 2 43/109 Memory and register map Table 7. STM8L052R8 General hardware register map (continued) Register label Register name Reset status 0x00 5311 TIM5_CCR1H TIM5 Capture/Compare register 1 high 0x00 0x00 5312 TIM5_CCR1L TIM5 Capture/Compare register 1 low 0x00 TIM5_CCR2H TIM5 Capture/Compare register 2 high 0x00 0x00 5314 TIM5_CCR2L TIM5 Capture/Compare register 2 low 0x00 0x00 5315 TIM5_BKR TIM5 break register 0x00 0x00 5316 TIM5_OISR TIM5 output idle state register 0x00 Address Block 0x00 5313 TIM5 0x00 5317 to 0x00 533F Reserved area 0x00 5340 ADC1_CR1 ADC1 configuration register 1 0x00 0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00 0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F 0x00 5343 ADC1_SR ADC1 status register 0x00 0x00 5344 ADC1_DRH ADC1 data register high 0x00 0x00 5345 ADC1_DRL ADC1 data register low 0x00 0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F 0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF ADC1_LTRH ADC1 low threshold register high 0x00 0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00 0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00 0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00 0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00 0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00 0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00 0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00 0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00 0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00 0x00 5348 ADC1 0x00 5352 to 0x00 53BF 44/109 Reserved area (110 bytes) Doc ID023337 Rev 2 STM8L052R8 Table 7. Memory and register map General hardware register map (continued) Register label Register name Reset status 0x00 53C0 SPI2_CR1 SPI2 control register 1 0x00 0x00 53C1 SPI2_CR2 SPI2 control register 2 0x00 0x00 53C2 SPI2_ICR SPI2 interrupt control register 0x00 SPI2_SR SPI2 status register 0x02 0x00 53C4 SPI2_DR SPI2 data register 0x00 0x00 53C5 SPI2_CRCPR SPI2 CRC polynomial register 0x07 0x00 53C6 SPI2_RXCRCR SPI2 Rx CRC register 0x00 0x00 53C7 SPI2_TXCRCR SPI2 Tx CRC register 0x00 Address Block 0x00 53C3 SPI2 0x00 53C8 to 0x00 53DF Reserved area 0x00 53E0 USART2_SR USART2 status register 0xC0 0x00 53E1 USART2_DR USART2 data register 0xXX 0x00 53E2 USART2_BRR1 USART2 baud rate register 1 0x00 0x00 53E3 USART2_BRR2 USART2 baud rate register 2 0x00 0x00 53E4 USART2_CR1 USART2 control register 1 0x00 USART2_CR2 USART2 control register 2 0x00 0x00 53E6 USART2_CR3 USART2 control register 3 0x00 0x00 53E7 USART2_CR4 USART2 control register 4 0x00 0x00 53E8 USART2_CR5 USART2 control register 5 0x00 0x00 53E9 USART2_GTR USART2 guard time register 0x00 0x00 53EA USART2_PSCR USART2 prescaler register 0x00 0x00 53E5 USART2 0x00 53EB to 0x00 53EF Reserved area 0x00 53F0 USART3_SR USART3 status register 0xC0 0x00 53F1 USART3_DR USART3 data register 0xXX 0x00 53F2 USART3_BRR1 USART3 baud rate register 1 0x00 0x00 53F3 USART3_BRR2 USART3 baud rate register 2 0x00 0x00 53F4 USART3_CR1 USART3 control register 1 0x00 USART3_CR2 USART3 control register 2 0x00 0x00 53F6 USART3_CR3 USART3 control register 3 0x00 0x00 53F7 USART3_CR4 USART3 control register 4 0x00 0x00 53F8 USART3_CR5 USART3 control register 5 0x00 0x00 53F9 USART3_GTR USART3 guard time register 0x00 0x00 53FA USART3_PSCR USART3 prescaler register 0x00 0x00 53F5 USART3 Doc ID023337 Rev 2 45/109 Memory and register map Table 7. STM8L052R8 General hardware register map (continued) Address Block Register label 0x00 53FB to 0x00 53FF Register name Reset status Reserved area 0x00 5400 LCD_CR1 LCD control register 1 0x00 0x00 5401 LCD_CR2 LCD control register 2 0x00 0x00 5402 LCD_CR3 LCD control register 3 0x00 LCD_FRQ LCD frequency selection register 0x00 0x00 5404 LCD_PM0 LCD Port mask register 0 0x00 0x00 5405 LCD_PM1 LCD Port mask register 1 0x00 0x00 5406 LCD_PM2 LCD Port mask register 2 0x00 0x00 5403 LCD 0x00 5407 Reserved area 0x00 5408 LCD_PM4 0x00 5409 to 0x00 540B LCD Port mask register 4 0x00 Reserved area (3 bytes) 0x00 540C LCD_RAM0 LCD display memory 0 0x00 0x00 540D LCD_RAM1 LCD display memory 1 0x00 0x00 540E LCD_RAM2 LCD display memory 2 0x00 0x00 540F LCD_RAM3 LCD display memory 3 0x00 0x00 5410 LCD_RAM4 LCD display memory 4 0x00 0x00 5411 LCD_RAM5 LCD display memory 5 0x00 0x00 5412 LCD_RAM6 LCD display memory 6 0x00 0x00 5413 LCD_RAM7 LCD display memory 7 0x00 0x00 5414 LCD_RAM8 LCD display memory 8 0x00 LCD_RAM9 LCD display memory 9 0x00 LCD_RAM10 LCD display memory 10 0x00 0x00 5417 LCD_RAM11 LCD display memory 11 0x00 0x00 5418 LCD_RAM12 LCD display memory 12 0x00 0x00 5419 LCD_RAM13 LCD display memory 13 0x00 0x00 5415 0x00 5416 LCD 0x00 541A 0x00 541B Reserved area LCD_RAM15 LCD display memory 15 0x00 541C 0x00 541D Reserved area LCD_RAM17 LCD display memory 17 0x00 541E 0x00 541F 46/109 0x00 Reserved area LCD_RAM19 LCD display memory 19 0x00 5420 0x00 5421 0x00 0x00 Reserved area LCD_RAM21 LCD display memory 21 Doc ID023337 Rev 2 0x00 STM8L052R8 Table 7. Memory and register map General hardware register map (continued) Address Block Register label 0x00 5422 to 0x00 542E 0x00 542F Register name Reset status Reserved area LCD LCD_CR4 0x00 5430 LCD control register 4 Reserved area (1 byte) 0x00 0x00 0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00 0x00 5432 RI_ICR2 Timer input capture routing register 2 0x00 0x00 5433 RI_IOIR1 I/O input register 1 0xXX 0x00 5434 RI_IOIR2 I/O input register 2 0xXX 0x00 5435 RI_IOIR3 I/O input register 3 0xXX 0x00 5436 RI_IOCMR1 I/O control mode register 1 0x00 RI_IOCMR2 I/O control mode register 2 0x00 0x00 5438 RI_IOCMR3 I/O control mode register 3 0x00 0x00 5439 RI_IOSR1 I/O switch register 1 0x00 0x00 543A RI_IOSR2 I/O switch register 2 0x00 0x00 543B RI_IOSR3 I/O switch register 3 0x00 0x00 543C RI_IOGCR I/O group control register 0x3F 0x00 543D RI_ASCR1 Analog switch register 1 0x00 0x00 543E RI_ASCR2 Analog switch register 2 0x00 0x00 543F RI_RCR Resistor control register 1 0x00 0x00 5437 RI 0x00 5440 to 0x00 5444 Reserved area (5 bytes) 1. These registers are not impacted by a system reset. They are reset at power-on. Doc ID023337 Rev 2 47/109 Memory and register map Table 8. STM8L052R8 CPU/SWIM/debug module/interrupt controller registers Register Label Register Name Reset Status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 Address Block 0x00 7F04 0x00 7F05 0x00 7F0B to 0x00 7F5F CPU(1) Reserved area (85 bytes) CPU 0x00 7F60 CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF ITC_SPR4 Interrupt Software priority register 4 0xFF 0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF 0x00 7F73 ITC-SPR 0x00 7F78 to 0x00 7F79 0x00 7F80 0x00 7F81 to 0x00 7F8F 48/109 Reserved area (2 bytes) SWIM SWIM_CSR SWIM control status register Reserved area (15 bytes) Doc ID023337 Rev 2 0x00 STM8L052R8 Table 8. Memory and register map CPU/SWIM/debug module/interrupt controller registers (continued) Register Label Register Name Reset Status 0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM Debug module control register 1 0x00 0x00 7F97 DM_CR2 DM Debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF Address 0x00 7F95 Block DM 0x00 7F9B to 0x00 7F9F Reserved area (5 bytes) 1. Accessible by debug module only Doc ID023337 Rev 2 49/109 Interrupt vector mapping STM8L052R8 6 Interrupt vector mapping Table 9. Interrupt mapping IRQ No. Source block RESET 0 1 2 Description Reset Yes Yes Yes 0x00 8000 0x00 8004 - - - - TLI(2) External Top level Interrupt - - - - FLASH DMA1 0/1 EOP/WR_PG_DIS - DMA1 channels 0/1 DMA1 channels 2/3 4 RTC/LSE_ CSS 5 6 Vector address Yes Software interrupt DMA1 2/3 - - 0x00 8008 Yes (5) Yes 0x00 800C Yes Yes(5) 0x00 8010 (5) 0x00 8014 - - Yes RTC alarm interrupt/LSE CSS interrupt Yes Yes Yes Yes 0x00 8018 EXTI E/F/ PVD(3) PortE/F interrupt/PVD interrupt Yes Yes Yes Yes(5) 0x00 801C EXTIB/G External interrupt port B/G Yes Yes Yes Yes(5) 0x00 8020 0x00 8024 7 EXTID/H 8 EXTI0 10 Wakeup Wakeup Wakeup from from Wait from Wait Active(WFI (WFE halt mode mode) mode)(1) TRAP 3 9 Wakeup from Halt mode EXTI1 EXTI2 Yes External interrupt port D Yes Yes Yes Yes(5) External interrupt 0 Yes Yes Yes Yes(5) 0x00 8028 Yes (5) Yes 0x00 802C Yes Yes(5) 0x00 8030 (5) External interrupt 1 Yes External interrupt 2 Yes Yes Yes 11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTI4 External interrupt 4 Yes Yes Yes Yes(5) 0x00 8038 Yes Yes(5) 0x00 803C Yes (5) 0x00 8040 (5) 0x00 8044 13 14 EXTI5 EXTI6 15 EXTI7 16 LCD 17 CLK/TIM1 18 ADC1 External interrupt 5 Yes External interrupt 6 Yes Yes Yes Yes Yes Yes LCD interrupt - - Yes Yes 0x00 8048 system clock switch/ CSS interrupt/ TIM 1 break - - Yes Yes(5) 0x00 804C ACD1 Yes Yes Yes Yes(5) 0x00 8050 19 TIM2 update/overflow/ trigger/break USART2 transmission TIM2/USART2 complete/transmit data register empty interrupt - - Yes Yes(5) 0x00 8054 20 TIM2/USART2 - - Yes Yes(5) 0x00 8058 50/109 External interrupt 7 Yes capture/ compare/USART2 interrupt Doc ID023337 Rev 2 Yes STM8L052R8 Table 9. IRQ No. Interrupt vector mapping Interrupt mapping (continued) Source block Wakeup from Halt mode Description Wakeup Wakeup Wakeup from from Wait from Wait Active(WFI (WFE halt mode mode) mode)(1) Vector address 21 TIM3 update/overflow/ trigger/break USART3 transmission TIM3/USART3 complete/transmit data register empty interrupt - - Yes Yes(5) 0x00 805C 22 TIM3 capture/compareUSART3 Receive register TIM3/USART3 data full/overrun/idle line detected/parity error/ interrupt - - Yes Yes(5) 0x00 8060 23 TIM1 Update /overflow/trigger/ COM - - - Yes(5) 0x00 8064 24 TIM1 Capture/compare - - - Yes(5) 0x00 8068 25 TIM4 TIM4 update/overflow/ trigger - - Yes Yes(5) 0x00 806C 26 SPI1 End of Transfer Yes Yes Yes Yes(5) 0x00 8070 27 USART1 transmission complete/transmit data USART1/TIM5 register empty/ TIM5 update/overflow/ trigger/break - - Yes Yes(5) 0x00 8074 28 USART1 received data ready/overrun error/ USART1/TIM5 idle line detected/parity error/TIM5 capture/compare - - Yes Yes(5) 0x00 8078 Yes Yes Yes Yes(5) 0x00 807C 29 I2C1/SPI2 I2C1 interrupt(4)/SPI2 1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. 2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts. 3. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031). 4. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. 5. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing. Doc ID023337 Rev 2 51/109 Option bytes 7 STM8L052R8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses. The option bytes can also be modified `on the fly' by the application in IAP mode, except for the ROP, UBC and PCODESIZE values which can only be taken into account when they are modified in ICP mode (with the SWIM). Refer to the STM8Lxx Flash programming manual (PM0054) and STM8 SWIM and Debug Manual (UM0320) for information on SWIM programming procedures. Table 10. Address Option byte addresses Option name Option byte No. Option bits 7 6 5 4 3 2 1 0 Factory default setting 00 4800 Read-out protection (ROP) OPT0 ROP[7:0] 0x00 00 4802 UBC (User Boot code size) OPT1 UBC[7:0] 0x00 00 4807 PCODESIZE OPT2 PCODE[7:0] 0x00 00 4808 Independent watchdog option OPT3 [3:0] Reserved 00 4809 Number of stabilization clock cycles for HSE and LSE oscillators OPT4 Reserved 00 480A Brownout reset (BOR) OPT5 [3:0] Reserved Bootloader option bytes (OPTBL) OPTBL [15:0] 00 480B 00 480C 52/109 WWDG WWDG IWDG _HALT _HW _HALT LSECNT[1:0] BOR_TH IWDG _HW HSECNT[1:0] BOR_ ON 0x00 0x00 0x01 0x00 OPTBL[15:0] 0x00 Doc ID023337 Rev 2 STM8L052R8 Option bytes Table 11. Option byte no. Option byte description Option description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Disable readout protection (write access via SWIM protocol) Refer to Readout protection section in the STM8L reference manual (RM0031). OPT1 UBC[7:0] Size of the user boot code area UBC[7:0] Size of the user boot code area 0x00: No UBC 0x01: Page 0 reserved for the UBC and write protected. ... 0xFF: Page 0 to 254 reserved for the UBC and write-protected. Refer to User boot code section in the STM8L reference manual (RM0031). OPT2 PCODESIZE[7:0] Size of the proprietary code area 0x00: No proprietary code area 0x01: Page 0 reserved for the proprietary code and read/write protected. ... 0xFF: Page 0 to 254 reserved for the proprietary code and read/write protected. Refer to Proprietary code area (PCODE) section in the STM8L reference manual (RM0031) for more details. IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware IWDG_HALT: Independent watchdog off in Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode OPT3 WWDG_HW: Window watchdog 0: Window watchdog activated by software 1: Window watchdog activated by hardware WWDG_HALT: Window window watchdog reset on Halt/Active-halt 0: Window watchdog stopped in Halt mode 1: Window watchdog generates a reset when MCU enters Halt mode HSECNT: Number of HSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles OPT4 LSECNT: Number of LSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles Doc ID023337 Rev 2 53/109 Option bytes STM8L052R8 Table 11. Option byte description (continued) Option byte no. OPT5 Option description BOR_ON: 0: Brownout reset off 1: Brownout reset on BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 16 for details on the thresholds according to the value of BOR_TH bits. OPTBL 54/109 OPTBL[15:0]: This option is checked by the boot ROM code after reset. Depending on the content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 bootloader user manual for more details. Doc ID023337 Rev 2 STM8L052R8 Electrical parameters 8 Electrical parameters 8.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 8.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 C and TA = TA max (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 8.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 8.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 8.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 5. Figure 5. Pin loading conditions STM8L PIN 50 pF Doc ID023337 Rev 2 55/109 Electrical parameters 8.1.5 STM8L052R8 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 6. Figure 6. Pin input voltage STM8L PIN VIN 8.2 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 12. Voltage characteristics Symbol VDD- VSS VIN(2) VESD Ratings Min Max - 0.3 4.0 Input voltage on true open-drain pins (PC0 and PC1) VSS - 0.3 VDD + 4.0 Input voltage on five-volt tolerant (FT) pins VSS - 0.3 VDD + 4.0 Input voltage on any other pin VSS - 0.3 4.0 External supply voltage (including VDDA)(1) Electrostatic discharge voltage Unit V see Absolute maximum ratings (electrical sensitivity) on page 102 1. All power (VDD1, VDD2, VDD3, VDD4, VDDA) and ground (VSS1, VSS2, VSS3, VSS4, VSSA) pins must always be connected to the external power supply. 2. VIN maximum must always be respected. Refer to Table 13. for maximum allowed injected current values. 56/109 Doc ID023337 Rev 2 STM8L052R8 Electrical parameters Table 13. Current characteristics Symbol Ratings Max. IVDD Total current into VDD power line (source) 80 IVSS Total current out of VSS ground line (sink) 80 Output current sunk by IR_TIM pin (with high sink LED driver capability) 80 Output current sunk by any other I/O and control pin 25 IIO Output current sourced by any I/Os and control pin IINJ(PIN) IINJ(PIN) - 25 Injected current on true open-drain pins (PC0 and PC1)(1) - 5 / +0 Injected current on five-volt tolerant (FT) pins(1) - 5 / +0 Injected current on any other pin (2) - 5 / +5 Total injected current (sum of all I/O and control pins) (3) Unit mA 25 1. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 12. for maximum allowed input voltage values. 2. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 12. for maximum allowed input voltage values. 3. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 14. Symbol TSTG TJ Thermal characteristics Ratings Storage temperature range Value Unit -65 to +150 C Maximum junction temperature Doc ID023337 Rev 2 150 57/109 Electrical parameters 8.3 STM8L052R8 Operating conditions Subject to general operating conditions for VDD and TA. 8.3.1 General operating conditions Table 15. General operating conditions Symbol fSYSCLK(1) Parameter System clock frequency Conditions Min. Max. Unit 1.8 V VDD < 3.6 V 0 16 MHz 1.8 3.6 V 1.8 3.6 V 288 mW VDD Standard operating voltage VDDA Analog operating voltage PD(2) Power dissipation at TA= 85 C LQFP64 TA Temperature range 1.8 V VDD < 3.6 V -40 85 TJ Junction temperature range -40 C TA < 85 C -40 105(3) Must be at the same potential as VDD 1. fSYSCLK = fCPU 2. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/JA with TJmax in this table and JA in "Thermal characteristics" table. 3. TJmax is given by the test limit. Above this value the product behavior is not guaranteed. 58/109 Doc ID023337 Rev 2 C STM8L052R8 Electrical parameters 8.3.2 Embedded reset and power control block characteristics Table 16. Embedded reset and power control block characteristics Symbol Parameter VDD rise time rate tVDD VDD fall time rate tTEMP VPOR Conditions Min. Typ. Max. Unit BOR detector enabled 0(1) (1) s/V BOR detector disabled 0(1) 1(1) ms/V BOR detector enabled 20(1) (1) s/V BOR detector disabled Reset below voltage functional range VDD rising BOR detector enabled 3 Reset release delay ms VDD rising BOR detector disabled Power-on reset threshold 1 Rising edge 1.3(2) 1.5 1.65 1.5 1.65 VPDR Power-down reset threshold Falling edge 1.3(2) Brown-out reset threshold 0 (BOR_TH[2:0]=000) Falling edge 1.67 1.7 1.74 VBOR0 Rising edge 1.69 1.75 1.80 Brown-out reset threshold 1 (BOR_TH[2:0]=001) Falling edge 1.87 1.93 1.97 VBOR1 Rising edge 1.96 2.04 2.07 Falling edge 2.22 2.3 2.35 VBOR2 Brown-out reset threshold 2 (BOR_TH[2:0]=010) Rising edge 2.31 2.41 2.44 Brown-out reset threshold 3 (BOR_TH[2:0]=011) Falling edge 2.45 2.55 2.60 VBOR3 Rising edge 2.54 2.66 2.7 Brown-out reset threshold 4 (BOR_TH[2:0]=100) Falling edge 2.68 2.80 2.85 VBOR4 Rising edge 2.78 2.90 2.95 V Doc ID023337 Rev 2 59/109 Electrical parameters Table 16. Symbol Embedded reset and power control block characteristics (continued) Parameter VPVD0 PVD threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst STM8L052R8 Hysteresis voltage Conditions Min. Typ. Max. Falling edge 1.80 1.84 1.88 Rising edge 1.88 1.94 1.99 Falling edge 1.98 2.04 2.09 Rising edge 2.08 2.14 2.18 Falling edge 2.2 2.24 2.28 Rising edge 2.28 2.34 2.38 Falling edge 2.39 2.44 2.48 Rising edge 2.47 2.54 2.58 Falling edge 2.57 2.64 2.69 Rising edge 2.68 2.74 2.79 Falling edge 2.77 2.83 2.88 Rising edge 2.87 2.94 2.99 Falling edge 2.97 3.05 3.09 Rising edge 3.08 3.15 3.20 V BOR0 threshold 40 All BOR and PVD thresholds excepting BOR0 100 1. Data guaranteed by design, not tested in production. 2. Data based on characterization results, not tested in production. 60/109 Unit Doc ID023337 Rev 2 mV STM8L052R8 Figure 7. Electrical parameters Power supply thresholds VD D /V D DA V PVD V BOR 100 mV hysteresis 100 mV hysteresis VPOR/ VPDR IT enabled PVD output BOR reset (NRST) BOR/PDR reset (NRST) POR/PDR reset (NRST) PVD BOR always active BOR disabled by option byte POR/PDR (BOR not available) (Note 1) (Note 2) (Note 3) (Note 4) Doc ID023337 Rev 2 ai17211b 61/109 Electrical parameters 8.3.3 STM8L052R8 Supply current characteristics Total current consumption The MCU is placed under the following conditions: All I/O pins in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if explicitly mentioned. In the following table, data are based on characterization results, unless otherwise specified. Subject to general operating conditions for VDD and TA. Table 17. Total current consumption in Run mode Max. Symbol Conditions(1) Parameter Supply IDD(RUN) current in run mode(2) 62/109 Unit 55C 85 C fCPU = 125 kHz 0.22 0.28 0.39 fCPU = 1 MHz 0.32 0.38 0.49 fCPU = 4 MHz 0.59 0.65 0.76 fCPU = 8 MHz 0.93 0.99 1.1 fCPU = 16 MHz 1.62 1.68 1.79(4) fCPU = 125 kHz 0.21 0.25 0.35 fCPU = 1 MHz 0.3 0.34 0.44 fCPU = 4 MHz 0.57 0.61 0.71 fCPU = 8 MHz 0.95 0.99 1.09 fCPU = 16 MHz 1.73 1.77 1.87(4) LSI RC osc. (typ. 38 kHz) fCPU = fLSI 0.029 0.035 0.039 LSE external clock (32.768 kHz) fCPU = fLSE 0.028 0.034 0.038 HSI RC osc. (16 MHz)(3) All peripherals OFF, code executed from RAM, VDD from 1.8 V to 3.6 V Typ. HSE external clock (fCPU=fHSE)(5) Doc ID023337 Rev 2 mA STM8L052R8 Table 17. Electrical parameters Total current consumption in Run mode (continued) Max. Symbol Conditions(1) Parameter HSI RC osc.(6) Supply current IDD(RUN) in Run mode All peripherals OFF, code executed from Flash, VDD from 1.8 V to 3.6 V HSE external clock (fCPU=fHSE) (5) LSI RC osc. Typ. Unit 55C 85 C fCPU = 125 kHz 0.35 0.46 0.48 fCPU = 1 MHz 0.54 0.65 0.67 fCPU = 4 MHz 1.16 1.27 1.29 fCPU = 8 MHz 1.97 2.08 2.1 fCPU = 16 MHz 3.54 3.65 3.67 fCPU = 125 kHz 0.35 0.44 0.46 fCPU = 1 MHz 0.53 0.62 0.64 fCPU = 4 MHz 1.13 1.22 1.24 fCPU = 8 MHz 2 2.09 2.11 fCPU = 16 MHz 3.69 3.78 3.8 fCPU = fLSI 0.110 0.123 0.130 0.100 0.101 0.104 LSE external clock fCPU = fLSE (32.768 kHz)(7) mA 1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc., fCPU=fSYSCLK 2. CPU executing typical data processing 3. The run from RAM consumption can be approximated with the linear formula: IDD(run_from_RAM) = Freq. * 95 A/MHz + 250 A 4. Tested in production. 5. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (IDD HSE) must be added. Refer to Table 28. 6. The run from Flash consumption can be approximated with the linear formula: IDD(run_from_Flash) = Freq. * 200 A/MHz + 330 A 7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 29 Doc ID023337 Rev 2 63/109 Electrical parameters Figure 8. STM8L052R8 Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz 1) 2 1.8 1.6 IDD Run HSI 16MHz (mA) 1.4 1.2 25C 1 85 C -40 C 0.8 0.6 0.4 0.2 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) MS19109V2 1. Typical current consumption measured with code executed from RAM. Figure 9. Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz 1) 4 IDD Run HSI EEP 16MHz (mA) 3.5 3 25C 85C -40C 2.5 2 1.5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) MS19112V2 1. Typical current consumption measured with code executed from Flash. 64/109 Doc ID023337 Rev 2 STM8L052R8 Electrical parameters In the following table, data are based on characterization results, unless otherwise specified. Table 18. Total current consumption in Wait mode Max Conditions(1) Symbol Parameter mode,(2) VDD from 1.8 V to 3.6 V Supply IDD(Wait) current in Wait mode 85 C 0.21 0.29 0.33 fCPU = 1 MHz 0.25 0.33 0.37 fCPU = 4 MHz 0.32 0.4 0.44 fCPU = 8 MHz 0.42 0.496 0.54 fCPU = 16 MHz 0.66 0.736 0.78(3) fCPU = 125 kHz 0.19 0.21 0.3 fCPU = 1 MHz 0.2 0.23 0.32 fCPU = 4 MHz 0.27 0.3 0.39 fCPU = 8 MHz 0.37 0.4 0.49 fCPU = 16 MHz 0.63 0.66 0.75(3) LSI fCPU = fLSI 0.028 0.037 0.039 LSE(5) external clock (32.768 kHz) fCPU = fLSE 0.027 0.035 0.038 fCPU = 125 kHz 0.27 0.36 0.42 fCPU = 1 MHz 0.29 0.38 0.44 fCPU = 4 MHz 0.37 0.46 0.52 fCPU = 8 MHz 0.45 0.55 0.61 fCPU = 16 MHz 0.69 0.79 0.85 fCPU = 125 kHz 0.23 0.29 0.32 fCPU = 1 MHz 0.24 0.31 0.34 fCPU = 4 MHz 0.32 0.39 0.42 fCPU = 8 MHz 0.42 0.49 0.51 fCPU = 16 MHz 0.7 0.77 0.79 HSE external clock (fCPU=fHSE)(4) HSI CPU not clocked, all peripherals OFF, code executed from Flash, VDD from 1.8 V to 3.6 V Unit 55C fCPU = 125 kHz HSI CPU not clocked, all peripherals OFF, code executed from RAM with Flash in IDDQ Typ HSE(4) external clock (fCPU= HSE) mA mA LSI fCPU = fLSI 0.037 0.085 0.105 LSE(5) external clock (32.768 kHz) fCPU = fLSE 0.036 0.082 0.095 1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc., fCPU = fSYSCLK 2. Flash is configured in IDDQ mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register. 3. Tested in production. 4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (IDD HSE) must be added. Refer to Table 28. Doc ID023337 Rev 2 65/109 Electrical parameters STM8L052R8 5. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (IDD HSE) must be added. Refer to Table 29 Figure 10. Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz 1) 0.8 0.7 IDD Wait HSI 16MHz (mA) 0.6 0.5 25C 0.4 85C -40C 0.3 0.2 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) MS19113V2 1. Typical current consumption measured with code executed from RAM. Figure 11. Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz 1) 0.8 IDD Wfi HSI 16MHz EEON (mA) 0.7 0.6 0.5 25C 85C -40C 0.4 0.3 0.2 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) MS19108V2 1. Typical current consumption measured with code executed from Flash. 66/109 Doc ID023337 Rev 2 STM8L052R8 Electrical parameters In the following table, data are based on characterization results, unless otherwise specified. Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V to 3.6 V Symbol Conditions(1) Parameter all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 IDD(LPR) active(2) Supply current in Low power run mode all peripherals OFF LSE (3) external clock (32.768 kHz) with TIM2 active (2) Typ. Max. TA = -40 C to 25 C 5.86 6.38 TA = 55 C 6.52 7.06 TA = 85 C 7.68 8.7 TA = -40 C to 25 C 6.2 6.73 TA = 55 C 6.86 7.41 TA = 85 C 9.71 10.81 TA = -40 C to 25 C 5.42 5.94 TA = 55 C 5.9 6.52 TA = 85 C 6.14 6.8 TA = -40 C to 25 C 5.87 6.48 TA = 55 C 6.44 6.95 TA = 85 C 6.7 7.65 Unit A 1. No floating I/Os 2. Timer 2 clock enabled and counter running 3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 29 Doc ID023337 Rev 2 67/109 Electrical parameters STM8L052R8 Figure 12. Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF 0.02 25C 0.015 IDD Lp Run LSI all off (mA) 85C - 40C 0.01 0.005 0 1.8 2 2.2 2.4 2.6 2.8 VDD (V) 68/109 Doc ID023337 Rev 2 3 3.2 3.4 3.6 MS19110V2 STM8L052R8 Electrical parameters In the following table, data are based on characterization results, unless otherwise specified. Table 20. Symbol Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V Conditions(1) Parameter all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 active(2) IDD(LPW) Supply current in Low power wait mode all peripherals OFF LSE external clock(3) (32.768 kHz) with TIM2 active (2) Typ. Max. Unit TA = -40 C to 25 C 3.03 3.41 TA = 55 C 3.38 3.78 TA = 85 C 4.6 5.34 TA = -40 C to 25 C 3.78 4.21 TA = 55 C 4.13 4.57 TA = 85 C 5.29 6.08 TA = -40 C to 25 C 2.46 2.89 TA = 55 C 2.58 3.07 TA = 85 C 3.32 4.05 TA = -40 C to 25 C 2.88 3.29 TA = 55 C 2.97 3.42 TA = 85 C 3.69 4.55 A 1. No floating I/Os. 2. Timer 2 clock enabled and counter is running. 3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 29. Figure 13. Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF (1) 0.02 25 C 85C -40C IDD Lp Wfi ram LSI all off (mA) 0.015 0.01 0.005 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) .47 1. Typical current consumption measured with code executed from RAM. Doc ID023337 Rev 2 69/109 Electrical parameters STM8L052R8 In the following table, data are based on characterization results, unless otherwise specified. Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V Symbol Conditions(1) Parameter LCD OFF(2) IDD(AH) Supply current in Active-halt mode LSI RC (at 38 kHz) LCD ON (static duty/ external VLCD) (3) LCD ON (1/4 duty/ external VLCD) (4) LCD ON (1/4 duty/ internal VLCD) (5) LCD OFF(7) IDD(AH) Supply current in Active-halt mode LSE external clock (32.768 kHz) (6) LCD ON (static duty/ external VLCD) (3) LCD ON (1/4 duty/ external VLCD) (4) LCD ON (1/4 duty/ internal VLCD) (5) IDD(WUFAH) Supply current during wakeup time from Active-halt mode (using HSI) Typ. Max. TA = -40 C to 25 C 0.92 2.25 TA = 55 C 1.32 3.44 TA = 85 C 1.63 3.87 TA = -40 C to 25 C 1.56 3.6 TA = 55 C 1.64 3.8 TA = 85 C 2.12 5.03 TA = -40 C to 25 C 1.92 4.56 TA = 55 C 2.1 4.97 TA = 85 C 2.6 6.14 TA = -40 C to 25 C 4.2 9.88 TA = 55 C 4.39 10.32 TA = 85 C 4.84 11.5 TA = -40 C to 25 C 0.54 1.35 TA = 55 C 0.61 1.44 TA = 85 C 0.91 2.27 TA = -40 C to 25 C 0.91 2.13 TA = 55 C 1.05 2.55 TA = 85 C 1.42 3.65 TA = -40 C to 25 C 1.6 2.84 TA = 55 C 1.76 4.37 TA = 85 C 2.14 5.23 TA = -40 C to 25 C 3.89 9.15 TA = 55 C 3.89 9.15 TA = 85 C 4.25 10.49 2.4 Wakeup time from tWU_HSI(AH)(8)(9) Active-halt mode to Run mode (using HSI) 4.7 Wakeup time from tWU_LSI(AH)(8)(9) Active-halt mode to Run mode (using LSI) 150 70/109 Doc ID023337 Rev 2 Unit A A mA 7 s s STM8L052R8 Electrical parameters 1. No floating I/O, unless otherwise specified. 2. RTC enabled. Clock source = LSI 3. RTC enabled, LCD enabled with external VLCD = 3 V, static duty, division ratio = 256, all pixels active, no LCD connected. 4. RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 5. LCD enabled with internal LCD booster VLCD = 3 V, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption (IDD LSE) must be added. Refer to Table 29 7. RTC enabled. Clock source = LSE 8. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after tWU. 9. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register. Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal Symbol Condition(1) Parameter Typ. LSE VDD = 1.8 V IDD(AH) (2) Supply current in Active-halt mode 1.2 (3) VDD = 3 V VDD = 3.6 V Unit LSE/32 0.9 LSE 1.4 LSE/32(3) 1.1 LSE 1.6 LSE/32(3) 1.3 A 1. No floating I/O, unless otherwise specified. 2. Based on measurements on bench with 32.768 kHz external crystal oscillator. 3. RTC clock is LSE divided by 32. Figure 14. Typical IDD(AH) vs. VDD (LSI clock source) 0.02 25C 85C -40C IDD AHalt (mA) 0.015 0.01 0.005 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) MS19117V2 Doc ID023337 Rev 2 71/109 Electrical parameters STM8L052R8 In the following table, data are based on characterization results, unless otherwise specified. Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V Condition(1) Symbol Parameter IDD(Halt) Supply current in Halt mode (Ultra low power ULP bit =1 in the PWR_CSR2 register) Typ. Max. TA = -40 C to 25 C 400 1600(2) TA = 55 C 810 2400 1600 4500(2) TA = 85 C IDD(WUHalt) Supply current during wakeup time from Halt mode (using HSI) 2.4 tWU_HSI(Halt)(3)(4) Wakeup time from Halt to Run mode (using HSI) 4.7 tWU_LSI(Halt) (3)(4) Wakeup time from Halt mode to Run mode (using LSI) 150 Unit nA mA 7 s s 1. TA = -40 to 85 C, no floating I/O, unless otherwise specified 2. Tested in production 3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register 4. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after tWU Figure 15. Typical IDD(Halt) vs. VDD (internal reference voltage OFF) 0.02 0.018 25C 0.016 -40C 85C IDD Haltbgoff (mA) 0.014 0.012 0.01 0.008 0.006 0 006 0.004 0.002 0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) MS19119V2 72/109 Doc ID023337 Rev 2 STM8L052R8 Electrical parameters Current consumption of on-chip peripherals Table 24. Peripheral current consumption Symbol Typ. Parameter VDD = 3.0 V IDD(ALL) Peripherals ON (1) 63 IDD(TIM1) TIM1 supply current(2) 10 IDD(TIM2) TIM2 supply current (2) 7 IDD(TIM3) TIM3 supply current (2) 7 IDD(TIM5) TIM5 supply current (2) 7 IDD(TIM4) TIM4 timer supply current (2) 3 IDD(USART1) USART1 supply current (3) 5 IDD(USART2) USART2 supply current (3) 5 IDD(USART3) USART3 supply current (3) 5 IDD(SPI1) SPI1 supply current (3) 3 IDD(SPI2) SPI2 supply current (3) 3 IDD(I2C1) I2C1 supply current (3) 4 IDD(DMA1) DMA1 supply current 3 IDD(WWDG) WWDG supply current 1 IDD(ADC1) ADC1 supply current(4) 1500 IDD(PVD/BOR) IDD(BOR) IDD(IDWDG) Power voltage detector and brownout Reset unit supply current (5) 2.6 Brownout Reset unit supply current (5) 2.4 including LSI supply current 0.45 excluding LSI supply current 0.05 Unit A/MHz A Independent watchdog supply current 1. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, TIM5, USART1, USART2, USART3, SPI1, SPI2, I2C1, DMA1, WWDG. 2. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production. 3. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling. Not tested in production. 4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion. 5. Including supply current of internal reference voltage. Doc ID023337 Rev 2 73/109 Electrical parameters Table 25. Current consumption under external reset Symbol IDD(RST) STM8L052R8 Parameter Conditions Supply current under external reset (1) PB1/PB3/PA5 pins are externally tied to VDD Typ. VDD = 1.8 V 48 VDD = 3 V 80 VDD = 3.6 V 95 Unit A 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset. PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger. 8.3.4 Clock and timing characteristics HSE external clock (HSEBYP = 1 in CLK_ECKCR) Subject to general operating conditions for VDD and TA. Table 26. Symbol fHSE_ext(1) HSE external clock characteristics Parameter Conditions External clock source frequency Min. Typ. Max. Unit 1 16 MHz VHSEH OSC_IN input pin high level voltage 0.7 x VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.3 x VDD V Cin(HSE)(1) OSC_IN input capacitance ILEAK_HSE OSC_IN input leakage current 2.6 VSS < VIN < VDD 1. Guaranteed by design, not tested in production. 74/109 Doc ID023337 Rev 2 pF 1 A STM8L052R8 Electrical parameters LSE external clock (LSEBYP=1 in CLK_ECKCR) Subject to general operating conditions for VDD and TA. Table 27. LSE external clock characteristics Symbol Parameter Min. Typ. Max. fLSE_ext(1) External clock source frequency VLSEH(2) OSC32_IN input pin high level voltage 0.7 x VDD VDD VLSEL(2) OSC32_IN input pin low level voltage VSS 0.3 x VDD 32.768 Unit kHz V Cin(LSE)(1) OSC32_IN input capacitance ILEAK_LSE OSC32_IN input leakage current 0.6 pF 1 A 1. Guaranteed by design, not tested in production. 2. Data based on characterization results, not tested in production. HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 28. HSE oscillator characteristics Symbol fHSE RF C(1)(2) IDD(HSE) gm tSU(HSE)(4) Parameter Conditions High speed external oscillator frequency Min. Typ. 1 Max. Unit 16 MHz Feedback resistor 200 k Recommended load capacitance 20 pF HSE oscillator power consumption C = 20 pF, fOSC = 16 MHz 2.5 (startup) 0.7 (stabilized)(3) C = 10 pF, fOSC =16 MHz 2.5 (startup) 0.46 (stabilized)(3) 3.5(3) Oscillator transconductance Startup time mA VDD is stabilized mA/V 1 ms 1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details 3. Guaranteed by design. Not tested in production. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Doc ID023337 Rev 2 75/109 Electrical parameters STM8L052R8 Figure 16. HSE oscillator circuit diagram fHSE to core Rm RF CO Lm CL1 OSC_IN Cm gm Resonator Consumption control Resonator STM8 OSC_OUT CL2 HSE oscillator critical gm formula g mcrit = ( 2 x x f HSE ) 2 x R m ( 2Co + C ) 2 Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification), Cm: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification), CL1=CL2=C: Grounded external capacitance gm >> gmcrit LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). Table 29. LSE oscillator characteristics Symbol Parameter fLSE Low speed external oscillator frequency RF Feedback resistor C(1)(2) IDD(LSE) Conditions Min. V = 200 mV Recommended load capacitance LSE oscillator power consumption tSU(LSE) Startup time 1.2 M 8 pF VDD = 3 V 600 nA 750 3(3) VDD is stabilized Unit kHz 450 Oscillator transconductance (4) Max. 32.768 VDD = 1.8 V VDD = 3.6 V gm Typ. A/V 1 1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD. 2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value. Refer to crystal manufacturer for more details. 3. Guaranteed by design. Not tested in production. 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. 76/109 Doc ID023337 Rev 2 s STM8L052R8 Electrical parameters Figure 17. LSE oscillator circuit diagram fLSE Rm Lm RF CO CL1 OSC_IN Cm gm Resonator Consumption control Resonator STM8 OSC_OUT CL2 Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) In the following table, data are based on characterization results, not tested in production, unless otherwise specified. Table 30. Symbol HSI oscillator characteristics Conditions(1) Parameter Frequency VDD = 3.0 V VDD = 3.0 V, TA = 25 C ACCHSI Accuracy of HSI oscillator (factory calibrated) TRIM HSI user trimming step(3) fHSI 1.8 V VDD 3.6 V, -40 C TA 85 C Trimming code multiple of 16 Min. Typ. Max. Unit 16 MHz -1 (2) 1 (2) % -5 5 % 0.7 % 1.5 % 0.4 Trimming code = multiple of 16 tsu(HSI) HSI oscillator setup time (wakeup time) 3.7 6 (4) s IDD(HSI) HSI oscillator power consumption 100 140(4) A 1. VDD = 3.0 V, TA = -40 to 85 C unless otherwise specified. 2. Tested in production. 3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 "STM8L15x internal RC oscillator calibration" application note for more details. 4. Guaranteed by design, not tested in production Doc ID023337 Rev 2 77/109 Electrical parameters STM8L052R8 Figure 18. Typical HSI frequency vs. VDD 18.0 17.5 HSI frequency [MHz] 17.0 16.5 16.0 15.5 15.0 -40C 25C 85C 14.5 14.0 13.5 13.0 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai18218V3 Low speed internal RC oscillator (LSI) In the following table, data are based on characterization results, not tested in production. Table 31. Symbol fLSI LSI oscillator characteristics Conditions(1) Parameter Frequency tsu(LSI) LSI oscillator wakeup time D(LSI) LSI oscillator frequency drift(3) 0 C TA 85 C Min. Typ. Max. Unit 26 38 56 kHz 200(2) s 11 % -12 1. VDD = 1.8 V to 3.6 V, TA = -40 to 85 C unless otherwise specified. 2. Guaranteed by Design, not tested in production. 3. This is a deviation for an individual part, once the initial frequency has been measured. 78/109 Doc ID023337 Rev 2 STM8L052R8 Electrical parameters Figure 19. Typical LSI clock source frequency vs. VDD 0.04 25C 85C -40C RC32K Check (MHz) 0.038 0.036 0.034 0.032 0.03 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD (V) MS19116V2 8.3.5 Memory characteristics TA = -40 to 85 C unless otherwise specified. Table 32. Symbol VRM RAM and hardware registers Parameter Data retention mode (1) Conditions Min. Halt mode (or Reset) 1.8 Typ. Max. Unit V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization, not tested in production. Doc ID023337 Rev 2 79/109 Electrical parameters STM8L052R8 Flash memory Table 33. Symbol VDD tprog Iprog tRET(2) Flash program and data EEPROM memory Parameter Operating voltage (all modes, read/write/erase) Conditions Min. fSYSCLK = 16 MHz 1.8 Max. (1) Unit 3.6 V Programming time for 1 or 128 bytes (block) erase/write cycles (on programmed byte) 6 ms Programming time for 1 to 128 bytes (block) write cycles (on erased byte) 3 ms 0.7 mA TA=+25 C, VDD = 3.0 V Programming/ erasing consumption TA=+25 C, VDD = 1.8 V Data retention (program memory) after 100 erase/write cycles at TA=-40 to +85 C TRET=+85 C 30(1) Data retention (data memory) after 100000 erase/write cycles at TA=-40 to +85 C TRET=+85 C 30(1) years 100(1) Erase/write cycles (program memory) NRW Typ. (3) TA=-40 to +85 C Erase/write cycles (data memory) 100 cycles (1) (4) kcycles 1. Data based on characterization results, not tested in production. 2. Conforming to JEDEC JESD22a117 3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. 4. Data based on characterization performed on the whole data memory. 80/109 Doc ID023337 Rev 2 STM8L052R8 8.3.6 Electrical parameters I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, LCD levels, etc.). The test results are given in the following table. Table 34. I/O current injection susceptibility Functional susceptibility Symbol IINJ 8.3.7 Description Negative injection Positive injection Injected current on true open-drain pins -5 +0 Injected current on all 5 V tolerant (FT) pins -5 +0 Injected current on any other pin -5 +5 Unit mA I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Doc ID023337 Rev 2 81/109 Electrical parameters Table 35. Symbol VIL STM8L052R8 I/O static characteristics Conditions(1) Parameter Input low level voltage(2) 0.3 x VDD Input voltage on fivevolt tolerant (FT) pins Vss-0.3 0.3 x VDD Input voltage on any other pin Vss-0.3 0.3 x VDD Input voltage on fivevolt tolerant (FT) pins with VDD < 2 V Input voltage on fivevolt tolerant (FT) pins with VDD 2 V Input voltage on any other pin Vhys Ilkg Schmitt trigger voltage hysteresis (3) Input leakage current (4) Max. Vss-0.3 Input voltage on true open-drain pins (PC0 and PC1) with VDD 2 V Input high level voltage (2) Typ. Input voltage on true open-drain pins (PC0 and PC1) Input voltage on true open-drain pins (PC0 and PC1) with VDD < 2 V VIH Min. V 5.2 0.70 x VDD 5.5 V 5.2 0.70 x VDD 5.5 VDD+0.3 0.70 x VDD Standard I/Os 200 True open drain I/Os 200 mV VSS VIN VDD Standard I/Os - - 50 (5) VSS VIN VDD True open drain I/Os - - 200(5) VSS VIN VDD PA0 with high sink LED driver capability - - 200(5) 30 45 60 RPU Weak pull-up equivalent resistor(2)(6) VIN=VSS CIO I/O pin capacitance 5 1. VDD = 3.0 V, TA = -40 to 85 C unless otherwise specified. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Not tested in production. 6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in Figure 23). 82/109 Unit Doc ID023337 Rev 2 nA k pF STM8L052R8 Electrical parameters Figure 20. Typical VIL and VIH vs. VDD (standard I/Os) 3 -40C 25C 85C 2.5 VIL and VIH [V] 2 1.5 1 0.5 0 1.8 2.1 2.6 3.1 3.6 VDD [V] ai18220V3 Figure 21. Typical VIL and VIH vs. VDD (true open drain I/Os) 3 -40C 25C 85C 2.5 VIL and VIH [V] 2 1.5 1 0.5 0 1.8 2.1 2.6 VDD [V] 3.1 3.6 ai18221V2 Figure 22. Typical pull-up resistance RPU vs. VDD with VIN=VSS 60 -40C 25C 85C Pull-Up resistance [k] 55 50 45 40 35 30 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD [V] ai18222V2 Doc ID023337 Rev 2 83/109 Electrical parameters STM8L052R8 Figure 23. Typical pull-up current Ipu vs. VDD with VIN=VSS 120 -40C 25C 85C Pull-Up current [A] 100 80 60 40 20 0 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] 3 3.15 3.3 3.45 3.6 ai18223V2 Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 36. Output driving current (high sink ports) I/O Symbol Type Output low level voltage for an I/O pin Standard VOL (1) Parameter VOH (2) Output high level voltage for an I/O pin Conditions Min. Max. Unit IIO = +2 mA, VDD = 3.0 V 0.45 V IIO = +2 mA, VDD = 1.8 V 0.45 V IIO = +10 mA, VDD = 3.0 V 0.7 V IIO = -2 mA, VDD = 3.0 V VDD-0.45 V IIO = -1 mA, VDD = 1.8 V VDD-0.45 V IIO = -10 mA, VDD = 3.0 V VDD-0.7 V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 84/109 Doc ID023337 Rev 2 STM8L052R8 Electrical parameters Table 37. Output driving current (true open drain ports) Open drain I/O Symbol Type (1) VOL Parameter Conditions Output low level voltage for an I/O pin Min. Max. IIO = +3 mA, VDD = 3.0 V 0.45 IIO = +1 mA, VDD = 1.8 V 0.45 Unit V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Table 38. Output driving current (PA0 with high sink LED driver capability) I/O Symbol Type IR VOL (1) Parameter Conditions Min. IIO = +20 mA, VDD = 2.0 V Output low level voltage for an I/O pin Max. Unit 0.45 V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Figure 24. Typical VOL @ VDD = 3.0 V (high sink ports) Figure 25. Typical VOL @ VDD = 1.8 V (high sink ports) 1 0.7 -40C 25C 85C 0.5 VOL [V] VOL [V] 0.6 -40C 25C 85C 0.75 0.5 0.4 0.3 0.2 0.25 0.1 0 0 2 4 6 8 10 12 14 16 18 IOL [mA] 0 20 0 1 2 3 Figure 26. Typical VOL @ VDD = 3.0 V (true open drain ports) 4 5 6 IOL [mA] ai18226V2 7 8 ai18227V2 Figure 27. Typical VOL @ VDD = 1.8 V (true open drain ports) 0.5 0.5 -40C 25C 85C 0.4 0.4 -40C 25C 85C 0.3 VOL [V] VOL [V] 0.3 0.2 0.2 0.1 0.1 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 IOL [mA] IOL [mA] ai18228V2 Doc ID023337 Rev 2 BJ7 85/109 Electrical parameters STM8L052R8 Figure 28. Typical VDD - VOH @ VDD = 3.0 V (high sink ports) Figure 29. Typical VDD - VOH @ VDD = 1.8 V (high sink ports) 2 0.5 -40C 25C 85C 1.75 -40C 25C 85C 1.25 0.4 VDD - VOH [V] VDD - VOH [V] 1.5 1 0.75 0.3 0.2 0.5 0.1 0.25 0 0 0 2 4 6 8 10 12 14 16 18 20 0 1 2 IOH [mA] 3 4 5 6 7 IOH [mA] BJ7 ai12830V2 NRST pin Subject to general operating conditions for VDD and TA unless otherwise specified. Table 39. NRST pin characteristics Symbol Parameter Conditions Min. Typ. Max. VIL(NRST) NRST input low level voltage (1) VSS 0.8 VIH(NRST) NRST input high level voltage (1) 1.4 VDD VOL(NRST) NRST output low level voltage (1) IOL = 2 mA for 2.7 V VDD 3.6 V Unit V 0.4 IOL = 1.5 mA for VDD < 2.7 V VHYST NRST input hysteresis(3) RPU(NRST) NRST pull-up equivalent resistor(1) 10%VDD mV (2) 30 VF(NRST) NRST input filtered pulse (3) VNF(NRST) NRST input not filtered pulse (3) 45 60 k 50 ns 1. Data based on characterization results, not tested in production. 2. 200 mV min. 3. Data guaranteed by design, not tested in production. 86/109 Doc ID023337 Rev 2 300 STM8L052R8 Electrical parameters Figure 30. Typical NRST pull-up resistance RPU vs. VDD 60 -40C 25C 85C Pull-up resistance [k] 55 50 45 40 35 30 1.8 2 2.2 2.4 2.6 VDD [V] 2.8 3 3.2 3.4 3.6 ai18224V2 Figure 31. Typical NRST pull-up current Ipu vs. VDD 120 Pull-Up current [A] 100 -40C 25C 85 C 80 60 40 20 0 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai18225V2 The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 39. Otherwise the reset is not taken into account internally. For power consumptionsensitive applications, the capacity of the external reset capacitor can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. The minimum recommended capacity is 10 nF. Doc ID023337 Rev 2 87/109 Electrical parameters STM8L052R8 Figure 32. Recommended NRST pin configuration VDD RPU RSTIN EXTERNAL RESET CIRCUIT INTERNAL RESET STM8L 0.1 F 88/109 Filter Doc ID023337 Rev 2 STM8L052R8 8.3.8 Electrical parameters Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under ambient temperature, fSYSCLK frequency and VDD supply voltage conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(2) th(NSS) (2) SPI1 characteristics Parameter Min. Max. Master mode 0 8 Slave mode 0 8 SPI1 clock rise and fall time Capacitive load: C = 30 pF - 30 NSS setup time Slave mode 4 x 1/fSYSCLK - NSS hold time Slave mode 80 - SCK high and low time Master mode, fMASTER = 8 MHz, fSCK= 4 MHz 105 145 Master mode 30 - Slave mode 3 - Master mode 15 - Slave mode 0 - tsu(MI) (2) tsu(SI)(2) Data input setup time th(MI) (2) th(SI)(2) Data input hold time ta(SO)(2)(3) Data output access time Slave mode - 3x 1/fSYSCLK tdis(SO)(2)(4) 30 - Data output disable time Slave mode (2) Data output valid time Slave mode (after enable edge) - 60 tv(MO)(2) Data output valid time Master mode (after enable edge) - 20 Slave mode (after enable edge) 15 - Master mode (after enable edge) 1 - tv(SO) th(SO)(2) th(MO)(2) Unit SPI1 clock frequency (2) tw(SCKH) tw(SCKL)(2) Conditions(1) Data output hold time MHz ns 1. Parameters are given by selecting 10 MHz I/O output frequency. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data. 4. Min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in Hi-Z. Doc ID023337 Rev 2 89/109 Electrical parameters STM8L052R8 Figure 33. SPI1 timing diagram - slave mode and CPHA=0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134 Figure 34. SPI1 timing diagram - slave mode and CPHA=1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 90/109 Doc ID023337 Rev 2 STM8L052R8 Electrical parameters Figure 35. SPI1 timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID023337 Rev 2 91/109 Electrical parameters STM8L052R8 I2C - Inter IC control interface Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified. The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 41. I2C characteristics Symbol Parameter Standard mode I2C Fast mode I2C(1) Unit Min.(2) Max. (2) Min. (2) Max. (2) tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 0 tr(SDA) tr(SCL) SDA and SCL rise time 1000 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 300 th(STA) START condition hold time 4.0 0.6 tsu(STA) Repeated START condition setup time 4.7 0.6 tsu(STO) STOP condition setup time 4.0 0.6 s STOP to START condition time (bus free) 4.7 1.3 s tw(STO:STA) Cb Capacitive load for each bus line 400 s 900 ns s 400 1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz). 2. Data based on standard I2C protocol requirement, not tested in production. Note: For speeds around 200 kHz, the achieved speed can have a 5% tolerance. For other speed ranges, the achieved speed can have a 2% tolerance. The above variations depend on the accuracy of the external components used. 92/109 Doc ID023337 Rev 2 pF STM8L052R8 Electrical parameters Figure 36. Typical application with I2C bus and timing diagram 1) VDD VDD 4.7k 4.7k I2C BUS 100 SDA 100 SCL STM8L REPEATED START START tsu(STA) tw(STO:STA) START SDA tr(SDA) tf(SDA) tsu(SDA) th(SDA) tr(SCL) tf(SCL) STOP SCL th(STA) tw(SCLH) tw(SCLL) tsu(STO) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD Doc ID023337 Rev 2 93/109 Electrical parameters 8.3.9 STM8L052R8 LCD controller In the following table, data are guaranteed by Design, not tested in production. Table 42. LCD characteristics Symbol Parameter VLCD LCD external voltage VLCD0 LCD internal reference voltage 0 2.6 VLCD1 LCD internal reference voltage 1 2.7 VLCD2 LCD internal reference voltage 2 2.8 VLCD3 LCD internal reference voltage 3 3.0 VLCD4 LCD internal reference voltage 4 3.1 VLCD5 LCD internal reference voltage 5 3.2 VLCD6 LCD internal reference voltage 6 3.4 VLCD7 LCD internal reference voltage 7 3.5 CEXT VLCD external capacitance Supply IDD current(1) Typ. Max. Unit 3.6 0.1 at VDD = 1.8 V (1) Supply current Min. 1 V 2 F 3 A at VDD = 3 V 3 RHN(2) High value resistive network (low drive) 6.6 M (3) Low value resistive network (high drive) 240 k RLN V33 Segment/Common higher level voltage VLCDx V34 Segment/Common 3/4 level voltage 3/4VLCDx V23 Segment/Common 2/3 level voltage 2/3VLCDx V12 Segment/Common 1/2 level voltage 1/2VLCDx V13 Segment/Common 1/3 level voltage 1/3VLCDx V14 Segment/Common 1/4 level voltage 1/4VLCDx V0 Segment/Common lowest level voltage V 0 1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels active, no LCD connected. 2. RHN is the total high value resistive network. 3. RLN is the total low value resistive network. VLCD external capacitor The application can achieve a stabilized LCD reference voltage by connecting an external capacitor CEXT to the VLCD pin. CEXT is specified in Table 42. 94/109 Doc ID023337 Rev 2 STM8L052R8 8.3.10 Electrical parameters Embedded reference voltage In the following table, data are based on characterization results, not tested in production, unless otherwise specified. Table 43. Reference voltage characteristics Symbol Parameter Conditions Min. IREFINT Internal reference voltage consumption 1.4 TS_VREFINT(1)(2) ADC sampling time when reading the internal reference voltage 5 10 s IBUF(1) Internal reference voltage buffer consumption (used for ADC) 13.5 25 A VREFINT out Reference voltage output ILPBUF(1) Internal reference voltage low power buffer consumption (used for comparators or output) IREFOUT(1)(4) 1.202 Typ. Unit A 1.242 (3) V 1200 nA Buffer output current 1 A CREFOUT Reference voltage output load 50 pF tVREFINT(1) Internal reference voltage startup time 3 ms tBUFEN(1)(2) Internal reference voltage buffer startup time once enabled 10 s 50 ppm/C 20 ppm/C TBD ppm STABVREFINT STABVREFINT (3) 730 2 Stability of VREFINT over temperature -40 C TA 85 C Stability of VREFINT over temperature 1.224 Max. 0 C TA 50 C Stability of VREFINT after 1000 hours 20 1. Guaranteed by design, not tested in production 2. Defined when ADC output reaches its final value 1/2LSB 3. Tested in production at VDD = 3 V 10 mV. 4. To guarantee less than 1% VREFOUT deviation Doc ID023337 Rev 2 95/109 Electrical parameters 8.3.11 STM8L052R8 12-bit ADC1 characteristics In the following table, data are guaranteed by design, not tested in production. Table 44. Symbol ADC1 characteristics Parameter VDDA Analog supply voltage VREF+ Reference supply voltage VREF- Lower reference voltage IVDDA Current on the VDDA input pin IVREF+ Current on the VREF+ input pin Conditions 2.4 V VDDA 3.6 V Min. Max. Unit 1.8 3.6 V 2.4 VDDA V 1.8 V VDDA 2.4 V Typ. VDDA V VSSA V 1000 1450 A 700 (peak)(1) A 450 (average)(1) A 400 VAIN Conversion voltage range 0(2) VREF+ TA Temperature range -40 85 C 50(3) k RAIN CADC External resistance on VAIN Internal sample and hold capacitor on PF0/1/2/3 fast channels on all other channels on PF0/1/2/3 fast channels 16 pF on all other channels fADC fCONV ADC sampling clock frequency 2.4 V VDDA 3.6 V without zooming 0.320 16 MHz 1.8 V VDDA 2.4 V with zooming 0.320 8 MHz VAIN on PF0/1/2/3 fast channels 1(3)(4) MHz VAIN on all other channels 760(3)(4) kHz 12-bit conversion rate fTRIG External trigger frequency tconv 1/fADC tLAT External trigger latency 3.5 1/fSYSCLK 96/109 Doc ID023337 Rev 2 STM8L052R8 Table 44. Symbol tS Electrical parameters ADC1 characteristics (continued) Parameter Sampling time Conditions Min. Typ. Max. Unit VAIN PF0/1/2/3 fast channels VDDA < 2.4 V 0.43(3)(4) s VAIN PF0/1/2/3 fast channels 2.4 V VDDA 3.6 V 0.22(3)(4) s VAIN on slow channels VDDA < 2.4 V 0.86(3)(4) s VAIN on slow channels 2.4 V VDDA 3.6 V 0.41(3)(4) s 12 + tS 1/fADC 1(3) s tconv 12-bit conversion time tWKUP Wakeup time from OFF state 3 s tIDLE(5) Time before a new conversion s tVREFINT Internal reference voltage startup time refer to Table 43 ms 16 MHz 1. The current consumption through VREF is composed of two parameters: - one constant (max 300 A) - one variable (max 400 A), only during sampling time + 2 first conversion pulses. So, peak consumption is 300+400 = 700 A and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 A at 1Msps 2. VREF- must be tied to ground. 3. Minimum sampling and conversion time is reached for maximum RAIN= 0.5 k.. 4. Value obtained for continuous conversion on fast channel. 5. The time between 2 conversions, or between ADC ON and the first conversion must be lower than tIDLE. Doc ID023337 Rev 2 97/109 Electrical parameters STM8L052R8 In the following three tables, data are guaranteed by characterization result, not tested in production. Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V Symbol Parameter Conditions Typ. Max. 1 1.6 Differential non linearity fADC = 8 MHz 1 1.6 fADC = 4 MHz 1 1.5 fADC = 16 MHz 1.2 2 fADC = 8 MHz 1.2 1.8 fADC = 4 MHz 1.2 1.7 fADC = 16 MHz 2.2 3.0 fADC = 8 MHz 1.8 2.5 fADC = 4 MHz 1.8 2.3 fADC = 16 MHz 1.5 2 fADC = 8 MHz 1 1.5 fADC = 4 MHz 0.7 1.2 fADC = 16 MHz DNL INL Integral non linearity TUE Total unadjusted error Offset Offset error Unit LSB LSB fADC = 16 MHz Gain Gain error fADC = 8 MHz 1 1.5 fADC = 4 MHz Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V Symbol Table 47. Parameter Max. Unit 1 2 LSB 1.7 3 LSB DNL Differential non linearity INL Integral non linearity TUE Total unadjusted error 2 4 LSB Offset Offset error 1 2 LSB Gain Gain error 1.5 3 LSB Typ. Max. Unit ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V Symbol 98/109 Typ. Parameter DNL Differential non linearity 1 2 LSB INL Integral non linearity 2 3 LSB TUE Total unadjusted error 3 5 LSB Offset Offset error 2 3 LSB Gain Gain error 2 3 LSB Doc ID023337 Rev 2 STM8L052R8 Electrical parameters Figure 37. ADC1 accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET 7 (1) 6 5 4 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (3) EO EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA ai14395b Figure 38. Typical connection diagram using the ADC STM8L05xxx VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC AINx VAIN Cparasitic VT 0.6 V IL50 nA 12-bit converter CADC(1) ai17090e 1. Refer to Table 44 for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 39 or Figure 40, depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF capacitors should be used. They should be placed as close as possible to the chip. Doc ID023337 Rev 2 99/109 Electrical parameters STM8L052R8 Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA) STM8L V REF+ External reference 1 F // 10 nF Supply V DDA 1 F // 10 nF V SSA/V REF- ai17031b Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA) STM8L VREF+/VDDA Supply 1 F // 10 nF VREF-/VSSA ai17032b 100/109 Doc ID023337 Rev 2 STM8L052R8 8.3.12 Electrical parameters EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 48. EMS data Symbol Parameter Conditions VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 C, fCPU= 16 MHz, conforms to IEC 61000 VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 C, Using HSI fCPU = 16 MHz, conforms to IEC 61000 Using HSE Level/ Class 2B 4A 2B Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm IEC61967-2 which specifies the board and the loading of each pin. Doc ID023337 Rev 2 101/109 Electrical parameters STM8L052R8 Table 49. EMI data (1) Symbol Parameter SEMI VDD = 3.6 V, TA = +25 C, LQFP80 conforming to IEC61967-2 Peak level Monitored frequency band Conditions Max vs. Unit 16 MHz 0.1 MHz to 30 MHz 10 30 MHz to 130 MHz 4 130 MHz to 1 GHz 1 SAE EMI Level dBV 1.5 - 1. Not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and charge device model. This test conforms to the JESD22-A114A/A115A standard. Table 50. ESD absolute maximum ratings Symbol Ratings Conditions VESD(HBM) Electrostatic discharge voltage (human body model) VESD(CDM) Electrostatic discharge voltage (charge device model) Maximum value (1) Unit 2000 TA = +25 C V 750 1. Data based on characterization results, not tested in production. Static latch-up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 51. Electrical sensitivities Symbol LU 102/109 Parameter Static latch-up class Doc ID023337 Rev 2 Class II STM8L052R8 8.4 Electrical parameters Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 58. The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x JA) Where: TAmax is the maximum ambient temperature in C JA is the package junction-to-ambient thermal resistance in C/W PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins Where: PI/Omax = (VOL*IOL) + ((VDD-VOH)*I OH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Table 52. Symbol JA Thermal characteristics(1) Parameter Thermal resistance junction-ambient LQFP 64- 10 x 10 mm Value Unit 48 C/W 1. Thermal resistance is based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. Doc ID023337 Rev 2 103/109 Package characteristics STM8L052R8 9 Package characteristics 9.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 104/109 Doc ID023337 Rev 2 STM8L052R8 Package characteristics Figure 41. LQFP64 - 10 x 10 mm, 64 pin low-profile quad flat package outline D ccc $ D1 " " D3 33 48 32 49 b L1 E3 E1 E L A1 64 17 Pin 1 D 16 1 MS19157V1 1. Drawing is not to scale. Table 53. LQFP64 - 10 x 10 mm, 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID023337 Rev 2 105/109 Package characteristics STM8L052R8 Figure 42. Recommended footprint 48 33 0.3 49 12.7 32 0.5 10.3 10.3 64 17 1.2 1 16 7.8 12.7 ai14909 1. Dimensions are in millimeters. 106/109 Doc ID023337 Rev 2 STM8L052R8 10 Ordering information scheme Ordering information scheme Figure 43. Ordering information scheme Example: STM8 L 052 R 8 T 6 Device family STM8 microcontroller Product type L = Low power Device subfamily 052: Devices with LCD Pin count R = 64 pins Program memory size 8 = 64 Kbytes of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, -40 to 85 C For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. Doc ID023337 Rev 2 107/109 Revision history 11 STM8L052R8 Revision history Table 54. 108/109 Document revision history Date Revision Changes 22-Jun-2012 1 Initial release. 27-May-2013 2 Modified 12-bit ADC up to 1 Msps/27 channels, Table 1: High density value line STM8L05xxx low power device features and peripheral counts and Section 3.9: Analog-to-digital converter. Doc ID023337 Rev 2 STM8L052R8 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT AUTHORIZED FOR USE IN WEAPONS. NOR ARE ST PRODUCTS DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER'S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR "AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL" INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID023337 Rev 2 109/109 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: STMicroelectronics: STM8L052R8T6