-15
-10
-5
5
15
35
GAIN (dB)
10k 100k 1M 10M 100M
FREQUENCY (Hz)
20
25
30
1G
ACL = 10
ACL = 5
ACL = 1
ACL = 2
10
0
FREQUENCY (Hz)
1
10
100
INPUT VOLTAGE NOISE (nV/
Hz)
100 1k 10M1M10k 100k
LMH6654, LMH6655
www.ti.com
SNOS956D –JUNE 2001–REVISED MARCH 2013
LMH6654/LMH6655 Single/Dual Low Power, 250 MHz, Low Noise Amplifiers
Check for Samples: LMH6654,LMH6655
1FEATURES DESCRIPTION
The LMH6654/LMH6655 single and dual high speed,
23• (VS= ±5V, TJ= 25°C, Typical Values Unless voltage feedback amplifiers are designed to have
Specified). unity-gain stable operation with a bandwidth of 250
• Voltage Feedback Architecture MHz. They operate from ±2.5V to ±6V and each
• Unity Gain Bandwidth 250 MHz channel consumes only 4.5 mA. The amplifiers
feature very low voltage noise and wide output swing
• Supply Voltage Range ±2.5V to ±6V to maximize signal-to-noise ratio.
• Slew Rate 200 V/µsec The LMH6654/LMH6655 have a true single supply
• Supply Current 4.5 mA/channel capability with input common mode voltage range
• Input Common Mode Voltage −5.15V to +3.7V extending 150 mV below negative rail and within 1.3V
• Output Voltage Swing (RL= 100Ω)−3.6V to of the positive rail.
3.4V LMH6654/LMH6655 high speed and low power
• Input Voltage Noise 4.5 nV/√Hz combination make these products an ideal choice for
many portable, high speed application where power is
• Input Current Noise 1.7 pA/√Hz at a premium.
• Settling Time to 0.01% 25 ns The LMH6654 is packaged in 5-Pin SOT-23 and 8-
Pin SOIC. The LMH6655 is packaged in 8-Pin
APPLICATIONS VSSOP (DGK) and 8-Pin SOIC.
• ADC Drivers The LMH6654/LMH6655 are built on TI’s Advance
• Consumer Video VIP10™ (Vertically Integrated PNP) complementary
• Active Filters bipolar process.
• Pulse Delay Circuits _
• xDSL Receiver _
• Pre-amps _
Typical Performance Characteristics
_
Input Voltage Noise vs. Frequency Closed Loop Gain vs. Frequency
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2VIP10 is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2001–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMH6654, LMH6655
SNOS956D –JUNE 2001–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
ESD Tolerance (2)
Human Body Model 2 kV
Machine Model 200V
VIN Differential ±1.2V
Output Short Circuit Duration (3)
Supply Voltage (V+−V−) 13.2V
Voltage at Input pins V++0.5V, V−−0.5V
Storage Temperature Range −65°C to +150°C
Junction Temperature (4) +150°C
Soldering Information
Infrared or Convection (20 sec.) 235°C
Wave Soldering (10 sec.) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Table.
(2) Human body model, 1.5 kΩin series with 100 pF. Machine model: 0Ωin series with 100 pF.
(3) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
(4) The maximum power dissipation is a function of TJ(MAX),θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) −TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
Operating Ratings (1)
Supply Voltage (V+- V−) ±2.5V to ±6.0V
Junction Temperature Range −40°C to +85°C
Thermal Resistance (θJA)
8-Pin SOIC 172°C/W
8-Pin VSSOP (DGK) 235°C/W
5-Pin SOT-23 265°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Table.
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SNOS956D –JUNE 2001–REVISED MARCH 2013
±5V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= +5V, V−=−5V, VCM = 0V, AV= +1, RF= 25Ωfor gain = +1,
RF= 402Ωfor gain = ≥+2, and RL= 100Ω.Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
Dynamic Performance
AV= +1 250
AV= +2 130
fCL Close Loop Bandwidth MHz
AV= +5 52
AV= +10 26
Gain Bandwidth Product AV≥+5 260 MHz
GBWP Bandwidth for 0.1 dB Flatness AV+1 18 MHz
φm Phase Margin 50 deg
SR Slew Rate (3) AV= +1, VIN = 2 VPP 200 V/µs
Settling Time 25 ns
0.01%
tSAV= +1, 2V Step
0.1% 15 ns
trRise Time AV= +1, 0.2V Step 1.4 ns
tfFall Time AV= +1, 0.2V Step 1.2 ns
Distortion and Noise Response
enInput Referred Voltage Noise f ≥0.1 MHz 4.5 nV/√Hz
inInput-Referred Current Noise f ≥0.1 MHz 1.7 pA/√Hz
Second Harmonic Distortion AV= +1, f = 5 MHz −80 dBc
Third Harmonic Distortion VO= 2 VPP, RL= 100Ω −85
Input Referred, 5 MHz, −80 dB
XtCrosstalk (for LMH6655 only) Channel-to-Channel
DG Differential Gain AV= +2, NTSC, RL= 150Ω0.01 %
DP Differential Phase AV= +2, NTSC, RL= 150Ω0.025 deg
Input Characteristics
−3 ±1 3
VOS Input Offset Voltage VCM = 0V mV
−4 4
TC VOS Input Offset Average Drift VCM = 0V (4) 6 µV/°C
5 12
IBInput Bias Current VCM = 0V µA
18
−1 0.3 1
IOS Input Offset Current VCM = 0V µA
−2 2
Common Mode 4 MΩ
RIN Input Resistance Differential Mode 20 kΩ
Common Mode 1.8
CIN Input Capacitance pF
Differential Mode 1
Input Referred, 70 90
CMRR Common Mode Rejection Ration dB
VCM = 0V to −5V 68
−5.15 −5.0
CMVR Input Common- Mode Voltage Range CMRR ≥50 dB V
3.5 3.7
Transfer Characteristics
VO= 4 VPP, RL= 100Ω60 67
AVOL Large Signal Voltage Gain dB
58
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
(4) Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
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SNOS956D –JUNE 2001–REVISED MARCH 2013
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= +5V, V−=−5V, VCM = 0V, AV= +1, RF= 25Ωfor gain = +1,
RF= 402Ωfor gain = ≥+2, and RL= 100Ω.Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
Output Characteristics
3.4 3.6
Output Swing High No Load 3.2
−3.9 −3.7
VOOutput Swing Low No Load V
−3.5
3.2 3.4
Output Swing High RL= 100Ω3.0
−3.6 −3.4
Output Swing Low RL= 100Ω−3.2
Sourcing, VO= 0V 145 280
ΔVIN = 200 mV 130
ISC Short Circuit Current (5) mA
Sinking, VO= 0V 100 185
ΔVIN = 200 mV 80
Sourcing, VO= +3V 80
IOUT Output Current mA
Sinking, VO=−3V 120
ROOutput Resistance AV= +1, f <100 kHz 0.08 Ω
Power Supply
Input Referred, 60 76 dB
PSRR Power Supply Rejection Ratio VS= ±5V to ±6V 4.5 6
ISSupply Current (per channel) mA
7
(5) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
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SNOS956D –JUNE 2001–REVISED MARCH 2013
5V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= +5V, V−=−0V, VCM = 2.5V, AV= +1, RF= 25Ωfor gain = +1,
RF= 402Ωfor gain = ≥+2, and RL= 100Ωto V+/2. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
Dynamic Performance
AV= +1 230
AV= +2 120
fCL Close Loop Bandwidth MHz
AV= +5 50
AV= +10 25
GBWP Gain Bandwidth Product AV≥+5 250 MHz
Bandwidth for 0.1 dB Flatness AV= +1 17 MHz
φm Phase Margin 48 deg
SR Slew Rate (3) AV= +1, VIN = 2 VPP 190 V/µs
Settling Time 30 ns
0.01%
tSAV= +1, 2V Step
0.1% 20 ns
trRise Time AV= +1, 0.2V Step 1.5 ns
tfFall Time AV= +1, 0.2V Step 1.35 ns
Distortion and Noise Response
enInput Referred Voltage Noise f ≥0.1 MHz 4.5 nV/√Hz
inInput Referred Current Noise f ≥0.1 MHz 1.7 pA/√Hz
Second Harmonic Distortion AV= +1, f = 5 MHz −65 dBc
Third Harmonic Distortion VO= 2 VPP, RL= 100Ω −70
XtCrosstalk (for LMH6655 only) Input Referred, 5 MHz −78 dB
Input Characteristics
−5 ±2 5
VOS Input Offset Voltage VCM = 2.5V mV
−6.5 6.5
TC VOS Input Offset Average Drift VCM = 2.5V (4) 6µV/°C
6 12
IBInput Bias Current VCM = 2.5V µA
18
−2 0.5 2
IOS Input Offset Current VCM = 2.5V µA
−3 3
Common Mode 4 MΩ
RIN Input Resistance Differential Mode 20 kΩ
Common Mode 1.8
CIN Input Capacitance pF
Differential Mode 1
Input Referred, 70 90
CMRR Common Mode Rejection Ration dB
VCM = 0V to −2.5V 68
CMRR ≥50 dB −0.15 0
CMVR Input Common Mode Voltage Range V
3.5 3.7
Transfer Characteristics
VO= 1.6 VPP, RL= 100Ω58 64
AVOL Large Signal Voltage Gain dB
55
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
(4) Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
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OUT B
1
2
3
4 5
6
7
8
OUT A
-IN A
+IN A
V-
V+
-IN B
+IN B
-+
+-
A
B
V+
1
2
3
4 5
6
7
8
N/C
-IN
+IN
V-
OUTPUT
N/C
N/C
+
-
OUTPUT
V-
+IN
V+
-IN
+-
1
2
3
5
4
LMH6654, LMH6655
SNOS956D –JUNE 2001–REVISED MARCH 2013
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= +5V, V−=−0V, VCM = 2.5V, AV= +1, RF= 25Ωfor gain = +1,
RF= 402Ωfor gain = ≥+2, and RL= 100Ωto V+/2. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
Output Characteristics
3.6 3.75
Output Swing High No Load 3.4
0.9 1.1
VOOutput Swing Low No Load V
1.3
3.5 3.70
Output Swing High RL= 100Ω3.35
1 1.3
Output Swing Low RL= 100Ω1.45
Sourcing , VO= 2.5V 90 170
ΔVIN = 200 mV 80
ISC Short Circuit Current (5) mA
Sinking, VO= 2.5V 70 140
ΔVIN = 200 mV 60
Sourcing, VO= +3.5V 30
IOUT Output Current mA
Sinking, VO= 1.5V 60
ROOutput Resistance AV= +1, f <100 kHz .08 Ω
Power Supply
Input Referred , 60 75 dB
PSRR Power Supply Rejection Ratio VS= ± 2.5V to ± 3V 4.5 6
ISSupply Current (per channel) mA
7
(5) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
at 150°C.
Connection Diagram
_
_
Figure 1. 8-Pin SOIC (LMH6654) Figure 2. 5-Pin SOT-23 Figure 3. 8-Pin SOIC and VSSOP
Top View (LMH6654) Top View (DGK) (LMH6655) Top View
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45 6 7 8 9 10 11 12
SUPPLY VOLTAGE (V)
4.1
4.3
4.4
4.5
4.6
4.7
5
SUPPLY CURRENT (mA)
85°C
-40°C
25°C
4.8
4.2
4.9
-60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
SUPPLY CURRENT (mA)
VS = ±5V
VS = 5V
1M 10M 100M 1G
FREQUENCY (Hz)
-25
-20
-15
-10
-5
0
5
10
15
20
25
GAIN (dB)
VS = ±5V
VS = ±2.5V
1M 10M 100M 1G
FREQUENCY (Hz)
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
GAIN (dB)
VS = ±2.5V
VS = ±5V
1M 10M 100M 1G
FREQUENCY (Hz)
-21
-18
-15
-12
-9
-6
-3
0
3
6
9
GAIN (dB)
VS = ±2.5V
VS = ±5V
LMH6654, LMH6655
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SNOS956D –JUNE 2001–REVISED MARCH 2013
Typical Performance Characteristics
TJ= 25°C, V+= ±5V, V−=−5, RF= 25Ωfor gain = +1, RF= 402Ωand for gain ≥+2, and RL= 100Ω, unless otherwise
specified.
Closed Loop Bandwidth (G = +1) Closed Loop Bandwidth (G = +2)
Figure 4. Figure 5.
Closed Loop Bandwidth (G = +5) Closed Loop Bandwidth (G = +10)
Figure 6. Figure 7.
Supply Current per Channel Supply Current per Channel
vs. vs.
Supply Voltage Temperature
Figure 8. Figure 9.
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00.5 1 1.5 2 2.5 3 3.5
VCM (V)
-1
0
1
2
3
4
5
6
7
POSITIVE IBIAS (µA)
-40°C
25°C
85°C
VS = 5V
0 0.5 1 1.5 2 2.5 3 3.5
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
VOS (mV)
VCM (V)
VS = ±2.5V
-40°C
85°C
25°C
-50 0 50 100
0
1
2
3
4
5
6
7
INPUT BIAS CURRENT (µA)
TEMPERATURE (°C)
IBIAS
VOS
OFFSET VOLTAGE (mV)
45 6 7 8 9 10 11 12
VSUPPLY (V)
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
VOS (mV)
85°C
-40°C
25°C
01 2 3 4 5 6 7 8
VCM (V)
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
VOS (mV)
VS = ±5V -40°C
85°C
25°C
LMH6654, LMH6655
SNOS956D –JUNE 2001–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
TJ= 25°C, V+= ±5V, V−=−5, RF= 25Ωfor gain = +1, RF= 402Ωand for gain ≥+2, and RL= 100Ω, unless otherwise
specified. Offset Voltage Offset Voltage
vs. vs.
Supply Voltage (VCM = 0V) Common Mode
Figure 10. Figure 11.
Offset Voltage Bias Current and Offset Voltage
vs. vs.
Common Mode Temperature
Figure 12. Figure 13.
Bias Current Bias Current
vs. vs.
Common Mode Voltage Common Mode Voltage
Figure 14. Figure 15.
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OUTPUT INPUT
(1 V/div)
TIME (12.5 ns/div)
OUTPUT INPUT
(100 mV/div)
TIME (12.5 ns/div)
OUTPUT INPUT
(1 V/div)
TIME (12.5 ns/div)
OUTPUT INPUT
TIME (12.5 ns/div)
(1 V/div)
-50 0 50 100
60
70
80
90
100
110
120
AoL, PSRR, AND CMRR (dB)
TEMPERATURE (°C)
CMRR
PSRR
AoL @ ±5V
AoL @ 5V
OUTPUT
TIME (12.5 ns/div)
INPUT
(1 V/div)
LMH6654, LMH6655
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SNOS956D –JUNE 2001–REVISED MARCH 2013
Typical Performance Characteristics (continued)
TJ= 25°C, V+= ±5V, V−=−5, RF= 25Ωfor gain = +1, RF= 402Ωand for gain ≥+2, and RL= 100Ω, unless otherwise
specified.
AOL, PSRR and CMRR
vs.
Temperature Inverting Large Signal Pulse Response (VS= 5V)
Figure 16. Figure 17.
Inverting Large Signal Pulse Response (VS= ±5V) Non-Inverting Large Signal Pulse Response (VS= 5V)
Figure 18. Figure 19.
Non-Inverting Large Signal Pulse Response (VS= ±5V) Non-Inverting Small Signal Pulse Response (VS= 5V)
Figure 20. Figure 21.
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0.1 1 10 100
FREQUENCY (MHz)
-110
-100
-90
-80
-70
-60
-50
-40
-30
HARMONIC DISTORTION (dBc)
3RD
2ND
1k 10k 1M 10M
FREQUENCY (Hz)
1
10
100
100k
100 1
10
100
INPUT VOLTAGE NOISE (nV/
Hz)
INPUT CURRENT NOISE (pA/
Hz)
en
in
OUTPUT
TIME (12.5 ns/div)
INPUT
(100 mV/div)
1k 10k 1M 10M
FREQUENCY (Hz)
1
10
100
100k
100 1
10
100
INPUT VOLTAGE NOISE (nV/
Hz)
INPUT CURRENT NOISE (pA/
Hz)
en
in
OUTPUT
TIME (12.5 ns/div)
INPUT
(100 mV/div)
OUTPUT INPUT
(100 mV/div)
TIME (12.5 ns/div)
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SNOS956D –JUNE 2001–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
TJ= 25°C, V+= ±5V, V−=−5, RF= 25Ωfor gain = +1, RF= 402Ωand for gain ≥+2, and RL= 100Ω, unless otherwise
specified.
Non-Inverting Small Signal Pulse Response (VS= ±5V) Inverting Small Signal Pulse Response (VS= 5V)
Figure 22. Figure 23.
Input Voltage and Current Noise
vs.
Inverting Small Signal Pulse Response (VS= ±5V) Frequency (VS= 5V)
Figure 24. Figure 25.
Input Voltage and Current Noise Harmonic Distortion
vs. vs.
Frequency Frequency
(VS= ±5V) G = +1, VO= 2 VPP, VS= 5V
Figure 26. Figure 27.
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1 2 3 4 5 6 7 8 9 10
-45
HARMONIC DISTORTION (dBc)
GAIN (V/V)
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
2ND
3RD
0.0 0.5 1.0 1.5 2.0 2.5
-100
-90
-80
-70
-60
-50
-40
-30
HARMONIC DISTORTION (dBc)
OUTPUT SWING (VPP)
2ND
3RD
-60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
-100
-95
-90
-85
-80
-75
-70
-65
-60
HARMONIC DISTORTION (dBc)
2ND
3RD
1 2 3 4 5 6 7 8 9 10
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
HARMONIC DISTORTION (dBc)
GAIN (V/V)
2ND
3RD
0.1 1 10 100
FREQUENCY (MHz)
-110
-100
-90
-80
-70
-60
-50
-40
-30
HARMONIC DISTORTION (dBc)
3RD
2ND
-60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
-100
-95
-90
-85
-80
-75
-70
-65
-60
HARMONIC DISTORTION (dBc)
2ND
3RD
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SNOS956D –JUNE 2001–REVISED MARCH 2013
Typical Performance Characteristics (continued)
TJ= 25°C, V+= ±5V, V−=−5, RF= 25Ωfor gain = +1, RF= 402Ωand for gain ≥+2, and RL= 100Ω, unless otherwise
specified. Harmonic Distortion Harmonic Distortion
vs. vs.
Frequency Temperature
G = +1, VO= 2 VPP, VS= ±5V VS= 5V, f = 5 MHz, VO= 2 VPP
Figure 28. Figure 29.
Harmonic Distortion Harmonic Distortion
vs. vs.
Temperature Gain
VS= ±5V, f = 5 MHz, VO= 2 VPP VS= 5V, f = 5 MHz, VO= 2 VPP
Figure 30. Figure 31.
Harmonic Distortion Harmonic Distortion
vs. vs.
Gain Output Swing
VS= ±5V, f = 5 MHz, VO= 2 VPP (G = +2, VS= 5V, f = 5 MHz)
Figure 32. Figure 33.
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0
1
2
5
VOUT REFERENCED TO V+ (V)
.01 0.1 1 10 100
3
4
1
k
VS = ±5V
OUTPUT SOURCING CURRENT (mA)
VS = 5V
100k 1M 10M 100M
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
CROSSTALK REJECTION (dB)
FREQUENCY (Hz)
VS = 5V
0
1
2
5
VOUT REFERENCED TO V- (V)
.01 0.1 1 10 100
OUTPUT SINKING CURRENT (mA)
3
4
1
k
VS = 5V
VS = ±5V
10 1k 100k 10M
FREQUENCY
0
40
80
120
CMRR (dB)
1M
10k
100
100
60
20
VS = ±5V
0 1 2 3 4 5 6 7 8
-100
-30
HARMONIC DISTORTION (dBc)
OUTPUT SWING (VPP)
-90
-80
-70
-60
-50
-40
2ND
3RD
PSRR (dB)
90
10 1k 100k 10M
FREQUENCY (Hz)
0
20
60
1M10k
100
80
70
50
30
10
40
100 NEGATIVE
POSITIVE
LMH6654, LMH6655
SNOS956D –JUNE 2001–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
TJ= 25°C, V+= ±5V, V−=−5, RF= 25Ωfor gain = +1, RF= 402Ωand for gain ≥+2, and RL= 100Ω, unless otherwise
specified. Harmonic Distortion
vs. PSRR
Output Swing vs.
(G = +2, VS= ±5V, f = 5 MHz) Frequency
Figure 34. Figure 35.
CMRR
vs.
Frequency Output Sinking Current
Figure 36. Figure 37.
CrossTalk
vs.
Output Sourcing Current Frequency (LMH6655 only)
Figure 38. Figure 39.
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Product Folder Links: LMH6654 LMH6655
1k 100k 10M 500M
FREQUENCY (Hz)
-20
20
60
100
GAIN (dB)
100M1M
10k
90
70
40
30
-10
80
10
0
50
PHASE
GAIN
180
144
108
72
36
0
-36
-72
-108
-144
-180
PHASE (°)
0 10 20 30 40 50 60 70 80 90 100
0
10
20
30
40
50
60
70
80
90
100
ISOLATION RESISTANCE, RISO (:)
CAPACITIVE LOAD, CL (pF)
RISO
25:
CL
-
+1 k:
×
100k 1M 10M 100M
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
CROSSTALK REJECTION (dB)
FREQUENCY (Hz)
VS = ±5V
LMH6654, LMH6655
www.ti.com
SNOS956D –JUNE 2001–REVISED MARCH 2013
Typical Performance Characteristics (continued)
TJ= 25°C, V+= ±5V, V−=−5, RF= 25Ωfor gain = +1, RF= 402Ωand for gain ≥+2, and RL= 100Ω, unless otherwise
specified. CrossTalk Isolation Resistance
vs. vs.
Frequency (LMH6655 only) Capacitive Load
Figure 40. Figure 41.
Open Loop Gain and Phase
vs.
Frequency
Figure 42.
APPLICATION INFORMATION
GENERAL INFORMATION
The LMH6654 single and LMH6655 dual high speed, voltage feedback amplifiers are manufactured on TI’s new
VIP10™ (Vertically Integrated PNP) complementary bipolar process. These amplifiers can operate from ±2.5V to
±6V power supply. They offer low supply current, wide bandwidth, very low voltage noise and large output swing.
Many of the typical performance plots found in the datasheet can be reproduced if 50Ωcoax and 50ΩRIN/ROUT
resistors are used.
CIRCUIT LAYOUT CONSIDERATION
With all high frequency devices, board layouts with stray capacitance have a strong influence on the AC
performance. The LMH6654/LMH6655 are not exception and the inverting input and output pins are particularly
sensitive to the coupling of parasitic capacitance to AC ground. Parasitic capacitances on the inverting input and
output nodes to ground could cause frequency response peaking and possible circuit oscillation. Therefore, the
power supply, ground traces and ground plan should be placed away from the inverting input and output pins.
Also, it is very important to keep the parasitic capacitance across the feedback to an absolute minimum.
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH6654 LMH6655
V+10 µF
0.1 µF
0.1 µF
10 µF
V-
+
+
LMH6654, LMH6655
SNOS956D –JUNE 2001–REVISED MARCH 2013
www.ti.com
The PCB should have a ground plane covering all unused portion of the component side of the board to provide
a low impedance path. All trace lengths should be minimized to reduce series inductance.
Supply bypassing is required for the amplifiers performance. The bypass capacitors provide a low impedance
return current path at the supply pins. They also provide high frequency filtering on the power supply traces. It is
recommended that a ceramic decoupling capacitor 0.1 µF chip should be placed with one end connected to the
ground plane and the other side as close as possible to the power pins. An additional 10 µF tantalum electrolytic
capacitor should be connected in parallel, to supply current for fast large signal changes at the output.
Figure 43. Supply Bypass Capacitors
EVALUATION BOARDS
TI provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing
and characterization.
Device Package Evalulation Board PN
LMH6654MF 5-Pin SOT-23 LMH730216
LMH6654MA 8-Pin SOIC LMH730227
LMH6655MA 8-Pin SOIC LMH730036
LMH6655MM 8-Pin VSSOP (DGK) LMH730123
Components Needed to Evaluate the LMH6654 on the LMH730227 Evaluation Board:
• RfRguse the datasheet to select values.
• RIN, ROUT typically 50Ω(Refer to the Basic Operation section of the evaluation board datasheet for details)
• Rfis an optional resistor for inverting again configurations (select Rfto yield desired input impedance = Rg||Rf)
• C1, C2use 0.1 µF ceramic capacitors
• C3, C4use 10 µF tantalum capacitors
Components not used:
1. C5, C6, C7, C8
2. R1 thru R8
The evaluation boards are designed to accommodate dual supplies. The board can be modified to provide single
operation. For best performance;
1) do not connect the unused supply.
2) ground the unused supply pin.
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Product Folder Links: LMH6654 LMH6655
-
+
25:
VIN
RISO VOUT
F = 1
2 S RISO CLOAD
LMH6654, LMH6655
www.ti.com
SNOS956D –JUNE 2001–REVISED MARCH 2013
POWER DISSIPATION
The package power dissipation should be taken into account when operating at high ambient temperature and/or
high power dissipative conditions. In determining maximum operable temperature of the device, make sure the
total power dissipation of the device is considered; this power dissipated in the device with a load connected to
the output as well as the nominal dissipation of the op amp.
DRIVING CAPACITIVE LOADS
Capacitive loads decrease the phase margin of all op amps. The output impedance of a feedback amplifier
becomes inductive at high frequencies, creating a resonant circuit when the load is capacitive. This can lead to
overshoot, ringing and oscillation. To eliminate oscillation or reduce ringing, an isolation resistor can be placed as
shown in Figure 44 below. At frequencies above
(1)
the load impedance of the Amplifier approaches RISO. The desired performance depends on the value of the
isolation resistor. The isolation resistance vs. capacitance load graph in the typical performance characteristics
provides the means for selection of the value of RSthat provides ≤3 dB peaking in closed loop AV= 1 response.
In general, the bigger the isolation resistor, the more damped the pulse response becomes. For initial evaluation,
a 50Ωisolation resistor is recommended.
Figure 44. Isolation Resistor Placement
COMPONENTS SELECTION AND FEEDBACK RESISTOR
It is important in high-speed applications to keep all component leads short since wires are inductive at high
frequency. For discrete components, choose carbon composition axially leaded resistors and micro type
capacitors. Surface mount components are preferred over discrete components for minimum inductive effect.
Never use wire wound type resistors in high frequency applications.
Large values of feedback resistors can couple with parasitic capacitance and cause undesired effects such as
ringing or oscillation in high-speed amplifiers. Keep resistors as low as possible consistent with output loading
consideration. For a gain of 2 and higher, 402Ωfeedback resistor used for the typical performance plots gives
optimal performance. For unity gain follower, a 25Ωfeedback resistor is recommended rather than a direct short.
This effectively reduces the Q of what would otherwise be a parasitic inductance (the feedback wire) into the
parasitic capacitance at the inverting input.
BIAS CURRENT CANCELLATION
In order to cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain
setting Rgand feedback Rfresistors should equal the equivalent source resistance Rseq as defined in Figure 45.
Combining this constraint with the non-inverting gain equation, allows both Rfand Rgto be determined explicitly
from the following equations:
Rf= AVRseq and Rg= Rf/(AV−1) (2)
For inverting configuration, bias current cancellation is accomplished by placing a resistor Rbon the non-inverting
input equal in value to the resistance seen by the inverting input (Rf//(Rg+Rs). The additional noise contribution of
Rbcan be minimized through the use of a shunt capacitor.
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMH6654 LMH6655
et = 4kTR
LMH6654, LMH6655
SNOS956D –JUNE 2001–REVISED MARCH 2013
www.ti.com
Figure 45. Non-Inverting Amplifier Configuration
Figure 46. Inverting Amplifier Configuration
TOTAL INPUT NOISE VS. SOURCE RESISTANCE
The noise model for the non-inverting amplifier configuration showing all noise sources is described in Figure 47.
In addition to the intrinsic input voltage noise (en) and current noise (in= in+ = in−) sources, there also exits
thermal voltage noise associated with each of the external resistors. Equation 3 provides the general
form for total equivalent input voltage noise density (eni). Equation 4 is a simplification of Equation 3 that
assumes Rf|| Rg= Rseq for bias current cancellation. Figure 48 illustrates the equivalent noise model using this
assumption. The total equivalent output voltage noise (eno) is eni * AV.
16 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: LMH6654 LMH6655
4kTRSeq
en
2+ in
2(RSeq + (Rf|| Rg))2+ 4KTRSeq + 4kt (Rf|| Rg)
NF = 10LOG Si/Ni
So/No= 10LOG eni2
et2
eni =en
2+ 2 (in· RSeq)2+ 4kT (2RSeq)
eni =en
2+ (in+ · RSeq)2+ 4kTRSeq + (in- · (Rf|| Rg))2+ 4kT(Rf|| Rg)
LMH6654, LMH6655
www.ti.com
SNOS956D –JUNE 2001–REVISED MARCH 2013
Figure 47. Non-Inverting Amplifier Noise Model
(3)
Figure 48. Noise Model with Rf|| Rg= Rseq
(4)
If bias current cancellation is not a requirement, then Rf|| Rgdoes not need to equal Rseq. In this case, according
to Equation 3, Rfand Rgshould be as low as possible in order to minimize noise. Results similar to Equation 3
are obtained for the inverting configuration on Figure 46 if Rseq is replaced by Rb|| Rgis replaced by Rg+ Rs.
With these substitutions, Equation 3 will yield an eni referred to the non-inverting input. Referring eni to the
inverting input is easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains.
Noise Figure
Noise Figure (NF) is a measure of the noise degradation caused by an amplifier.
(5)
The noise figure formula is shown in Equation 5. The addition of a terminating resistor RT, reduces the external
thermal noise but increases the resulting NF.
The NF is increased because the RTreduces the input signal amplitude thus reducing the input SNR.
(6)
The noise figure is related to the equivalent source resistance (Rseq) and the parallel combination of Rfand Rg.
To minimize noise figure, the following steps are recommended:
1. Minimize Rf||Rg
2. Choose the Optimum Rs(ROPT)
ROPT is the point at which the NF curve reaches a minimum and is approximated by:
ROPT ≈(en/in)
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMH6654 LMH6655
LMH6654, LMH6655
SNOS956D –JUNE 2001–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 17
18 Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: LMH6654 LMH6655
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6654MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
54MA
LMH6654MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
54MA
LMH6654MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A66A
LMH6654MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A66A
LMH6654MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A66A
LMH6655MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMH66
55MA
LMH6655MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
55MA
LMH6655MAX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMH66
55MA
LMH6655MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
55MA
LMH6655MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A67A
LMH6655MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A67A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6654MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6654MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6654MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6654MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6655MAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6655MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6654MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6654MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6654MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6654MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMH6655MAX SOIC D 8 2500 367.0 367.0 35.0
LMH6655MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
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