LMH6654, LMH6655 www.ti.com SNOS956D - JUNE 2001 - REVISED MARCH 2013 LMH6654/LMH6655 Single/Dual Low Power, 250 MHz, Low Noise Amplifiers Check for Samples: LMH6654, LMH6655 FEATURES DESCRIPTION * The LMH6654/LMH6655 single and dual high speed, voltage feedback amplifiers are designed to have unity-gain stable operation with a bandwidth of 250 MHz. They operate from 2.5V to 6V and each channel consumes only 4.5 mA. The amplifiers feature very low voltage noise and wide output swing to maximize signal-to-noise ratio. 1 23 * * * * * * * * * * (VS = 5V, TJ = 25C, Typical Values Unless Specified). Voltage Feedback Architecture Unity Gain Bandwidth 250 MHz Supply Voltage Range 2.5V to 6V Slew Rate 200 V/sec Supply Current 4.5 mA/channel Input Common Mode Voltage -5.15V to +3.7V Output Voltage Swing (RL = 100) -3.6V to 3.4V Input Voltage Noise 4.5 nV/Hz Input Current Noise 1.7 pA/Hz Settling Time to 0.01% 25 ns The LMH6654/LMH6655 have a true single supply capability with input common mode voltage range extending 150 mV below negative rail and within 1.3V of the positive rail. LMH6654/LMH6655 high speed and low power combination make these products an ideal choice for many portable, high speed application where power is at a premium. The LMH6654 is packaged in 5-Pin SOT-23 and 8Pin SOIC. The LMH6655 is packaged in 8-Pin VSSOP (DGK) and 8-Pin SOIC. APPLICATIONS * * * * * * ADC Drivers Consumer Video Active Filters Pulse Delay Circuits xDSL Receiver Pre-amps The LMH6654/LMH6655 are built on TI's Advance VIP10TM (Vertically Integrated PNP) complementary bipolar process. _ _ _ Typical Performance Characteristics _ Input Voltage Noise vs. Frequency Closed Loop Gain vs. Frequency 35 30 25 ACL = 10 20 GAIN (dB) INPUT VOLTAGE NOISE (nV/ Hz) 100 10 15 ACL = 5 10 ACL = 2 5 ACL = 1 0 -5 -10 1 100 1k 10k 100k 1M FREQUENCY (Hz) 10M -15 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VIP10 is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2001-2013, Texas Instruments Incorporated LMH6654, LMH6655 SNOS956D - JUNE 2001 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) Human Body Model 2 kV Machine Model 200V VIN Differential 1.2V (3) Output Short Circuit Duration Supply Voltage (V+ - V-) 13.2V + V +0.5V, V -0.5V Voltage at Input pins -65C to +150C Storage Temperature Range Junction Temperature - (4) +150C Soldering Information (1) (2) (3) (4) Infrared or Convection (20 sec.) 235C Wave Soldering (10 sec.) 260C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Table. Human body model, 1.5 k in series with 100 pF. Machine model: 0 in series with 100 pF. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature at 150C. The maximum power dissipation is a function of TJ(MAX), JA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/JA. All numbers apply for packages soldered directly onto a PC board. Operating Ratings + (1) - Supply Voltage (V - V ) 2.5V to 6.0V -40C to +85C Junction Temperature Range Thermal Resistance (JA) (1) 2 8-Pin SOIC 172C/W 8-Pin VSSOP (DGK) 235C/W 5-Pin SOT-23 265C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Table. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 LMH6654, LMH6655 www.ti.com SNOS956D - JUNE 2001 - REVISED MARCH 2013 5V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = +5V, V- = -5V, VCM = 0V, AV = +1, RF = 25 for gain = +1, RF = 402 for gain = +2, and RL = 100. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units Dynamic Performance fCL Close Loop Bandwidth GBWP AV = +1 250 AV = +2 130 AV = +5 52 MHz AV = +10 26 Gain Bandwidth Product AV +5 260 MHz Bandwidth for 0.1 dB Flatness AV +1 18 MHz 50 deg AV = +1, VIN = 2 VPP 200 V/s 25 ns m Phase Margin SR Slew Rate tS Settling Time 0.01% 15 ns tr Rise Time AV = +1, 0.2V Step 1.4 ns tf Fall Time AV = +1, 0.2V Step 1.2 ns (3) AV = +1, 2V Step 0.1% Distortion and Noise Response en Input Referred Voltage Noise f 0.1 MHz 4.5 nV/Hz in Input-Referred Current Noise f 0.1 MHz 1.7 pA/Hz Second Harmonic Distortion AV = +1, f = 5 MHz -80 Third Harmonic Distortion VO = 2 VPP, RL = 100 -85 Xt Crosstalk (for LMH6655 only) Input Referred, 5 MHz, Channel-to-Channel -80 DG Differential Gain AV = +2, NTSC, RL = 150 0.01 % DP Differential Phase AV = +2, NTSC, RL = 150 0.025 deg dBc dB Input Characteristics VOS Input Offset Voltage TC VOS -3 -4 VCM = 0V Input Offset Average Drift VCM = 0V IB Input Bias Current VCM = 0V IOS Input Offset Current VCM = 0V RIN Input Resistance (4) 1 3 4 6 -1 -2 mV V/C 5 12 18 A 0.3 1 2 A Common Mode 4 M Differential Mode 20 k Common Mode 1.8 CIN Input Capacitance CMRR Common Mode Rejection Ration Input Referred, VCM = 0V to -5V CMVR Input Common- Mode Voltage Range CMRR 50 dB Differential Mode pF 1 70 68 90 -5.15 3.5 3.7 60 58 67 dB -5.0 V Transfer Characteristics AVOL (1) (2) (3) (4) VO = 4 VPP, RL = 100 Large Signal Voltage Gain dB All limits are specified by testing or statistical analysis. Typical Values represent the most likely parametric norm. Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step. Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change. Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 Submit Documentation Feedback 3 LMH6654, LMH6655 SNOS956D - JUNE 2001 - REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25C, V+ = +5V, V- = -5V, VCM = 0V, AV = +1, RF = 25 for gain = +1, RF = 402 for gain = +2, and RL = 100. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min Typ 3.4 3.2 3.6 (1) (2) Max Units -3.7 -3.5 V (1) Output Characteristics VO Output Swing High No Load Output Swing Low No Load Output Swing High RL = 100 Output Swing Low RL = 100 ISC Short Circuit Current IOUT Output Current RO Output Resistance (5) -3.9 3.2 3.0 3.4 -3.6 Sourcing, VO = 0V VIN = 200 mV 145 130 280 Sinking, VO = 0V VIN = 200 mV 100 80 185 -3.4 -3.2 mA Sourcing, VO = +3V 80 Sinking, VO = -3V 120 AV = +1, f <100 kHz 0.08 76 dB mA Power Supply PSRR Power Supply Rejection Ratio IS Supply Current (per channel) (5) 4 Input Referred, VS = 5V to 6V 60 4.5 6 7 mA Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature at 150C. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 LMH6654, LMH6655 www.ti.com SNOS956D - JUNE 2001 - REVISED MARCH 2013 5V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = +5V, V- = -0V, VCM = 2.5V, AV = +1, RF = 25 for gain = +1, RF = 402 for gain = +2, and RL = 100 to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units Dynamic Performance AV = +1 230 AV = +2 120 AV = +5 50 fCL Close Loop Bandwidth MHz AV = +10 25 GBWP Gain Bandwidth Product AV +5 250 MHz Bandwidth for 0.1 dB Flatness AV = +1 17 MHz 48 deg AV = +1, VIN = 2 VPP 190 V/s 30 ns m Phase Margin SR Slew Rate tS Settling Time 0.01% 20 ns tr Rise Time AV = +1, 0.2V Step 1.5 ns tf Fall Time AV = +1, 0.2V Step 1.35 ns (3) AV = +1, 2V Step 0.1% Distortion and Noise Response en Input Referred Voltage Noise f 0.1 MHz 4.5 nV/Hz in Input Referred Current Noise f 0.1 MHz 1.7 pA/Hz Second Harmonic Distortion AV = +1, f = 5 MHz -65 Third Harmonic Distortion VO = 2 VPP, RL = 100 -70 Crosstalk (for LMH6655 only) Input Referred, 5 MHz -78 Xt dBc dB Input Characteristics VOS Input Offset Voltage VCM = 2.5V TC VOS Input Offset Average Drift VCM = 2.5V IB Input Bias Current VCM = 2.5V IOS Input Offset Current VCM = 2.5V RIN Input Resistance CIN Input Capacitance CMRR Common Mode Rejection Ration CMVR Input Common Mode Voltage Range -5 -6.5 (4) 2 5 6.5 6 -2 -3 mV V/C 6 12 18 A 0.5 2 3 A Common Mode 4 M Differential Mode 20 k Common Mode 1.8 Differential Mode Input Referred, VCM = 0V to -2.5V pF 1 70 68 CMRR 50 dB 90 -0.15 3.5 3.7 58 55 64 dB 0 V Transfer Characteristics AVOL (1) (2) (3) (4) VO = 1.6 VPP, RL = 100 Large Signal Voltage Gain dB All limits are specified by testing or statistical analysis. Typical Values represent the most likely parametric norm. Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step. Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change. Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 Submit Documentation Feedback 5 LMH6654, LMH6655 SNOS956D - JUNE 2001 - REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25C, V+ = +5V, V- = -0V, VCM = 2.5V, AV = +1, RF = 25 for gain = +1, RF = 402 for gain = +2, and RL = 100 to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min Typ 3.6 3.4 3.75 (1) (2) Max Units 1.1 1.3 V (1) Output Characteristics VO Output Swing High No Load Output Swing Low No Load Output Swing High RL = 100 Output Swing Low RL = 100 ISC Short Circuit Current IOUT Output Current RO Output Resistance (5) 0.9 3.5 3.35 3.70 1 Sourcing , VO = 2.5V VIN = 200 mV 90 80 170 Sinking, VO = 2.5V VIN = 200 mV 70 60 140 1.3 1.45 mA Sourcing, VO = +3.5V 30 Sinking, VO = 1.5V 60 AV = +1, f <100 kHz .08 75 dB mA Power Supply PSRR Power Supply Rejection Ratio IS Supply Current (per channel) (5) Input Referred , VS = 2.5V to 3V 60 4.5 6 7 mA Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature at 150C. Connection Diagram _ _ 1 8 N/C N/C 5 1 OUTPUT V 1 + 8 + V OUT A A -IN 2 - 7 + V 2 V +IN 3 + 6 - - + 7 -IN A 2 OUTPUT + OUT B 3 6 +IN A - V 4 5 N/C +IN 3 4 + V Figure 1. 8-Pin SOIC (LMH6654) Top View 6 Submit Documentation Feedback Figure 2. 5-Pin SOT-23 (LMH6654) Top View - -IN B B -IN 4 5 +IN B Figure 3. 8-Pin SOIC and VSSOP (DGK) (LMH6655) Top View Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 LMH6654, LMH6655 www.ti.com SNOS956D - JUNE 2001 - REVISED MARCH 2013 Typical Performance Characteristics - + TJ = 25C, V = 5V, V = -5, RF = 25 for gain = +1, RF = 402 and for gain +2, and RL = 100, unless otherwise specified. Closed Loop Bandwidth (G = +2) 9 2 6 0 3 -2 0 -4 -3 GAIN (dB) GAIN (dB) Closed Loop Bandwidth (G = +1) 4 VS = 2.5V -6 -8 VS = 5V -10 -9 VS = 5V -12 -12 -15 -14 -18 -16 1M VS = 2.5V -6 10M 100M FREQUENCY (Hz) -21 1M 1G Figure 4. Closed Loop Bandwidth (G = +5) Closed Loop Bandwidth (G = +10) 25 19 20 VS = 5V 14 VS = 5V 15 9 10 GAIN (dB) 4 GAIN (dB) 1G Figure 5. 24 -1 -6 VS = 2.5V -11 5 0 -5 -16 -10 -21 -15 VS = 2.5V -20 -26 1M 10M 100M FREQUENCY (dB) 1G -25 1M 1G 10M 100M FREQUENCY (Hz) Figure 6. Figure 7. Supply Current per Channel vs. Supply Voltage Supply Current per Channel vs. Temperature 5.0 5 4.9 4.9 85C 4.8 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 10M 100M FREQUENCY (Hz) 4.7 4.6 4.5 4.4 25C 4.3 -40C 4.8 4.7 VS = 5V 4.6 4.5 4.4 4.2 4.3 4.1 4.2 20 40 60 -60 -40 -20 0 TEMPERATURE (C) 4 5 6 7 8 9 10 SUPPLY VOLTAGE (V) 11 12 Figure 8. VS = 5V 80 100 Figure 9. Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 Submit Documentation Feedback 7 LMH6654, LMH6655 SNOS956D - JUNE 2001 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) - + TJ = 25C, V = 5V, V = -5, RF = 25 for gain = +1, RF = 402 and for gain +2, and RL = 100, unless otherwise specified. Offset Voltage vs. Supply Voltage (VCM = 0V) Offset Voltage vs. Common Mode 0 0 -0.2 -0.1 VS = 5V -40C -40C -0.2 VOS (mV) -0.6 85C -0.8 -0.3 85C -0.4 25C -0.5 -1 -0.6 -1.2 4 5 6 7 8 9 VSUPPLY (V) 10 11 0 12 1 2 3 4 5 VCM (V) 6 7 8 Figure 10. Figure 11. Offset Voltage vs. Common Mode Bias Current and Offset Voltage vs. Temperature 0 7 VS = 2.5V IBIAS INPUT BIAS CURRENT (A) -0.1 -0.2 -0.3 VOS (mV) 25C -0.4 -40C -0.5 -0.6 25C -0.7 -0.8 85C 6 OFFSET VOLTAGE (mV) VOS (mV) -0.4 5 4 3 2 VOS 1 -0.9 -1 0 0.5 1 1.5 2 2.5 3 3.5 0 -50 0 50 100 TEMPERATURE (C) VCM (V) Figure 12. Figure 13. Bias Current vs. Common Mode Voltage Bias Current vs. Common Mode Voltage 7 -40C VS = 5V 6 POSITIVE IBIAS (A) 25C 5 4 85C 3 2 1 0 -1 0 0.5 1 1.5 2 2.5 3 3.5 VCM (V) Figure 14. 8 Submit Documentation Feedback Figure 15. Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 LMH6654, LMH6655 www.ti.com SNOS956D - JUNE 2001 - REVISED MARCH 2013 Typical Performance Characteristics (continued) - + TJ = 25C, V = 5V, V = -5, RF = 25 for gain = +1, RF = 402 and for gain +2, and RL = 100, unless otherwise specified. AOL, PSRR and CMRR vs. Temperature Inverting Large Signal Pulse Response (VS = 5V) INPUT 110 100 (1 V/div) CMRR 90 PSRR 80 OUTPUT AoL, PSRR, AND CMRR (dB) 120 70 AoL @ 5V 60 -50 AoL @ 5V 0 50 100 TIME (12.5 ns/div) TEMPERATURE (C) Figure 17. Inverting Large Signal Pulse Response (VS = 5V) Non-Inverting Large Signal Pulse Response (VS = 5V) OUTPUT OUTPUT (1 V/div) (1 V/div) INPUT INPUT Figure 16. TIME (12.5 ns/div) TIME (12.5 ns/div) Figure 19. Non-Inverting Large Signal Pulse Response (VS = 5V) Non-Inverting Small Signal Pulse Response (VS = 5V) OUTPUT OUTPUT (1 V/div) (100 mV/div) INPUT INPUT Figure 18. TIME (12.5 ns/div) TIME (12.5 ns/div) Figure 20. Figure 21. Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 Submit Documentation Feedback 9 LMH6654, LMH6655 SNOS956D - JUNE 2001 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) - + TJ = 25C, V = 5V, V = -5, RF = 25 for gain = +1, RF = 402 and for gain +2, and RL = 100, unless otherwise specified. Inverting Small Signal Pulse Response (VS = 5V) OUTPUT OUTPUT (100 mV/div) (100 mV/div) INPUT INPUT Non-Inverting Small Signal Pulse Response (VS = 5V) TIME (12.5 ns/div) TIME (12.5 ns/div) Figure 22. Figure 23. Inverting Small Signal Pulse Response (VS = 5V) Input Voltage and Current Noise vs. Frequency (VS = 5V) 100 10 10 en in 1 100 1k 100k 10k FREQUENCY (Hz) 1M INPUT CURRENT NOISE (pA/ Hz) OUTPUT (100 mV/div) INPUT VOLTAGE NOISE (nV/ Hz) INPUT 100 1 10M TIME (12.5 ns/div) Figure 24. Figure 25. Input Voltage and Current Noise vs. Frequency (VS = 5V) Harmonic Distortion vs. Frequency G = +1, VO = 2 VPP, VS = 5V 100 en 10 in 1 100 1k 100k 10k FREQUENCY (Hz) 1M 1 10M HARMONIC DISTORTION (dBc) 10 -30 INPUT CURRENT NOISE (pA/ Hz) INPUT VOLTAGE NOISE (nV/ Hz) 100 -40 -50 -60 3RD -70 2ND -80 -90 -100 -110 0.1 Figure 26. 10 Submit Documentation Feedback 1 10 100 FREQUENCY (MHz) Figure 27. Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 LMH6654, LMH6655 www.ti.com SNOS956D - JUNE 2001 - REVISED MARCH 2013 Typical Performance Characteristics (continued) - + TJ = 25C, V = 5V, V = -5, RF = 25 for gain = +1, RF = 402 and for gain +2, and RL = 100, unless otherwise specified. Harmonic Distortion vs. Temperature VS = 5V, f = 5 MHz, VO = 2 VPP -30 -60 -40 -65 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) Harmonic Distortion vs. Frequency G = +1, VO = 2 VPP, VS = 5V -50 -60 -70 -80 3RD -90 2ND -100 -110 0.1 1 10 2ND -70 -75 -80 3RD -85 -90 -95 -100 20 40 60 -60 -40 -20 0 TEMPERATURE (C) 100 FREQUENCY (MHz) 80 100 Figure 28. Figure 29. Harmonic Distortion vs. Temperature VS = 5V, f = 5 MHz, VO = 2 VPP Harmonic Distortion vs. Gain VS = 5V, f = 5 MHz, VO = 2 VPP -45 -60 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 2ND -65 -70 -75 3RD -80 -85 2ND -90 -50 -55 -60 -65 -70 3RD -75 -80 -85 -90 -95 -95 -100 20 40 60 -60 -40 -20 0 TEMPERATURE (C) 1 80 2 3 4 100 5 6 7 8 9 10 GAIN (V/V) Figure 30. Figure 31. Harmonic Distortion vs. Gain VS = 5V, f = 5 MHz, VO = 2 VPP Harmonic Distortion vs. Output Swing (G = +2, VS = 5V, f = 5 MHz) -45 -30 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) -50 2ND -55 -60 -65 -70 -75 -80 3RD -85 -90 -95 1 2 3 4 5 6 7 8 9 10 -40 -50 2ND -60 -70 -80 3RD -90 -100 0.0 0.5 1.0 1.5 2.0 2.5 OUTPUT SWING (VPP) GAIN (V/V) Figure 32. Figure 33. Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 Submit Documentation Feedback 11 LMH6654, LMH6655 SNOS956D - JUNE 2001 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) - + TJ = 25C, V = 5V, V = -5, RF = 25 for gain = +1, RF = 402 and for gain +2, and RL = 100, unless otherwise specified. Harmonic Distortion vs. Output Swing (G = +2, VS = 5V, f = 5 MHz) PSRR vs. Frequency 100 -30 NEGATIVE 80 -50 70 PSRR (dB) HARMONIC DISTORTION (dBc) 90 -40 2ND -60 -70 60 POSITIVE 50 40 30 -80 3RD 20 -90 10 0 10 -100 0 1 2 3 4 5 6 7 8 100 10k 1k 100k 1M 10M FREQUENCY (Hz) OUTPUT SWING (VPP) Figure 34. Figure 35. CMRR vs. Frequency Output Sinking Current 5 120 VOUT REFERENCED TO V (V) VS = 5V 4 - 100 CMRR (dB) 80 60 40 20 0 10 3 2 VS = 5V 1 VS = 5V 100 1k 10k 100k FREQUENCY 1M 0 .01 10M 0.1 1 10 1 k 100 OUTPUT SINKING CURRENT (mA) Figure 36. Figure 37. Output Sourcing Current CrossTalk vs. Frequency (LMH6655 only) -20 4 3 VS = 5V 2 1 VS = 5V 0 .01 12 VS = 5V -30 CROSSTALK REJECTION (dB) + VOUT REFERENCED TO V (V) 5 0.1 1 10 100 -40 -50 -60 -70 -80 -90 -100 -110 1 k -120 100k OUTPUT SOURCING CURRENT (mA) 10M 1M FREQUENCY (Hz) Figure 38. Figure 39. Submit Documentation Feedback 100M Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 LMH6654, LMH6655 www.ti.com SNOS956D - JUNE 2001 - REVISED MARCH 2013 Typical Performance Characteristics (continued) - + TJ = 25C, V = 5V, V = -5, RF = 25 for gain = +1, RF = 402 and for gain +2, and RL = 100, unless otherwise specified. CrossTalk vs. Frequency (LMH6655 only) Isolation Resistance vs. Capacitive Load -20 100 VS = 5V ISOLATION RESISTANCE, RISO (:) CROSSTALK REJECTION (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 100k 25: 90 + 80 RISO x 70 CL 1 k: 60 50 40 30 20 10 0 10M 1M FREQUENCY (Hz) 100M 0 10 20 30 40 50 60 70 80 90 100 CAPACITIVE LOAD, CL (pF) Figure 40. Figure 41. Open Loop Gain and Phase vs. Frequency 100 90 80 180 GAIN (dB) 144 60 108 50 72 40 36 30 0 20 -36 GAIN 10 -72 0 -108 -10 -144 -20 1k PHASE () PHASE 70 -180 10k 100k 1M 10M 100M 500M FREQUENCY (Hz) Figure 42. APPLICATION INFORMATION GENERAL INFORMATION The LMH6654 single and LMH6655 dual high speed, voltage feedback amplifiers are manufactured on TI's new VIP10TM (Vertically Integrated PNP) complementary bipolar process. These amplifiers can operate from 2.5V to 6V power supply. They offer low supply current, wide bandwidth, very low voltage noise and large output swing. Many of the typical performance plots found in the datasheet can be reproduced if 50 coax and 50 RIN/ROUT resistors are used. CIRCUIT LAYOUT CONSIDERATION With all high frequency devices, board layouts with stray capacitance have a strong influence on the AC performance. The LMH6654/LMH6655 are not exception and the inverting input and output pins are particularly sensitive to the coupling of parasitic capacitance to AC ground. Parasitic capacitances on the inverting input and output nodes to ground could cause frequency response peaking and possible circuit oscillation. Therefore, the power supply, ground traces and ground plan should be placed away from the inverting input and output pins. Also, it is very important to keep the parasitic capacitance across the feedback to an absolute minimum. Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 Submit Documentation Feedback 13 LMH6654, LMH6655 SNOS956D - JUNE 2001 - REVISED MARCH 2013 www.ti.com The PCB should have a ground plane covering all unused portion of the component side of the board to provide a low impedance path. All trace lengths should be minimized to reduce series inductance. Supply bypassing is required for the amplifiers performance. The bypass capacitors provide a low impedance return current path at the supply pins. They also provide high frequency filtering on the power supply traces. It is recommended that a ceramic decoupling capacitor 0.1 F chip should be placed with one end connected to the ground plane and the other side as close as possible to the power pins. An additional 10 F tantalum electrolytic capacitor should be connected in parallel, to supply current for fast large signal changes at the output. + V 10 F + 0.1 F 0.1 F + 10 F V - Figure 43. Supply Bypass Capacitors EVALUATION BOARDS TI provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. Device Package Evalulation Board PN LMH6654MF 5-Pin SOT-23 LMH730216 LMH6654MA 8-Pin SOIC LMH730227 LMH6655MA 8-Pin SOIC LMH730036 LMH6655MM 8-Pin VSSOP (DGK) LMH730123 Components Needed to Evaluate the LMH6654 on the LMH730227 Evaluation Board: * RfRg use the datasheet to select values. * RIN, ROUT typically 50 (Refer to the Basic Operation section of the evaluation board datasheet for details) * Rf is an optional resistor for inverting again configurations (select Rf to yield desired input impedance = Rg||Rf) * C1, C2 use 0.1 F ceramic capacitors * C3, C4 use 10 F tantalum capacitors Components not used: 1. C5, C6, C7, C8 2. R1 thru R8 The evaluation boards are designed to accommodate dual supplies. The board can be modified to provide single operation. For best performance; 1) do not connect the unused supply. 2) ground the unused supply pin. 14 Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 LMH6654, LMH6655 www.ti.com SNOS956D - JUNE 2001 - REVISED MARCH 2013 POWER DISSIPATION The package power dissipation should be taken into account when operating at high ambient temperature and/or high power dissipative conditions. In determining maximum operable temperature of the device, make sure the total power dissipation of the device is considered; this power dissipated in the device with a load connected to the output as well as the nominal dissipation of the op amp. DRIVING CAPACITIVE LOADS Capacitive loads decrease the phase margin of all op amps. The output impedance of a feedback amplifier becomes inductive at high frequencies, creating a resonant circuit when the load is capacitive. This can lead to overshoot, ringing and oscillation. To eliminate oscillation or reduce ringing, an isolation resistor can be placed as shown in Figure 44 below. At frequencies above 1 F= 2 S RISO CLOAD (1) the load impedance of the Amplifier approaches RISO. The desired performance depends on the value of the isolation resistor. The isolation resistance vs. capacitance load graph in the typical performance characteristics provides the means for selection of the value of RS that provides 3 dB peaking in closed loop AV = 1 response. In general, the bigger the isolation resistor, the more damped the pulse response becomes. For initial evaluation, a 50 isolation resistor is recommended. 25: - RISO VOUT VIN + Figure 44. Isolation Resistor Placement COMPONENTS SELECTION AND FEEDBACK RESISTOR It is important in high-speed applications to keep all component leads short since wires are inductive at high frequency. For discrete components, choose carbon composition axially leaded resistors and micro type capacitors. Surface mount components are preferred over discrete components for minimum inductive effect. Never use wire wound type resistors in high frequency applications. Large values of feedback resistors can couple with parasitic capacitance and cause undesired effects such as ringing or oscillation in high-speed amplifiers. Keep resistors as low as possible consistent with output loading consideration. For a gain of 2 and higher, 402 feedback resistor used for the typical performance plots gives optimal performance. For unity gain follower, a 25 feedback resistor is recommended rather than a direct short. This effectively reduces the Q of what would otherwise be a parasitic inductance (the feedback wire) into the parasitic capacitance at the inverting input. BIAS CURRENT CANCELLATION In order to cancel the bias current errors of the non-inverting configuration, the parallel combination of the gain setting Rg and feedback Rf resistors should equal the equivalent source resistance Rseq as defined in Figure 45. Combining this constraint with the non-inverting gain equation, allows both Rf and Rg to be determined explicitly from the following equations: Rf = AVRseq and Rg = Rf/(AV-1) (2) For inverting configuration, bias current cancellation is accomplished by placing a resistor Rb on the non-inverting input equal in value to the resistance seen by the inverting input (Rf//(Rg+Rs). The additional noise contribution of Rb can be minimized through the use of a shunt capacitor. Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 Submit Documentation Feedback 15 LMH6654, LMH6655 SNOS956D - JUNE 2001 - REVISED MARCH 2013 www.ti.com Figure 45. Non-Inverting Amplifier Configuration Figure 46. Inverting Amplifier Configuration TOTAL INPUT NOISE VS. SOURCE RESISTANCE The noise model for the non-inverting amplifier configuration showing all noise sources is described in Figure 47. In addition to the intrinsic input voltage noise (en) and current noise (in = in+ = in-) sources, there also exits thermal voltage noise et = 4kTR associated with each of the external resistors. Equation 3 provides the general form for total equivalent input voltage noise density (eni). Equation 4 is a simplification of Equation 3 that assumes Rf || Rg = Rseq for bias current cancellation. Figure 48 illustrates the equivalent noise model using this assumption. The total equivalent output voltage noise (eno) is eni * AV. 16 Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 LMH6654, LMH6655 www.ti.com SNOS956D - JUNE 2001 - REVISED MARCH 2013 Figure 47. Non-Inverting Amplifier Noise Model eni = en2 + (in+ * RSeq)2 + 4kTRSeq + (in- * (Rf || Rg))2 + 4kT(Rf || Rg) (3) Figure 48. Noise Model with Rf || Rg = Rseq eni = en2 + 2 (in * RSeq)2 + 4kT (2RSeq) (4) If bias current cancellation is not a requirement, then Rf || Rg does not need to equal Rseq. In this case, according to Equation 3, Rf and Rg should be as low as possible in order to minimize noise. Results similar to Equation 3 are obtained for the inverting configuration on Figure 46 if Rseq is replaced by Rb || Rg is replaced by Rg + Rs. With these substitutions, Equation 3 will yield an eni referred to the non-inverting input. Referring eni to the inverting input is easily accomplished by multiplying eni by the ratio of non-inverting to inverting gains. Noise Figure Noise Figure (NF) is a measure of the noise degradation caused by an amplifier. Si/Ni NF = 10LOG So/No eni = 10LOG 2 2 et (5) The noise figure formula is shown in Equation 5. The addition of a terminating resistor RT, reduces the external thermal noise but increases the resulting NF. The NF is increased because the RT reduces the input signal amplitude thus reducing the input SNR. en2 + in2 (RSeq + (Rf || Rg))2 + 4KTRSeq + 4kt (Rf || Rg) 4kTRSeq (6) The noise figure is related to the equivalent source resistance (Rseq) and the parallel combination of Rf and Rg. To minimize noise figure, the following steps are recommended: 1. Minimize Rf||Rg 2. Choose the Optimum Rs (ROPT) ROPT is the point at which the NF curve reaches a minimum and is approximated by: ROPT (en/in) Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 Submit Documentation Feedback 17 LMH6654, LMH6655 SNOS956D - JUNE 2001 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision C (March 2013) to Revision D * 18 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 17 Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LMH6654 LMH6655 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMH6654MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66 54MA LMH6654MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66 54MA LMH6654MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A66A LMH6654MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A66A LMH6654MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A66A LMH6655MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMH66 55MA LMH6655MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66 55MA LMH6655MAX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMH66 55MA LMH6655MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66 55MA LMH6655MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A67A LMH6655MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A67A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6654MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6654MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6654MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6654MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6655MAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6655MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6654MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6654MF SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6654MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6654MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMH6655MAX SOIC D 8 2500 367.0 367.0 35.0 LMH6655MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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