Triple-Channel, Digital Isolators,
Enhanced System-Level ESD Reliability
Data Sheet ADuM3300/ADuM3301
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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FEATURES
Enhanced system-level ESD performance per IEC 61000-4-x
Low power operation
5 V operation
2.0 mA per channel maximum @ 0 Mbps to 2 Mbps
4.1 mA per channel maximum @ 10 Mbps
36 mA per channel maximum @ 90 Mbps
3 V operation
1.0 mA per channel maximum @ 0 Mbps to 2 Mbps
2.8 mA per channel maximum @ 10 Mbps
17 mA per channel maximum @ 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body, RoHS-compliant package
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peak
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM330x1 are 3-channel digital isolators based on the
Analog Devices, Inc. iCoupler® technology. Combining high
speed CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocoupler devices.
iCoupler devices remove the design difficulties commonly
associated with optocouplers. Typical optocoupler concerns
regarding uncertain current transfer ratios, nonlinear transfer
functions, and temperature and lifetime effects are eliminated
with the simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-sixth
the power of optocouplers at comparable signal data rates.
The ADuM330x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). All models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. The
ADuM330x isolators have a patented refresh feature that ensures dc
correctness in the absence of input logic transitions and during
power-up/power-down conditions.
In comparison to ADuM130x isolators, ADuM330x isolators
contain various circuit and layout changes to provide increased
capability relative to system-level IEC 61000-4-x testing (ESD,
burst, and surge). The precise capability in these tests for either
the ADuM130x or ADuM330x products is strongly determined
by the design and layout of the user’s system.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
IC
NC
NC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
NC
V
E2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
05984-001
Figure 1. ADuM3300 Functional Block Diagram
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
OC
NC
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
NC
V
E2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
05984-002
Figure 2. ADuM3301 Functional Block Diagram
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 5
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
Package Characteristics ............................................................. 10
Regulatory Information............................................................. 10
Insulation and Safety-Related Specifications.......................... 10
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 11
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings ......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions......................... 13
Typical Performance Characteristics ........................................... 15
Application Information................................................................ 17
PC Board Layout ........................................................................ 17
System-Level ESD Considerations and Enhancements ........ 17
Propagation Delay-Related Parameters................................... 17
DC Correctness and Magnetic Field Immunity........................... 17
Power Consumption .................................................................. 18
Insulation Lifetime..................................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
2/12—Rev. A to Rev. B
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section............................................ 17
Updated Outline Dimensions....................................................... 20
6/07—Rev. 0 to Rev. A
Updated VDE Certification Throughout ...................................... 1
Changes to Features, General Description, and Note 1............... 1
Changes to Regulatory Information Section .............................. 10
Changes to DIN V VDE V 0884-10 (VDE V 0884-10)
Insulation Characteristics.............................................................. 11
Added Table 10 ............................................................................... 12
Added Insulation Lifetime Section .............................................. 19
3/06—Revision 0: Initial Version
Data Sheet ADuM3300/ADuM3301
Rev. B | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.66 0.97 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.39 0.55 mA
ADuM3300, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 2.4 3.3 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.1 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 7.0 8.1 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.7 3.6 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 54 77 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 15 31 mA 45 MHz logic signal freq.
ADuM3301, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 2.0 3.1 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.6 2.3 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 5.5 6.9 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 3.9 5.4 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 41 57 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 28 41 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VIDVDD1 or VDD2,
0 V ≤ VE1, VE2VDD1 or VDD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold VIL, VEL 0.8 V
(VDD1 or
VDD2) − 0.1
5.0 V IOx = −20 μA, VIx = VIxH Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or
VDD2) − 0.4
4.8 V IOx = −4 mA, VIx = VIxH
0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM330xARWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 t
PSKCD/OD 50 ns CL = 15 pF, CMOS signal levels
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 4 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM330xBRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 20 32 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 15 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels6
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM330xCRWZ
Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 10 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels6
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance-to-High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output7
|CMH| 25 35 kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output7
|CML| 25 35 kV/μs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel8 I
DDI (D) 0.20 mA/Mbps
Output Dynamic Supply Current per Channel8 I
DDO (D) 0.05 mA/Mbps
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section.
See Figure through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through
for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.
ower Consumption
Power Consumption
6
Figure 6
9
Figure 12
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.
Figure 8
Data Sheet ADuM3300/ADuM3301
Rev. B | Page 5 of 20
ELECTRICAL CHARACTERISTICS—3 V OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.37 0.57 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.25 0.37 mA
ADuM3300, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.4 1.9 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 3.8 5.3 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.5 2.1 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 28 41 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 8.2 11 mA 45 MHz logic signal freq.
ADuM3301, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.1 1.6 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 3.0 4.1 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.2 2.9 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 22 31 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 15 21 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1,VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
(VDD1 or
VDD2) − 0.1
3.0 V IOx = −20 μA, VIx = VIxH Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or
VDD2) − 0.4
2.8 V IOx = −4 mA, VIx = VIxH
0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM330xARWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 50 75 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 t
PSKCD/OD 50 ns CL = 15 pF, CMOS signal levels
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 6 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM330xBRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 20 38 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels6
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM330xCRWZ
Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 16 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels6
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance-to-High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output7
|CMH| 25 35 kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output7
|CML| 25 35 kV/μs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel8 I
DDI (D) 0.10 mA/Mbps
Output Dynamic Supply Current per Channel8 I
DDO (D) 0.03 mA/Mbps
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P section.
See Figure through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through
for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.
ower Consumption
Power Consumption
6
Figure 6
9
Figure 12
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information
on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating the per-channel supply current
for a given data rate.
Figure 8
Data Sheet ADuM3300/ADuM3301
Rev. B | Page 7 of 20
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation:
2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q)
5 V/3 V Operation 0.66 0.97 mA
3 V/5 V Operation 0.37 0.57 mA
Output Supply Current per Channel, Quiescent IDDO (Q)
5 V/3 V Operation 0.25 0.37 mA
3 V/5 V Operation 0.39 0.55 mA
ADuM3300, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 2.4 3.3 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.4 1.9 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.1 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 7.0 8.1 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.8 5.3 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.5 2.1 mA 5 MHz logic signal freq.
3 V/5 V Operation 2.7 3.6 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 54 77 mA 45 MHz logic signal freq.
3 V/5 V Operation 28 41 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 8.2 11 mA 45 MHz logic signal freq.
3 V/5 V Operation 15 31 mA 45 MHz logic signal freq.
ADuM3301, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 2.0 3.1 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.1 1.6 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.6 2.3 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 5.5 6.9 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.0 4.1 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 2.2 2.9 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.9 5.4 mA 5 MHz logic signal freq.
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 8 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 41 57 mA 45 MHz logic signal freq.
3 V/5 V Operation 22 31 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 15 21 mA 45 MHz logic signal freq.
3 V/5 V Operation 28 41 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH
5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V
Logic Low Input Threshold VIL, VEL
5 V/3 V Operation 0.8 V
3 V/5 V Operation 0.4 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or
VDD2) − 0.1
(VDD1 or VDD2) V I
Ox = −20 μA, VIx = VIxH
(VDD1 or
VDD2) − 0.4
(VDD1 or
VDD2) − 0.2
V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM330xARWZ
Minimum Pulse Width2 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6 t
PSKCD/OD 50 ns CL = 15 pF, CMOS signal levels
ADuM330xBRWZ
Minimum Pulse Width2 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 15 35 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels6
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM330xCRWZ
Minimum Pulse Width2 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate3 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay4 t
PHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew5 t
PSK 14 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels6
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels6
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
Data Sheet ADuM3300/ADuM3301
Rev. B | Page 9 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance-to-High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF C
L = 15 pF, CMOS signal levels
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity
at Logic High Output7
|CMH| 25 35 kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output7
|CML| 25 35 kV/μs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current per Channel8 I
DDI (D)
5 V/3 V Operation 0.20 mA/Mbps
3 V/5 V Operation 0.10 mA/Mbps
Output Dynamic Supply Current per Channel8 I
DDO (D)
5 V/3 V Operation 0.05 mA/Mbps
3 V/5 V Operation 0.03 mA/Mbps
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301/ADuM3302 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 10 of 20
PACKAGE CHARACTERISTICS
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input to Output)1 R
I-O 1012 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 C
I 4.0 pF
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W
Thermocouple located at
center of package underside
1 The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM330x is approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for details regarding
recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL CSA VDE
Recognized under UL 1577
Component Recognition
Program1
Approved under CSA Component Acceptance Notice #5A Certified according to DIN V VDE V
0884-10 (VDE V 0884-10): 2006-122
Double/reinforced insulation,
2500 V rms isolation voltage
Basic insulation per CSA 60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak) maximum working voltage
Reinforced insulation per CSA 60950-1-03 and IEC 60950-1,
400 V rms (566 V peak) maximum working voltage
Reinforced insulation, 560 V peak
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL1577, each ADuM330x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM330x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection
limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.1 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Data Sheet ADuM3300/ADuM3301
Rev. B | Page 11 of 20
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.
Table 7.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 560 V peak
Input-to-Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1050 V peak
Input-to-Output Test Voltage, Method A VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR
After Environmental Tests Subgroup 1 896 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak
Safety-Limiting Values Maximum value allowed in the event of a failure
(see Figure 3)
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
CASE T E M P E RATURE (°C)
SAFETY-LIMITING CURRENT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
SIDE #1
SIDE #2
05984-003
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +105 °C
Supply Voltages1 V
DD1, VDD2 2.7 5.5 V
Input Signal Rise and Fall Times 1.0 ms
1 All voltages are relative to their respective ground. See the
section for information on immunity to external
magnetic fields.
DC Correctness
and Magnetic Field Immunity
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 12 of 20
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 9.
Parameter Symbol Min Max Unit
Storage Temperature TST −65 +150 °C
Ambient Operating
Temperature
TA −40 +105 °C
Supply Voltages1 V
DD1, VDD2 −0.5 +7.0 V
Input Voltage1, 2 VIA, VIB, VIC,
VID, VE1, VE2
−0.5 VDDI + 0.5 V
Output Voltage1, 2 VOA, VOB, VOC,
VOD
−0.5 VDDO + 0.5 V
Average Output
Current per Pin3
Side 1 IO1 −23 +23 mA
Side 2 IO2 −30 +30 mA
Common-Mode
Transients4
CMH, CML −100 +100 kV/μs
1 All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively.
3 See Figure 3 for maximum rated current values for various temperatures.
4 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the Absolute Maximum Rating can cause latch-up
or permanent damage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Table 10. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 11. Truth Table (Positive Logic)
VIX Input1 V
EX Input2 V
DDI State1 V
DDO State1 V
OX Output1 Notes
H H or NC Powered Powered H
L H or NC Powered Powered L
X L Powered Powered Z
X H or NC Unpowered Powered H Outputs return to the input state within 1 μs of VDDI power
restoration
X L Unpowered Powered Z
X X Powered Unpowered Indeterminate
Outputs return to the input state within 1 μs of VDDO power
restoration if VEX state is H or NC
Outputs return to high impedance state within 8 ns of VDDO
power restoration if VEX state is L
1 VIX and VOX refer to the input and output signals of a given channel (A, B, or C). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and VDDO
refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEX to an external logic high or low is recommended.
Data Sheet ADuM3300/ADuM3301
Rev. B | Page 13 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
GND1*2
VIA 3
VIB 4
VDD2
16
GND2**15
VOA
14
VOB
13
VIC 5VOC
12
NC 6NC11
NC 7VE2
10
GND1*8GND2**9
NC = NO CO NNE CT
ADuM3300
TOP VI EW
(No t t o S cale)
05984-004
*PIN 2 AND PIN 8 ARE INTE RNALLY CONNECT E D, AND
CONNECT ING BOTH TO GND1 IS RECOMMENDED.
**PIN 9 AND P IN 15 ARE INTERNAL LY CONNECT E D, AND CONNE CT ING
BO TH TO GND2 IS RECOMM E NDED. IN NOIS Y ENVI RONMENTS,
CONNECTING OUTP UT ENABLES ( P IN 7 F OR ADuM3301 AND PI N 10 FO R
ALL M ODEL S ) TO AN EX TERNAL LOGIC HIGH OR L OW IS RECOMME NDE D.
Figure 4. ADuM3300 Pin Configuration
Table 12. ADuM3300 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
2, 8 GND1 Ground 1. Ground Reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6, 7, 11 NC No Connect.
9, 15 GND2 Ground 2. Ground Reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected.
VOA, VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VDD2 Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 14 of 20
V
DD1 1
*GND
12
V
IA 3
V
IB 4
V
DD2
16
GND
2
**
15
V
OA
14
V
OB
13
V
OC 5
V
IC
12
NC
6
NC
11
V
E1 7
V
E2
10
*GND
18
GND
2
**
9
NC = NO CONNECT
ADuM3301
TOP VIEW
(No t t o S cale)
05984-005
*PIN 2 AND PIN 8 ARE INTE RNAL LY CO NNE CTED,
AND CONNECT ING BOT H T O G ND
1
IS RECOMM E NDE D.
*
*PIN 9 AND P IN 15 ARE INTERNAL LY CO NNE CTED,
AND CONNECT ING BOT H T O GND
2
IS RECOMMENDED.
Figure 5. ADuM3301 Pin Configuration
Table 13. ADuM3301 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
2, 8 GND1 Ground 1. Ground reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6, 11 NC No Connect.
7 VE1 Output Enable 1. Active high logic input. VOC output is enabled when VE1 is high or disconnected. VOC is
disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is
recommended.
9, 15 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected.
VOA and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VDD2 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Data Sheet ADuM3300/ADuM3301
Rev. B | Page 15 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
DATA RAT E ( M bp s)
CURRENT/ CHANNE L (mA)
0
0
20
4020 60 80 100
5V
3V
05984-006
15
10
5
Figure 6. Typical Input Supply Current per Channel vs. Data Rate (No Load)
DATA RAT E ( M bp s)
CURRENT/CHANNEL ( mA)
0
0
20
4020 60 80 100
5V
3V
05984-007
15
10
5
Figure 7. Typical Output Supply Current per Channel vs. Data Rate (No Load)
DATA RAT E ( M bp s)
CURRENT/ CHANNE L (mA)
0
0
20
4020 60 80 100
5V
3V
05984-008
15
10
5
Figure 8. Typical Output Supply Current per Channel vs. Data Rate
(15 pF Output Load)
DATA RAT E ( M bp s)
CURRENT ( mA)
0
0
80
4020 60 80 100
5V
3V
05984-009
60
40
20
Figure 9. Typical ADuM3300 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
DATA RAT E ( M bp s)
CURRENT ( mA)
0
0
80
4020 60 80 100
5V
3V
05984-010
60
40
20
Figure 10. Typical ADuM3300 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
DATA RAT E ( M bp s)
CURRENT ( mA)
0
0
80
4020 60 80 100
5V
3V
05984-011
60
40
20
Figure 11. Typical ADuM3301 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 16 of 20
DATA RAT E ( M bp s)
CURRENT ( mA)
0
0
80
4020 60 80 100
5V
3V
05984-012
60
40
20
Figure 12. Typical ADuM3301 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
TEM P E RATURE (°C)
PROP AGATION DE LAY (ns)
–50 –25
25
30
35
40
0507525 100
3V
5V
05984-019
Figure 13. Propagation Delay vs. Temperature, C Grade
Data Sheet ADuM3300/ADuM3301
Rev. B | Page 17 of 20
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM330x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 14). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and
Pin 16 for VDD2. The capacitor value should be between 0.01 μF
and 0.1 μF. The total lead length between both ends of the
capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 should be considered unless the ground pair on each
package side is connected close to the package.
V
DD1
GND
1
V
IA
V
IB
V
IC/OC
NC
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC/IC
NC
V
E2
GND
2
05984-015
Figure 14. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side. Failure to
ensure this could cause voltage differentials between pins
exceeding the devices absolute maximum ratings, thereby
leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x) is
highly dependent on system design, which varies widely by
application. The ADuM330x incorporate many enhancements
to make ESD reliability less dependent on system design. The
enhancements include
ESD protection cells added to all input/output interfaces.
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
The SCR effect inherent in CMOS devices minimized by
use of guarding and isolation technique between PMOS
and NMOS devices.
Areas of high electric field concentration eliminated using
45° corners on metal traces.
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
While the ADuM330x improve system-level ESD reliability,
they are no substitute for a robust system-level design. See
Application Note AN-793 ESD/Latch-Up Considerations with
iCoupler Isolation Products for detailed recommendations on
board layout and system-level design.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high.
INPUT (
V
IX
)
OUTPUT (V
OX
)
t
PLH
t
PHL
50%
50%
05984-016
Figure 15. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM330x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM330x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1 μs, a periodic set
of refresh pulses indicative of the correct input state is sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than about 5 μs, the input side is
assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a default state (see Table 11) by the
watchdog timer circuit.
The limitation on the ADuM330x’s magnetic field immunity is
set by the condition in which induced voltage in the transformer’s
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur. The 3 V operating condition of the
ADuM330x is examined because it represents the most
susceptible mode of operation.
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 18 of 20
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) π rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM330x and
an imposed requirement that the induced voltage is at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 16.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLO WABLE MAGNETI C FL UX
DENSI TY ( kgauss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
05984-017
Figure 16. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM330x transformers. Figure 17 expresses these allowable
current magnitudes as a function of frequency for selected
distances. The ADuM330x is extremely immune and can be
affected only by extremely large currents operated at high
frequency very close to the component (see Figure 17). For the
1 MHz example noted, a 0.5 kA current would have to be placed
5 mm away from the ADuM330x to affect the components
operation.
MAGNETIC FIELD FREQUENCY (Hz)
MAXIMUM ALLOW ABLE CURRENT (kA)
1000
100
10
1
0.1
0.011k 10k 100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 1 00mm
05984-018
Figure 17. Maximum Allowable Current
for Various Current-to-ADuM330x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM330x
isolator is a function of the supply voltage, the channel’s data
rate, and the channels output load.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5 fr
IDDI = IDDI (D) × (2ffr) + IDDI (Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 6 provides per-
channel input supply current as a function of data rate. Figure 7
and Figure 8 provide per-channel output supply current as a
function of data rate for an unloaded output condition and for a
15 pF output condition, respectively. Figure 9 through Figure 12
provide total VDD1 and VDD2 supply current as a function of data
rate for ADuM3300/ADuM3301 channel configurations.
Data Sheet ADuM3300/ADuM3301
Rev. B | Page 19 of 20
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices executes an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM330x.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage.
The values shown in Table 10 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition, and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life.
The insulation lifetime of the ADuM330x depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 18, Figure 19, and Figure 20 illustrate these
different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
In the case of unipolar ac or dc voltage, the stress on the insula-
tion is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 10 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms
to either the unipolar ac or dc voltage cases. Any cross-insulation
voltage waveform that does not conform to Figure 19 or Figure 20
should be treated as a bipolar ac waveform, and its peak voltage
should be limited to the 50-year lifetime voltage value listed in
Table 10.
Note that the voltage presented in Figure 19 is shown as
sinusoidal for illustration purposes only. It is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
0V
RATED P E AK V OLTAGE
05984-020
Figure 18. Bipolar AC Waveform
0V
RATED P E AK V OLTAGE
05984-021
Figure 19. Unipolar AC Waveform
0V
RATED P E AK V OLTAGE
05984-022
Figure 20. DC Waveform
ADuM3300/ADuM3301 Data Sheet
Rev. B | Page 20 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 21. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1, 2 Temperature Range (°C)
Number of
Inputs,
VDD1 Side
Number of
Inputs,
VDD2 Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Package
Option3
ADuM3300ARWZ −40 to +105 3 0 1 100 40 RW-16
ADuM3300BRWZ −40 to +105 3 0 10 50 3 RW-16
ADuM3300CRWZ −40 to +105 3 0 90 32 2 RW-16
ADuM3301ARWZ −40 to +105 2 1 1 100 40 RW-16
ADuM3301BRWZ −40 to +105 2 1 10 50 3 RW-16
ADuM3301CRWZ −40 to +105 2 1 90 32 2 RW-16
1 Z = RoHS Compliant Part.
2 Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option.
3 RW-16 = 16-lead wide body SOIC.
©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05984-0-2/12(B)