NCV4269AD250R2G - ON Semiconductor

December, 2009 − Rev. 1

1Publication Order Number:

NCV4269A/D

NCV4269A

5.0 V Micropower 150 mA

LDO Linear Regulator with

DELAY, Adjustable RESET,

and Sense Output

The NCV4269A is a 5.0 V precision micropower voltage regulator

with an output current capability of 150 mA.

The output voltage is accurate within ±2.0% with a maximum

dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature

drawing only 240 mA with a 1.0 mA load. This part is ideal for any and

all battery operated microprocessor equipment.

Microprocessor control logic includes an active reset output RO

with delay and a SI/SO monitor which can be used to provide an early

warning signal to the microprocessor of a potential impending reset

signal. The use of the SI/SO monitor allows the microprocessor to

finish any signal processing before the reset shuts the microprocessor

down.

The active Reset circuit operates correctly at an output voltage as

low as 1.0 V. The Reset function is activated during the power up

sequence or during normal operation if the output voltage drops

outside the regulation limits.

The reset threshold voltage can be decreased by the connection of an

external resistor divider to the RADJ lead. The regulator is protected

against reverse battery, short circuit, and thermal overload conditions.

The device can withstand load dump transients making it suitable for

use in automotive environments. The device has also been optimized

for EMC conditions.

Features

•5.0 V ± 2.0% Output

•Low 240 mA Quiescent Current

•Active Reset Output Low Down to VQ = 1.0 V

•Adjustable Reset Threshold

•150 mA Output Current Capability

•Fault Protection

♦+60 V Peak Transient Voltage

♦−40 V Reverse Voltage

♦Short Circuit

♦Thermal Overload

•Early Warning through SI/SO Leads

•Internally Fused Leads in SO−14 and SO−20 Packages

•Integrated Pullup Resistor at Logic Outputs (To Use External

Resistors, Select the NCV4279A)

•Very Low Dropout Voltage

•Electrical Parameters Guaranteed Over Entire Temperature Range

•NCV Prefix for Automotive and Other Applications Requiring Site

and Control Changes

•These are Pb−Free Devices

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SO−14

D SUFFIX

CASE 751A

MARKING

DIAGRAMS

NCV4269A5G

AWLYWW

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G, G= Pb Free

SO−8

D SUFFIX

CASE 751

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 13 of this data sheet.

84269A5

ALYW

4269A5

ALYW

SO−8

EXPOSED PAD

PD SUFFIX

CASE 751AC

NCV4269A5

AWLYYWWG

SO−20

DW SUFFIX

CASE 751D

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RADJ

Figure 1. Block Diagram

GND

Reference

RRO

RSO

Error

Amplifier

Reference

and Trim

Current and

Saturation

Control

−

PIN CONNECTIONS

SORO

QGND

GNDGND

114

GNDGND

SIRADJ

120

NCNC

GNDGND

GND

GNDGND

NCNC

SIRADJ

QNC

SORO

SO−20LSO−14

GNDD

RORADJ

SOSI

SO−8

PACKAGE PIN DESCRIPTION

Package Pin Number

Symbol Function

SO−8SO−8 EP SO−14 SO−20L

3 3 1 1 RADJ Reset Threshold Adjust; if not used to connect to GND.

4 4 2 2 D Reset Delay; To Set Time Delay, Connect to GND with Capacitor

5 5 3, 4, 5, 6,

10, 11, 12

4, 5, 6, 7, 14,

15, 16, 17

GND Ground

− − − 3, 8, 9, 13, 18 NC No connection to these pins from the IC.

6 6 7 10 RO Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor

to Q. Leave Open if Not Used.

7 7 8 11 SO Sense Output; This Open−Collector Output is Internally Pulled Up by

20 kW pullup resistor to Q. If not used, keep open.

8 8 9 12 Q 5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W.

1 1 13 19 I Input; Connect to GND Directly at the IC with a Ceramic Capacitor.

2 2 14 20 SI Sense Input; If not used, Connect to Q.

−EPAD − − EPAD Connect to ground potential or leave unconnected

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MAXIMUM RATINGS (TJ = −40°C to 150°C)

Parameter Symbol Min Max Unit

Input to Regulator VI

−40

Internally Limited

Input Transient to Regulator VI−60 V

Sense Input VSI

ISI

−40

−1

Reset Threshold Adjust VRADJ

IRADJ

−0.3

−10

Reset Delay VD

−0.3

Internally Limited

Ground Iq50 −mA

Reset Output VRO

IRO

−0.3

Internally Limited

Sense Output VSO

ISO

−0.3

Internally Limited

Regulated Output VQ

−0.5

−10

7.0

−

Junction Temperature

Storage Temperature

TSTG

−

−50

150

°C

Input Voltage Operating Range

Junction Temperature Operating Range

−

−40

150

°C

LEAD TEMPERATURE SOLDERING AND MSL

Parameter Symbol Value

MSL, 20−Lead LS Temperature 265°C Peak (Note 3) MSL 3

MSL, 8−Lead, 14−Lead, LS Temperature 265°C Peak (Note 3) MSL 1

MSL, 8−Lead EP, LS Temperature 260°C MSL 2

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series incorporates ESD protection and exceeds the following ratings:

Human Body Model (HBM) ≤ 4.0 kV per AEC−Q100−002.

Machine Model (MM) ≤ 200 V per AEC−Q100−003.

2. Latchup Current Maximum Rating: ≤ 150 mA per AEC−Q100−004.

3. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.

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THERMAL CHARACTERISTICS

Characteristic Test Conditions (Typical Values) Unit

SO−8 Package (Note 4)

Junction−to−Pin 4 ( Y − JL4, YL4)53.8 °C/W

Junction−to−Ambient Thermal Resistance (RqJA, qJA)170.9 °C/W

SO−8 EP Package (Note 4)

Junction−to−Pin 8 ( Y − JL8, YL8)23.7 °C/W

Junction−to−Ambient Thermal Resistance (RqJA, qJA)71.4 °C/W

Junction−to−Pad ( Y − JPad) 7.7 °C/W

SO−14 Package (Note 4)

Junction−to−Pin 4 ( Y − JL4, YL4)18.4 °C/W

Junction−to−Ambient Thermal Resistance (RqJA, qJA)111.6 °C/W

SO−20 Package (Note 4)

Junction−to−Pin 4 ( Y − JL4, YL4)21.8 °C/W

Junction−to−Ambient Thermal Resistance (RqJA, qJA)95.3 °C/W

4. 2 oz copper, 50 mm2 copper area, 1.5 mm thick FR4

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ELECTRICAL CHARACTERISTICS (TJ = −40°C ≤ TJ ≤ 125°C, VI = 13.5 V unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

REGULATOR

Output Voltage VQ1 mA v IQ v 100 mA 6 V v VI v 16 V 4.90 5.00 5.10 V

Current Limit IQ−150 200 500 mA

Current Consumption; Iq = II – IQIqIQ = 1 mA, RO, SO High −190 250 mA

Current Consumption; Iq = II – IQIqIQ = 10 mA, RO, SO High −250 450 mA

Current Consumption; Iq = II – IQIqIQ = 50 mA, RO, SO High −2.0 3.0 mA

Dropout Voltage Vdr VI = 5 V, IQ = 100 mA −0.25 0.5 V

Load Regulation DVQIQ = 5 mA to 100 mA −10 20 mV

Line Regulation DVQVI = 6 V to 26 V IQ = 1 mA −10 30 mV

RESET GENERATOR

Reset Switching Threshold VRT −4.50 4.65 4.80 V

Reset Adjust Switching Threshold VRADJ,TH VQ > 3.5 V 1.26 1.35 1.44 V

Reset Pullup Resistance RSO,INT −10 20 40 kW

Reset Output Saturation Voltage VRO,SAT VQ < VRT

, RRO, INT −0.1 0.4 V

Upper Delay Switching Threshold VUD −1.4 1.8 2.2 V

Lower Delay Switching Threshold VLD −0.3 0.45 0.60 V

Saturation Voltage on Delay Capacitor VD,SAT VQ < VRT − − 0.1 V

Charge Current ID,C VD = 1 V 3.0 6.5 9.5 mA

Delay Time L ³ H tdCD = 100 nF 17 28 −ms

Delay Time H ³ L tRR CD = 100 nF −3.15 −ms

INPUT VOLTAGE SENSE

Sense Threshold High VSI,High −1.24 1.31 1.38 V

Sense Threshold Low VSI,Low −1.16 1.20 1.28 V

Sense Output Saturation Voltage VSO,Low VSI < 1.20 V; VQ > 3 V; RSO −0.1 0.4 V

Sense Resistor Pullup RSO,INT −10 20 40 kW

Sense Input Current ISI − −1.0 0.1 1.0 mA

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Figure 2. Measuring Circuit

RADJ1

IRADJ

VSI

100 nF

IDIqVRO VSO

VRADJ

RADJ2

470 nF

1000 mF

ISI

22 mF

D GND RO SO

RADJ

VLD

VRT

VRO,SAT

VRO

< tRR

dt +ID

VUD

Power−on−Reset Thermal

Shutdown

Voltage Dip

at Input

Undervoltage Secondary

Spike

Overload

at Output

tRR

Figure 3. Reset Timing Diagram

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Sense Input Voltage

VSI,High

VSI,Low

High

Low

Sense Output Voltage

Figure 4. Sense Timing Diagram

TYPICAL PERFORMANCE CHARACTERISTICS

3.2

−40 0 40 80 120 160

TJ, (°C)

VD, (V)

−40 0 40 80 120 160

Figure 5. Charge Current ID,C vs. Temperature TJFigure 6. Switching Voltage VUD and VLD vs.

Temperature TJ

TJ, (°C)

ID,C, (mA)

VI = 13.5 V

VD = 1.0 V

VI = 13.5 V

VUD

VLD

2.8

2.4

2.0

1.6

1.2

0.8

0.4

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TYPICAL PERFORMANCE CHARACTERISTICS

Iq, (mA)

VI, (V)

10 20 30 40 50

RL = 33 W

RL = 50 W

RL = 100 W

RL = 200 W

1.7

−40

VRAD,JTH, (V)

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

TJ, (°C)

0 40 80 120 160

IQ, (mA)

Vdr, (mV)

TJ = 125°C

TJ = 25°C

TJ = −40°C

Figure 7. Drop Voltage Vdr vs. Output Current IQ

100

200

300

400

500

0 30 60 90 120 150 180

Figure 8. Reset Adjust Switching Threshold,

VRADJ,TH vs. Temperature TJ

Figure 9. Current Consumption Iq vs. Input

Voltage VI

Figure 10. Output Voltage VQ vs. Input Voltage VI

VQ (V)

VI, (V)

246810

RL = 50 W

Figure 11. Sense Threshold VSI vs. Temperature TJFigure 12. Output Voltage VQ vs. Temperature TJ

1.6

−40 0 40 80 120 160

TJ, (°C)

VSI, (V)

VI = 13.5 V

1.5

1.4

1.3

1.2

1.1

1.0

VSI, High

VSI, Low

5.2

−40 0 40 80 120 160

TJ, (°C)

VQ, (V)

VI = 13.5 V

5.1

5.0

4.9

4.8

4.7

4.6

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TYPICAL PERFORMANCE CHARACTERISTICS

250

Iq, (mA)

VI, (V)

IQ = 100 mA

8 1012141618 20222426

1.6

01020 4050

IQ, (mA)

Iq, (mA)

VI, (V)

IQ = 100 mA

IQ = 50 mA

IQ = 10 mA

VI, (V)

IQ, (mA)

TJ = 125°C

TJ = 25°C

350

0 1020304050

300

250

200

150

100

02040 80 12

IQ, (mA)

Iq, (mA)

VI = 13.5 V

TJ = 25°C

Figure 13. Output Current Limit IQ vs. Input

Voltage VI

Figure 14. Current Consumption Iq vs. Output

Current IQ

Figure 15. Current Consumption Iq vs.

Output Current IQ

Figure 16. Quiescent Current Iq vs.

Input Voltage VI

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

VI = 13.5 V

TJ = 25°C

100

8101214161820222426

Figure 17. Quiescent Current Iq vs. Input Voltage VIFigure 18. Output Stability, Capacitance ESR

vs. Output Load Current

200

150

100

TJ = 25°C

100

ESR (W)

OUTPUT CURRENT IN MILLIAMPS

Unstable Region

0.1 25 50 75 100 125 150

Stable Region for

2.2 mF to 10 mF

TJ = 125°C

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TYPICAL THERMAL CHARACTERISTICS

SO−8 Std Package NCV4269A, 1.0 oz

SO−8 Std Package NCV4269A, 2.0 oz

SO−14 w/6 Thermal Leads NCV4269A, 1.0 oz

SO−14 w/6 Thermal Leads NCV4269A, 2.0 oz

SO−20 w/8 Thermal Leads NCV4269A, 1.0 oz

SO−20 w/8 Thermal Leads NCV4269A, 2.0 oz

Figure 19. Junction−to−Ambient Thermal Resistance (qJA) vs. Heat Spreader Area

Figure 20. R(t) vs. Pulse Time

qJA (°C/W)

COPPER HEAT−SPREADER AREA (mm2)

700600400300200100 5000

200

180

160

140

120

100

Single Pulse (SO−8 Std Package) PCB = 50 mm2, 2.0 oz

Single Pulse (SO−8 EP Package)

Single Pulse (SO−14 w/6 Thermal Leads) PCB = 50 mm2, 2.0 oz

Single Pulse (SO−20 w/8 Thermal Leads) PCB = 50 mm2, 2.0 oz

YLA (SO−8)

YLA (SO−14)

YLA (SO−20)

R(t) (°C/W)

PULSE TIME (s)

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

1000

100

0.1

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APPLICATION DESCRIPTION

OUTPUT REGULATOR

The output is controlled by a precision trimmed reference.

The PNP output has base drive quiescent current control for

regulation while the input voltage is low, preventing over

saturation. Current limit and voltage monitors complement

the regulator design to give safe operating signals to the

processor and control circuits.

RESET OUTPUT (RO)

A reset signal, Reset Output, RO, (low voltage) is

generated as the IC powers up. After the output voltage VQ

increases above the reset threshold voltage VRT, the delay

timer D is started. When the voltage on the delay timer VD

passes VUD, the reset signal RO goes high. A discharge of

the delay timer VD is started when VQ drops and stays below

the reset threshold voltage VRT. When the voltage of the

delay timer VD drops below the lower threshold voltage VLD

the reset output voltage VRO is brought low to reset the

processor.

The reset output RO is an open collector NPN transistor

with an internal 20 kW pullup resistor connected to the

output Q, controlled by a low voltage detection circuit. The

circuit is functionally independent of the rest of the IC,

thereby guaranteeing that RO is valid for VQ as low as 1.0 V.

RESET ADJUST (RADJ)

The reset threshold VRT can be decreased from a typical

value of 4.65 V to as low as 3.5 V by using an external

voltage divider connected from the Q lead to the pin RADJ,

as shown in Figure 21. The resistor divider keeps the voltage

above the VRADJ,TH (typical 1.35 V) for the desired input

voltages, and overrides the internal threshold detector.

Adjust the voltage divider according to the following

relationship:

VRT +VRADJ, TH @(RADJ1 )RADJ2)ńRADJ2 (eq. 1)

If the reset adjust option is not needed, the RADJ pin

should be connected to GND causing the reset threshold to

go to its default value (typically 4.65 V).

RESET DELAY (D)

The reset delay circuit provides a delay (programmable by

capacitor CD) on the reset output lead RO. The delay lead D

provides charge current ID,C (typically 6.5 mA) to the

external delay capacitor CD during the following times:

1. During Powerup (once the regulation threshold has

been exceeded).

2. After a reset event has occurred and the device is

back in regulation. The delay capacitor is set to

discharge when the regulation (VRT, reset

threshold voltage) has been violated. When the

delay capacitor discharges to VLD, the reset signal

RO pulls low.

SETTING THE DELAY TIME

The delay time is set by the delay capacitor CD and the

charge current ID. The time is measured by the delay

capacitor voltage charging from the low level of VDSAT to

the higher level VUD. The time delay follows the equation:

td+[CD(VUD *VD, SAT)]ńID, C (eq. 2)

Example:

Using CD = 100 nF.

Use the typical value for VD,SAT = 0.1 V.

Use the typical value for VUD = 1.8 V.

Use the typical value for Delay Charge Current ID = 6.5 mA.

td+[100 nF (1.8 *0.1 V)] ń6.5 mA+26.2 ms (eq. 3)

GND

RADJ

NCV4269A

CQ**

10 mF

(2.2 mF)

0.1 mF

Microprocessor

VBAT VDD

Figure 21. Application Diagram

I/O I/O

RADJ2

RADJ1

RSI1

RSI2

CI*

*CI required if regulator is located far from the power supply filter.

** CQ − minimum cap required for stability is 2.2 mF while higher over/under−shoots may be

expected. Cap must operate at minimum temperature expected.

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SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE

MONITOR

An on−chip comparator is available to provide early

warning to the microprocessor of a possible reset signal

(Figure 4). The output is from an open collector driver with

an internal 20 kW pull up resistor to output Q. The reset signal

typically turns the microprocessor off instantaneously. This

can cause unpredictable results with the microprocessor. The

signal received from the SO pin will allow the microprocessor

time to complete its present task before shutting down. This

function is performed by a comparator referenced to the band

gap voltage. The actual trip point can be programmed

externally using a resistor divider to the input monitor SI

(Figure 21). The values for RSI1 and RSI2 are selected for a

typical threshold of 1.20 V on the SI Pin.

SIGNAL OUTPUT

Figure 22 shows the SO Monitor timing waveforms as a

result of the circuit depicted in Figure 21. As the output

voltage (VQ) falls, the monitor threshold (VSI,Low), is

crossed. This causes the voltage on the SO output to go low

sending a warning signal to the microprocessor that a reset

signal may occur in a short period of time. TWA RNIN G is the

time the microprocessor has to complete the function it is

currently working on and get ready for the reset

shutdown signal. When the voltage on the SO goes low and

the RO stays high the current consumption is typically

560 mA at 1 mA load current.

Figure 22. SO Warning Waveform Time Diagram

VRO

VSI,Low

TWARNING

STABILITY CONSIDERATIONS

The input capacitor CI in Figure 21 is necessary for

compensating input line reactance. Possible oscillations caused

by input inductance and input capacitance can be damped by

using a resistor of approximately 1.0 W in series with CI.

The output or compensation capacitor helps determine

three main characteristics of a linear regulator: startup delay,

load transient response and loop stability.

The capacitor value and type should be based on cost,

availability, size and temperature constraints. The

aluminum electrolytic capacitor is the least expensive

solution, but, if the circuit operates at low temperatures

(−25°C to −40°C), both the value and ESR of the capacitor

will vary considerably. The capacitor manufacturer’s data

sheet usually provides this information.

The 10 mF output capacitor CQ shown in Figure 21 should

work for most applications; however, it is not necessarily the

optimized solution. Stability is guaranteed at CQ is min

2.2 mF and max ESR is 10 W. There is no min ESR limit

which was proved with MURATA’s ceramic caps

GRM31MR71A225KA01 (2.2 mF, 10 V, X7R, 1206) and

GRM31CR71A106KA01 (10 mF, 10 V, X7R, 1206) directly

soldered between output and ground pins.

CALCULATING POWER DISSIPATION IN A SINGLE

OUTPUT LINEAR REGULATOR

The maximum power dissipation for a single output

regulator (Figure 21) is:

PD(max) +[VI(max) *VQ(min)]I

Q(max) )VI(max)Iq(eq. 4)

where:

VI(max) is the maximum input voltage,

VQ(min) is the minimum output voltage,

IQ(max) is the maximum output current for the application,

and Iq is the quiescent current the regulator consumes at

IQ(max).

Once the value of PD(max) is known, the maximum

permissible value of RqJA can be calculated:

(eq. 5)

RqJA = (150°C – TA) / PD

The value of RqJA can then be compared with those in the

package section of the data sheet. Those packages with

RqJA

’s less than the calculated value in equation 2 will keep

the die temperature below 150°C. In some cases, none of the

packages will be sufficient to dissipate the heat generated by

the IC, and an external heatsink will be required. The current

flow and voltages are shown in the

Measurement Circuit Diagram.

HEATSINKS

A heatsink effectively increases the surface area of the

package to improve the flow of heat away from the IC and

into the surrounding air.

Each material in the heat flow path between the IC and the

outside environment will have a thermal resistance. Like

series electrical resistances, these resistances are summed to

determine the value of RqJA:

RqJA +RqJC )RqCS )RqSA (eq. 6)

where:

RqJC = the junction−to−case thermal resistance,

RqCS = the case−to−heat sink thermal resistance, and

RqSA = the heat sink−to−ambient thermal resistance.

RqJC appears in the package section of the data sheet. Like

RqJA, it too is a function of package type. RqCS and RqSA are

functions of the package type, heatsink and the interface

between them. These values appear in data sheets of

heatsink manufacturers. Thermal, mounting, and

heatsinking considerations are discussed in the

ON Semiconductor application note AN1040/D, available

on the ON Semiconductor website.

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ORDERING INFORMATION

Device Output Voltage Package Shipping†

NCV4269AD150G

5.0 V

SO−8

(Pb−Free) 98 Units/Rail

NCV4269AD150R2G SO−8

(Pb−Free) 2500 Tape & Reel

NCV4269APD50G SO−8 EP

(Pb−Free) 98 Units/Rail

NCV4269APD50R2G SO−8 EP

(Pb−Free) 2500 Tape & Reel

NCV4269AD250G SO−14

(Pb−Free) 55 Units/Rail

NCV4269AD250R2G SO−14

(Pb−Free) 2500 Tape & Reel

NCV4269ADW50G SO−20L

(Pb−Free) 38 Units/Rail

NCV4269ADW50R2G SO−20L

(Pb−Free) 1000 Tape & Reel

†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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PACKAGE DIMENSIONS

SOIC−8 EP

CASE 751AC−01

ISSUE B

ÉÉÉ

ÉÉ

ÇÇ

C0.10

PIN ONE

2 X

8 X

SEATING

PLANE

EXPOSED

GAUGE

PLANE

C0.10 A-B

2 X

C0.10

2 X

TOP VIEW

SIDE VIEW

BOTTOM VIEW

DETAIL A

END VIEW

SECTION A−A

8 X b

A-B0.25 D

C0.10

C0.20

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS (ANGLES

IN DEGREES).

3. DIMENSION b DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE

0.08 MM TOTAL IN EXCESS OF THE “b”

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

4. DATUMS A AND B TO BE DETERMINED

AT DATUM PLANE H.

DIM MIN MAX

MILLIMETERS

A1.35 1.75

A1 0.00 0.10

A2 1.35 1.65

b0.31 0.51

b1 0.28 0.48

c0.17 0.25

c1 0.17 0.23

D4.90 BSC

E6.00 BSC

e1.27 BSC

L0.40 1.27

L1 1.04 REF

F2.24 3.20

G1.55 2.51

h0.25 0.50

q0 8

DETAIL A

(b)

0.25

(L1)

PAD

E1 3.90 BSC

LOCATION

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Exposed

Pad

1.52

0.060

2.03

0.08

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

7.0

0.275

2.72

0.107

NCV4269A

http://onsemi.com

PACKAGE DIMENSIONS

SO−14

CASE 751A−03

ISSUE G

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

−A−

−B−

P7 PL

14 8

71 M

0.25 (0.010) B M

0.25 (0.010) A S

−T−

RX 45

SEATING

PLANE D14 PL K

_DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

__ __

NCV4269A

http://onsemi.com

PACKAGE DIMENSIONS

SO−20 WB

CASE 751D−05

ISSUE G

B20X

H10X

18X A1

SEATING

PLANE

hX 45_

0.25 M

0.25 S

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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NCV4269A/D

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