FDB070AN06A0_F085 N-Channel PowerTrench
FDB070AN06A0_F085
N-Channel PowerTrench® MOSFET
60V, 80A, 7mΩ
Features
•r
DS(ON) = 6.1mΩ (Typ.), VGS = 10V, ID = 80A
•Q
g(tot) = 51nC (Typ.), VGS = 10V
• Low Miller Charge
•Low Q
RR Body Diode
• UIS Capability (Single Pulse and Repetitive Pulse)
• Qualified to AEC Q101
Formerly developmental type 82567
Applications
• Motor / Body Load Control
• ABS Systems
• Powertrain Management
• Injection Systems
• DC-DC converters and Off-line UPS
• Distributed Power Architectures and VRMs
• Primary Switch for 12V and 24V systems
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Thermal Characteristics
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 60 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current
80 A
Continuous (TC < 97oC, VGS = 10V)
Continuous (TA = 25oC, VGS = 10V, RθJA = 43oC/W) 15 A
Pulsed Figure 4 A
EAS Single Pulse Avalanche Energy (Note 1) 190 mJ
PD
Power dissipation 175 W
Derate above 25oC1.17W/
oC
TJ, TSTG Operating and Storage Temperature -55 to 175 oC
RθJC Thermal Resistance Junction to Case TO-220,TO-263 0.86 oC/W
RθJA Thermal Resistance Junction to Ambient TO-220,TO-263 (Note 2) 62 oC/W
RθJA Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43 oC/W
D
G
S
TO-263AB
FDB SERIES
GATE
SOURCE DRAIN
(FLANGE)
May 2012
• RoHS Compliant
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
® MOSFET
Package Marking and Ordering Information
Electrical Characteristics TC = 25°C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics (VGS = 10V)
Drain-Source Diode Characteristics
Notes:
1: Starting TJ = 25°C, L = 93µH, IAS = 64A.
2: Pulse width = 100s.
Device Marking Device Package Reel Size Tape Width Quantity
FDB070AN06A0 FDB070AN06A0_F085 TO-263AB 330mm 24mm 800 units
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 60 - - V
IDSS Zero Gate Voltage Drain Current VDS = 50V - - 1 µA
VGS = 0V TC = 150oC- -250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V
rDS(ON) Drain to Source On Resistance
ID = 80A, VGS = 10V - 0.0061 0.007
Ω
ID = 80A, VGS = 10V,
TJ = 175oC- 0.0127 0.015
CISS Input Capacitance VDS = 25V, VGS = 0V,
f = 1MHz
- 3000 - pF
COSS Output Capacitance - 510 - pF
CRSS Reverse Transfer Capacitance - 230 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V
VDD = 30V
ID = 80A
Ig = 1.0mA
51 66 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 2V - 5.4 7 nC
Qgs Gate to Source Gate Charge - 17 - nC
Qgs2 Gate Charge Threshold to Plateau - 11.6 - nC
Qgd Gate to Drain “Miller” Charge - 16 - nC
tON Turn-On Time
VDD = 30V, ID = 80A
VGS = 10V, RGS = 5.6Ω
--256ns
td(ON) Turn-On Delay Time - 12 - ns
trRise Time - 159 - ns
td(OFF) Turn-Off Delay Time - 27 - ns
tfFall Time - 35 - ns
tOFF Turn-Off Time - - 93 ns
VSD Source to Drain Diode Voltage ISD = 80A - - 1.25 V
ISD = 40A - - 1.0 V
trr Reverse Recovery Time ISD = 75A, dISD/dt = 100A/µs- -34ns
QRR Reverse Recovered Charge ISD = 75A, dISD/dt = 100A/µs- -35nC
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0255075100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
0
20
40
60
80
100
120
25 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
CURRENT LIMITED
BY PACKAGE
0.1
1
10-5 10-4 10-3 10-2 10-1 100101
0.01
2
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
THERMAL IMPEDANCE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
100
1000
2000
50
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
10-5 10-4 10-3 10-2 10-1 100101
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 10V
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics
Figure 9. Drain to Source On Resistance vs Drain
Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
Typical Characteristics TC = 25°C unless otherwise noted
0.1
1
10
100
1000
110100
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
SINGLE PULSE
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
10µs
1ms
DC
100µs
10ms
1
10
100
0.01 0.1 1 10 100
500
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0
40
80
120
160
4.0 4.5 5.0 5.5 6.0 6.5 7.0
ID, DRAIN CURRENT (A)
VGS , GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 175oC
TJ = 25oC
TJ = -55oC
0
40
80
120
160
00.51.01.52.0
ID, DRAIN CURRENT (A)
VDS , DRAIN TO SOURCE VOLTAGE (V)
VGS = 6V
VGS = 5V
VGS = 10V VGS = 7V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
6
8
10
12
14
16
0 20406080
ID, DRAIN CURRENT (A)
VGS = 6V
VGS = 10V
DRAIN TO SOURCE ON RESISTANCE(mΩ)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.5
1.0
1.5
2.0
2.5
-80 -40 0 40 80 120 160 200
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID =80A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Current
Typical Characteristics TC = 25°C unless otherwise noted
0.4
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 160 200
VGS = VDS, ID = 250µA
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
0.90
0.95
1.00
1.05
1.10
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
BREAKDOWN VOLTAGE
100
1000
10000
0.1 1 10 60
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
0
2
4
6
8
10
0 102030405060
VGS , GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 30V
ID = 80A
ID = 15A
WAVEFORMS IN
DESCENDING ORDER:
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS +
-
VDS
VDD
DUT
Ig(REF)
L
VDD
Qg(TH)
VGS = 2V
Qgs2
Qg(TOT)
VGS = 10V
VDS VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%50%
10%
PULSE WIDTH
VGS
0
0
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
(EQ. 1)
PDM
TJM TA
–()
RθJA
-----------------------------=
Area in Inches Squared
(EQ. 2)
RθJA 26.51 19.84
0.262 Area+()
-------------------------------------+
=
(EQ. 3)
RθJA 26.51 128
1.69 Area+()
----------------------------------+
=
Area in Centimeters Squared
Figure 21. Thermal Resistance vs Mounting
Pad Area
20
40
60
80
1100.1
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA (oC/W)
AREA, TOP COPPER AREA in2 (cm2)
(0.645) (6.45) (64.5)
RθJA = 26.51+ 128/(1.69+Area) EQ.3
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
PSPICE Electrical Model
.SUBCKT FDB070AN06A0 2 1 3 ; rev March 2003
Ca 12 8 1.5e-9
Cb 15 14 1.5e-9
Cin 6 8 2.9e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 62
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 4.8e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 3e-9
RLgate 1 9 48
RLdrain 2 5 10
RLsource 3 7 3
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.3e-3
Rgate 9 20 2.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3.1e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))}
.MODEL DbodyMOD D (IS=7.6E-12 N=1.04 RS=2.2e-3 TRS1=2.7e-3 TRS2=2e-7
+ CJO=1.6e-9 M=0.55 TT=5e-12 XTI=3.9)
.MODEL DbreakMOD D (RS=8e-1 TRS1=5e-4 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.05e-9 IS=1e-30 N=10 M=0.45)
.MODEL MmedMOD NMOS (VTO=3.7 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.7)
.MODEL MstroMOD NMOS (VTO=4.7 KP=100 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.01 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=27 RS=0.1)
.MODEL RbreakMOD RES (TC1=7.1e-4 TC2=-5.5e-7)
.MODEL RdrainMOD RES (TC1=1.7e-2 TC2=4e-5)
.MODEL RSLCMOD RES (TC1=3e-3 TC2=1e-5)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.2e-3 TC2=-1.5e-5)
.MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
SABER Electrical Model
rev March 2003
template FDB070AN06A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=7.6e-12,nl=1.04,rs=2.2e-3,trs1=2.7e-3,trs2=2e-7,cjo=1.6e-9,m=0.55,tt=5e-12,xti=3.9)
dp..model dbreakmod = (rs=8e-1,trs1=5e-4,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.05e-9,isl=10e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=3.7,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.7,kp=100,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.01,kp=0.03,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.5)
c.ca n12 n8 = 1.5e-9
c.cb n15 n14 = 1.5e-9
c.cin n6 n8 = 2.9e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 62
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 4.8e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 3e-9
res.rlgate n1 n9 = 48
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=7.1e-4,tc2=-5.5e-7
res.rdrain n50 n16 = 1.3e-3, tc1=1.7e-2,tc2=4e-5
res.rgate n9 n20 = 2.7
res.rslc1 n5 n51 = 1e-6, tc1=3e-3,tc2=1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.1e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.2e-3,tc2=-1.5e-5
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1.3e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
PSPICE Thermal Model
REV 23 March 2003
FDB070AN06A0T
CTHERM1 TH 6 3.5e-3
CTHERM2 6 5 1.7e-2
CTHERM3 5 4 1.8e-2
CTHERM4 4 3 1.9e-2
CTHERM5 3 2 4.7e-2
CTHERM6 2 TL 7e-2
RTHERM1 TH 6 2e-2
RTHERM2 6 5 7e-2
RTHERM3 5 4 1e-1
RTHERM4 4 3 1.5e-1
RTHERM5 3 2 1.6e-1
RTHERM6 2 TL 1.85e-1
SABER Thermal Model
SABER thermal model FDB070AN06A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.5e-3
ctherm.ctherm2 6 5 =1.7e-2
ctherm.ctherm3 5 4 =1.8e-2
ctherm.ctherm4 4 3 =1.9e-2
ctherm.ctherm5 3 2 =4.7e-2
ctherm.ctherm6 2 tl =7e-2
rtherm.rtherm1 th 6 =2e-2
rtherm.rtherm2 6 5 =7e-2
rtherm.rtherm3 5 4 =1e-1
rtherm.rtherm4 4 3 =1.5e-1
rtherm.rtherm5 3 2 =1.6e-1
rtherm.rtherm6 2 tl =1.85e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
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tm
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Rev. I61
tm
®
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
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