LM9036M-5.0/NOPB - NATIONAL SEMICONDUCTOR

LM9036

www.ti.com

SNVS140E –AUGUST 2003–REVISED MARCH 2013

LM9036 Ultra-Low Quiescent Current Voltage Regulator

Check for Samples: LM9036

1FEATURES DESCRIPTION

The LM9036 ultra-low quiescent current regulator

2• Ultra low Ground Pin Current (IGND ≤25µA for features low dropout voltage and low current in the

IOUT = 0.1mA) standby mode. With less than 25µA Ground Pin

• Fixed 5V, 3.3V, 50mA Output current at a 0.1mA load, the LM9036 is ideally suited

• Output Tolerance ±5% Over Line, Load, and for automotive and other battery operated systems.

The LM9036 retains all of the features that are

Temperature common to low dropout regulators including a low

• Dropout Voltage Typically 200mV @ IOUT =dropout PNP pass device, short circuit protection,

50mA reverse battery protection, and thermal shutdown.

•−45V Reverse Transient Protection The LM9036 has a 40V maximum operating voltage

limit, a −40°C to +125°C operating temperature

• Internal Short Circuit Current Limit range, and ±5% output voltage tolerance over the

• Internal Thermal Shutdown Protection entire output current, input voltage, and temperature

• 40V Operating Voltage Limit range.

Typical Application

* Required if regulator is located more than 2″from power supply filter capacitor.

** Required for stability. Must be rated over intended operating temperature range. Effective series resistance (ESR)

is critical, see Electrical Characteristics. Locate capacitor as close as possible to the regulator output and ground

pins. Capacitance may be increased without bound.

Connection Diagram

Figure 1. PFM

Top View

Order Number LM9036DT-5.0, LM9036DTX-5.0,

LM9036DT-3.3, LM9036DTX-3.3

See NS Package Number NDP0003B

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM9036

SNVS140E –AUGUST 2003–REVISED MARCH 2013

www.ti.com

Figure 2. 8 Lead VSSOP Figure 3. 8 Lead SOIC

Top View Top View

LM9036MM-3.3, , LM9036MMX-3.3, LM9036MM-5.0, LM9036M-3.3, LM9036MX-3.3, LM9036M-5.0,

LM9036MMX-5.0 LM9036MX-5.0

See NS Package Number DGK See NS Package Number D

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)

Input Voltage (Survival) +55V, −45V

ESD Susceptibility(3) ±1.9kV

Power Dissipation(4) Internally limited

Junction Temperature (TJmax) 150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature (Soldering, 10 sec.) 260°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not

apply when operating the device beyond its specified operating ratings.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) Human body model, 100pF discharge through a 1.5kΩresistor.

(4) The maximum power dissipation is a function of TJmax,θJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJmax −TA)/θJA. If this dissipation is exceeded, the die temperature will rise above 150°C and the LM9036 will go

into thermal shutdown.

Operating Ratings

Operating Temperature Range −40°C to +125°C

Maximum Input Voltage (Operational) 40V

SOIC-8 (D) θJA(1) 140°C/W

PFM (NDP0003B) θJA(1) 125°C/W

PFM (NDP0003B) θJA(2) 50°C/W

PFM (NDP0003B) θJC(1) 11°C/W

MSO-8 (DGK) θJA(1) 200°C/W

(1) Worst case (Free Air) per EIA / JESD51-3.

(2) Typical θJA with 1 square inch of 2oz copper pad area directly under the ground tab.

Product Folder Links: LM9036

LM9036

www.ti.com

SNVS140E –AUGUST 2003–REVISED MARCH 2013

Electrical Characteristics - LM9036-5.0

VIN = 14V, IOUT = 10 mA, TJ= 25°C, unless otherwise specified. Boldface limits apply over entire operating temperature

range Min Typical Max

Parameter Conditions Units

(1) (2) (1)

4.80 5.00 5.20

Output Voltage (VOUT) V

5.5V ≤VIN ≤26V, 4.75 5.00 5.25

0.1mA ≤IOUT ≤50mA(3)

IOUT = 0.1mA, 8V ≤VIN ≤24V 20 25 µA

IOUT = 1mA, 8V ≤VIN ≤24V 50 100

Quiescent Current (IGND)IOUT = 10mA, 8V ≤VIN ≤24V 0.3 0.5 mA

IOUT = 50mA, 8V ≤VIN ≤24V 2.0 2.5

Line Regulation (ΔVOUT) 6V ≤VIN ≤40V, IOUT = 1mA 10 30 mV

Load Regulation (ΔVOUT) 0.1mA ≤IOUT ≤5mA 10 30 mV

5mA ≤IOUT ≤50mA 10 30 mV

Dropout Voltage (ΔVOUT) IOUT = 0.1mA 0.05 0.10 V

IOUT = 50mA 0.20 0.40 V

Short Circuit Current (ISC) VOUT = 0V 65 120 250 mA

Ripple Rejection (PSRR) Vripple = 1Vrms, Fripple = 120Hz −40 −60 dB

Output Bypass Capacitance 0.3Ω ≤ ESR ≤8Ω10 22 µF

(COUT) 0.1mA ≤IOUT ≤50mA

(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level) and 100% tested.

(2) Typicals are at 25°C (unless otherwise specified) and represent the most likely parametric norm.

(3) To ensure constant junction temperature, pulse testing is used.

Electrical Characteristics - LM9036-3.3

VIN = 14V, IOUT = 10 mA, TJ= 25°C, unless otherwise specified. Boldface limits apply over entire operating temperature

range Min Typical Max

Parameter Conditions Units

(1) (2) (1)

3.168 3.30 3.432

Output Voltage (VOUT) V

5.5V ≤VIN ≤26V, 3.135 3.30 3.465

0.1mA ≤IOUT ≤50mA(3)

IOUT = 0.1mA, 8V ≤VIN ≤24V 20 25 µA

IOUT = 1mA, 8V ≤VIN ≤24V 50 100

Quiescent Current (IGND)IOUT = 10mA, 8V ≤VIN ≤24V 0.3 0.5 mA

IOUT = 50mA, 8V ≤VIN ≤24V 2.0 2.5

Line Regulation (ΔVOUT) 6V ≤VIN ≤40V, IOUT = 1mA 10 30 mV

Load Regulation (ΔVOUT) 0.1mA ≤IOUT ≤5mA 10 30 mV

5mA ≤IOUT ≤50mA 10 30 mV

Dropout Voltage (ΔVOUT) IOUT = 0.1mA 0.05 0.10 V

IOUT = 50mA 0.20 0.40 V

Short Circuit Current (ISC) VOUT = 0V 65 120 250 mA

Ripple Rejection (PSRR) Vripple = 1Vrms, Fripple = 120Hz −40 −60 dB

Output Bypass Capacitance 0.3Ω ≤ ESR ≤8Ω22 33 µF

(COUT) 0.1mA ≤IOUT ≤50mA

(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level) and 100% tested.

(2) Typicals are at 25°C (unless otherwise specified) and represent the most likely parametric norm.

(3) To ensure constant junction temperature, pulse testing is used.

Product Folder Links: LM9036

LM9036

SNVS140E –AUGUST 2003–REVISED MARCH 2013

www.ti.com

Typical Performance Characteristics

Dropout Voltage Quiescent Current

Figure 4. Figure 5.

Quiescent Current Quiescent Current

Figure 6. Figure 7.

Peak Output Current

Figure 8.

Product Folder Links: LM9036

LM9036

www.ti.com

SNVS140E –AUGUST 2003–REVISED MARCH 2013

APPLICATIONS INFORMATION

Unlike other PNP low dropout regulators, the LM9036 remains fully operational to 40V. Owing to power

dissipation characteristics of the package, full output current cannot be ensured for all combinations of ambient

temperature and input voltage.

The junction to ambient thermal resistance θJA rating has two distinct components: the junction to case thermal

resistance rating θJC; and the case to ambient thermal resistance rating θCA. The relationship is defined as: θJA =

θJC +θCA.

On the PFM package the ground tab is thermally connected to the backside of the die. Adding 1 square inch of 2

oz. copper pad area directly under the ground tab will improve the θJA rating to approximately 50°C/W.

While the LM9036 has an internally set thermal shutdown point of typically 150°C, this is intended as a safety

feature only. Continuous operation near the thermal shutdown temperature should be avoided as it may have a

negative affect on the life of the device.

Using the θJA for a LM9036DT mounted on a circuit board as defined at, see(1), and using the formula for

maximum allowable dissipation given in, see(2), for an ambient temperature (TA) of +85°C, we find that PDMAX =

1.3W. Including the small contribution of the quiescent current IQto the total power dissipation, the maximum

input voltage (while still delivering 50mA output current) is 29.5V. The LM9036DT will go into thermal shutdown

when attempting to deliver the full output current of 50mA, with an ambient temperature of +85°C, and the input

voltage is greater than 29.5V. Similarly, with an ambient temperature of 25°C the PDMAX = 2.5W, and the

LM9036DT can deliver the full output current of 50mA with an input voltage of up to 40V.

While the LM9036 maintains regulation to 55V, it will not withstand a short circuit above 40V because of safe

operating area limitations in the internal PNP pass device. Above 55V the LM9036 will break down with

catastrophic effects on the regulator and possibly the load as well. Do not use this device in a design where the

input operating voltage may exceed 40V, or where transients are likely to exceed 55V.

(1) Typical θJA with 1 square inch of 2oz copper pad area directly under the ground tab.

(2) The maximum power dissipation is a function of TJmax,θJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJmax −TA)/θJA. If this dissipation is exceeded, the die temperature will rise above 150°C and the LM9036 will go

into thermal shutdown.

Product Folder Links: LM9036

LM9036

SNVS140E –AUGUST 2003–REVISED MARCH 2013

www.ti.com

REVISION HISTORY

Changes from Revision D (March 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format ............................................................................................................ 5

Product Folder Links: LM9036

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM9036DT-5.0/NOPB ACTIVE TO-252 NDP 3 75 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM9036D

T-5.0

LM9036DTX-5.0/NOPB ACTIVE TO-252 NDP 3 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM9036D

T-5.0

LM9036M-3.3/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM903

6M-3

LM9036M-5.0 NRND SOIC D 8 95 Non-RoHS

& Green Call TI Call TI -40 to 125 LM903

6M-5

LM9036M-5.0/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM903

6M-5

LM9036MM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 KDB

LM9036MM-5.0/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 KDA

LM9036MX-3.3/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM903

6M-3

LM9036MX-5.0/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM903

6M-5

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 2

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM9036DTX-5.0/NOPB TO-252 NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2

LM9036MM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM9036MM-5.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM9036MX-3.3/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM9036MX-5.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM9036DTX-5.0/NOPB TO-252 NDP 3 2500 367.0 367.0 38.0

LM9036MM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LM9036MM-5.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LM9036MX-3.3/NOPB SOIC D 8 2500 367.0 367.0 35.0

LM9036MX-5.0/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

10.42

9.40

6.73

6.35

6.22

5.97 1.27

0.88

5.46

4.96

2.285

4.57

1.02

0.64

3X 0.88

0.64

2.55 MAX

0.88

0.46

1.14

0.89

0.60

0.46

0.17

0.51 MIN

4.32 MIN

(2.345)

(2.5)

TO-252 - 2.55 mm max heightNDP0003B

TRANSISTOR OUTLINE

4219870/A 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC registration TO-252.

0.25 C A B

TOP & BOTTOM

PKG

OPTIONAL

SEATING PLANE

SCALE 1.500

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

(4.57)

2X (1.3) 2X (2.15) (5.7)

(5.5)

(2.285)(4.38)

(R0.05) TYP

TO-252 - 2.55 mm max heightNDP0003B

TRANSISTOR OUTLINE

4219870/A 03/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers

SLMA002(www.ti.com/lit/slm002) and SLMA004 (www.ti.com/lit/slma004).

5. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SYMM

PKG

SEE SOLDER MASK

DETAIL

EXPOSED

METAL

METAL EDGE

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED) SOLDER MASK DETAIL

EXPOSED

METAL

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

2X (2.15)

2X (1.3)

(4.57)

(4.38)

(1.32) TYP

(1.35) TYP

(0.26) (R0.05) TYP

16X (1.12)

16X (1.15)

TO-252 - 2.55 mm max heightNDP0003B

TRANSISTOR OUTLINE

4219870/A 03/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 8X

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265