LT1027
1
sn1027 1027fcs
Precision
5V Reference
ANALOG
INPUTS
V
IN
V
OUT
V
TRIM
GND
10k 22µF
8V TO 40V
LT1027
TO µC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V
CC
REF
+
REF
–
COM
AGND V
–
DGND
LTC1290
1027 TA01
S
CLK
A
CLK
D
OUT
D
IN
CS
+
2.2µF
+
TEMPERATURE (°C)
–50
OUTPUT VOLTAGE (V)
5.002
5.004
5.006
25 75
1027 TA02
5.000
4.998
–25 0 50 100
4.996
4.994
Output Voltage
, LTC and LT are registered trademarks of Linear Technology Corporation.
Supplying V
REF
and V
CC
to the LTC
®
1290 12-bit ADC
■
Very Low Drift: 2ppm/°C Max TC
■
Pin Compatible with LT1021-5, REF-02,
(PDIP Package)
■
Output Sources 15mA, Sinks 10mA
■
Excellent Transient Response Suitable for
A-to-D Reference Inputs
■
Noise Reduction Pin
■
Excellent Long Term Stability
■
Less Than 1ppm
P-P
Noise (0.1Hz to 10Hz)
The LT
®
1027 is a precision reference with extra-low drift,
superior accuracy, excellent line and load regulation and
low output impedance at high frequency. This device is
intended for use in 12- to 16-bit A-to-D and D-to-A
systems where demanding accuracy requirements must
be met without the use of power hungry, heated substrate
references. The fast settling output recovers quickly from
load transients such as those presented by A-to-D converter
reference inputs. The LT1027 brings together both
outstanding accuracy and temperature coefficient
specifications.
The LT1027 reference is based on LTC’s proprietary
advanced subsurface Zener bipolar process which
eliminates noise and stability problems associated with
surface breakdown devices.
■
A-to-D and D-to-A Converters
■
Digital Voltmeters
■
Reference Standard
■
Precision Current Source
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
LT1027
2
sn1027 1027fcs
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OUT
Output Voltage (Note 2) LT1027A 4.9990 5.000 5.0010 V
LT1027B, C, D 4.9975 5.000 5.0025
LT1027E 4.9950 5.000 5.0050
TCV
OUT
Output Voltage Temperature Coefficient LT1027A, B ●1 2 ppm/°C
(Note 3) LT1027C ●23
LT1027D ●25
LT1027E ●3 7.5
Supply Voltage (V
IN
)............................................... 40V
Input-Output Voltage Differential ............................ 35V
Output to Ground Voltage ......................................... 7V
V
TRIM
to Ground Voltage
Positive ................................................................ 5V
Negative .......................................................... –0.3V
Output Short-Circuit Duration
V
IN
> 20V........................................................ 10 sec
V
IN
≤ 20V ................................................... Indefinite
Operating Temperature Range
LT1027C................................................ 0°C to 70°C
LT1027M (OBSOLETE) ............... –55°C to 125°C
Storage Temperature Range
All Devices....................................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
WU
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
NC*
NC*
NC*
V
IN
V
OUT
V
TRIM
NR
GND
87
6
5
3
2
1
4
H PACKAGE
8-LEAD TO-5 METAL CAN
T
JMAX
= 150°C, θ
JA
= 150°C/W, θ
JC
= 45°C/W
ORDER PART NUMBER ORDER PART NUMBER ORDER PART NUMBER
T
JMAX
= 100°C, θ
JA
= 130°C/W T
JMAX
= 100°C, θ
JA
= 180°C/W
1
2
3
4
8
7
6
5
TOP VIEW
V
IN
NC*
NC*
NC*
NR
GND
V
TRIM
V
OUT
S8 PACKAGE
8-LEAD PLASTIC SO
1
2
3
45
6
7
8
TOP VIEW
NC*
NC*
NC*
V
IN
V
OUT
V
TRIM
NR
GND
N8 PACKAGE
8-LEAD PDIP
LT1027ACH-5
LT1027BCH-5
LT1027CCH-5
LT1027DCH-5
LT1027ECH-5
LT1027BCN8-5
LT1027CCN8-5
LT1027DCN8-5
LT1027ECN8-5
LT1027CCS8-5
LT1027DCS8-5
LT1027ECS8-5
1027C5
1027D5
1027E5
S8 PART MARKING
*Connected internally. Do not connect external circuitry to these pins. Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL C CHARA TERISTICS
The ● denotes specifications which apply over the full operating
temperature range otherwise specifications are at TA = 25°C. VIN = 10V, ILOAD = 0, unless otherwise specified.
(Note 1)
OBSOLETE PACKAGE
Consider the N8 or S8 Packages for Alternate Source
LT1027
3
sn1027 1027fcs
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Line Regulation (Note 4) 8V ≤ V
IN
≤ 10V 6 12 ppm/V
●25 ppm/V
10V ≤ V
IN
≤ 40V 3 6 ppm/V
●8 ppm/V
Load Regulation (Notes 4, 6) Sourcing Current –8 –3 6 ppm/mA
0 ≤ I
OUT
≤ 15mA ●–10 8 ppm/mA
Sinking Current ●30 120 ppm/mA
0 ≥ I
OUT
≥ –10mA
Supply Current 2.2 3.1 mA
●3.5 mA
V
TRIM
Adjust Range ●±30 ±50 mV
e
n
Output Noise (Note 5) 0.1Hz ≤ f ≤ 10Hz 3 µV
P-P
10Hz ≤ f ≤ 1kHz 2.0 6.0 µV
RMS
Temperature Hysteresis H package; ∆T = 25°C 10 ppm
Long Term Stability H package 20 ppm/month
Note 5: RMS noise is measured with an 8-pole bandpass filter with a
center frequency of 30Hz and a Q of 1.5. The filter output is then rectified
and integrated for a fixed time period, resulting in an average, as opposed
to RMS voltage. A correction factor is used to convert average to RMS.
This value is then used to obtain RMS noise voltage in the 10Hz to 1000Hz
frequency band. This test also screens for low frequency "popcorn" noise
within the bandwidth of the filter. Consult factory for 100% 0.1Hz to 10Hz
noise testing.
Note 6: Devices typically exhibit a slight negative DC output impedance of
–0.015Ω. This compensates for PC trace resistance, improving regulation
at the load.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the part may be impaired.
Note 2: Output voltage is measured immediately after turn-on. Changes
due to chip warm-up are typically less than 0.005%.
Note 3: Temperature coefficient is determined by the "box" method in
which the maximum ∆V
OUT
over the temperature range is divided by ∆T.
Note 4: Line and load regulation measurements are done on a pulse basis.
Output voltage changes due to die temperature change must be taken into
account separately. Package thermal resistance is 150°C/W for TO-5 (H),
130°C/W for PDIP (N8), and 180°C/W for plastic SO (SO-8).
Ripple Rejection
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
FREQUENCY (Hz)
10
90
REJECTION (dB)
100
110
120
100
100 1k 10k
1027 G01
80
70
60
50
V
IN
= 10V
FREQUENCY (Hz)
0.01
OUTPUT IMPEDANCE (Ω)
0.1
1
10
100
10 10k 100k 1M
1027 G02
100 1k
∆I = ±3mA AC
ISOURCE = 5mA
Output Impedance vs Frequency Output Voltage
TEMPERATURE (°C)
–50
OUTPUT VOLTAGE (V)
5.002
5.004
5.006
25 75
1027 G03
5.000
4.998
–25 0 50 100
4.996
4.994
ELECTRICAL C CHARA TERISTICS
The ● denotes specifications which apply over the full operating
temperature range otherwise specifications are at TA = 25°C. VIN = 10V, ILOAD = 0, unless otherwise specified.
LT1027
4
sn1027 1027fcs
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
V
OUT
1V/DIV
Start-Up and Turn-Off
10V
V
IN
R
L
= 1k, C
L
= 4.7µF
Quiescent Current
10V
V
IN
Start-Up and Turn-Off (No Load)
1µs/DIV
V
OUT
1V/DIV
1027 G04 500µs/DIV 1027 G05
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
1.5
2.0
2.5
15 25 40
1027 G06
1.0
0.5
0510 20 30 35
–10
CHANGE IN OUTPUT VOLTAGE (µV)
0
400
800
8
1027 G07
–400
–800
–1600 264
–1200
–8 –6 –4 –2 0 10 12 14 16
I
OUT
(mA)
Sink Source
Load Regulation
Output Settling Time (Sourcing)
V
OUT
400µV/DIV
AC COUPLED
Line Regulation
FREQUENCY (Hz)
10
80
100
120
140
160
100 1k 10k
1027 G09
60
40
20
0
180
200
C
NR
= 1µF
C
NR
= 0
OUTPUT NOISE DENSITY (nV/√Hz)
Output Noise Voltage Density
INPUT VOLTAGE (V)
8
CHANGE IN OUTPUT VOLTAGE (µV)
300
400
500
20 28 40
1027 G08
200
0
100
12 16 24 32 36
–100
–200
–300
–400
–500
10mA
LOAD STEP
2µs/DIV 1027 G10
0.1Hz to 10Hz Output Noise
Filtering = 1 zero at 0.1Hz
2 poles at 10Hz
1sec/DIV
5µV/DIV
1027 G12
Output Settling Time (Sinking)
–10mA
LOAD STEP
2µs/DIV
V
OUT
400µV/DIV
AC COUPLED
1027 G11
LT1027
5
sn1027 1027fcs
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
to approximately 1.2µV
RMS
in a 10Hz to 1kHz bandwidth.
Transient response is not affected by this capacitor. Start-
up settling time will increase to several milliseconds due
to the 7kΩ impedance looking into the NR pin. The
capacitor
must
be a low leakage type. Electrolytics are
not
suitable for this application. Just 100nA leakage current
will result in a 150ppm error in output voltage. This pin is
the most sensitive pin on the device. For maximum protec-
tion a guard ring is recommended. The ring should be
driven from a resistive divider from V
OUT
set to 4.4V (the
open-circuit voltage on the NR pin).
Transient Response
The LT1027 has been optimized for transient response.
Settling time is under 2µs when an AC-coupled 10mA load
transient is applied to the output. The LT1027 achieves
fast settling by using a class B NPN/PNP output stage.
When sinking current, the device may oscillate with ca-
pacitive loads greater than 100pF. The LT1027 is stable
with all capacitive loads when at no DC load or when
sourcing current, although for best settling time either no
output bypass capactor or a 4.7µF tantalum unit is recom-
mended. An 0.1µF ceramic output capacitor will
maximize
output ringing
and is
not
recommended.
Kelvin Connections
Although the LT1027 does not have true force-sense
capability, proper hook-up can improve line loss and
ground loop problems significantly. Since the ground pin
of the LT1027 carries only 2mA, it can be used as a low-
side sense line, greatly reducing ground loop problems on
the low side of the reference. The V
OUT
pin should be close
to the load or connected via a heavy trace as the resistance
of this trace directly affects load regulation. It is important
to remember that a 1.22mV drop due to trace resistance is
equivalent to a 1LSB error in a 5V
FS
, 12-bit system.
The circuits in Figures 2 and 3 illustrate proper hook-up to
minimize errors due to ground loops and line losses.
Losses in the output lead can be further reduced by adding
a PNP boost transistor if load current is 5mA or higher. R2
can be added to further reduce current in the output sense
load.
Effect of Reference Drift on System Accuracy
A large portion of the temperature drift error budget in
many systems is the system reference voltage. Figure 1
indicates the maximum temperature coefficient allowable
if the reference is to contribute no more than 0.5LSB error
to the overall system performance. The example shown is
a 12-bit system designed to operate over a temperature
range from 25°C to 65°C. Assuming the system calibra-
tion is performed at 25°C, the temperature span is 40°C.
It can be seen from the graph that the temperature coeffi-
cient of the reference must be no worse than 3ppm/°C if
it is to contribute less than 0.5LSB error. For this reason,
the LT1027 has been optimized for low drift.
Figure 1. Maximum Allowable Reference Drift
Trimming Output Voltage
The LT1027 has an adjustment pin for trimming output
voltage. The impedance of the V
ADJ
pin is about 20kΩ with
an open-circuit voltage of 2.5V. A ±30mV guaranteed trim
range is achievable by tying the V
ADJ
pin to the wiper of a
10k potentiometer connecting between the output and
ground. Trimming output voltage does not affect the TC of
the device.
Noise Reduction
The positive input of the internal scaling amplifier is
brought out as the Noise Reduction (NR) pin. Connecting
a 1µF Mylar capacitor between this pin and ground will
reduce the wideband noise of the LT1027 from 2.0µV
RMS
TEMPERATURE SPAN (°C)
100
MAXIMUM TEMPERATURE COEFFICIENT FOR
0.5LSB ERROR (ppm/°C)
30
100
1027 AI01
1.0
10
20 100
90
807060
50
40
8-BIT
10-BIT
12-BIT
14-BIT
LT1027
6
sn1027 1027fcs
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
IN OUT
GND
+
GROUND
RETURN
KEEP THIS LINE RESISTANCE LOW
1027 F02
INPUT LT1027
LOAD
Figure 2. Standard Hook-Up
IN
OUT
GND
LT1027
GROUND
RETURN
INPUT
R1
91Ω
R2*
2.4k LOAD
1027 F03
*OPTIONAL–REDUCES CURRENT IN OUTPUT SENSE LEAD
4.7µF
+
2N4403
Figure 3. Driving Higher Load Currents
LT1027
V
IN
7
1µF
1µF
0.01µF
V
OUT
16
13
12
11
17
14
LTC1043
8
1027 TA04
V
IN
OUT
GND
–
+
LT1097
LT1027
V
IN
1027 TA03
IN
OUT
V
TRIM
GND 5k
5k*
10.00V
OUTPUT
5k*
* 0.1% METAL FILM
10V Reference 10V Reference
Operating 5V Reference from 5V Supply
C2
5µF*
≈8.5V 5V
REFERENCE
1N914
LT1027
C1
5µF*
1N914
5V
LOGIC SUPPLY
CMOS LOGIC GATE**
*FOR HIGHER FREQUENCIES C1 AND C2 MAY BE DECREASED
**PARALLEL GATES FOR HIGHER REFERENCE CURRENT LOADING
f
IN
≥ 2kHz* IN OUT
GND
1027 TA05
+
+
TYPICAL APPLICATIONS
U
LT1027
7
sn1027 1027fcs
0.050
(1.270)
MAX
0.016 – 0.021**
(0.406 – 0.533)
0.010 – 0.045*
(0.254 – 1.143)
SEATING
PLANE
0.040
(1.016)
MAX 0.165 – 0.185
(4.191 – 4.699)
GAUGE
PLANE
REFERENCE
PLANE
0.500 – 0.750
(12.700 – 19.050)
0.305 – 0.335
(7.747 – 8.509)
0.335 – 0.370
(8.509 – 9.398)
DIA
0.230
(5.842)
TYP
0.027 – 0.045
(0.686 – 1.143)
0.028 – 0.034
(0.711 – 0.864)
0.110 – 0.160
(2.794 – 4.064)
INSULATING
STANDOFF
45°TYP
H8 (TO-5) 0.230 PCD 1197
LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE
AND 0.045" BELOW THE REFERENCE PLANE
FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS 0.016 – 0.024
(0.406 – 0.610)
*
**
PIN 1
PACKAGE DESCRIPTIO
U
H Package
8-Lead TO-5 Metal Can (.230 Inch PCD)
(Reference LTC DWG # 05-08-1321)
OBSOLETE PACKAGE
SCHETEQUIVALE ATIC
UW
OUTPUT CURRENT LIMIT AND
BIAS CIRCUITS NOT SHOWN
NR
GND
V
OUT
V
ADJ
1027 ES
V
IN
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1027
8
sn1027 1027fcs
PACKAGE DESCRIPTIO
U
LINEAR TECHNOLOGY CORPORATION 1992
LT/CPI 1101 1.5K REV C • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LT1019 Precision Series Bandgap Reference, 0.05%, 5ppm/°C Drift 2.5V, 4.5V, 5V, 10V Outputs; Industrial, Military Grades Available
LT1021 Precision Buried Zener Diode Reference, 5V, 7V, 10V Outputs; 8-Pin PDIP, SO, TO-5 Packages;
0.5%, 5ppm/°C Drift Military Grades Available
LT1236 Precision Series Reference, 0.05%, 5ppm/°C Drift 5V, 10V Outputs; 8-Pin PDIP, SO Packages; Industrial Grade Available
LT1460 Micropower Precision Series Bandgap Reference, 2.5V, 5V, 10V Outputs; 8-Pin PDIP, SO, MSOP;
0.075%, 10ppm/°C Drift TO-92 and SOT-23 Packages
LT1461 Low Dropout 3ppm/°C Drift, 0.04% Series Reference 2.5V, SO-8 Package
LT1798 Low Dropout, Micropower Reference 2.5V, 3V, 4.096V, 5V, Adjustable in SO-8
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.016 – 0.050
(0.406 – 1.270)
0.010 – 0.020
(0.254 – 0.508)× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 1298
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
1234
0.150 – 0.157**
(3.810 – 3.988)
8765
0.189 – 0.197*
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
N8 1098
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.035
–0.015
+0.889
–0.381
8.255
()
0.100
(2.54)
BSC
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN 12 34
8765
0.255 ± 0.015*
(6.477 ± 0.381)
0.400*
(10.160)
MAX
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
